exception.S revision 221893
1/*- 2 * Copyright (c) 2003,2004 Marcel Moolenaar 3 * Copyright (c) 2000 Doug Rabson 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <machine/asm.h> 29__FBSDID("$FreeBSD: head/sys/ia64/ia64/exception.S 221893 2011-05-14 14:47:19Z marcel $"); 30 31#include "opt_xtrace.h" 32 33#include <machine/pte.h> 34#include <assym.s> 35 36/* 37 * Nested TLB restart tokens. These are used by the 38 * nested TLB handler for jumping back to the code 39 * where the nested TLB was caused. 40 */ 41#define NTLBRT_SAVE 0x12c12c 42#define NTLBRT_RESTORE 0x12c12d 43 44/* 45 * ar.k7 = kernel memory stack 46 * ar.k6 = kernel register stack 47 * ar.k5 = EPC gateway page 48 * ar.k4 = PCPU data 49 */ 50 51 .section .ivt.data, "aw" 52 53 .global pmap_ptc_g_sem 54pmap_ptc_g_sem: data8 0 55 56 .global ia64_kptdir 57ia64_kptdir: data8 0 58 59#ifdef EXCEPTION_TRACING 60 61 .global xtrace, xhead 62xtrace: .space 1024*5*8 63xhead: data8 xtrace 64 65#define XTRACE(offset) \ 66{ .mmi ; \ 67 mov r24=ar.itc ; \ 68 mov r25=cr.iip ; \ 69 mov r27=offset ; \ 70} ; \ 71{ .mlx ; \ 72 mov r28=cr.ifa ; \ 73 movl r29=xhead ;; \ 74} ; \ 75{ .mmi ; \ 76 ld8 r29=[r29] ;; \ 77 st8 [r29]=r24,8 ; \ 78 nop 0 ;; \ 79} ; \ 80{ .mmi ; \ 81 st8 [r29]=r27,8 ;; \ 82 mov r24=cr.isr ; \ 83 add r27=8,r29 ;; \ 84} ; \ 85{ .mmi ; \ 86 st8 [r29]=r25,16 ;; \ 87 st8 [r27]=r28,16 ; \ 88 mov r25=pr ;; \ 89} ; \ 90{ .mlx ; \ 91 st8 [r29]=r24 ; \ 92 movl r28=xhead ;; \ 93} ; \ 94{ .mii ; \ 95 cmp.eq p15,p0=r27,r28 ; \ 96 addl r29=1024*5*8,r0 ;; \ 97(p15) sub r27=r28,r29 ;; \ 98} ; \ 99{ .mmi ; \ 100 st8 [r28]=r27 ; \ 101 nop 0 ; \ 102 mov pr=r25,0x1ffff ;; \ 103} 104 105#else 106 107#define XTRACE(offset) 108 109#endif 110 111 .section .ivt.text, "ax" 112 113/* 114 * exception_save: save interrupted state 115 * 116 * Arguments: 117 * r16 address of bundle that contains the branch. The 118 * return address will be the next bundle. 119 * r17 the value to save as ifa in the trapframe. This 120 * normally is cr.ifa, but some interruptions set 121 * set cr.iim and not cr.ifa. 122 * 123 * Returns: 124 * p15 interrupted from user stack 125 * p14 interrupted from kernel stack 126 * p13 interrupted from user backing store 127 * p12 interrupted from kernel backing store 128 * p11 interrupts were enabled 129 * p10 interrupts were disabled 130 */ 131ENTRY_NOPROFILE(exception_save, 0) 132{ .mii 133 mov r20=ar.unat 134 extr.u r31=sp,61,3 135 mov r18=pr 136 ;; 137} 138{ .mmi 139 cmp.le p14,p15=IA64_VM_MINKERN_REGION,r31 140 ;; 141(p15) mov r23=ar.k7 // kernel memory stack 142(p14) mov r23=sp 143 ;; 144} 145{ .mii 146 mov r21=ar.rsc 147 add r30=-SIZEOF_TRAPFRAME,r23 148 ;; 149 dep r30=0,r30,0,10 150 ;; 151} 152{ .mmi 153 mov ar.rsc=0 154 sub r19=r23,r30 155 add r31=8,r30 156 ;; 157} 158{ .mmi 159 mov r22=cr.iip 160 nop 0 161 addl r29=NTLBRT_SAVE,r0 // 22-bit restart token. 162 ;; 163} 164 165 /* 166 * We have a 1KB aligned trapframe, pointed to by sp. If we write 167 * to the trapframe, we may trigger a data nested TLB fault. By 168 * aligning the trapframe on a 1KB boundary, we guarantee that if 169 * we get a data nested TLB fault, it will be on the very first 170 * write. Since the data nested TLB fault does not preserve any 171 * state, we have to be careful what we clobber. Consequently, we 172 * have to be careful what we use here. Below a list of registers 173 * that are currently alive: 174 * r16,r17=arguments 175 * r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS 176 * r29=restart point 177 * r30,r31=trapframe pointers 178 * p14,p15=memory stack switch 179 */ 180 181 /* PTC.G enter non-exclusive */ 182 mov r24 = ar.ccv 183 movl r25 = pmap_ptc_g_sem 184 ;; 185.ptc_g_0: 186 ld8.acq r26 = [r25] 187 ;; 188 tbit.nz p12, p0 = r26, 63 189(p12) br.cond.spnt.few .ptc_g_0 190 ;; 191 mov ar.ccv = r26 192 adds r27 = 1, r26 193 ;; 194 cmpxchg8.rel r27 = [r25], r27, ar.ccv 195 ;; 196 cmp.ne p12, p0 = r26, r27 197(p12) br.cond.spnt.few .ptc_g_0 198 ;; 199 mov ar.ccv = r24 200 201exception_save_restart: 202{ .mmi 203 st8 [r30]=r19,16 // length 204 st8 [r31]=r0,16 // flags 205 add r29=16,r19 // Clobber restart token 206 ;; 207} 208{ .mmi 209 st8.spill [r30]=sp,16 // sp 210 st8 [r31]=r20,16 // unat 211 sub sp=r23,r29 212 ;; 213} 214{ .mmi 215 mov r19=ar.rnat 216 mov r20=ar.bspstore 217 mov r23=rp 218 ;; 219} 220 // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp 221{ .mmi 222 st8 [r30]=r23,16 // rp 223 st8 [r31]=r18,16 // pr 224 mov r24=ar.pfs 225 ;; 226} 227{ .mmb 228 st8 [r30]=r24,16 // pfs 229 st8 [r31]=r20,16 // bspstore 230 cover 231 ;; 232} 233{ .mmi 234 mov r18=ar.fpsr 235 mov r23=cr.ipsr 236 extr.u r24=r20,61,3 237 ;; 238} 239 // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr 240{ .mmi 241 st8 [r30]=r19,16 // rnat 242 st8 [r31]=r0,16 // __spare 243 cmp.le p12,p13=IA64_VM_MINKERN_REGION,r24 244 ;; 245} 246{ .mmi 247 st8.spill [r30]=r13,16 // tp 248 st8 [r31]=r21,16 // rsc 249 tbit.nz p11,p10=r23,14 // p11=interrupts enabled 250 ;; 251} 252{ .mmi 253(p13) mov r21=ar.k6 // kernel register stack 254 ;; 255 st8 [r30]=r18,16 // fpsr 256(p13) dep r20=r20,r21,0,9 // align dirty registers 257 ;; 258} 259 // r19=rnat, r20=bspstore, r22=iip, r23=ipsr 260{ .mmi 261 st8 [r31]=r23,16 // psr 262(p13) mov ar.bspstore=r20 263 nop 0 264 ;; 265} 266{ .mmi 267(p13) mov ar.rnat=r19 268 mov r18=ar.bsp 269 nop 0 270 ;; 271} 272{ .mmi 273 mov r19=cr.ifs 274 st8.spill [r30]=gp,16 // gp 275 sub r18=r18,r20 276 ;; 277} 278 // r19=ifs, r22=iip 279{ .mmi 280 st8 [r31]=r18,16 // ndirty 281 st8 [r30]=r19,16 // cfm 282 nop 0 283 ;; 284} 285{ .mmi 286 mov r18=cr.isr 287 st8 [r31]=r22,16 // iip 288 add r29=16,r30 289 ;; 290} 291{ .mmi 292 st8 [r30]=r17,24 // ifa 293 st8 [r31]=r18,24 // isr 294 nop 0 295 ;; 296} 297{ .mmi 298 .mem.offset 0,0 299 st8.spill [r30]=r2,16 // r2 300 .mem.offset 8,0 301 st8.spill [r31]=r3,16 // r3 302 add r2=9*8,r29 303 ;; 304} 305{ .mmi 306 .mem.offset 0,0 307 st8.spill [r30]=r8,16 // r8 308 .mem.offset 8,0 309 st8.spill [r31]=r9,16 // r9 310 add r3=8,r2 311 ;; 312} 313{ .mmi 314 .mem.offset 0,0 315 st8.spill [r30]=r10,16 // r10 316 .mem.offset 8,0 317 st8.spill [r31]=r11,16 // r11 318 add r8=16,r16 319 ;; 320} 321{ .mmi 322 .mem.offset 0,0 323 st8.spill [r30]=r14 // r14 324 .mem.offset 8,0 325 st8.spill [r31]=r15 // r15 326 mov r9=r29 327} 328{ .mmb 329 mov r10=ar.csd 330 mov r11=ar.ssd 331 bsw.1 332 ;; 333} 334{ .mmi 335 .mem.offset 0,0 336 st8.spill [r2]=r16,16 // r16 337 .mem.offset 8,0 338 st8.spill [r3]=r17,16 // r17 339 mov r14=b6 340 ;; 341} 342{ .mmi 343 .mem.offset 0,0 344 st8.spill [r2]=r18,16 // r18 345 .mem.offset 8,0 346 st8.spill [r3]=r19,16 // r19 347 mov r15=b7 348 ;; 349} 350{ .mmi 351 .mem.offset 0,0 352 st8.spill [r2]=r20,16 // r20 353 .mem.offset 8,0 354 st8.spill [r3]=r21,16 // r21 355 mov b7=r8 356 ;; 357} 358{ .mmi 359 .mem.offset 0,0 360 st8.spill [r2]=r22,16 // r22 361 .mem.offset 8,0 362 st8.spill [r3]=r23,16 // r23 363 ;; 364} 365 366 .mem.offset 0,0 367 st8.spill [r2]=r24,16 // r24 368 .mem.offset 8,0 369 st8.spill [r3]=r25,16 // r25 370 ;; 371 .mem.offset 0,0 372 st8.spill [r2]=r26,16 // r26 373 .mem.offset 8,0 374 st8.spill [r3]=r27,16 // r27 375 ;; 376 .mem.offset 0,0 377 st8.spill [r2]=r28,16 // r28 378 .mem.offset 8,0 379 st8.spill [r3]=r29,16 // r29 380 ;; 381 .mem.offset 0,0 382 st8.spill [r2]=r30,16 // r30 383 .mem.offset 8,0 384 st8.spill [r3]=r31,16 // r31 385 ;; 386 387{ .mmi 388 st8 [r2]=r14,16 // b6 389 mov r17=ar.unat 390 nop 0 391 ;; 392} 393{ .mmi 394 st8 [r3]=r15,16 // b7 395 mov r16=ar.ccv 396 nop 0 397 ;; 398} 399{ .mmi 400 st8 [r2]=r16,16 // ccv 401 st8 [r3]=r10,16 // csd 402 nop 0 403 ;; 404} 405{ .mmi 406 st8 [r2]=r11,24 // ssd 407 st8 [r9]=r17 408 nop 0 409 ;; 410} 411 412 stf.spill [r3]=f6,32 // f6 413 stf.spill [r2]=f7,32 // f7 414 ;; 415 stf.spill [r3]=f8,32 // f8 416 stf.spill [r2]=f9,32 // f9 417 ;; 418 stf.spill [r3]=f10,32 // f10 419 stf.spill [r2]=f11,32 // f11 420 ;; 421 stf.spill [r3]=f12,32 // f12 422 stf.spill [r2]=f13,32 // f13 423 ;; 424 stf.spill [r3]=f14 // f14 425 stf.spill [r2]=f15 // f15 426 ;; 427{ .mmi 428 mov ar.rsc=3 429 mov r13=ar.k4 430 nop 0 431 ;; 432} 433{ .mlx 434 ssm psr.ic|psr.dfh 435 movl gp=__gp 436 ;; 437} 438 439 /* PTC.G leave non-exclusive */ 440 srlz.d 441 movl r25 = pmap_ptc_g_sem 442 ;; 443.ptc_g_1: 444 ld8.acq r26 = [r25] 445 ;; 446 mov ar.ccv = r26 447 adds r27 = -1, r26 448 ;; 449 cmpxchg8.rel r27 = [r25], r27, ar.ccv 450 ;; 451 cmp.ne p12, p0 = r26, r27 452(p12) br.cond.spnt.few .ptc_g_1 453 ;; 454 455{ .mib 456 srlz.d 457 nop 0 458 br.sptk b7 459 ;; 460} 461END(exception_save) 462 463/* 464 * exception_restore: restore interrupted state 465 * 466 * Arguments: 467 * sp+16 trapframe pointer 468 */ 469ENTRY_NOPROFILE(exception_restore, 0) 470{ .mmi 471 rsm psr.i 472 add r3=SIZEOF_TRAPFRAME-16,sp 473 add r2=SIZEOF_TRAPFRAME,sp 474 ;; 475} 476{ .mmi 477 srlz.d 478 add r8=SIZEOF_SPECIAL+32,sp 479 nop 0 480 ;; 481} 482 // The next load can trap. Let it be... 483 ldf.fill f15=[r2],-32 // f15 484 ldf.fill f14=[r3],-32 // f14 485 add sp=16,sp 486 ;; 487 ldf.fill f13=[r2],-32 // f13 488 ldf.fill f12=[r3],-32 // f12 489 ;; 490 ldf.fill f11=[r2],-32 // f11 491 ldf.fill f10=[r3],-32 // f10 492 ;; 493 ldf.fill f9=[r2],-32 // f9 494 ldf.fill f8=[r3],-32 // f8 495 ;; 496 ldf.fill f7=[r2],-24 // f7 497 ldf.fill f6=[r3],-16 // f6 498 ;; 499 500{ .mmi 501 ld8 r8=[r8] // unat (after) 502 ;; 503 mov ar.unat=r8 504 nop 0 505 ;; 506} 507 508 ld8 r10=[r2],-16 // ssd 509 ld8 r11=[r3],-16 // csd 510 ;; 511 mov ar.ssd=r10 512 mov ar.csd=r11 513 514 ld8 r14=[r2],-16 // ccv 515 ld8 r15=[r3],-16 // b7 516 ;; 517 518{ .mmi 519 mov ar.ccv=r14 520 ld8 r8=[r2],-16 // b6 521 mov b7=r15 522 ;; 523} 524{ .mmi 525 ld8.fill r31=[r3],-16 // r31 526 ld8.fill r30=[r2],-16 // r30 527 mov b6=r8 528 ;; 529} 530 531 ld8.fill r29=[r3],-16 // r29 532 ld8.fill r28=[r2],-16 // r28 533 ;; 534 ld8.fill r27=[r3],-16 // r27 535 ld8.fill r26=[r2],-16 // r26 536 ;; 537 ld8.fill r25=[r3],-16 // r25 538 ld8.fill r24=[r2],-16 // r24 539 ;; 540 ld8.fill r23=[r3],-16 // r23 541 ld8.fill r22=[r2],-16 // r22 542 ;; 543 ld8.fill r21=[r3],-16 // r21 544 ld8.fill r20=[r2],-16 // r20 545 ;; 546 ld8.fill r19=[r3],-16 // r19 547 ld8.fill r18=[r2],-16 // r18 548 ;; 549 550{ .mmb 551 ld8.fill r17=[r3],-16 // r17 552 ld8.fill r16=[r2],-16 // r16 553 bsw.0 554 ;; 555} 556{ .mmi 557 ld8.fill r15=[r3],-16 // r15 558 ld8.fill r14=[r2],-16 // r14 559 add r31=16,sp 560 ;; 561} 562{ .mmi 563 ld8 r16=[sp] // tf_length 564 ld8.fill r11=[r3],-16 // r11 565 add r30=24,sp 566 ;; 567} 568{ .mmi 569 ld8.fill r10=[r2],-16 // r10 570 ld8.fill r9=[r3],-16 // r9 571 add r16=r16,sp // ar.k7 572 ;; 573} 574{ .mmi 575 ld8.fill r8=[r2],-16 // r8 576 ld8.fill r3=[r3] // r3 577 ;; 578} 579 // We want nested TLB faults from here on... 580 rsm psr.ic|psr.i 581 ld8.fill r2=[r2] // r2 582 nop 0 583 ;; 584 srlz.d 585 ld8.fill sp=[r31],16 // sp 586 nop 0 587 ;; 588 589 ld8 r17=[r30],16 // unat 590 ld8 r29=[r31],16 // rp 591 ;; 592 ld8 r18=[r30],16 // pr 593 ld8 r28=[r31],16 // pfs 594 mov rp=r29 595 ;; 596 ld8 r20=[r30],24 // bspstore 597 ld8 r21=[r31],24 // rnat 598 mov ar.pfs=r28 599 ;; 600 ld8.fill r26=[r30],16 // tp 601 ld8 r22=[r31],16 // rsc 602 ;; 603{ .mmi 604 ld8 r23=[r30],16 // fpsr 605 ld8 r24=[r31],16 // psr 606 extr.u r28=r20,61,3 607 ;; 608} 609{ .mmi 610 ld8.fill r1=[r30],16 // gp 611 ld8 r27=[r31],16 // ndirty 612 cmp.le p14,p15=IA64_VM_MINKERN_REGION,r28 613 ;; 614} 615{ .mmi 616 ld8 r25=[r30] // cfm 617 ld8 r19=[r31] // ip 618 nop 0 619 ;; 620} 621{ .mii 622 // Switch register stack 623 alloc r30=ar.pfs,0,0,0,0 // discard current frame 624 shl r31=r27,16 // value for ar.rsc 625(p15) mov r13=r26 626 ;; 627} 628 // The loadrs can fault if the backing store is not currently 629 // mapped. We assured forward progress by getting everything we 630 // need from the trapframe so that we don't care if the CPU 631 // purges that translation when it needs to insert a new one for 632 // the backing store. 633{ .mmi 634 mov ar.rsc=r31 // setup for loadrs 635 mov ar.k7=r16 636 addl r29=NTLBRT_RESTORE,r0 // 22-bit restart token 637 ;; 638} 639exception_restore_restart: 640{ .mmi 641 mov r30=ar.bspstore 642 ;; 643 loadrs // load user regs 644 mov r29=0 // Clobber restart token 645 ;; 646} 647{ .mmi 648 mov r31=ar.bspstore 649 ;; 650 mov ar.bspstore=r20 651 dep r31=0,r31,0,13 // 8KB aligned 652 ;; 653} 654{ .mmi 655 mov ar.k6=r31 656 mov ar.rnat=r21 657 nop 0 658 ;; 659} 660{ .mmi 661 mov ar.unat=r17 662 mov cr.iip=r19 663 nop 0 664} 665{ .mmi 666 mov cr.ipsr=r24 667 mov cr.ifs=r25 668 mov pr=r18,0x1ffff 669 ;; 670} 671{ .mmb 672 mov ar.rsc=r22 673 mov ar.fpsr=r23 674 rfi 675 ;; 676} 677END(exception_restore) 678 679/* 680 * Call exception_save_regs to preserve the interrupted state in a 681 * trapframe. Note that we don't use a call instruction because we 682 * must be careful not to lose track of the RSE state. We then call 683 * trap() with the value of _n_ as an argument to handle the 684 * exception. We arrange for trap() to return to exception_restore 685 * which will restore the interrupted state before executing an rfi to 686 * resume it. 687 */ 688#define CALL(_func_, _n_, _ifa_) \ 689{ .mib ; \ 690 mov r17=_ifa_ ; \ 691 mov r16=ip ; \ 692 br.sptk exception_save ;; \ 693} ; \ 694{ .mmi ; \ 695 alloc r15=ar.pfs,0,0,2,0 ;; \ 696(p11) ssm psr.i ; \ 697 mov out0=_n_ ;; \ 698} ; \ 699{ .mib ; \ 700(p11) srlz.d ; \ 701 add out1=16,sp ; \ 702 br.call.sptk rp=_func_ ;; \ 703} ; \ 704{ .mib ; \ 705 nop 0 ; \ 706 nop 0 ; \ 707 br.sptk exception_restore ;; \ 708} 709 710#define IVT_ENTRY(name, offset) \ 711 .org ia64_vector_table + offset; \ 712 .global ivt_##name; \ 713 .proc ivt_##name; \ 714 .prologue; \ 715 .unwabi @svr4, 'I'; \ 716 .save rp, r0; \ 717 .body; \ 718ivt_##name: \ 719 XTRACE(offset) 720 721#define IVT_END(name) \ 722 .endp ivt_##name 723 724#ifdef COMPAT_FREEBSD32 725#define IA32_TRAP ia32_trap 726#else 727#define IA32_TRAP trap 728#endif 729 730/* 731 * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64 732 * bundles per vector and 48 slots with 16 bundles per vector. 733 */ 734 735 .section .ivt, "ax" 736 737 .align 32768 738 .global ia64_vector_table 739 .size ia64_vector_table, 32768 740ia64_vector_table: 741 742IVT_ENTRY(VHPT_Translation, 0x0000) 743 CALL(trap, 0, cr.ifa) 744IVT_END(VHPT_Translation) 745 746IVT_ENTRY(Instruction_TLB, 0x0400) 747 mov r16=cr.ifa 748 mov r17=pr 749 ;; 750 thash r18=r16 751 ttag r19=r16 752 ;; 753 add r21=16,r18 // tag 754 add r20=24,r18 // collision chain 755 ;; 756 ld8 r21=[r21] // check VHPT tag 757 ld8 r20=[r20] // bucket head 758 ;; 759 cmp.ne p15,p0=r21,r19 760(p15) br.dpnt.few 1f 761 ;; 762 ld8 r21=[r18] // read pte 763 ;; 764 itc.i r21 // insert pte 765 mov pr=r17,0x1ffff 766 ;; 767 rfi // done 768 ;; 7691: rsm psr.dt // turn off data translations 770 dep r20=0,r20,61,3 // convert vhpt ptr to physical 771 ;; 772 srlz.d // serialize 773 ld8 r20=[r20] // first entry 774 ;; 7752: cmp.eq p15,p0=r0,r20 // done? 776(p15) br.cond.spnt.few 9f // bail if done 777 ;; 778 add r21=16,r20 // tag location 779 ;; 780 ld8 r21=[r21] // read tag 781 ;; 782 cmp.ne p15,p0=r21,r19 // compare tags 783(p15) br.cond.sptk.few 3f // if not, read next in chain 784 ;; 785 ld8 r21=[r20] // read pte 786 mov r22=PTE_ACCESSED 787 ;; 788 or r21=r21,r22 789 ;; 790 st8 [r20]=r21,8 791 ;; 792 ld8 r22=[r20] // read rest of pte 793 ;; 794 dep r18=0,r18,61,3 // convert vhpt ptr to physical 795 ;; 796 add r20=16,r18 // address of tag 797 ;; 798 ld8.acq r23=[r20] // read old tag 799 ;; 800 dep r23=-1,r23,63,1 // set ti bit 801 ;; 802 st8.rel [r20]=r23 // store old tag + ti 803 ;; 804 mf // make sure everyone sees 805 ;; 806 st8 [r18]=r21,8 // store pte 807 ;; 808 st8 [r18]=r22,8 809 ;; 810 st8.rel [r18]=r19 // store new tag 811 ;; 812 itc.i r21 // and place in TLB 813 ssm psr.dt 814 ;; 815 srlz.d 816 mov pr=r17,0x1ffff // restore predicates 817 rfi 818 ;; 8193: add r20=24,r20 // next in chain 820 ;; 821 ld8 r20=[r20] // read chain 822 br.sptk 2b // loop 823 ;; 8249: ssm psr.dt 825 mov pr=r17,0x1ffff // restore predicates 826 ;; 827 srlz.d 828 ;; 829 CALL(trap, 20, cr.ifa) // Page Not Present trap 830IVT_END(Instruction_TLB) 831 832IVT_ENTRY(Data_TLB, 0x0800) 833 mov r16=cr.ifa 834 mov r17=pr 835 ;; 836 thash r18=r16 837 ttag r19=r16 838 ;; 839 add r21=16,r18 // tag 840 add r20=24,r18 // collision chain 841 ;; 842 ld8 r21=[r21] // check VHPT tag 843 ld8 r20=[r20] // bucket head 844 ;; 845 cmp.ne p15,p0=r21,r19 846(p15) br.dpnt.few 1f 847 ;; 848 ld8 r21=[r18] // read pte 849 ;; 850 itc.d r21 // insert pte 851 mov pr=r17,0x1ffff 852 ;; 853 rfi // done 854 ;; 8551: rsm psr.dt // turn off data translations 856 dep r20=0,r20,61,3 // convert vhpt ptr to physical 857 ;; 858 srlz.d // serialize 859 ld8 r20=[r20] // first entry 860 ;; 8612: cmp.eq p15,p0=r0,r20 // done? 862(p15) br.cond.spnt.few 9f // bail if done 863 ;; 864 add r21=16,r20 // tag location 865 ;; 866 ld8 r21=[r21] // read tag 867 ;; 868 cmp.ne p15,p0=r21,r19 // compare tags 869(p15) br.cond.sptk.few 3f // if not, read next in chain 870 ;; 871 ld8 r21=[r20] // read pte 872 mov r22=PTE_ACCESSED 873 ;; 874 or r21=r21,r22 875 ;; 876 st8 [r20]=r21,8 877 ;; 878 ld8 r22=[r20] // read rest of pte 879 ;; 880 dep r18=0,r18,61,3 // convert vhpt ptr to physical 881 ;; 882 add r20=16,r18 // address of tag 883 ;; 884 ld8.acq r23=[r20] // read old tag 885 ;; 886 dep r23=-1,r23,63,1 // set ti bit 887 ;; 888 st8.rel [r20]=r23 // store old tag + ti 889 ;; 890 mf // make sure everyone sees 891 ;; 892 st8 [r18]=r21,8 // store pte 893 ;; 894 st8 [r18]=r22,8 895 ;; 896 st8.rel [r18]=r19 // store new tag 897 ;; 898 itc.d r21 // and place in TLB 899 ssm psr.dt 900 ;; 901 srlz.d 902 mov pr=r17,0x1ffff // restore predicates 903 rfi 904 ;; 9053: add r20=24,r20 // next in chain 906 ;; 907 ld8 r20=[r20] // read chain 908 br.sptk 2b // loop 909 ;; 9109: ssm psr.dt 911 mov pr=r17,0x1ffff // restore predicates 912 ;; 913 srlz.d 914 ;; 915 CALL(trap, 20, cr.ifa) // Page Not Present trap 916IVT_END(Data_TLB) 917 918IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00) 919 mov r16=cr.ifa // where did it happen 920 mov r18=pr // save predicates 921 ;; 922 extr.u r17=r16,61,3 // get region number 923 mov r19=PTE_PRESENT+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+PTE_AR_RWX 924 ;; 925 cmp.eq p13,p0=IA64_PBVM_RR,r17 // RR4? 926(p13) br.cond.sptk.few 4f 927 ;; 928 cmp.ge p13,p0=5,r17 // RR0-RR5? 929 cmp.eq p14,p15=7,r17 // RR7? 930(p13) br.cond.spnt.few 9f 931 ;; 932(p14) add r19=PTE_MA_WB,r19 933(p15) add r19=PTE_MA_UC,r19 934 dep r17=0,r16,50,14 // clear bits above PPN 935 ;; 9361: dep r16=r19,r17,0,12 // put pte bits in 0..11 937 ;; 938 itc.i r16 939 mov pr=r18,0x1ffff // restore predicates 940 ;; 941 rfi 942 ;; 9434: 944 add r19=PTE_MA_WB,r19 945 movl r17=IA64_PBVM_BASE 946 ;; 947 sub r17=r16,r17 948 movl r16=IA64_PBVM_PGTBL 949 ;; 950 extr.u r17=r17,IA64_PBVM_PAGE_SHIFT,61-IA64_PBVM_PAGE_SHIFT 951 ;; 952 shladd r16=r17,3,r16 953 ;; 954 ld8 r17=[r16] 955 br.sptk 1b 956 ;; 9579: mov pr=r18,0x1ffff // restore predicates 958 CALL(trap, 3, cr.ifa) 959IVT_END(Alternate_Instruction_TLB) 960 961IVT_ENTRY(Alternate_Data_TLB, 0x1000) 962 mov r16=cr.ifa // where did it happen 963 mov r18=pr // save predicates 964 ;; 965 extr.u r17=r16,61,3 // get region number 966 mov r19=PTE_PRESENT+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+PTE_AR_RWX 967 ;; 968 cmp.eq p13,p0=IA64_PBVM_RR,r17 // RR4? 969(p13) br.cond.sptk.few 4f 970 ;; 971 cmp.ge p13,p0=5,r17 // RR0-RR5? 972 cmp.eq p14,p15=7,r17 // RR7? 973(p13) br.cond.spnt.few 9f 974 ;; 975(p14) add r19=PTE_MA_WB,r19 976(p15) add r19=PTE_MA_UC,r19 977 dep r17=0,r16,50,14 // clear bits above PPN 978 ;; 9791: dep r16=r19,r17,0,12 // put pte bits in 0..11 980 ;; 981 itc.d r16 982 mov pr=r18,0x1ffff // restore predicates 983 ;; 984 rfi 985 ;; 9864: 987 add r19=PTE_MA_WB,r19 988 movl r17=IA64_PBVM_BASE 989 ;; 990 sub r17=r16,r17 991 movl r16=IA64_PBVM_PGTBL 992 ;; 993 extr.u r17=r17,IA64_PBVM_PAGE_SHIFT,61-IA64_PBVM_PAGE_SHIFT 994 ;; 995 shladd r16=r17,3,r16 996 ;; 997 ld8 r17=[r16] 998 br.sptk 1b 999 ;; 10009: mov pr=r18,0x1ffff // restore predicates 1001 CALL(trap, 4, cr.ifa) 1002IVT_END(Alternate_Data_TLB) 1003 1004IVT_ENTRY(Data_Nested_TLB, 0x1400) 1005 // See exception_save_restart and exception_restore_restart for the 1006 // contexts that may cause a data nested TLB. We can only use the 1007 // banked general registers and predicates, but don't use: 1008 // p14 & p15 - Set in exception save 1009 // r16 & r17 - Arguments to exception save 1010 // r30 - Faulting address (modulo page size) 1011 // We assume r30 has the virtual addresses that relate to the data 1012 // nested TLB fault. The address does not have to be exact, as long 1013 // as it's in the same page. We use physical addressing to avoid 1014 // double nested faults. Since all virtual addresses we encounter 1015 // here are direct mapped region 7 addresses, we have no problem 1016 // constructing physical addresses. 1017 1018{ .mlx 1019 nop 0 1020 movl r27=ia64_kptdir 1021 ;; 1022} 1023{ .mii 1024 ld8 r27=[r27] 1025 extr.u r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3 // dir L0 index 1026 extr.u r26=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3 // dir L1 index 1027 ;; 1028} 1029{ .mmi 1030 rsm psr.dt 1031 ;; 1032 srlz.d 1033 dep r27=0,r27,61,3 1034 ;; 1035} 1036{ .mmi 1037 shladd r27=r28,3,r27 1038 ;; 1039 ld8 r27=[r27] // dir L1 page 1040 extr.u r28=r30,PAGE_SHIFT,PAGE_SHIFT-5 // pte index 1041 ;; 1042} 1043{ .mmi 1044 shladd r27=r26,3,r27 1045 ;; 1046 mov r26=rr[r30] 1047 dep r27=0,r27,61,3 1048 ;; 1049} 1050{ .mii 1051 ld8 r27=[r27] // pte page 1052 shl r28=r28,5 1053 dep r26=0,r26,0,2 1054 ;; 1055} 1056{ .mmi 1057 add r27=r28,r27 1058 ;; 1059 mov cr.ifa=r30 1060 dep r27=0,r27,61,3 1061 ;; 1062} 1063{ .mmi 1064 ld8 r28=[r27] // pte 1065 ;; 1066 mov cr.itir=r26 1067 or r28=PTE_DIRTY+PTE_ACCESSED,r28 1068 ;; 1069} 1070{ .mmi 1071 st8 [r27]=r28 1072 ;; 1073 addl r26=NTLBRT_SAVE,r0 1074 addl r27=NTLBRT_RESTORE,r0 1075} 1076{ .mmi 1077 itc.d r28 1078 ;; 1079 ssm psr.dt 1080 cmp.eq p12,p0=r29,r26 1081 ;; 1082} 1083{ .mib 1084 srlz.d 1085 cmp.eq p13,p0=r29,r27 1086(p12) br.cond.sptk.few exception_save_restart 1087 ;; 1088} 1089{ .mib 1090 nop 0 1091 nop 0 1092(p13) br.cond.sptk.few exception_restore_restart 1093 ;; 1094} 1095{ .mlx 1096 mov r26=ar.bsp 1097 movl r29=kstack 1098 ;; 1099} 1100{ .mlx 1101 mov r28=sp 1102 movl r27=kstack_top 1103 ;; 1104} 1105{ .mmi 1106 add sp=-16,r27 1107 ;; 1108 mov r27=ar.bspstore 1109 nop 0 1110 ;; 1111} 1112 mov ar.rsc=0 1113 dep r29=r27,r29,0,9 1114 ;; 1115 mov ar.bspstore=r29 1116 ;; 1117 CALL(trap, 5, r30) 1118IVT_END(Data_Nested_TLB) 1119 1120IVT_ENTRY(Instruction_Key_Miss, 0x1800) 1121 CALL(trap, 6, cr.ifa) 1122IVT_END(Instruction_Key_Miss) 1123 1124IVT_ENTRY(Data_Key_Miss, 0x1c00) 1125 CALL(trap, 7, cr.ifa) 1126IVT_END(Data_Key_Miss) 1127 1128IVT_ENTRY(Dirty_Bit, 0x2000) 1129 mov r16=cr.ifa 1130 mov r17=pr 1131 ;; 1132 thash r18=r16 1133 ;; 1134 ttag r19=r16 1135 add r20=24,r18 // collision chain 1136 ;; 1137 ld8 r20=[r20] // bucket head 1138 ;; 1139 rsm psr.dt // turn off data translations 1140 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1141 ;; 1142 srlz.d // serialize 1143 ld8 r20=[r20] // first entry 1144 ;; 11451: cmp.eq p15,p0=r0,r20 // done? 1146(p15) br.cond.spnt.few 9f // bail if done 1147 ;; 1148 add r21=16,r20 // tag location 1149 ;; 1150 ld8 r21=[r21] // read tag 1151 ;; 1152 cmp.ne p15,p0=r21,r19 // compare tags 1153(p15) br.cond.sptk.few 2f // if not, read next in chain 1154 ;; 1155 ld8 r21=[r20] // read pte 1156 mov r22=PTE_DIRTY+PTE_ACCESSED 1157 ;; 1158 or r21=r22,r21 // set dirty & access bit 1159 ;; 1160 st8 [r20]=r21,8 // store back 1161 ;; 1162 ld8 r22=[r20] // read rest of pte 1163 ;; 1164 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1165 ;; 1166 add r20=16,r18 // address of tag 1167 ;; 1168 ld8.acq r23=[r20] // read old tag 1169 ;; 1170 dep r23=-1,r23,63,1 // set ti bit 1171 ;; 1172 st8.rel [r20]=r23 // store old tag + ti 1173 ;; 1174 mf // make sure everyone sees 1175 ;; 1176 st8 [r18]=r21,8 // store pte 1177 ;; 1178 st8 [r18]=r22,8 1179 ;; 1180 st8.rel [r18]=r19 // store new tag 1181 ;; 1182 itc.d r21 // and place in TLB 1183 ssm psr.dt 1184 ;; 1185 srlz.d 1186 mov pr=r17,0x1ffff // restore predicates 1187 rfi 1188 ;; 11892: add r20=24,r20 // next in chain 1190 ;; 1191 ld8 r20=[r20] // read chain 1192 br.sptk 1b // loop 1193 ;; 11949: ssm psr.dt 1195 mov pr=r17,0x1ffff // restore predicates 1196 ;; 1197 srlz.d 1198 ;; 1199 CALL(trap, 8, cr.ifa) // die horribly 1200IVT_END(Dirty_Bit) 1201 1202IVT_ENTRY(Instruction_Access_Bit, 0x2400) 1203 mov r16=cr.ifa 1204 mov r17=pr 1205 ;; 1206 thash r18=r16 1207 ;; 1208 ttag r19=r16 1209 add r20=24,r18 // collision chain 1210 ;; 1211 ld8 r20=[r20] // bucket head 1212 ;; 1213 rsm psr.dt // turn off data translations 1214 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1215 ;; 1216 srlz.d // serialize 1217 ld8 r20=[r20] // first entry 1218 ;; 12191: cmp.eq p15,p0=r0,r20 // done? 1220(p15) br.cond.spnt.few 9f // bail if done 1221 ;; 1222 add r21=16,r20 // tag location 1223 ;; 1224 ld8 r21=[r21] // read tag 1225 ;; 1226 cmp.ne p15,p0=r21,r19 // compare tags 1227(p15) br.cond.sptk.few 2f // if not, read next in chain 1228 ;; 1229 ld8 r21=[r20] // read pte 1230 mov r22=PTE_ACCESSED 1231 ;; 1232 or r21=r22,r21 // set accessed bit 1233 ;; 1234 st8 [r20]=r21,8 // store back 1235 ;; 1236 ld8 r22=[r20] // read rest of pte 1237 ;; 1238 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1239 ;; 1240 add r20=16,r18 // address of tag 1241 ;; 1242 ld8.acq r23=[r20] // read old tag 1243 ;; 1244 dep r23=-1,r23,63,1 // set ti bit 1245 ;; 1246 st8.rel [r20]=r23 // store old tag + ti 1247 ;; 1248 mf // make sure everyone sees 1249 ;; 1250 st8 [r18]=r21,8 // store pte 1251 ;; 1252 st8 [r18]=r22,8 1253 ;; 1254 st8.rel [r18]=r19 // store new tag 1255 ;; 1256 itc.i r21 // and place in TLB 1257 ssm psr.dt 1258 ;; 1259 srlz.d 1260 mov pr=r17,0x1ffff // restore predicates 1261 rfi // walker will retry the access 1262 ;; 12632: add r20=24,r20 // next in chain 1264 ;; 1265 ld8 r20=[r20] // read chain 1266 br.sptk 1b // loop 1267 ;; 12689: ssm psr.dt 1269 mov pr=r17,0x1ffff // restore predicates 1270 ;; 1271 srlz.d 1272 ;; 1273 CALL(trap, 9, cr.ifa) 1274IVT_END(Instruction_Access_Bit) 1275 1276IVT_ENTRY(Data_Access_Bit, 0x2800) 1277 mov r16=cr.ifa 1278 mov r17=pr 1279 ;; 1280 thash r18=r16 1281 ;; 1282 ttag r19=r16 1283 add r20=24,r18 // collision chain 1284 ;; 1285 ld8 r20=[r20] // bucket head 1286 ;; 1287 rsm psr.dt // turn off data translations 1288 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1289 ;; 1290 srlz.d // serialize 1291 ld8 r20=[r20] // first entry 1292 ;; 12931: cmp.eq p15,p0=r0,r20 // done? 1294(p15) br.cond.spnt.few 9f // bail if done 1295 ;; 1296 add r21=16,r20 // tag location 1297 ;; 1298 ld8 r21=[r21] // read tag 1299 ;; 1300 cmp.ne p15,p0=r21,r19 // compare tags 1301(p15) br.cond.sptk.few 2f // if not, read next in chain 1302 ;; 1303 ld8 r21=[r20] // read pte 1304 mov r22=PTE_ACCESSED 1305 ;; 1306 or r21=r22,r21 // set accessed bit 1307 ;; 1308 st8 [r20]=r21,8 // store back 1309 ;; 1310 ld8 r22=[r20] // read rest of pte 1311 ;; 1312 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1313 ;; 1314 add r20=16,r18 // address of tag 1315 ;; 1316 ld8.acq r23=[r20] // read old tag 1317 ;; 1318 dep r23=-1,r23,63,1 // set ti bit 1319 ;; 1320 st8.rel [r20]=r23 // store old tag + ti 1321 ;; 1322 mf // make sure everyone sees 1323 ;; 1324 st8 [r18]=r21,8 // store pte 1325 ;; 1326 st8 [r18]=r22,8 1327 ;; 1328 st8.rel [r18]=r19 // store new tag 1329 ;; 1330 itc.d r21 // and place in TLB 1331 ssm psr.dt 1332 ;; 1333 srlz.d 1334 mov pr=r17,0x1ffff // restore predicates 1335 rfi // walker will retry the access 1336 ;; 13372: add r20=24,r20 // next in chain 1338 ;; 1339 ld8 r20=[r20] // read chain 1340 br.sptk 1b // loop 1341 ;; 13429: ssm psr.dt 1343 mov pr=r17,0x1ffff // restore predicates 1344 ;; 1345 srlz.d 1346 ;; 1347 CALL(trap, 10, cr.ifa) 1348IVT_END(Data_Access_Bit) 1349 1350IVT_ENTRY(Break_Instruction, 0x2c00) 1351{ .mib 1352 mov r17=cr.iim 1353 mov r16=ip 1354 br.sptk exception_save 1355 ;; 1356} 1357{ .mmi 1358 alloc r15=ar.pfs,0,0,2,0 1359 ;; 1360(p11) ssm psr.i 1361 mov out0=11 1362 ;; 1363} 1364{ .mmi 1365 flushrs 1366 ;; 1367(p11) srlz.d 1368 add out1=16,sp 1369} 1370{ .mib 1371 nop 0 1372 nop 0 1373 br.call.sptk rp=trap 1374 ;; 1375} 1376{ .mib 1377 nop 0 1378 nop 0 1379 br.sptk exception_restore 1380 ;; 1381} 1382IVT_END(Break_Instruction) 1383 1384IVT_ENTRY(External_Interrupt, 0x3000) 1385{ .mib 1386 mov r17=ar.itc // Put the ITC in the trapframe. 1387 mov r16=ip 1388 br.sptk exception_save 1389 ;; 1390} 1391{ .mmi 1392 alloc r15=ar.pfs,0,0,1,0 1393 nop 0 1394 nop 0 1395 ;; 1396} 1397{ .mib 1398 add out0=16,sp 1399 nop 0 1400 br.call.sptk rp=ia64_handle_intr 1401 ;; 1402} 1403{ .mib 1404 nop 0 1405 nop 0 1406 br.sptk exception_restore 1407 ;; 1408} 1409IVT_END(External_Interrupt) 1410 1411IVT_ENTRY(Reserved_3400, 0x3400) 1412 CALL(trap, 13, cr.ifa) 1413IVT_END(Reserved_3400) 1414 1415IVT_ENTRY(Reserved_3800, 0x3800) 1416 CALL(trap, 14, cr.ifa) 1417IVT_END(Reserved_3800) 1418 1419IVT_ENTRY(Reserved_3c00, 0x3c00) 1420 CALL(trap, 15, cr.ifa) 1421IVT_END(Reserved_3c00) 1422 1423IVT_ENTRY(Reserved_4000, 0x4000) 1424 CALL(trap, 16, cr.ifa) 1425IVT_END(Reserved_4000) 1426 1427IVT_ENTRY(Reserved_4400, 0x4400) 1428 CALL(trap, 17, cr.ifa) 1429IVT_END(Reserved_4400) 1430 1431IVT_ENTRY(Reserved_4800, 0x4800) 1432 CALL(trap, 18, cr.ifa) 1433IVT_END(Reserved_4800) 1434 1435IVT_ENTRY(Reserved_4c00, 0x4c00) 1436 CALL(trap, 19, cr.ifa) 1437IVT_END(Reserved_4c00) 1438 1439IVT_ENTRY(Page_Not_Present, 0x5000) 1440 CALL(trap, 20, cr.ifa) 1441IVT_END(Page_Not_Present) 1442 1443IVT_ENTRY(Key_Permission, 0x5100) 1444 CALL(trap, 21, cr.ifa) 1445IVT_END(Key_Permission) 1446 1447IVT_ENTRY(Instruction_Access_Rights, 0x5200) 1448 CALL(trap, 22, cr.ifa) 1449IVT_END(Instruction_Access_Rights) 1450 1451IVT_ENTRY(Data_Access_Rights, 0x5300) 1452 CALL(trap, 23, cr.ifa) 1453IVT_END(Data_Access_Rights) 1454 1455IVT_ENTRY(General_Exception, 0x5400) 1456 CALL(trap, 24, cr.ifa) 1457IVT_END(General_Exception) 1458 1459IVT_ENTRY(Disabled_FP_Register, 0x5500) 1460 CALL(trap, 25, cr.ifa) 1461IVT_END(Disabled_FP_Register) 1462 1463IVT_ENTRY(NaT_Consumption, 0x5600) 1464 CALL(trap, 26, cr.ifa) 1465IVT_END(NaT_Consumption) 1466 1467IVT_ENTRY(Speculation, 0x5700) 1468 CALL(trap, 27, cr.iim) 1469IVT_END(Speculation) 1470 1471IVT_ENTRY(Reserved_5800, 0x5800) 1472 CALL(trap, 28, cr.ifa) 1473IVT_END(Reserved_5800) 1474 1475IVT_ENTRY(Debug, 0x5900) 1476 CALL(trap, 29, cr.ifa) 1477IVT_END(Debug) 1478 1479IVT_ENTRY(Unaligned_Reference, 0x5a00) 1480 CALL(trap, 30, cr.ifa) 1481IVT_END(Unaligned_Reference) 1482 1483IVT_ENTRY(Unsupported_Data_Reference, 0x5b00) 1484 CALL(trap, 31, cr.ifa) 1485IVT_END(Unsupported_Data_Reference) 1486 1487IVT_ENTRY(Floating_Point_Fault, 0x5c00) 1488 CALL(trap, 32, cr.ifa) 1489IVT_END(Floating_Point_Fault) 1490 1491IVT_ENTRY(Floating_Point_Trap, 0x5d00) 1492 CALL(trap, 33, cr.ifa) 1493IVT_END(Floating_Point_Trap) 1494 1495IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00) 1496 CALL(trap, 34, cr.ifa) 1497IVT_END(Lower_Privilege_Transfer_Trap) 1498 1499IVT_ENTRY(Taken_Branch_Trap, 0x5f00) 1500 CALL(trap, 35, cr.ifa) 1501IVT_END(Taken_Branch_Trap) 1502 1503IVT_ENTRY(Single_Step_Trap, 0x6000) 1504 CALL(trap, 36, cr.ifa) 1505IVT_END(Single_Step_Trap) 1506 1507IVT_ENTRY(Reserved_6100, 0x6100) 1508 CALL(trap, 37, cr.ifa) 1509IVT_END(Reserved_6100) 1510 1511IVT_ENTRY(Reserved_6200, 0x6200) 1512 CALL(trap, 38, cr.ifa) 1513IVT_END(Reserved_6200) 1514 1515IVT_ENTRY(Reserved_6300, 0x6300) 1516 CALL(trap, 39, cr.ifa) 1517IVT_END(Reserved_6300) 1518 1519IVT_ENTRY(Reserved_6400, 0x6400) 1520 CALL(trap, 40, cr.ifa) 1521IVT_END(Reserved_6400) 1522 1523IVT_ENTRY(Reserved_6500, 0x6500) 1524 CALL(trap, 41, cr.ifa) 1525IVT_END(Reserved_6500) 1526 1527IVT_ENTRY(Reserved_6600, 0x6600) 1528 CALL(trap, 42, cr.ifa) 1529IVT_END(Reserved_6600) 1530 1531IVT_ENTRY(Reserved_6700, 0x6700) 1532 CALL(trap, 43, cr.ifa) 1533IVT_END(Reserved_6700) 1534 1535IVT_ENTRY(Reserved_6800, 0x6800) 1536 CALL(trap, 44, cr.ifa) 1537IVT_END(Reserved_6800) 1538 1539IVT_ENTRY(IA_32_Exception, 0x6900) 1540 CALL(IA32_TRAP, 45, cr.ifa) 1541IVT_END(IA_32_Exception) 1542 1543IVT_ENTRY(IA_32_Intercept, 0x6a00) 1544 CALL(IA32_TRAP, 46, cr.iim) 1545IVT_END(IA_32_Intercept) 1546 1547IVT_ENTRY(IA_32_Interrupt, 0x6b00) 1548 CALL(IA32_TRAP, 47, cr.ifa) 1549IVT_END(IA_32_Interrupt) 1550 1551IVT_ENTRY(Reserved_6c00, 0x6c00) 1552 CALL(trap, 48, cr.ifa) 1553IVT_END(Reserved_6c00) 1554 1555IVT_ENTRY(Reserved_6d00, 0x6d00) 1556 CALL(trap, 49, cr.ifa) 1557IVT_END(Reserved_6d00) 1558 1559IVT_ENTRY(Reserved_6e00, 0x6e00) 1560 CALL(trap, 50, cr.ifa) 1561IVT_END(Reserved_6e00) 1562 1563IVT_ENTRY(Reserved_6f00, 0x6f00) 1564 CALL(trap, 51, cr.ifa) 1565IVT_END(Reserved_6f00) 1566 1567IVT_ENTRY(Reserved_7000, 0x7000) 1568 CALL(trap, 52, cr.ifa) 1569IVT_END(Reserved_7000) 1570 1571IVT_ENTRY(Reserved_7100, 0x7100) 1572 CALL(trap, 53, cr.ifa) 1573IVT_END(Reserved_7100) 1574 1575IVT_ENTRY(Reserved_7200, 0x7200) 1576 CALL(trap, 54, cr.ifa) 1577IVT_END(Reserved_7200) 1578 1579IVT_ENTRY(Reserved_7300, 0x7300) 1580 CALL(trap, 55, cr.ifa) 1581IVT_END(Reserved_7300) 1582 1583IVT_ENTRY(Reserved_7400, 0x7400) 1584 CALL(trap, 56, cr.ifa) 1585IVT_END(Reserved_7400) 1586 1587IVT_ENTRY(Reserved_7500, 0x7500) 1588 CALL(trap, 57, cr.ifa) 1589IVT_END(Reserved_7500) 1590 1591IVT_ENTRY(Reserved_7600, 0x7600) 1592 CALL(trap, 58, cr.ifa) 1593IVT_END(Reserved_7600) 1594 1595IVT_ENTRY(Reserved_7700, 0x7700) 1596 CALL(trap, 59, cr.ifa) 1597IVT_END(Reserved_7700) 1598 1599IVT_ENTRY(Reserved_7800, 0x7800) 1600 CALL(trap, 60, cr.ifa) 1601IVT_END(Reserved_7800) 1602 1603IVT_ENTRY(Reserved_7900, 0x7900) 1604 CALL(trap, 61, cr.ifa) 1605IVT_END(Reserved_7900) 1606 1607IVT_ENTRY(Reserved_7a00, 0x7a00) 1608 CALL(trap, 62, cr.ifa) 1609IVT_END(Reserved_7a00) 1610 1611IVT_ENTRY(Reserved_7b00, 0x7b00) 1612 CALL(trap, 63, cr.ifa) 1613IVT_END(Reserved_7b00) 1614 1615IVT_ENTRY(Reserved_7c00, 0x7c00) 1616 CALL(trap, 64, cr.ifa) 1617IVT_END(Reserved_7c00) 1618 1619IVT_ENTRY(Reserved_7d00, 0x7d00) 1620 CALL(trap, 65, cr.ifa) 1621IVT_END(Reserved_7d00) 1622 1623IVT_ENTRY(Reserved_7e00, 0x7e00) 1624 CALL(trap, 66, cr.ifa) 1625IVT_END(Reserved_7e00) 1626 1627IVT_ENTRY(Reserved_7f00, 0x7f00) 1628 CALL(trap, 67, cr.ifa) 1629IVT_END(Reserved_7f00) 1630