exception.S revision 199566
172847Sgshapiro/*- 250472Speter * Copyright (c) 2003,2004 Marcel Moolenaar 372847Sgshapiro * Copyright (c) 2000 Doug Rabson 472847Sgshapiro * All rights reserved. 572847Sgshapiro * 672847Sgshapiro * Redistribution and use in source and binary forms, with or without 772847Sgshapiro * modification, are permitted provided that the following conditions 872847Sgshapiro * are met: 972847Sgshapiro * 1. Redistributions of source code must retain the above copyright 1072847Sgshapiro * notice, this list of conditions and the following disclaimer. 1172847Sgshapiro * 2. Redistributions in binary form must reproduce the above copyright 1272847Sgshapiro * notice, this list of conditions and the following disclaimer in the 1372847Sgshapiro * documentation and/or other materials provided with the distribution. 1472847Sgshapiro * 1572847Sgshapiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1672847Sgshapiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1772847Sgshapiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1872847Sgshapiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1972847Sgshapiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2072847Sgshapiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2172847Sgshapiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2272847Sgshapiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2372847Sgshapiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2472847Sgshapiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2572847Sgshapiro * SUCH DAMAGE. 2672847Sgshapiro */ 2772847Sgshapiro 2872847Sgshapiro#include <machine/asm.h> 2972847Sgshapiro__FBSDID("$FreeBSD: head/sys/ia64/ia64/exception.S 199566 2009-11-20 03:14:54Z marcel $"); 3072847Sgshapiro 3172847Sgshapiro#include "opt_kstack_pages.h" 3272847Sgshapiro#include "opt_xtrace.h" 3372847Sgshapiro 3472847Sgshapiro#include <machine/pte.h> 3572847Sgshapiro#include <assym.s> 3672847Sgshapiro 3772847Sgshapiro/* 3872847Sgshapiro * Nested TLB restart tokens. These are used by the 3939146Sbrian * nested TLB handler for jumping back to the code 4072847Sgshapiro * where the nested TLB was caused. 4173209Sgshapiro */ 4230581Sjmb#define NTLBRT_SAVE 0x12c12c 4372847Sgshapiro#define NTLBRT_RESTORE 0x12c12d 4457947Srwatson 4572847Sgshapiro/* 4672847Sgshapiro * ar.k7 = kernel memory stack 4772847Sgshapiro * ar.k6 = kernel register stack 4872847Sgshapiro * ar.k5 = EPC gateway page 4972847Sgshapiro * ar.k4 = PCPU data 5072847Sgshapiro */ 5172847Sgshapiro 5272847Sgshapiro#ifdef EXCEPTION_TRACING 5372847Sgshapiro 5457947Srwatson .data 5572847Sgshapiro .global xtrace, xhead 5672847Sgshapiroxtrace: .space 1024*5*8 5772847Sgshapiroxhead: data8 xtrace 5872847Sgshapiro 5957947Srwatson#define XTRACE(offset) \ 6072847Sgshapiro{ .mmi ; \ 6172847Sgshapiro mov r24=ar.itc ; \ 6272847Sgshapiro mov r25=cr.iip ; \ 6372847Sgshapiro mov r27=offset ; \ 6472847Sgshapiro} ; \ 6572847Sgshapiro{ .mlx ; \ 6672847Sgshapiro mov r28=cr.ifa ; \ 6764567Sgshapiro movl r29=xhead ;; \ 6872847Sgshapiro} ; \ 6972847Sgshapiro{ .mmi ; \ 7057947Srwatson ld8 r29=[r29] ;; \ 7172847Sgshapiro st8 [r29]=r24,8 ; \ 7272847Sgshapiro nop 0 ;; \ 7372847Sgshapiro} ; \ 7472847Sgshapiro{ .mmi ; \ 7572847Sgshapiro st8 [r29]=r27,8 ;; \ 7672847Sgshapiro mov r24=cr.isr ; \ 7772847Sgshapiro add r27=8,r29 ;; \ 7872847Sgshapiro} ; \ 7972847Sgshapiro{ .mmi ; \ 8072847Sgshapiro st8 [r29]=r25,16 ;; \ 8157947Srwatson st8 [r27]=r28,16 ; \ 8272847Sgshapiro mov r25=pr ;; \ 8372847Sgshapiro} ; \ 8472847Sgshapiro{ .mlx ; \ 8572847Sgshapiro st8 [r29]=r24 ; \ 8672847Sgshapiro movl r28=xhead ;; \ 8757947Srwatson} ; \ 8872847Sgshapiro{ .mii ; \ 8972847Sgshapiro cmp.eq p15,p0=r27,r28 ; \ 9072847Sgshapiro addl r29=1024*5*8,r0 ;; \ 9172847Sgshapiro(p15) sub r27=r28,r29 ;; \ 9272847Sgshapiro} ; \ 9372847Sgshapiro{ .mib ; \ 9472847Sgshapiro st8 [r28]=r27 ; \ 9572847Sgshapiro mov pr=r25,0x1ffff ; \ 9672847Sgshapiro nop 0 ;; \ 9772847Sgshapiro} 9872847Sgshapiro 9972847Sgshapiro#else 10072847Sgshapiro 10172847Sgshapiro#define XTRACE(offset) 10272847Sgshapiro 10372847Sgshapiro#endif 10472847Sgshapiro 10572847Sgshapiro .text 10672847Sgshapiro 10772847Sgshapiro/* 10872847Sgshapiro * exception_save: save interrupted state 10972847Sgshapiro * 11072847Sgshapiro * Arguments: 11172847Sgshapiro * r16 address of bundle that contains the branch. The 11272847Sgshapiro * return address will be the next bundle. 11372847Sgshapiro * r17 the value to save as ifa in the trapframe. This 11472847Sgshapiro * normally is cr.ifa, but some interruptions set 11572847Sgshapiro * set cr.iim and not cr.ifa. 11672847Sgshapiro * 11772847Sgshapiro * Returns: 11872847Sgshapiro * p15 interrupted from user stack 11972847Sgshapiro * p14 interrupted from kernel stack 12072847Sgshapiro * p13 interrupted from user backing store 12172847Sgshapiro * p12 interrupted from kernel backing store 12272847Sgshapiro * p11 interrupts were enabled 12372847Sgshapiro * p10 interrupts were disabled 12472847Sgshapiro */ 12572847SgshapiroENTRY_NOPROFILE(exception_save, 0) 12672847Sgshapiro{ .mii 12772847Sgshapiro mov r20=ar.unat 12857947Srwatson extr.u r31=sp,61,3 12972847Sgshapiro mov r18=pr 13072847Sgshapiro ;; 13172847Sgshapiro} 13273209Sgshapiro{ .mmi 13372847Sgshapiro cmp.le p14,p15=5,r31 13472847Sgshapiro ;; 13572847Sgshapiro(p15) mov r23=ar.k7 // kernel memory stack 13672847Sgshapiro(p14) mov r23=sp 13772847Sgshapiro ;; 13873209Sgshapiro} 13973209Sgshapiro{ .mii 14072847Sgshapiro mov r21=ar.rsc 14172847Sgshapiro add r30=-SIZEOF_TRAPFRAME,r23 14272847Sgshapiro ;; 14372847Sgshapiro dep r30=0,r30,0,10 14472847Sgshapiro ;; 14572847Sgshapiro} 14672847Sgshapiro{ .mmi 14772847Sgshapiro mov ar.rsc=0 14872847Sgshapiro sub r19=r23,r30 14972847Sgshapiro add r31=8,r30 15072847Sgshapiro ;; 15172847Sgshapiro} 15272847Sgshapiro{ .mib 15372847Sgshapiro mov r22=cr.iip 154 addl r29=NTLBRT_SAVE,r0 // 22-bit restart token. 155 nop 0 156 ;; 157} 158 159 /* 160 * We have a 1KB aligned trapframe, pointed to by sp. If we write 161 * to the trapframe, we may trigger a data nested TLB fault. By 162 * aligning the trapframe on a 1KB boundary, we guarantee that if 163 * we get a data nested TLB fault, it will be on the very first 164 * write. Since the data nested TLB fault does not preserve any 165 * state, we have to be careful what we clobber. Consequently, we 166 * have to be careful what we use here. Below a list of registers 167 * that are currently alive: 168 * r16,r17=arguments 169 * r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS 170 * r29=restart point 171 * r30,r31=trapframe pointers 172 * p14,p15=memory stack switch 173 */ 174exception_save_restart: 175{ .mmi 176 st8 [r30]=r19,16 // length 177 st8 [r31]=r0,16 // flags 178 add r19=16,r19 179 ;; 180} 181{ .mmi 182 st8.spill [r30]=sp,16 // sp 183 st8 [r31]=r20,16 // unat 184 sub sp=r23,r19 185 ;; 186} 187{ .mmi 188 mov r19=ar.rnat 189 mov r20=ar.bspstore 190 mov r23=rp 191 ;; 192} 193 // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp 194{ .mmi 195 st8 [r30]=r23,16 // rp 196 st8 [r31]=r18,16 // pr 197 mov r24=ar.pfs 198 ;; 199} 200{ .mmb 201 st8 [r30]=r24,16 // pfs 202 st8 [r31]=r20,16 // bspstore 203 cover 204 ;; 205} 206{ .mmi 207 mov r18=ar.fpsr 208 mov r23=cr.ipsr 209 extr.u r24=r20,61,3 210 ;; 211} 212 // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr 213{ .mmi 214 st8 [r30]=r19,16 // rnat 215 st8 [r31]=r0,16 // __spare 216 cmp.le p12,p13=5,r24 217 ;; 218} 219{ .mmi 220 st8.spill [r30]=r13,16 // tp 221 st8 [r31]=r21,16 // rsc 222 tbit.nz p11,p10=r23,14 // p11=interrupts enabled 223 ;; 224} 225{ .mmi 226(p13) mov r21=ar.k6 // kernel register stack 227 ;; 228 st8 [r30]=r18,16 // fpsr 229(p13) dep r20=r20,r21,0,9 // align dirty registers 230 ;; 231} 232 // r20=bspstore, r22=iip, r23=ipsr 233{ .mmi 234 st8 [r31]=r23,16 // psr 235(p13) mov ar.bspstore=r20 236 nop 0 237 ;; 238} 239{ .mmi 240 mov r18=ar.bsp 241 ;; 242 mov r19=cr.ifs 243 sub r18=r18,r20 244 ;; 245} 246{ .mmi 247 st8.spill [r30]=gp,16 // gp 248 st8 [r31]=r18,16 // ndirty 249 nop 0 250 ;; 251} 252 // r19=ifs, r22=iip 253{ .mmi 254 st8 [r30]=r19,16 // cfm 255 st8 [r31]=r22,16 // iip 256 nop 0 257 ;; 258} 259{ .mmi 260 st8 [r30]=r17 // ifa 261 mov r18=cr.isr 262 add r29=16,r30 263 ;; 264} 265{ .mmi 266 st8 [r31]=r18 // isr 267 add r30=8,r29 268 add r31=16,r29 269 ;; 270} 271{ .mmi 272 .mem.offset 0,0 273 st8.spill [r30]=r2,16 // r2 274 .mem.offset 8,0 275 st8.spill [r31]=r3,16 // r3 276 add r2=9*8,r29 277 ;; 278} 279{ .mmi 280 .mem.offset 0,0 281 st8.spill [r30]=r8,16 // r8 282 .mem.offset 8,0 283 st8.spill [r31]=r9,16 // r9 284 add r3=8,r2 285 ;; 286} 287{ .mmi 288 .mem.offset 0,0 289 st8.spill [r30]=r10,16 // r10 290 .mem.offset 8,0 291 st8.spill [r31]=r11,16 // r11 292 add r8=16,r16 293 ;; 294} 295{ .mmi 296 .mem.offset 0,0 297 st8.spill [r30]=r14 // r14 298 .mem.offset 8,0 299 st8.spill [r31]=r15 // r15 300 mov r9=r29 301} 302{ .mmb 303 mov r10=ar.csd 304 mov r11=ar.ssd 305 bsw.1 306 ;; 307} 308{ .mmi 309 .mem.offset 0,0 310 st8.spill [r2]=r16,16 // r16 311 .mem.offset 8,0 312 st8.spill [r3]=r17,16 // r17 313 mov r14=b6 314 ;; 315} 316{ .mmi 317 .mem.offset 0,0 318 st8.spill [r2]=r18,16 // r18 319 .mem.offset 8,0 320 st8.spill [r3]=r19,16 // r19 321 mov r15=b7 322 ;; 323} 324{ .mmi 325 .mem.offset 0,0 326 st8.spill [r2]=r20,16 // r20 327 .mem.offset 8,0 328 st8.spill [r3]=r21,16 // r21 329 mov b7=r8 330 ;; 331} 332{ .mmi 333 .mem.offset 0,0 334 st8.spill [r2]=r22,16 // r22 335 .mem.offset 8,0 336 st8.spill [r3]=r23,16 // r23 337 ;; 338} 339 340 .mem.offset 0,0 341 st8.spill [r2]=r24,16 // r24 342 .mem.offset 8,0 343 st8.spill [r3]=r25,16 // r25 344 ;; 345 .mem.offset 0,0 346 st8.spill [r2]=r26,16 // r26 347 .mem.offset 8,0 348 st8.spill [r3]=r27,16 // r27 349 ;; 350 .mem.offset 0,0 351 st8.spill [r2]=r28,16 // r28 352 .mem.offset 8,0 353 st8.spill [r3]=r29,16 // r29 354 ;; 355 .mem.offset 0,0 356 st8.spill [r2]=r30,16 // r30 357 .mem.offset 8,0 358 st8.spill [r3]=r31,16 // r31 359 ;; 360 361{ .mmi 362 st8 [r2]=r14,16 // b6 363 mov r17=ar.unat 364 nop 0 365 ;; 366} 367{ .mmi 368 st8 [r3]=r15,16 // b7 369 mov r16=ar.ccv 370 nop 0 371 ;; 372} 373{ .mmi 374 st8 [r2]=r16,16 // ccv 375 st8 [r3]=r10,16 // csd 376 nop 0 377 ;; 378} 379{ .mmi 380 st8 [r2]=r11,24 // ssd 381 st8 [r9]=r17 382 nop 0 383 ;; 384} 385 386 stf.spill [r3]=f6,32 // f6 387 stf.spill [r2]=f7,32 // f7 388 ;; 389 stf.spill [r3]=f8,32 // f8 390 stf.spill [r2]=f9,32 // f9 391 ;; 392 stf.spill [r3]=f10,32 // f10 393 stf.spill [r2]=f11,32 // f11 394 ;; 395 stf.spill [r3]=f12,32 // f12 396 stf.spill [r2]=f13,32 // f13 397 ;; 398 stf.spill [r3]=f14 // f14 399 stf.spill [r2]=f15 // f15 400 ;; 401{ .mmi 402 mov ar.rsc=3 403 mov r13=ar.k4 404 nop 0 405 ;; 406} 407{ .mlx 408 ssm psr.ic|psr.dfh 409 movl gp=__gp 410 ;; 411} 412{ .mfb 413 srlz.d 414 nop 0 415 br.sptk b7 416 ;; 417} 418END(exception_save) 419 420/* 421 * exception_restore: restore interrupted state 422 * 423 * Arguments: 424 * sp+16 trapframe pointer 425 */ 426ENTRY_NOPROFILE(exception_restore, 0) 427{ .mmi 428 rsm psr.i 429 add r3=SIZEOF_TRAPFRAME-16,sp 430 add r2=SIZEOF_TRAPFRAME,sp 431 ;; 432} 433{ .mmi 434 srlz.d 435 add r8=SIZEOF_SPECIAL+32,sp 436 nop 0 437 ;; 438} 439 // The next load can trap. Let it be... 440 ldf.fill f15=[r2],-32 // f15 441 ldf.fill f14=[r3],-32 // f14 442 add sp=16,sp 443 ;; 444 ldf.fill f13=[r2],-32 // f13 445 ldf.fill f12=[r3],-32 // f12 446 ;; 447 ldf.fill f11=[r2],-32 // f11 448 ldf.fill f10=[r3],-32 // f10 449 ;; 450 ldf.fill f9=[r2],-32 // f9 451 ldf.fill f8=[r3],-32 // f8 452 ;; 453 ldf.fill f7=[r2],-24 // f7 454 ldf.fill f6=[r3],-16 // f6 455 ;; 456 457{ .mmi 458 ld8 r8=[r8] // unat (after) 459 ;; 460 mov ar.unat=r8 461 nop 0 462 ;; 463} 464 465 ld8 r10=[r2],-16 // ssd 466 ld8 r11=[r3],-16 // csd 467 ;; 468 mov ar.ssd=r10 469 mov ar.csd=r11 470 471 ld8 r14=[r2],-16 // ccv 472 ld8 r15=[r3],-16 // b7 473 ;; 474 475{ .mmi 476 mov ar.ccv=r14 477 ld8 r8=[r2],-16 // b6 478 mov b7=r15 479 ;; 480} 481{ .mmi 482 ld8.fill r31=[r3],-16 // r31 483 ld8.fill r30=[r2],-16 // r30 484 mov b6=r8 485 ;; 486} 487 488 ld8.fill r29=[r3],-16 // r29 489 ld8.fill r28=[r2],-16 // r28 490 ;; 491 ld8.fill r27=[r3],-16 // r27 492 ld8.fill r26=[r2],-16 // r26 493 ;; 494 ld8.fill r25=[r3],-16 // r25 495 ld8.fill r24=[r2],-16 // r24 496 ;; 497 ld8.fill r23=[r3],-16 // r23 498 ld8.fill r22=[r2],-16 // r22 499 ;; 500 ld8.fill r21=[r3],-16 // r21 501 ld8.fill r20=[r2],-16 // r20 502 ;; 503 ld8.fill r19=[r3],-16 // r19 504 ld8.fill r18=[r2],-16 // r18 505 ;; 506 507{ .mmb 508 ld8.fill r17=[r3],-16 // r17 509 ld8.fill r16=[r2],-16 // r16 510 bsw.0 511 ;; 512} 513{ .mmi 514 ld8.fill r15=[r3],-16 // r15 515 ld8.fill r14=[r2],-16 // r14 516 add r31=16,sp 517 ;; 518} 519{ .mmi 520 ld8 r16=[sp] // tf_length 521 ld8.fill r11=[r3],-16 // r11 522 add r30=24,sp 523 ;; 524} 525{ .mmi 526 ld8.fill r10=[r2],-16 // r10 527 ld8.fill r9=[r3],-16 // r9 528 add r16=r16,sp // ar.k7 529 ;; 530} 531{ .mmi 532 ld8.fill r8=[r2],-16 // r8 533 ld8.fill r3=[r3] // r3 534 ;; 535} 536 // We want nested TLB faults from here on... 537 rsm psr.ic|psr.i 538 ld8.fill r2=[r2] // r2 539 nop 0 540 ;; 541 srlz.d 542 ld8.fill sp=[r31],16 // sp 543 nop 0 544 ;; 545 546 ld8 r17=[r30],16 // unat 547 ld8 r29=[r31],16 // rp 548 ;; 549 ld8 r18=[r30],16 // pr 550 ld8 r28=[r31],16 // pfs 551 mov rp=r29 552 ;; 553 ld8 r20=[r30],24 // bspstore 554 ld8 r21=[r31],24 // rnat 555 mov ar.pfs=r28 556 ;; 557 ld8.fill r26=[r30],16 // tp 558 ld8 r22=[r31],16 // rsc 559 ;; 560{ .mmi 561 ld8 r23=[r30],16 // fpsr 562 ld8 r24=[r31],16 // psr 563 extr.u r28=r20,61,3 564 ;; 565} 566{ .mmi 567 ld8.fill r1=[r30],16 // gp 568 ld8 r27=[r31],16 // ndirty 569 cmp.le p14,p15=5,r28 570 ;; 571} 572{ .mmb 573 ld8 r25=[r30] // cfm 574 ld8 r19=[r31] // ip 575 nop 0 576 ;; 577} 578{ .mii 579 // Switch register stack 580 alloc r30=ar.pfs,0,0,0,0 // discard current frame 581 shl r31=r27,16 // value for ar.rsc 582(p15) mov r13=r26 583 ;; 584} 585 // The loadrs can fault if the backing store is not currently 586 // mapped. We assured forward progress by getting everything we 587 // need from the trapframe so that we don't care if the CPU 588 // purges that translation when it needs to insert a new one for 589 // the backing store. 590{ .mmi 591 mov ar.rsc=r31 // setup for loadrs 592 mov ar.k7=r16 593 addl r29=NTLBRT_RESTORE,r0 // 22-bit restart token 594 ;; 595} 596exception_restore_restart: 597{ .mmi 598 mov r30=ar.bspstore 599 ;; 600 loadrs // load user regs 601 nop 0 602 ;; 603} 604{ .mmi 605 mov r31=ar.bspstore 606 ;; 607 mov ar.bspstore=r20 608 dep r31=0,r31,0,13 // 8KB aligned 609 ;; 610} 611{ .mmb 612 mov ar.k6=r31 613 mov ar.rnat=r21 614 nop 0 615 ;; 616} 617{ .mmb 618 mov ar.unat=r17 619 mov cr.iip=r19 620 nop 0 621} 622{ .mmi 623 mov cr.ipsr=r24 624 mov cr.ifs=r25 625 mov pr=r18,0x1ffff 626 ;; 627} 628{ .mmb 629 mov ar.rsc=r22 630 mov ar.fpsr=r23 631 rfi 632 ;; 633} 634END(exception_restore) 635 636/* 637 * Call exception_save_regs to preserve the interrupted state in a 638 * trapframe. Note that we don't use a call instruction because we 639 * must be careful not to lose track of the RSE state. We then call 640 * trap() with the value of _n_ as an argument to handle the 641 * exception. We arrange for trap() to return to exception_restore 642 * which will restore the interrupted state before executing an rfi to 643 * resume it. 644 */ 645#define CALL(_func_, _n_, _ifa_) \ 646{ .mib ; \ 647 mov r17=_ifa_ ; \ 648 mov r16=ip ; \ 649 br.sptk exception_save ;; \ 650} ; \ 651{ .mmi ; \ 652 alloc r15=ar.pfs,0,0,2,0 ;; \ 653(p11) ssm psr.i ; \ 654 mov out0=_n_ ;; \ 655} ; \ 656{ .mib ; \ 657(p11) srlz.d ; \ 658 add out1=16,sp ; \ 659 br.call.sptk rp=_func_ ;; \ 660} ; \ 661{ .mfb ; \ 662 nop 0 ; \ 663 nop 0 ; \ 664 br.sptk exception_restore ;; \ 665} 666 667#define IVT_ENTRY(name, offset) \ 668 .org ia64_vector_table + offset; \ 669 .global ivt_##name; \ 670 .proc ivt_##name; \ 671 .prologue; \ 672 .unwabi @svr4, 'I'; \ 673 .save rp, r0; \ 674 .body; \ 675ivt_##name: \ 676 XTRACE(offset) 677 678#define IVT_END(name) \ 679 .endp ivt_##name 680 681#ifdef COMPAT_IA32 682#define IA32_TRAP ia32_trap 683#else 684#define IA32_TRAP trap 685#endif 686 687/* 688 * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64 689 * bundles per vector and 48 slots with 16 bundles per vector. 690 */ 691 692 .section .text.ivt,"ax" 693 694 .align 32768 695 .global ia64_vector_table 696 .size ia64_vector_table, 32768 697ia64_vector_table: 698 699IVT_ENTRY(VHPT_Translation, 0x0000) 700 CALL(trap, 0, cr.ifa) 701IVT_END(VHPT_Translation) 702 703IVT_ENTRY(Instruction_TLB, 0x0400) 704 mov r16=cr.ifa 705 mov r17=pr 706 ;; 707 thash r18=r16 708 ttag r19=r16 709 ;; 710 add r21=16,r18 // tag 711 add r20=24,r18 // collision chain 712 ;; 713 ld8 r21=[r21] // check VHPT tag 714 ld8 r20=[r20] // bucket head 715 ;; 716 cmp.ne p15,p0=r21,r19 717(p15) br.dpnt.few 1f 718 ;; 719 ld8 r21=[r18] // read pte 720 ;; 721 itc.i r21 // insert pte 722 mov pr=r17,0x1ffff 723 ;; 724 rfi // done 725 ;; 7261: rsm psr.dt // turn off data translations 727 dep r20=0,r20,61,3 // convert vhpt ptr to physical 728 ;; 729 srlz.d // serialize 730 ld8 r20=[r20] // first entry 731 ;; 7322: cmp.eq p15,p0=r0,r20 // done? 733(p15) br.cond.spnt.few 9f // bail if done 734 ;; 735 add r21=16,r20 // tag location 736 ;; 737 ld8 r21=[r21] // read tag 738 ;; 739 cmp.ne p15,p0=r21,r19 // compare tags 740(p15) br.cond.sptk.few 3f // if not, read next in chain 741 ;; 742 ld8 r21=[r20] // read pte 743 mov r22=PTE_ACCESSED 744 ;; 745 or r21=r21,r22 746 ;; 747 st8 [r20]=r21,8 748 ;; 749 ld8 r22=[r20] // read rest of pte 750 ;; 751 dep r18=0,r18,61,3 // convert vhpt ptr to physical 752 ;; 753 add r20=16,r18 // address of tag 754 ;; 755 ld8.acq r23=[r20] // read old tag 756 ;; 757 dep r23=-1,r23,63,1 // set ti bit 758 ;; 759 st8.rel [r20]=r23 // store old tag + ti 760 ;; 761 mf // make sure everyone sees 762 ;; 763 st8 [r18]=r21,8 // store pte 764 ;; 765 st8 [r18]=r22,8 766 ;; 767 st8.rel [r18]=r19 // store new tag 768 ;; 769 itc.i r21 // and place in TLB 770 ssm psr.dt 771 ;; 772 srlz.d 773 mov pr=r17,0x1ffff // restore predicates 774 rfi 775 ;; 7763: add r20=24,r20 // next in chain 777 ;; 778 ld8 r20=[r20] // read chain 779 br.cond.sptk.few 2b // loop 780 ;; 7819: ssm psr.dt 782 mov pr=r17,0x1ffff // restore predicates 783 ;; 784 srlz.d 785 ;; 786 CALL(trap, 20, cr.ifa) // Page Not Present trap 787IVT_END(Instruction_TLB) 788 789IVT_ENTRY(Data_TLB, 0x0800) 790 mov r16=cr.ifa 791 mov r17=pr 792 ;; 793 thash r18=r16 794 ttag r19=r16 795 ;; 796 add r21=16,r18 // tag 797 add r20=24,r18 // collision chain 798 ;; 799 ld8 r21=[r21] // check VHPT tag 800 ld8 r20=[r20] // bucket head 801 ;; 802 cmp.ne p15,p0=r21,r19 803(p15) br.dpnt.few 1f 804 ;; 805 ld8 r21=[r18] // read pte 806 ;; 807 itc.d r21 // insert pte 808 mov pr=r17,0x1ffff 809 ;; 810 rfi // done 811 ;; 8121: rsm psr.dt // turn off data translations 813 dep r20=0,r20,61,3 // convert vhpt ptr to physical 814 ;; 815 srlz.d // serialize 816 ld8 r20=[r20] // first entry 817 ;; 8182: cmp.eq p15,p0=r0,r20 // done? 819(p15) br.cond.spnt.few 9f // bail if done 820 ;; 821 add r21=16,r20 // tag location 822 ;; 823 ld8 r21=[r21] // read tag 824 ;; 825 cmp.ne p15,p0=r21,r19 // compare tags 826(p15) br.cond.sptk.few 3f // if not, read next in chain 827 ;; 828 ld8 r21=[r20] // read pte 829 mov r22=PTE_ACCESSED 830 ;; 831 or r21=r21,r22 832 ;; 833 st8 [r20]=r21,8 834 ;; 835 ld8 r22=[r20] // read rest of pte 836 ;; 837 dep r18=0,r18,61,3 // convert vhpt ptr to physical 838 ;; 839 add r20=16,r18 // address of tag 840 ;; 841 ld8.acq r23=[r20] // read old tag 842 ;; 843 dep r23=-1,r23,63,1 // set ti bit 844 ;; 845 st8.rel [r20]=r23 // store old tag + ti 846 ;; 847 mf // make sure everyone sees 848 ;; 849 st8 [r18]=r21,8 // store pte 850 ;; 851 st8 [r18]=r22,8 852 ;; 853 st8.rel [r18]=r19 // store new tag 854 ;; 855 itc.d r21 // and place in TLB 856 ssm psr.dt 857 ;; 858 srlz.d 859 mov pr=r17,0x1ffff // restore predicates 860 rfi 861 ;; 8623: add r20=24,r20 // next in chain 863 ;; 864 ld8 r20=[r20] // read chain 865 br.cond.sptk.few 2b // loop 866 ;; 8679: ssm psr.dt 868 mov pr=r17,0x1ffff // restore predicates 869 ;; 870 srlz.d 871 ;; 872 CALL(trap, 20, cr.ifa) // Page Not Present trap 873IVT_END(Data_TLB) 874 875IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00) 876 mov r16=cr.ifa // where did it happen 877 mov r18=pr // save predicates 878 ;; 879 extr.u r17=r16,61,3 // get region number 880 ;; 881 cmp.ge p13,p0=5,r17 // RR0-RR5? 882 cmp.eq p15,p14=7,r17 // RR7->p15, RR6->p14 883(p13) br.spnt 9f 884 ;; 885(p15) movl r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 886 PTE_AR_RX+PTE_ED 887(p14) movl r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 888 PTE_AR_RX 889 ;; 890 dep r16=0,r16,50,14 // clear bits above PPN 891 ;; 892 dep r16=r17,r16,0,12 // put pte bits in 0..11 893 ;; 894 itc.i r16 895 mov pr=r18,0x1ffff // restore predicates 896 ;; 897 rfi 898 ;; 8999: mov pr=r18,0x1ffff // restore predicates 900 CALL(trap, 3, cr.ifa) 901IVT_END(Alternate_Instruction_TLB) 902 903IVT_ENTRY(Alternate_Data_TLB, 0x1000) 904 mov r16=cr.ifa // where did it happen 905 mov r18=pr // save predicates 906 ;; 907 extr.u r17=r16,61,3 // get region number 908 ;; 909 cmp.ge p13,p0=5,r17 // RR0-RR5? 910 cmp.eq p15,p14=7,r17 // RR7->p15, RR6->p14 911(p13) br.spnt 9f 912 ;; 913(p15) movl r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 914 PTE_AR_RW+PTE_ED 915(p14) movl r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 916 PTE_AR_RW 917 ;; 918 dep r16=0,r16,50,14 // clear bits above PPN 919 ;; 920 dep r16=r17,r16,0,12 // put pte bits in 0..11 921 ;; 922 itc.d r16 923 mov pr=r18,0x1ffff // restore predicates 924 ;; 925 rfi 926 ;; 9279: mov pr=r18,0x1ffff // restore predicates 928 CALL(trap, 4, cr.ifa) 929IVT_END(Alternate_Data_TLB) 930 931IVT_ENTRY(Data_Nested_TLB, 0x1400) 932 // See exception_save_restart and exception_restore_restart for the 933 // contexts that may cause a data nested TLB. We can only use the 934 // banked general registers and predicates, but don't use: 935 // p14 & p15 - Set in exception save 936 // r16 & r17 - Arguments to exception save 937 // r30 - Faulting address (modulo page size) 938 // We assume r30 has the virtual addresses that relate to the data 939 // nested TLB fault. The address does not have to be exact, as long 940 // as it's in the same page. We use physical addressing to avoid 941 // double nested faults. Since all virtual addresses we encounter 942 // here are direct mapped region 7 addresses, we have no problem 943 // constructing physical addresses. 944{ .mlx 945 rsm psr.dt 946 movl r27=ia64_kptdir 947 ;; 948} 949{ .mii 950 srlz.d 951 dep r27=0,r27,61,3 952 ;; 953 extr.u r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3 // dir L0 index 954} 955{ .mii 956 ld8 r27=[r27] // dir L0 page 957 extr.u r26=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3 // dir L1 index 958 ;; 959 dep r27=0,r27,61,3 960 ;; 961} 962{ .mmi 963 shladd r27=r28,3,r27 964 ;; 965 ld8 r27=[r27] // dir L1 page 966 extr.u r28=r30,PAGE_SHIFT,PAGE_SHIFT-5 // pte index 967 ;; 968} 969{ .mmi 970 shladd r27=r26,3,r27 971 ;; 972 mov r26=rr[r30] 973 dep r27=0,r27,61,3 974 ;; 975} 976{ .mii 977 ld8 r27=[r27] // pte page 978 shl r28=r28,5 979 dep r26=0,r26,0,2 980 ;; 981} 982{ .mmi 983 add r27=r28,r27 984 ;; 985 mov cr.ifa=r30 986 dep r27=0,r27,61,3 987 ;; 988} 989{ .mmi 990 ld8 r28=[r27] // pte 991 ;; 992 mov cr.itir=r26 993 or r28=PTE_DIRTY+PTE_ACCESSED,r28 994 ;; 995} 996{ .mmi 997 st8 [r27]=r28 998 ;; 999 addl r26=NTLBRT_SAVE,r0 1000 addl r27=NTLBRT_RESTORE,r0 1001} 1002{ .mmi 1003 itc.d r28 1004 ;; 1005 ssm psr.dt 1006 cmp.eq p12,p0=r29,r26 1007 ;; 1008} 1009{ .mib 1010 srlz.d 1011 cmp.eq p13,p0=r29,r27 1012(p12) br.sptk exception_save_restart 1013 ;; 1014} 1015{ .mib 1016 nop 0 1017 nop 0 1018(p13) br.sptk exception_restore_restart 1019 ;; 1020} 1021{ .mlx 1022 mov r26=ar.bsp 1023 movl r27=kstack 1024 ;; 1025} 1026{ .mib 1027 mov r28=sp 1028 addl r27=KSTACK_PAGES*PAGE_SIZE-16,r0 1029 nop 0 1030 ;; 1031} 1032{ .mmi 1033 mov sp=r27 1034 ;; 1035 mov r27=ar.bspstore 1036 nop 0 1037 ;; 1038} 1039 CALL(trap, 5, r30) 1040IVT_END(Data_Nested_TLB) 1041 1042IVT_ENTRY(Instruction_Key_Miss, 0x1800) 1043 CALL(trap, 6, cr.ifa) 1044IVT_END(Instruction_Key_Miss) 1045 1046IVT_ENTRY(Data_Key_Miss, 0x1c00) 1047 CALL(trap, 7, cr.ifa) 1048IVT_END(Data_Key_Miss) 1049 1050IVT_ENTRY(Dirty_Bit, 0x2000) 1051 mov r16=cr.ifa 1052 mov r17=pr 1053 ;; 1054 thash r18=r16 1055 ;; 1056 ttag r19=r16 1057 add r20=24,r18 // collision chain 1058 ;; 1059 ld8 r20=[r20] // bucket head 1060 ;; 1061 rsm psr.dt // turn off data translations 1062 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1063 ;; 1064 srlz.d // serialize 1065 ld8 r20=[r20] // first entry 1066 ;; 10671: cmp.eq p15,p0=r0,r20 // done? 1068(p15) br.cond.spnt.few 9f // bail if done 1069 ;; 1070 add r21=16,r20 // tag location 1071 ;; 1072 ld8 r21=[r21] // read tag 1073 ;; 1074 cmp.ne p15,p0=r21,r19 // compare tags 1075(p15) br.cond.sptk.few 2f // if not, read next in chain 1076 ;; 1077 ld8 r21=[r20] // read pte 1078 mov r22=PTE_DIRTY+PTE_ACCESSED 1079 ;; 1080 or r21=r22,r21 // set dirty & access bit 1081 ;; 1082 st8 [r20]=r21,8 // store back 1083 ;; 1084 ld8 r22=[r20] // read rest of pte 1085 ;; 1086 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1087 ;; 1088 add r20=16,r18 // address of tag 1089 ;; 1090 ld8.acq r23=[r20] // read old tag 1091 ;; 1092 dep r23=-1,r23,63,1 // set ti bit 1093 ;; 1094 st8.rel [r20]=r23 // store old tag + ti 1095 ;; 1096 mf // make sure everyone sees 1097 ;; 1098 st8 [r18]=r21,8 // store pte 1099 ;; 1100 st8 [r18]=r22,8 1101 ;; 1102 st8.rel [r18]=r19 // store new tag 1103 ;; 1104 itc.d r21 // and place in TLB 1105 ssm psr.dt 1106 ;; 1107 srlz.d 1108 mov pr=r17,0x1ffff // restore predicates 1109 rfi 1110 ;; 11112: add r20=24,r20 // next in chain 1112 ;; 1113 ld8 r20=[r20] // read chain 1114 br.cond.sptk.few 1b // loop 1115 ;; 11169: ssm psr.dt 1117 mov pr=r17,0x1ffff // restore predicates 1118 ;; 1119 srlz.d 1120 ;; 1121 CALL(trap, 8, cr.ifa) // die horribly 1122IVT_END(Dirty_Bit) 1123 1124IVT_ENTRY(Instruction_Access_Bit, 0x2400) 1125 mov r16=cr.ifa 1126 mov r17=pr 1127 ;; 1128 thash r18=r16 1129 ;; 1130 ttag r19=r16 1131 add r20=24,r18 // collision chain 1132 ;; 1133 ld8 r20=[r20] // bucket head 1134 ;; 1135 rsm psr.dt // turn off data translations 1136 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1137 ;; 1138 srlz.d // serialize 1139 ld8 r20=[r20] // first entry 1140 ;; 11411: cmp.eq p15,p0=r0,r20 // done? 1142(p15) br.cond.spnt.few 9f // bail if done 1143 ;; 1144 add r21=16,r20 // tag location 1145 ;; 1146 ld8 r21=[r21] // read tag 1147 ;; 1148 cmp.ne p15,p0=r21,r19 // compare tags 1149(p15) br.cond.sptk.few 2f // if not, read next in chain 1150 ;; 1151 ld8 r21=[r20] // read pte 1152 mov r22=PTE_ACCESSED 1153 ;; 1154 or r21=r22,r21 // set accessed bit 1155 ;; 1156 st8 [r20]=r21,8 // store back 1157 ;; 1158 ld8 r22=[r20] // read rest of pte 1159 ;; 1160 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1161 ;; 1162 add r20=16,r18 // address of tag 1163 ;; 1164 ld8.acq r23=[r20] // read old tag 1165 ;; 1166 dep r23=-1,r23,63,1 // set ti bit 1167 ;; 1168 st8.rel [r20]=r23 // store old tag + ti 1169 ;; 1170 mf // make sure everyone sees 1171 ;; 1172 st8 [r18]=r21,8 // store pte 1173 ;; 1174 st8 [r18]=r22,8 1175 ;; 1176 st8.rel [r18]=r19 // store new tag 1177 ;; 1178 itc.i r21 // and place in TLB 1179 ssm psr.dt 1180 ;; 1181 srlz.d 1182 mov pr=r17,0x1ffff // restore predicates 1183 rfi // walker will retry the access 1184 ;; 11852: add r20=24,r20 // next in chain 1186 ;; 1187 ld8 r20=[r20] // read chain 1188 br.cond.sptk.few 1b // loop 1189 ;; 11909: ssm psr.dt 1191 mov pr=r17,0x1ffff // restore predicates 1192 ;; 1193 srlz.d 1194 ;; 1195 CALL(trap, 9, cr.ifa) 1196IVT_END(Instruction_Access_Bit) 1197 1198IVT_ENTRY(Data_Access_Bit, 0x2800) 1199 mov r16=cr.ifa 1200 mov r17=pr 1201 ;; 1202 thash r18=r16 1203 ;; 1204 ttag r19=r16 1205 add r20=24,r18 // collision chain 1206 ;; 1207 ld8 r20=[r20] // bucket head 1208 ;; 1209 rsm psr.dt // turn off data translations 1210 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1211 ;; 1212 srlz.d // serialize 1213 ld8 r20=[r20] // first entry 1214 ;; 12151: cmp.eq p15,p0=r0,r20 // done? 1216(p15) br.cond.spnt.few 9f // bail if done 1217 ;; 1218 add r21=16,r20 // tag location 1219 ;; 1220 ld8 r21=[r21] // read tag 1221 ;; 1222 cmp.ne p15,p0=r21,r19 // compare tags 1223(p15) br.cond.sptk.few 2f // if not, read next in chain 1224 ;; 1225 ld8 r21=[r20] // read pte 1226 mov r22=PTE_ACCESSED 1227 ;; 1228 or r21=r22,r21 // set accessed bit 1229 ;; 1230 st8 [r20]=r21,8 // store back 1231 ;; 1232 ld8 r22=[r20] // read rest of pte 1233 ;; 1234 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1235 ;; 1236 add r20=16,r18 // address of tag 1237 ;; 1238 ld8.acq r23=[r20] // read old tag 1239 ;; 1240 dep r23=-1,r23,63,1 // set ti bit 1241 ;; 1242 st8.rel [r20]=r23 // store old tag + ti 1243 ;; 1244 mf // make sure everyone sees 1245 ;; 1246 st8 [r18]=r21,8 // store pte 1247 ;; 1248 st8 [r18]=r22,8 1249 ;; 1250 st8.rel [r18]=r19 // store new tag 1251 ;; 1252 itc.d r21 // and place in TLB 1253 ssm psr.dt 1254 ;; 1255 srlz.d 1256 mov pr=r17,0x1ffff // restore predicates 1257 rfi // walker will retry the access 1258 ;; 12592: add r20=24,r20 // next in chain 1260 ;; 1261 ld8 r20=[r20] // read chain 1262 br.cond.sptk.few 1b // loop 1263 ;; 12649: ssm psr.dt 1265 mov pr=r17,0x1ffff // restore predicates 1266 ;; 1267 srlz.d 1268 ;; 1269 CALL(trap, 10, cr.ifa) 1270IVT_END(Data_Access_Bit) 1271 1272IVT_ENTRY(Break_Instruction, 0x2c00) 1273{ .mib 1274 mov r17=cr.iim 1275 mov r16=ip 1276 br.sptk exception_save 1277 ;; 1278} 1279{ .mmi 1280 alloc r15=ar.pfs,0,0,2,0 1281 ;; 1282(p11) ssm psr.i 1283 mov out0=11 1284 ;; 1285} 1286{ .mmi 1287 flushrs 1288 ;; 1289(p11) srlz.d 1290 add out1=16,sp 1291} 1292{ .mfb 1293 nop 0 1294 nop 0 1295 br.call.sptk rp=trap 1296 ;; 1297} 1298{ .mfb 1299 nop 0 1300 nop 0 1301 br.sptk exception_restore 1302 ;; 1303} 1304IVT_END(Break_Instruction) 1305 1306IVT_ENTRY(External_Interrupt, 0x3000) 1307{ .mib 1308 mov r17=cr.ivr // Put the vector in the trap frame. 1309 mov r16=ip 1310 br.sptk exception_save 1311 ;; 1312} 1313{ .mfb 1314 alloc r15=ar.pfs,0,0,1,0 1315 nop 0 1316 nop 0 1317 ;; 1318} 1319{ .mfb 1320 add out0=16,sp 1321 nop 0 1322 br.call.sptk rp=interrupt 1323 ;; 1324} 1325{ .mfb 1326 nop 0 1327 nop 0 1328 br.sptk exception_restore 1329 ;; 1330} 1331IVT_END(External_Interrupt) 1332 1333IVT_ENTRY(Reserved_3400, 0x3400) 1334 CALL(trap, 13, cr.ifa) 1335IVT_END(Reserved_3400) 1336 1337IVT_ENTRY(Reserved_3800, 0x3800) 1338 CALL(trap, 14, cr.ifa) 1339IVT_END(Reserved_3800) 1340 1341IVT_ENTRY(Reserved_3c00, 0x3c00) 1342 CALL(trap, 15, cr.ifa) 1343IVT_END(Reserved_3c00) 1344 1345IVT_ENTRY(Reserved_4000, 0x4000) 1346 CALL(trap, 16, cr.ifa) 1347IVT_END(Reserved_4000) 1348 1349IVT_ENTRY(Reserved_4400, 0x4400) 1350 CALL(trap, 17, cr.ifa) 1351IVT_END(Reserved_4400) 1352 1353IVT_ENTRY(Reserved_4800, 0x4800) 1354 CALL(trap, 18, cr.ifa) 1355IVT_END(Reserved_4800) 1356 1357IVT_ENTRY(Reserved_4c00, 0x4c00) 1358 CALL(trap, 19, cr.ifa) 1359IVT_END(Reserved_4c00) 1360 1361IVT_ENTRY(Page_Not_Present, 0x5000) 1362 CALL(trap, 20, cr.ifa) 1363IVT_END(Page_Not_Present) 1364 1365IVT_ENTRY(Key_Permission, 0x5100) 1366 CALL(trap, 21, cr.ifa) 1367IVT_END(Key_Permission) 1368 1369IVT_ENTRY(Instruction_Access_Rights, 0x5200) 1370 CALL(trap, 22, cr.ifa) 1371IVT_END(Instruction_Access_Rights) 1372 1373IVT_ENTRY(Data_Access_Rights, 0x5300) 1374 CALL(trap, 23, cr.ifa) 1375IVT_END(Data_Access_Rights) 1376 1377IVT_ENTRY(General_Exception, 0x5400) 1378 CALL(trap, 24, cr.ifa) 1379IVT_END(General_Exception) 1380 1381IVT_ENTRY(Disabled_FP_Register, 0x5500) 1382 CALL(trap, 25, cr.ifa) 1383IVT_END(Disabled_FP_Register) 1384 1385IVT_ENTRY(NaT_Consumption, 0x5600) 1386 CALL(trap, 26, cr.ifa) 1387IVT_END(NaT_Consumption) 1388 1389IVT_ENTRY(Speculation, 0x5700) 1390 CALL(trap, 27, cr.iim) 1391IVT_END(Speculation) 1392 1393IVT_ENTRY(Reserved_5800, 0x5800) 1394 CALL(trap, 28, cr.ifa) 1395IVT_END(Reserved_5800) 1396 1397IVT_ENTRY(Debug, 0x5900) 1398 CALL(trap, 29, cr.ifa) 1399IVT_END(Debug) 1400 1401IVT_ENTRY(Unaligned_Reference, 0x5a00) 1402 CALL(trap, 30, cr.ifa) 1403IVT_END(Unaligned_Reference) 1404 1405IVT_ENTRY(Unsupported_Data_Reference, 0x5b00) 1406 CALL(trap, 31, cr.ifa) 1407IVT_END(Unsupported_Data_Reference) 1408 1409IVT_ENTRY(Floating_Point_Fault, 0x5c00) 1410 CALL(trap, 32, cr.ifa) 1411IVT_END(Floating_Point_Fault) 1412 1413IVT_ENTRY(Floating_Point_Trap, 0x5d00) 1414 CALL(trap, 33, cr.ifa) 1415IVT_END(Floating_Point_Trap) 1416 1417IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00) 1418 CALL(trap, 34, cr.ifa) 1419IVT_END(Lower_Privilege_Transfer_Trap) 1420 1421IVT_ENTRY(Taken_Branch_Trap, 0x5f00) 1422 CALL(trap, 35, cr.ifa) 1423IVT_END(Taken_Branch_Trap) 1424 1425IVT_ENTRY(Single_Step_Trap, 0x6000) 1426 CALL(trap, 36, cr.ifa) 1427IVT_END(Single_Step_Trap) 1428 1429IVT_ENTRY(Reserved_6100, 0x6100) 1430 CALL(trap, 37, cr.ifa) 1431IVT_END(Reserved_6100) 1432 1433IVT_ENTRY(Reserved_6200, 0x6200) 1434 CALL(trap, 38, cr.ifa) 1435IVT_END(Reserved_6200) 1436 1437IVT_ENTRY(Reserved_6300, 0x6300) 1438 CALL(trap, 39, cr.ifa) 1439IVT_END(Reserved_6300) 1440 1441IVT_ENTRY(Reserved_6400, 0x6400) 1442 CALL(trap, 40, cr.ifa) 1443IVT_END(Reserved_6400) 1444 1445IVT_ENTRY(Reserved_6500, 0x6500) 1446 CALL(trap, 41, cr.ifa) 1447IVT_END(Reserved_6500) 1448 1449IVT_ENTRY(Reserved_6600, 0x6600) 1450 CALL(trap, 42, cr.ifa) 1451IVT_END(Reserved_6600) 1452 1453IVT_ENTRY(Reserved_6700, 0x6700) 1454 CALL(trap, 43, cr.ifa) 1455IVT_END(Reserved_6700) 1456 1457IVT_ENTRY(Reserved_6800, 0x6800) 1458 CALL(trap, 44, cr.ifa) 1459IVT_END(Reserved_6800) 1460 1461IVT_ENTRY(IA_32_Exception, 0x6900) 1462 CALL(IA32_TRAP, 45, cr.ifa) 1463IVT_END(IA_32_Exception) 1464 1465IVT_ENTRY(IA_32_Intercept, 0x6a00) 1466 CALL(IA32_TRAP, 46, cr.iim) 1467IVT_END(IA_32_Intercept) 1468 1469IVT_ENTRY(IA_32_Interrupt, 0x6b00) 1470 CALL(IA32_TRAP, 47, cr.ifa) 1471IVT_END(IA_32_Interrupt) 1472 1473IVT_ENTRY(Reserved_6c00, 0x6c00) 1474 CALL(trap, 48, cr.ifa) 1475IVT_END(Reserved_6c00) 1476 1477IVT_ENTRY(Reserved_6d00, 0x6d00) 1478 CALL(trap, 49, cr.ifa) 1479IVT_END(Reserved_6d00) 1480 1481IVT_ENTRY(Reserved_6e00, 0x6e00) 1482 CALL(trap, 50, cr.ifa) 1483IVT_END(Reserved_6e00) 1484 1485IVT_ENTRY(Reserved_6f00, 0x6f00) 1486 CALL(trap, 51, cr.ifa) 1487IVT_END(Reserved_6f00) 1488 1489IVT_ENTRY(Reserved_7000, 0x7000) 1490 CALL(trap, 52, cr.ifa) 1491IVT_END(Reserved_7000) 1492 1493IVT_ENTRY(Reserved_7100, 0x7100) 1494 CALL(trap, 53, cr.ifa) 1495IVT_END(Reserved_7100) 1496 1497IVT_ENTRY(Reserved_7200, 0x7200) 1498 CALL(trap, 54, cr.ifa) 1499IVT_END(Reserved_7200) 1500 1501IVT_ENTRY(Reserved_7300, 0x7300) 1502 CALL(trap, 55, cr.ifa) 1503IVT_END(Reserved_7300) 1504 1505IVT_ENTRY(Reserved_7400, 0x7400) 1506 CALL(trap, 56, cr.ifa) 1507IVT_END(Reserved_7400) 1508 1509IVT_ENTRY(Reserved_7500, 0x7500) 1510 CALL(trap, 57, cr.ifa) 1511IVT_END(Reserved_7500) 1512 1513IVT_ENTRY(Reserved_7600, 0x7600) 1514 CALL(trap, 58, cr.ifa) 1515IVT_END(Reserved_7600) 1516 1517IVT_ENTRY(Reserved_7700, 0x7700) 1518 CALL(trap, 59, cr.ifa) 1519IVT_END(Reserved_7700) 1520 1521IVT_ENTRY(Reserved_7800, 0x7800) 1522 CALL(trap, 60, cr.ifa) 1523IVT_END(Reserved_7800) 1524 1525IVT_ENTRY(Reserved_7900, 0x7900) 1526 CALL(trap, 61, cr.ifa) 1527IVT_END(Reserved_7900) 1528 1529IVT_ENTRY(Reserved_7a00, 0x7a00) 1530 CALL(trap, 62, cr.ifa) 1531IVT_END(Reserved_7a00) 1532 1533IVT_ENTRY(Reserved_7b00, 0x7b00) 1534 CALL(trap, 63, cr.ifa) 1535IVT_END(Reserved_7b00) 1536 1537IVT_ENTRY(Reserved_7c00, 0x7c00) 1538 CALL(trap, 64, cr.ifa) 1539IVT_END(Reserved_7c00) 1540 1541IVT_ENTRY(Reserved_7d00, 0x7d00) 1542 CALL(trap, 65, cr.ifa) 1543IVT_END(Reserved_7d00) 1544 1545IVT_ENTRY(Reserved_7e00, 0x7e00) 1546 CALL(trap, 66, cr.ifa) 1547IVT_END(Reserved_7e00) 1548 1549IVT_ENTRY(Reserved_7f00, 0x7f00) 1550 CALL(trap, 67, cr.ifa) 1551IVT_END(Reserved_7f00) 1552