exception.S revision 171739
1/*- 2 * Copyright (c) 2003,2004 Marcel Moolenaar 3 * Copyright (c) 2000 Doug Rabson 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <machine/asm.h> 29__FBSDID("$FreeBSD: head/sys/ia64/ia64/exception.S 171739 2007-08-06 05:11:01Z marcel $"); 30 31#include <opt_xtrace.h> 32 33#include <machine/pte.h> 34#include <assym.s> 35 36/* 37 * ar.k7 = kernel memory stack 38 * ar.k6 = kernel register stack 39 * ar.k5 = EPC gateway page 40 * ar.k4 = PCPU data 41 */ 42 43#ifdef EXCEPTION_TRACING 44 45 .data 46 .global xtrace, xhead 47xtrace: .space 1024*5*8 48xhead: data8 xtrace 49 50#define XTRACE(offset) \ 51{ .mmi ; \ 52 mov r24=ar.itc ; \ 53 mov r25=cr.iip ; \ 54 mov r27=offset ; \ 55} ; \ 56{ .mlx ; \ 57 mov r28=cr.ifa ; \ 58 movl r29=xhead ;; \ 59} ; \ 60{ .mmi ; \ 61 ld8 r29=[r29] ;; \ 62 st8 [r29]=r24,8 ; \ 63 nop 0 ;; \ 64} ; \ 65{ .mmi ; \ 66 st8 [r29]=r27,8 ;; \ 67 mov r24=cr.isr ; \ 68 add r27=8,r29 ;; \ 69} ; \ 70{ .mmi ; \ 71 st8 [r29]=r25,16 ;; \ 72 st8 [r27]=r28,16 ; \ 73 mov r25=pr ;; \ 74} ; \ 75{ .mlx ; \ 76 st8 [r29]=r24 ; \ 77 movl r28=xhead ;; \ 78} ; \ 79{ .mii ; \ 80 cmp.eq p15,p0=r27,r28 ; \ 81 addl r29=1024*5*8,r0 ;; \ 82(p15) sub r27=r28,r29 ;; \ 83} ; \ 84{ .mib ; \ 85 st8 [r28]=r27 ; \ 86 mov pr=r25,0x1ffff ; \ 87 nop 0 ;; \ 88} 89 90#else 91 92#define XTRACE(offset) 93 94#endif 95 96 .text 97 98/* 99 * exception_save: save interrupted state 100 * 101 * Arguments: 102 * r16 address of bundle that contains the branch. The 103 * return address will be the next bundle. 104 * r17 the value to save as ifa in the trapframe. This 105 * normally is cr.ifa, but some interruptions set 106 * set cr.iim and not cr.ifa. 107 * 108 * Returns: 109 * p15 interrupted from user stack 110 * p14 interrupted from kernel stack 111 * p13 interrupted from user backing store 112 * p12 interrupted from kernel backing store 113 * p11 interrupts were enabled 114 * p10 interrupts were disabled 115 */ 116ENTRY_NOPROFILE(exception_save, 0) 117{ .mii 118 mov r20=ar.unat 119 extr.u r31=sp,61,3 120 mov r18=pr 121 ;; 122} 123{ .mmi 124 cmp.le p14,p15=5,r31 125 ;; 126(p15) mov r23=ar.k7 // kernel memory stack 127(p14) mov r23=sp 128 ;; 129} 130{ .mii 131 mov r21=ar.rsc 132 add r30=-SIZEOF_TRAPFRAME,r23 133 ;; 134 dep r30=0,r30,0,10 135 ;; 136} 137{ .mmi 138 mov ar.rsc=0 139 sub r19=r23,r30 140 add r31=8,r30 141 ;; 142} 143{ .mlx 144 mov r22=cr.iip 145 movl r26=exception_save_restart 146 ;; 147} 148 149 /* 150 * We have a 1KB aligned trapframe, pointed to by sp. If we write 151 * to the trapframe, we may trigger a data nested TLB fault. By 152 * aligning the trapframe on a 1KB boundary, we guarantee that if 153 * we get a data nested TLB fault, it will be on the very first 154 * write. Since the data nested TLB fault does not preserve any 155 * state, we have to be careful what we clobber. Consequently, we 156 * have to be careful what we use here. Below a list of registers 157 * that are currently alive: 158 * r16,r17=arguments 159 * r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS 160 * r26=restart point 161 * r30,r31=trapframe pointers 162 * p14,p15=memory stack switch 163 */ 164exception_save_restart: 165{ .mmi 166 st8 [r30]=r19,16 // length 167 st8 [r31]=r0,16 // flags 168 add r19=16,r19 169 ;; 170} 171{ .mmi 172 st8.spill [r30]=sp,16 // sp 173 st8 [r31]=r20,16 // unat 174 sub sp=r23,r19 175 ;; 176} 177{ .mmi 178 mov r19=ar.rnat 179 mov r20=ar.bspstore 180 mov r23=rp 181 ;; 182} 183 // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp 184{ .mmi 185 st8 [r30]=r23,16 // rp 186 st8 [r31]=r18,16 // pr 187 mov r24=ar.pfs 188 ;; 189} 190{ .mmb 191 st8 [r30]=r24,16 // pfs 192 st8 [r31]=r20,16 // bspstore 193 cover 194 ;; 195} 196{ .mmi 197 mov r18=ar.fpsr 198 mov r23=cr.ipsr 199 extr.u r24=r20,61,3 200 ;; 201} 202 // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr 203{ .mmi 204 st8 [r30]=r19,16 // rnat 205 st8 [r31]=r0,16 // __spare 206 cmp.le p12,p13=5,r24 207 ;; 208} 209{ .mmi 210 st8.spill [r30]=r13,16 // tp 211 st8 [r31]=r21,16 // rsc 212 tbit.nz p11,p10=r23,14 // p11=interrupts enabled 213 ;; 214} 215{ .mmi 216(p13) mov r21=ar.k6 // kernel register stack 217 ;; 218 st8 [r30]=r18,16 // fpsr 219(p13) dep r20=r20,r21,0,9 // align dirty registers 220 ;; 221} 222 // r20=bspstore, r22=iip, r23=ipsr 223{ .mmi 224 st8 [r31]=r23,16 // psr 225(p13) mov ar.bspstore=r20 226 nop 0 227 ;; 228} 229{ .mmi 230 mov r18=ar.bsp 231 ;; 232 mov r19=cr.ifs 233 sub r18=r18,r20 234 ;; 235} 236{ .mmi 237 st8.spill [r30]=gp,16 // gp 238 st8 [r31]=r18,16 // ndirty 239 nop 0 240 ;; 241} 242 // r19=ifs, r22=iip 243{ .mmi 244 st8 [r30]=r19,16 // cfm 245 st8 [r31]=r22,16 // iip 246 nop 0 247 ;; 248} 249{ .mmi 250 st8 [r30]=r17 // ifa 251 mov r18=cr.isr 252 add r29=16,r30 253 ;; 254} 255{ .mmi 256 st8 [r31]=r18 // isr 257 add r30=8,r29 258 add r31=16,r29 259 ;; 260} 261{ .mmi 262 .mem.offset 0,0 263 st8.spill [r30]=r2,16 // r2 264 .mem.offset 8,0 265 st8.spill [r31]=r3,16 // r3 266 add r2=9*8,r29 267 ;; 268} 269{ .mmi 270 .mem.offset 0,0 271 st8.spill [r30]=r8,16 // r8 272 .mem.offset 8,0 273 st8.spill [r31]=r9,16 // r9 274 add r3=8,r2 275 ;; 276} 277{ .mmi 278 .mem.offset 0,0 279 st8.spill [r30]=r10,16 // r10 280 .mem.offset 8,0 281 st8.spill [r31]=r11,16 // r11 282 add r8=16,r16 283 ;; 284} 285{ .mmi 286 .mem.offset 0,0 287 st8.spill [r30]=r14 // r14 288 .mem.offset 8,0 289 st8.spill [r31]=r15 // r15 290 mov r9=r29 291} 292{ .mmb 293 mov r10=ar.csd 294 mov r11=ar.ssd 295 bsw.1 296 ;; 297} 298{ .mmi 299 .mem.offset 0,0 300 st8.spill [r2]=r16,16 // r16 301 .mem.offset 8,0 302 st8.spill [r3]=r17,16 // r17 303 mov r14=b6 304 ;; 305} 306{ .mmi 307 .mem.offset 0,0 308 st8.spill [r2]=r18,16 // r18 309 .mem.offset 8,0 310 st8.spill [r3]=r19,16 // r19 311 mov r15=b7 312 ;; 313} 314{ .mmi 315 .mem.offset 0,0 316 st8.spill [r2]=r20,16 // r20 317 .mem.offset 8,0 318 st8.spill [r3]=r21,16 // r21 319 mov b7=r8 320 ;; 321} 322{ .mmi 323 .mem.offset 0,0 324 st8.spill [r2]=r22,16 // r22 325 .mem.offset 8,0 326 st8.spill [r3]=r23,16 // r23 327 ;; 328} 329 330 .mem.offset 0,0 331 st8.spill [r2]=r24,16 // r24 332 .mem.offset 8,0 333 st8.spill [r3]=r25,16 // r25 334 ;; 335 .mem.offset 0,0 336 st8.spill [r2]=r26,16 // r26 337 .mem.offset 8,0 338 st8.spill [r3]=r27,16 // r27 339 ;; 340 .mem.offset 0,0 341 st8.spill [r2]=r28,16 // r28 342 .mem.offset 8,0 343 st8.spill [r3]=r29,16 // r29 344 ;; 345 .mem.offset 0,0 346 st8.spill [r2]=r30,16 // r30 347 .mem.offset 8,0 348 st8.spill [r3]=r31,16 // r31 349 ;; 350 351{ .mmi 352 st8 [r2]=r14,16 // b6 353 mov r17=ar.unat 354 nop 0 355 ;; 356} 357{ .mmi 358 st8 [r3]=r15,16 // b7 359 mov r16=ar.ccv 360 nop 0 361 ;; 362} 363{ .mmi 364 st8 [r2]=r16,16 // ccv 365 st8 [r3]=r10,16 // csd 366 nop 0 367 ;; 368} 369{ .mmi 370 st8 [r2]=r11,24 // ssd 371 st8 [r9]=r17 372 nop 0 373 ;; 374} 375 376 stf.spill [r3]=f6,32 // f6 377 stf.spill [r2]=f7,32 // f7 378 ;; 379 stf.spill [r3]=f8,32 // f8 380 stf.spill [r2]=f9,32 // f9 381 ;; 382 stf.spill [r3]=f10,32 // f10 383 stf.spill [r2]=f11,32 // f11 384 ;; 385 stf.spill [r3]=f12,32 // f12 386 stf.spill [r2]=f13,32 // f13 387 ;; 388 stf.spill [r3]=f14 // f14 389 stf.spill [r2]=f15 // f15 390 ;; 391{ .mmi 392 mov ar.rsc=3 393 mov r13=ar.k4 394 nop 0 395 ;; 396} 397{ .mlx 398 ssm psr.ic|psr.dfh 399 movl gp=__gp 400 ;; 401} 402{ .mfb 403 srlz.d 404 nop 0 405 br.sptk b7 406 ;; 407} 408END(exception_save) 409 410/* 411 * exception_restore: restore interrupted state 412 * 413 * Arguments: 414 * sp+16 trapframe pointer 415 */ 416ENTRY_NOPROFILE(exception_restore, 0) 417{ .mmi 418 rsm psr.i 419 add r3=SIZEOF_TRAPFRAME-16,sp 420 add r2=SIZEOF_TRAPFRAME,sp 421 ;; 422} 423{ .mmi 424 srlz.d 425 add r8=SIZEOF_SPECIAL+32,sp 426 nop 0 427 ;; 428} 429 // The next load can trap. Let it be... 430 ldf.fill f15=[r2],-32 // f15 431 ldf.fill f14=[r3],-32 // f14 432 add sp=16,sp 433 ;; 434 ldf.fill f13=[r2],-32 // f13 435 ldf.fill f12=[r3],-32 // f12 436 ;; 437 ldf.fill f11=[r2],-32 // f11 438 ldf.fill f10=[r3],-32 // f10 439 ;; 440 ldf.fill f9=[r2],-32 // f9 441 ldf.fill f8=[r3],-32 // f8 442 ;; 443 ldf.fill f7=[r2],-24 // f7 444 ldf.fill f6=[r3],-16 // f6 445 ;; 446 447{ .mmi 448 ld8 r8=[r8] // unat (after) 449 ;; 450 mov ar.unat=r8 451 nop 0 452 ;; 453} 454 455 ld8 r10=[r2],-16 // ssd 456 ld8 r11=[r3],-16 // csd 457 ;; 458 mov ar.ssd=r10 459 mov ar.csd=r11 460 461 ld8 r14=[r2],-16 // ccv 462 ld8 r15=[r3],-16 // b7 463 ;; 464 465{ .mmi 466 mov ar.ccv=r14 467 ld8 r8=[r2],-16 // b6 468 mov b7=r15 469 ;; 470} 471{ .mmi 472 ld8.fill r31=[r3],-16 // r31 473 ld8.fill r30=[r2],-16 // r30 474 mov b6=r8 475 ;; 476} 477 478 ld8.fill r29=[r3],-16 // r29 479 ld8.fill r28=[r2],-16 // r28 480 ;; 481 ld8.fill r27=[r3],-16 // r27 482 ld8.fill r26=[r2],-16 // r26 483 ;; 484 ld8.fill r25=[r3],-16 // r25 485 ld8.fill r24=[r2],-16 // r24 486 ;; 487 ld8.fill r23=[r3],-16 // r23 488 ld8.fill r22=[r2],-16 // r22 489 ;; 490 ld8.fill r21=[r3],-16 // r21 491 ld8.fill r20=[r2],-16 // r20 492 ;; 493 ld8.fill r19=[r3],-16 // r19 494 ld8.fill r18=[r2],-16 // r18 495 ;; 496 497{ .mmb 498 ld8.fill r17=[r3],-16 // r17 499 ld8.fill r16=[r2],-16 // r16 500 bsw.0 501 ;; 502} 503{ .mmi 504 ld8.fill r15=[r3],-16 // r15 505 ld8.fill r14=[r2],-16 // r14 506 add r31=16,sp 507 ;; 508} 509{ .mmi 510 ld8 r16=[sp] // tf_length 511 ld8.fill r11=[r3],-16 // r11 512 add r30=24,sp 513 ;; 514} 515{ .mmi 516 ld8.fill r10=[r2],-16 // r10 517 ld8.fill r9=[r3],-16 // r9 518 add r16=r16,sp // ar.k7 519 ;; 520} 521{ .mmi 522 ld8.fill r8=[r2],-16 // r8 523 ld8.fill r3=[r3] // r3 524 ;; 525} 526 // We want nested TLB faults from here on... 527 rsm psr.ic|psr.i 528 ld8.fill r2=[r2] // r2 529 nop 0 530 ;; 531 srlz.d 532 ld8.fill sp=[r31],16 // sp 533 nop 0 534 ;; 535 536 ld8 r17=[r30],16 // unat 537 ld8 r29=[r31],16 // rp 538 ;; 539 ld8 r18=[r30],16 // pr 540 ld8 r28=[r31],16 // pfs 541 mov rp=r29 542 ;; 543 ld8 r20=[r30],24 // bspstore 544 ld8 r21=[r31],24 // rnat 545 mov ar.pfs=r28 546 ;; 547 ld8.fill r29=[r30],16 // tp 548 ld8 r22=[r31],16 // rsc 549 ;; 550{ .mmi 551 ld8 r23=[r30],16 // fpsr 552 ld8 r24=[r31],16 // psr 553 extr.u r28=r20,61,3 554 ;; 555} 556{ .mmi 557 ld8.fill r1=[r30],16 // gp 558 ld8 r25=[r31],16 // ndirty 559 cmp.le p14,p15=5,r28 560 ;; 561} 562{ .mmb 563 ld8 r26=[r30] // cfm 564 ld8 r19=[r31] // ip 565 nop 0 566 ;; 567} 568{ .mib 569 // Switch register stack 570 alloc r30=ar.pfs,0,0,0,0 // discard current frame 571 shl r31=r25,16 // value for ar.rsc 572 nop 0 573 ;; 574} 575 // The loadrs can fault if the backing store is not currently 576 // mapped. We assured forward progress by getting everything we 577 // need from the trapframe so that we don't care if the CPU 578 // purges that translation when it needs to insert a new one for 579 // the backing store. 580{ .mmi 581 mov ar.rsc=r31 // setup for loadrs 582 mov ar.k7=r16 583(p15) mov r13=r29 584 ;; 585} 586exception_restore_restart: 587{ .mmi 588 mov r30=ar.bspstore 589 ;; 590 loadrs // load user regs 591 nop 0 592 ;; 593} 594{ .mmi 595 mov r31=ar.bspstore 596 ;; 597 mov ar.bspstore=r20 598 dep r31=0,r31,0,13 // 8KB aligned 599 ;; 600} 601{ .mmb 602 mov ar.k6=r31 603 mov ar.rnat=r21 604 nop 0 605 ;; 606} 607{ .mmb 608 mov ar.unat=r17 609 mov cr.iip=r19 610 nop 0 611} 612{ .mmi 613 mov cr.ipsr=r24 614 mov cr.ifs=r26 615 mov pr=r18,0x1ffff 616 ;; 617} 618{ .mmb 619 mov ar.rsc=r22 620 mov ar.fpsr=r23 621 rfi 622 ;; 623} 624END(exception_restore) 625 626/* 627 * Call exception_save_regs to preserve the interrupted state in a 628 * trapframe. Note that we don't use a call instruction because we 629 * must be careful not to lose track of the RSE state. We then call 630 * trap() with the value of _n_ as an argument to handle the 631 * exception. We arrange for trap() to return to exception_restore 632 * which will restore the interrupted state before executing an rfi to 633 * resume it. 634 */ 635#define CALL(_func_, _n_, _ifa_) \ 636{ .mib ; \ 637 mov r17=_ifa_ ; \ 638 mov r16=ip ; \ 639 br.sptk exception_save ;; \ 640} ; \ 641{ .mmi ; \ 642 alloc r15=ar.pfs,0,0,2,0 ;; \ 643(p11) ssm psr.i ; \ 644 mov out0=_n_ ;; \ 645} ; \ 646{ .mib ; \ 647(p11) srlz.d ; \ 648 add out1=16,sp ; \ 649 br.call.sptk rp=_func_ ;; \ 650} ; \ 651{ .mfb ; \ 652 nop 0 ; \ 653 nop 0 ; \ 654 br.sptk exception_restore ;; \ 655} 656 657#define IVT_ENTRY(name, offset) \ 658 .org ia64_vector_table + offset; \ 659 .global ivt_##name; \ 660 .proc ivt_##name; \ 661 .prologue; \ 662 .unwabi @svr4, 'I'; \ 663 .save rp, r0; \ 664 .body; \ 665ivt_##name: \ 666 XTRACE(offset) 667 668#define IVT_END(name) \ 669 .endp ivt_##name 670 671#ifdef COMPAT_IA32 672#define IA32_TRAP ia32_trap 673#else 674#define IA32_TRAP trap 675#endif 676 677/* 678 * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64 679 * bundles per vector and 48 slots with 16 bundles per vector. 680 */ 681 682 .section .text.ivt,"ax" 683 684 .align 32768 685 .global ia64_vector_table 686 .size ia64_vector_table, 32768 687ia64_vector_table: 688 689IVT_ENTRY(VHPT_Translation, 0x0000) 690 CALL(trap, 0, cr.ifa) 691IVT_END(VHPT_Translation) 692 693IVT_ENTRY(Instruction_TLB, 0x0400) 694 mov r16=cr.ifa 695 mov r17=pr 696 ;; 697 thash r18=r16 698 ttag r19=r16 699 ;; 700 add r21=16,r18 // tag 701 add r20=24,r18 // collision chain 702 ;; 703 ld8 r21=[r21] // check VHPT tag 704 ld8 r20=[r20] // bucket head 705 ;; 706 cmp.ne p15,p0=r21,r19 707(p15) br.dpnt.few 1f 708 ;; 709 ld8 r21=[r18] // read pte 710 ;; 711 itc.i r21 // insert pte 712 mov pr=r17,0x1ffff 713 ;; 714 rfi // done 715 ;; 7161: rsm psr.dt // turn off data translations 717 dep r20=0,r20,61,3 // convert vhpt ptr to physical 718 ;; 719 srlz.d // serialize 720 ld8 r20=[r20] // first entry 721 ;; 7222: cmp.eq p15,p0=r0,r20 // done? 723(p15) br.cond.spnt.few 9f // bail if done 724 ;; 725 add r21=16,r20 // tag location 726 ;; 727 ld8 r21=[r21] // read tag 728 ;; 729 cmp.ne p15,p0=r21,r19 // compare tags 730(p15) br.cond.sptk.few 3f // if not, read next in chain 731 ;; 732 ld8 r21=[r20],8 // read pte 733 ;; 734 ld8 r22=[r20] // read rest of pte 735 ;; 736 dep r18=0,r18,61,3 // convert vhpt ptr to physical 737 ;; 738 add r20=16,r18 // address of tag 739 ;; 740 ld8.acq r23=[r20] // read old tag 741 ;; 742 dep r23=-1,r23,63,1 // set ti bit 743 ;; 744 st8.rel [r20]=r23 // store old tag + ti 745 ;; 746 mf // make sure everyone sees 747 ;; 748 st8 [r18]=r21,8 // store pte 749 ;; 750 st8 [r18]=r22,8 751 ;; 752 st8.rel [r18]=r19 // store new tag 753 ;; 754 itc.i r21 // and place in TLB 755 ssm psr.dt 756 ;; 757 srlz.d 758 mov pr=r17,0x1ffff // restore predicates 759 rfi 760 ;; 7613: add r20=24,r20 // next in chain 762 ;; 763 ld8 r20=[r20] // read chain 764 br.cond.sptk.few 2b // loop 765 ;; 7669: ssm psr.dt 767 mov pr=r17,0x1ffff // restore predicates 768 ;; 769 srlz.d 770 ;; 771 CALL(trap, 20, cr.ifa) // Page Not Present trap 772IVT_END(Instruction_TLB) 773 774IVT_ENTRY(Data_TLB, 0x0800) 775 mov r16=cr.ifa 776 mov r17=pr 777 ;; 778 thash r18=r16 779 ttag r19=r16 780 ;; 781 add r21=16,r18 // tag 782 add r20=24,r18 // collision chain 783 ;; 784 ld8 r21=[r21] // check VHPT tag 785 ld8 r20=[r20] // bucket head 786 ;; 787 cmp.ne p15,p0=r21,r19 788(p15) br.dpnt.few 1f 789 ;; 790 ld8 r21=[r18] // read pte 791 ;; 792 itc.d r21 // insert pte 793 mov pr=r17,0x1ffff 794 ;; 795 rfi // done 796 ;; 7971: rsm psr.dt // turn off data translations 798 dep r20=0,r20,61,3 // convert vhpt ptr to physical 799 ;; 800 srlz.d // serialize 801 ld8 r20=[r20] // first entry 802 ;; 8032: cmp.eq p15,p0=r0,r20 // done? 804(p15) br.cond.spnt.few 9f // bail if done 805 ;; 806 add r21=16,r20 // tag location 807 ;; 808 ld8 r21=[r21] // read tag 809 ;; 810 cmp.ne p15,p0=r21,r19 // compare tags 811(p15) br.cond.sptk.few 3f // if not, read next in chain 812 ;; 813 ld8 r21=[r20],8 // read pte 814 ;; 815 ld8 r22=[r20] // read rest of pte 816 ;; 817 dep r18=0,r18,61,3 // convert vhpt ptr to physical 818 ;; 819 add r20=16,r18 // address of tag 820 ;; 821 ld8.acq r23=[r20] // read old tag 822 ;; 823 dep r23=-1,r23,63,1 // set ti bit 824 ;; 825 st8.rel [r20]=r23 // store old tag + ti 826 ;; 827 mf // make sure everyone sees 828 ;; 829 st8 [r18]=r21,8 // store pte 830 ;; 831 st8 [r18]=r22,8 832 ;; 833 st8.rel [r18]=r19 // store new tag 834 ;; 835 itc.d r21 // and place in TLB 836 ssm psr.dt 837 ;; 838 srlz.d 839 mov pr=r17,0x1ffff // restore predicates 840 rfi 841 ;; 8423: add r20=24,r20 // next in chain 843 ;; 844 ld8 r20=[r20] // read chain 845 br.cond.sptk.few 2b // loop 846 ;; 8479: ssm psr.dt 848 mov pr=r17,0x1ffff // restore predicates 849 ;; 850 srlz.d 851 ;; 852 CALL(trap, 20, cr.ifa) // Page Not Present trap 853IVT_END(Data_TLB) 854 855IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00) 856 mov r16=cr.ifa // where did it happen 857 mov r18=pr // save predicates 858 ;; 859 extr.u r17=r16,61,3 // get region number 860 ;; 861 cmp.ge p13,p0=5,r17 // RR0-RR5? 862 cmp.eq p15,p14=7,r17 // RR7->p15, RR6->p14 863(p13) br.spnt 9f 864 ;; 865(p15) movl r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 866 PTE_AR_RX+PTE_ED 867(p14) movl r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 868 PTE_AR_RX 869 ;; 870 dep r16=0,r16,50,14 // clear bits above PPN 871 ;; 872 dep r16=r17,r16,0,12 // put pte bits in 0..11 873 ;; 874 itc.i r16 875 mov pr=r18,0x1ffff // restore predicates 876 ;; 877 rfi 878 ;; 8799: mov pr=r18,0x1ffff // restore predicates 880 CALL(trap, 3, cr.ifa) 881IVT_END(Alternate_Instruction_TLB) 882 883IVT_ENTRY(Alternate_Data_TLB, 0x1000) 884 mov r16=cr.ifa // where did it happen 885 mov r18=pr // save predicates 886 ;; 887 extr.u r17=r16,61,3 // get region number 888 ;; 889 cmp.ge p13,p0=5,r17 // RR0-RR5? 890 cmp.eq p15,p14=7,r17 // RR7->p15, RR6->p14 891(p13) br.spnt 9f 892 ;; 893(p15) movl r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 894 PTE_AR_RW+PTE_ED 895(p14) movl r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \ 896 PTE_AR_RW 897 ;; 898 dep r16=0,r16,50,14 // clear bits above PPN 899 ;; 900 dep r16=r17,r16,0,12 // put pte bits in 0..11 901 ;; 902 itc.d r16 903 mov pr=r18,0x1ffff // restore predicates 904 ;; 905 rfi 906 ;; 9079: mov pr=r18,0x1ffff // restore predicates 908 CALL(trap, 4, cr.ifa) 909IVT_END(Alternate_Data_TLB) 910 911IVT_ENTRY(Data_Nested_TLB, 0x1400) 912 // See exception_save_restart and exception_restore_restart for the 913 // contexts that may cause a data nested TLB. We can only use the 914 // banked general registers and predicates, but don't use: 915 // p14 & p15 - Set in exception save 916 // r16 & r17 - Arguments to exception save 917 // r30 - Faulting address (modulo page size) 918 // We assume r30 has the virtual addresses that relate to the data 919 // nested TLB fault. The address does not have to be exact, as long 920 // as it's in the same page. We use physical addressing to avoid 921 // double nested faults. Since all virtual addresses we encounter 922 // here are direct mapped region 7 addresses, we have no problem 923 // constructing physical addresses. 924{ .mlx 925 rsm psr.dt 926 movl r27=ia64_kptdir 927 ;; 928} 929{ .mii 930 srlz.d 931 dep r27=0,r27,61,3 932 ;; 933 extr.u r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3 // dir L0 index 934} 935{ .mii 936 ld8 r27=[r27] // dir L0 page 937 extr.u r29=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3 // dir L1 index 938 ;; 939 dep r27=0,r27,61,3 940 ;; 941} 942{ .mmi 943 shladd r27=r28,3,r27 944 ;; 945 ld8 r27=[r27] // dir L1 page 946 extr.u r28=r30,PAGE_SHIFT,PAGE_SHIFT-5 // pte index 947 ;; 948} 949{ .mmi 950 shladd r27=r29,3,r27 951 ;; 952 mov r29=rr[r30] 953 dep r27=0,r27,61,3 954 ;; 955} 956{ .mii 957 ld8 r27=[r27] // pte page 958 shl r28=r28,5 959 dep r29=0,r29,0,2 960 ;; 961} 962{ .mmi 963 add r27=r28,r27 964 ;; 965 mov cr.ifa=r30 966 dep r27=0,r27,61,3 967 ;; 968} 969{ .mmi 970 ld8 r28=[r27] // pte 971 ;; 972 mov cr.itir=r29 973 or r28=PTE_DIRTY+PTE_ACCESSED,r28 974 ;; 975} 976{ .mlx 977 st8 [r27]=r28 978 movl r29=exception_save_restart 979 ;; 980} 981{ .mmi 982 itc.d r28 983 ;; 984 ssm psr.dt 985 cmp.eq p12,p13=r26,r29 986 ;; 987} 988{ .mbb 989 srlz.d 990(p12) br.sptk exception_save_restart 991(p13) br.sptk exception_restore_restart 992 ;; 993} 994IVT_END(Data_Nested_TLB) 995 996IVT_ENTRY(Instruction_Key_Miss, 0x1800) 997 CALL(trap, 6, cr.ifa) 998IVT_END(Instruction_Key_Miss) 999 1000IVT_ENTRY(Data_Key_Miss, 0x1c00) 1001 CALL(trap, 7, cr.ifa) 1002IVT_END(Data_Key_Miss) 1003 1004IVT_ENTRY(Dirty_Bit, 0x2000) 1005 mov r16=cr.ifa 1006 mov r17=pr 1007 ;; 1008 thash r18=r16 1009 ;; 1010 ttag r19=r16 1011 add r20=24,r18 // collision chain 1012 ;; 1013 ld8 r20=[r20] // bucket head 1014 ;; 1015 rsm psr.dt // turn off data translations 1016 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1017 ;; 1018 srlz.d // serialize 1019 ld8 r20=[r20] // first entry 1020 ;; 10211: cmp.eq p15,p0=r0,r20 // done? 1022(p15) br.cond.spnt.few 9f // bail if done 1023 ;; 1024 add r21=16,r20 // tag location 1025 ;; 1026 ld8 r21=[r21] // read tag 1027 ;; 1028 cmp.ne p15,p0=r21,r19 // compare tags 1029(p15) br.cond.sptk.few 2f // if not, read next in chain 1030 ;; 1031 ld8 r21=[r20] // read pte 1032 mov r22=PTE_DIRTY+PTE_ACCESSED 1033 ;; 1034 or r21=r22,r21 // set dirty & access bit 1035 ;; 1036 st8 [r20]=r21,8 // store back 1037 ;; 1038 ld8 r22=[r20] // read rest of pte 1039 ;; 1040 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1041 ;; 1042 add r20=16,r18 // address of tag 1043 ;; 1044 ld8.acq r23=[r20] // read old tag 1045 ;; 1046 dep r23=-1,r23,63,1 // set ti bit 1047 ;; 1048 st8.rel [r20]=r23 // store old tag + ti 1049 ;; 1050 mf // make sure everyone sees 1051 ;; 1052 st8 [r18]=r21,8 // store pte 1053 ;; 1054 st8 [r18]=r22,8 1055 ;; 1056 st8.rel [r18]=r19 // store new tag 1057 ;; 1058 itc.d r21 // and place in TLB 1059 ssm psr.dt 1060 ;; 1061 srlz.d 1062 mov pr=r17,0x1ffff // restore predicates 1063 rfi 1064 ;; 10652: add r20=24,r20 // next in chain 1066 ;; 1067 ld8 r20=[r20] // read chain 1068 br.cond.sptk.few 1b // loop 1069 ;; 10709: ssm psr.dt 1071 mov pr=r17,0x1ffff // restore predicates 1072 ;; 1073 srlz.d 1074 ;; 1075 CALL(trap, 8, cr.ifa) // die horribly 1076IVT_END(Dirty_Bit) 1077 1078IVT_ENTRY(Instruction_Access_Bit, 0x2400) 1079 mov r16=cr.ifa 1080 mov r17=pr 1081 ;; 1082 thash r18=r16 1083 ;; 1084 ttag r19=r16 1085 add r20=24,r18 // collision chain 1086 ;; 1087 ld8 r20=[r20] // bucket head 1088 ;; 1089 rsm psr.dt // turn off data translations 1090 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1091 ;; 1092 srlz.d // serialize 1093 ld8 r20=[r20] // first entry 1094 ;; 10951: cmp.eq p15,p0=r0,r20 // done? 1096(p15) br.cond.spnt.few 9f // bail if done 1097 ;; 1098 add r21=16,r20 // tag location 1099 ;; 1100 ld8 r21=[r21] // read tag 1101 ;; 1102 cmp.ne p15,p0=r21,r19 // compare tags 1103(p15) br.cond.sptk.few 2f // if not, read next in chain 1104 ;; 1105 ld8 r21=[r20] // read pte 1106 mov r22=PTE_ACCESSED 1107 ;; 1108 or r21=r22,r21 // set accessed bit 1109 ;; 1110 st8 [r20]=r21,8 // store back 1111 ;; 1112 ld8 r22=[r20] // read rest of pte 1113 ;; 1114 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1115 ;; 1116 add r20=16,r18 // address of tag 1117 ;; 1118 ld8.acq r23=[r20] // read old tag 1119 ;; 1120 dep r23=-1,r23,63,1 // set ti bit 1121 ;; 1122 st8.rel [r20]=r23 // store old tag + ti 1123 ;; 1124 mf // make sure everyone sees 1125 ;; 1126 st8 [r18]=r21,8 // store pte 1127 ;; 1128 st8 [r18]=r22,8 1129 ;; 1130 st8.rel [r18]=r19 // store new tag 1131 ;; 1132 itc.i r21 // and place in TLB 1133 ssm psr.dt 1134 ;; 1135 srlz.d 1136 mov pr=r17,0x1ffff // restore predicates 1137 rfi // walker will retry the access 1138 ;; 11392: add r20=24,r20 // next in chain 1140 ;; 1141 ld8 r20=[r20] // read chain 1142 br.cond.sptk.few 1b // loop 1143 ;; 11449: ssm psr.dt 1145 mov pr=r17,0x1ffff // restore predicates 1146 ;; 1147 srlz.d 1148 ;; 1149 CALL(trap, 9, cr.ifa) 1150IVT_END(Instruction_Access_Bit) 1151 1152IVT_ENTRY(Data_Access_Bit, 0x2800) 1153 mov r16=cr.ifa 1154 mov r17=pr 1155 ;; 1156 thash r18=r16 1157 ;; 1158 ttag r19=r16 1159 add r20=24,r18 // collision chain 1160 ;; 1161 ld8 r20=[r20] // bucket head 1162 ;; 1163 rsm psr.dt // turn off data translations 1164 dep r20=0,r20,61,3 // convert vhpt ptr to physical 1165 ;; 1166 srlz.d // serialize 1167 ld8 r20=[r20] // first entry 1168 ;; 11691: cmp.eq p15,p0=r0,r20 // done? 1170(p15) br.cond.spnt.few 9f // bail if done 1171 ;; 1172 add r21=16,r20 // tag location 1173 ;; 1174 ld8 r21=[r21] // read tag 1175 ;; 1176 cmp.ne p15,p0=r21,r19 // compare tags 1177(p15) br.cond.sptk.few 2f // if not, read next in chain 1178 ;; 1179 ld8 r21=[r20] // read pte 1180 mov r22=PTE_ACCESSED 1181 ;; 1182 or r21=r22,r21 // set accessed bit 1183 ;; 1184 st8 [r20]=r21,8 // store back 1185 ;; 1186 ld8 r22=[r20] // read rest of pte 1187 ;; 1188 dep r18=0,r18,61,3 // convert vhpt ptr to physical 1189 ;; 1190 add r20=16,r18 // address of tag 1191 ;; 1192 ld8.acq r23=[r20] // read old tag 1193 ;; 1194 dep r23=-1,r23,63,1 // set ti bit 1195 ;; 1196 st8.rel [r20]=r23 // store old tag + ti 1197 ;; 1198 mf // make sure everyone sees 1199 ;; 1200 st8 [r18]=r21,8 // store pte 1201 ;; 1202 st8 [r18]=r22,8 1203 ;; 1204 st8.rel [r18]=r19 // store new tag 1205 ;; 1206 itc.d r21 // and place in TLB 1207 ssm psr.dt 1208 ;; 1209 srlz.d 1210 mov pr=r17,0x1ffff // restore predicates 1211 rfi // walker will retry the access 1212 ;; 12132: add r20=24,r20 // next in chain 1214 ;; 1215 ld8 r20=[r20] // read chain 1216 br.cond.sptk.few 1b // loop 1217 ;; 12189: ssm psr.dt 1219 mov pr=r17,0x1ffff // restore predicates 1220 ;; 1221 srlz.d 1222 ;; 1223 CALL(trap, 10, cr.ifa) 1224IVT_END(Data_Access_Bit) 1225 1226IVT_ENTRY(Break_Instruction, 0x2c00) 1227{ .mib 1228 mov r17=cr.iim 1229 mov r16=ip 1230 br.sptk exception_save 1231 ;; 1232} 1233{ .mmi 1234 alloc r15=ar.pfs,0,0,2,0 1235 ;; 1236(p11) ssm psr.i 1237 mov out0=11 1238 ;; 1239} 1240{ .mmi 1241 flushrs 1242 ;; 1243(p11) srlz.d 1244 add out1=16,sp 1245} 1246{ .mfb 1247 nop 0 1248 nop 0 1249 br.call.sptk rp=trap 1250 ;; 1251} 1252{ .mfb 1253 nop 0 1254 nop 0 1255 br.sptk exception_restore 1256 ;; 1257} 1258IVT_END(Break_Instruction) 1259 1260IVT_ENTRY(External_Interrupt, 0x3000) 1261{ .mib 1262 mov r17=cr.ivr // Put the vector in the trap frame. 1263 mov r16=ip 1264 br.sptk exception_save 1265 ;; 1266} 1267{ .mfb 1268 alloc r15=ar.pfs,0,0,1,0 1269 nop 0 1270 nop 0 1271 ;; 1272} 1273{ .mfb 1274 add out0=16,sp 1275 nop 0 1276 br.call.sptk rp=interrupt 1277 ;; 1278} 1279{ .mfb 1280 nop 0 1281 nop 0 1282 br.sptk exception_restore 1283 ;; 1284} 1285IVT_END(External_Interrupt) 1286 1287IVT_ENTRY(Reserved_3400, 0x3400) 1288 CALL(trap, 13, cr.ifa) 1289IVT_END(Reserved_3400) 1290 1291IVT_ENTRY(Reserved_3800, 0x3800) 1292 CALL(trap, 14, cr.ifa) 1293IVT_END(Reserved_3800) 1294 1295IVT_ENTRY(Reserved_3c00, 0x3c00) 1296 CALL(trap, 15, cr.ifa) 1297IVT_END(Reserved_3c00) 1298 1299IVT_ENTRY(Reserved_4000, 0x4000) 1300 CALL(trap, 16, cr.ifa) 1301IVT_END(Reserved_4000) 1302 1303IVT_ENTRY(Reserved_4400, 0x4400) 1304 CALL(trap, 17, cr.ifa) 1305IVT_END(Reserved_4400) 1306 1307IVT_ENTRY(Reserved_4800, 0x4800) 1308 CALL(trap, 18, cr.ifa) 1309IVT_END(Reserved_4800) 1310 1311IVT_ENTRY(Reserved_4c00, 0x4c00) 1312 CALL(trap, 19, cr.ifa) 1313IVT_END(Reserved_4c00) 1314 1315IVT_ENTRY(Page_Not_Present, 0x5000) 1316 CALL(trap, 20, cr.ifa) 1317IVT_END(Page_Not_Present) 1318 1319IVT_ENTRY(Key_Permission, 0x5100) 1320 CALL(trap, 21, cr.ifa) 1321IVT_END(Key_Permission) 1322 1323IVT_ENTRY(Instruction_Access_Rights, 0x5200) 1324 CALL(trap, 22, cr.ifa) 1325IVT_END(Instruction_Access_Rights) 1326 1327IVT_ENTRY(Data_Access_Rights, 0x5300) 1328 CALL(trap, 23, cr.ifa) 1329IVT_END(Data_Access_Rights) 1330 1331IVT_ENTRY(General_Exception, 0x5400) 1332 CALL(trap, 24, cr.ifa) 1333IVT_END(General_Exception) 1334 1335IVT_ENTRY(Disabled_FP_Register, 0x5500) 1336 CALL(trap, 25, cr.ifa) 1337IVT_END(Disabled_FP_Register) 1338 1339IVT_ENTRY(NaT_Consumption, 0x5600) 1340 CALL(trap, 26, cr.ifa) 1341IVT_END(NaT_Consumption) 1342 1343IVT_ENTRY(Speculation, 0x5700) 1344 CALL(trap, 27, cr.iim) 1345IVT_END(Speculation) 1346 1347IVT_ENTRY(Reserved_5800, 0x5800) 1348 CALL(trap, 28, cr.ifa) 1349IVT_END(Reserved_5800) 1350 1351IVT_ENTRY(Debug, 0x5900) 1352 CALL(trap, 29, cr.ifa) 1353IVT_END(Debug) 1354 1355IVT_ENTRY(Unaligned_Reference, 0x5a00) 1356 CALL(trap, 30, cr.ifa) 1357IVT_END(Unaligned_Reference) 1358 1359IVT_ENTRY(Unsupported_Data_Reference, 0x5b00) 1360 CALL(trap, 31, cr.ifa) 1361IVT_END(Unsupported_Data_Reference) 1362 1363IVT_ENTRY(Floating_Point_Fault, 0x5c00) 1364 CALL(trap, 32, cr.ifa) 1365IVT_END(Floating_Point_Fault) 1366 1367IVT_ENTRY(Floating_Point_Trap, 0x5d00) 1368 CALL(trap, 33, cr.ifa) 1369IVT_END(Floating_Point_Trap) 1370 1371IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00) 1372 CALL(trap, 34, cr.ifa) 1373IVT_END(Lower_Privilege_Transfer_Trap) 1374 1375IVT_ENTRY(Taken_Branch_Trap, 0x5f00) 1376 CALL(trap, 35, cr.ifa) 1377IVT_END(Taken_Branch_Trap) 1378 1379IVT_ENTRY(Single_Step_Trap, 0x6000) 1380 CALL(trap, 36, cr.ifa) 1381IVT_END(Single_Step_Trap) 1382 1383IVT_ENTRY(Reserved_6100, 0x6100) 1384 CALL(trap, 37, cr.ifa) 1385IVT_END(Reserved_6100) 1386 1387IVT_ENTRY(Reserved_6200, 0x6200) 1388 CALL(trap, 38, cr.ifa) 1389IVT_END(Reserved_6200) 1390 1391IVT_ENTRY(Reserved_6300, 0x6300) 1392 CALL(trap, 39, cr.ifa) 1393IVT_END(Reserved_6300) 1394 1395IVT_ENTRY(Reserved_6400, 0x6400) 1396 CALL(trap, 40, cr.ifa) 1397IVT_END(Reserved_6400) 1398 1399IVT_ENTRY(Reserved_6500, 0x6500) 1400 CALL(trap, 41, cr.ifa) 1401IVT_END(Reserved_6500) 1402 1403IVT_ENTRY(Reserved_6600, 0x6600) 1404 CALL(trap, 42, cr.ifa) 1405IVT_END(Reserved_6600) 1406 1407IVT_ENTRY(Reserved_6700, 0x6700) 1408 CALL(trap, 43, cr.ifa) 1409IVT_END(Reserved_6700) 1410 1411IVT_ENTRY(Reserved_6800, 0x6800) 1412 CALL(trap, 44, cr.ifa) 1413IVT_END(Reserved_6800) 1414 1415IVT_ENTRY(IA_32_Exception, 0x6900) 1416 CALL(IA32_TRAP, 45, cr.ifa) 1417IVT_END(IA_32_Exception) 1418 1419IVT_ENTRY(IA_32_Intercept, 0x6a00) 1420 CALL(IA32_TRAP, 46, cr.iim) 1421IVT_END(IA_32_Intercept) 1422 1423IVT_ENTRY(IA_32_Interrupt, 0x6b00) 1424 CALL(IA32_TRAP, 47, cr.ifa) 1425IVT_END(IA_32_Interrupt) 1426 1427IVT_ENTRY(Reserved_6c00, 0x6c00) 1428 CALL(trap, 48, cr.ifa) 1429IVT_END(Reserved_6c00) 1430 1431IVT_ENTRY(Reserved_6d00, 0x6d00) 1432 CALL(trap, 49, cr.ifa) 1433IVT_END(Reserved_6d00) 1434 1435IVT_ENTRY(Reserved_6e00, 0x6e00) 1436 CALL(trap, 50, cr.ifa) 1437IVT_END(Reserved_6e00) 1438 1439IVT_ENTRY(Reserved_6f00, 0x6f00) 1440 CALL(trap, 51, cr.ifa) 1441IVT_END(Reserved_6f00) 1442 1443IVT_ENTRY(Reserved_7000, 0x7000) 1444 CALL(trap, 52, cr.ifa) 1445IVT_END(Reserved_7000) 1446 1447IVT_ENTRY(Reserved_7100, 0x7100) 1448 CALL(trap, 53, cr.ifa) 1449IVT_END(Reserved_7100) 1450 1451IVT_ENTRY(Reserved_7200, 0x7200) 1452 CALL(trap, 54, cr.ifa) 1453IVT_END(Reserved_7200) 1454 1455IVT_ENTRY(Reserved_7300, 0x7300) 1456 CALL(trap, 55, cr.ifa) 1457IVT_END(Reserved_7300) 1458 1459IVT_ENTRY(Reserved_7400, 0x7400) 1460 CALL(trap, 56, cr.ifa) 1461IVT_END(Reserved_7400) 1462 1463IVT_ENTRY(Reserved_7500, 0x7500) 1464 CALL(trap, 57, cr.ifa) 1465IVT_END(Reserved_7500) 1466 1467IVT_ENTRY(Reserved_7600, 0x7600) 1468 CALL(trap, 58, cr.ifa) 1469IVT_END(Reserved_7600) 1470 1471IVT_ENTRY(Reserved_7700, 0x7700) 1472 CALL(trap, 59, cr.ifa) 1473IVT_END(Reserved_7700) 1474 1475IVT_ENTRY(Reserved_7800, 0x7800) 1476 CALL(trap, 60, cr.ifa) 1477IVT_END(Reserved_7800) 1478 1479IVT_ENTRY(Reserved_7900, 0x7900) 1480 CALL(trap, 61, cr.ifa) 1481IVT_END(Reserved_7900) 1482 1483IVT_ENTRY(Reserved_7a00, 0x7a00) 1484 CALL(trap, 62, cr.ifa) 1485IVT_END(Reserved_7a00) 1486 1487IVT_ENTRY(Reserved_7b00, 0x7b00) 1488 CALL(trap, 63, cr.ifa) 1489IVT_END(Reserved_7b00) 1490 1491IVT_ENTRY(Reserved_7c00, 0x7c00) 1492 CALL(trap, 64, cr.ifa) 1493IVT_END(Reserved_7c00) 1494 1495IVT_ENTRY(Reserved_7d00, 0x7d00) 1496 CALL(trap, 65, cr.ifa) 1497IVT_END(Reserved_7d00) 1498 1499IVT_ENTRY(Reserved_7e00, 0x7e00) 1500 CALL(trap, 66, cr.ifa) 1501IVT_END(Reserved_7e00) 1502 1503IVT_ENTRY(Reserved_7f00, 0x7f00) 1504 CALL(trap, 67, cr.ifa) 1505IVT_END(Reserved_7f00) 1506