vf610.dtsi revision 262569 
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "skeleton.dtsi"
11#include "vf610-pinfunc.h"
12#include <dt-bindings/clock/vf610-clock.h>
13
14/ {
15	aliases {
16		serial0 = &uart0;
17		serial1 = &uart1;
18		serial2 = &uart2;
19		serial3 = &uart3;
20		serial4 = &uart4;
21		serial5 = &uart5;
22		gpio0 = &gpio1;
23		gpio1 = &gpio2;
24		gpio2 = &gpio3;
25		gpio3 = &gpio4;
26		gpio4 = &gpio5;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		cpu@0 {
34			compatible = "arm,cortex-a5";
35			device_type = "cpu";
36			reg = <0x0>;
37			next-level-cache = <&L2>;
38		};
39	};
40
41	clocks {
42		#address-cells = <1>;
43		#size-cells = <0>;
44
45		sxosc {
46			compatible = "fixed-clock";
47			clock-frequency = <32768>;
48		};
49
50		fxosc {
51			compatible = "fixed-clock";
52			clock-frequency = <24000000>;
53		};
54	};
55
56	soc {
57		#address-cells = <1>;
58		#size-cells = <1>;
59		compatible = "simple-bus";
60		interrupt-parent = <&intc>;
61		ranges;
62
63		aips0: aips-bus@40000000 {
64			compatible = "fsl,aips-bus", "simple-bus";
65			#address-cells = <1>;
66			#size-cells = <1>;
67			interrupt-parent = <&intc>;
68			reg = <0x40000000 0x70000>;
69			ranges;
70
71			intc: interrupt-controller@40002000 {
72				compatible = "arm,cortex-a9-gic";
73				#interrupt-cells = <3>;
74				#address-cells = <1>;
75				#size-cells = <1>;
76				interrupt-controller;
77				reg = <0x40003000 0x1000>,
78				      <0x40002100 0x100>;
79			};
80
81			L2: l2-cache@40006000 {
82				compatible = "arm,pl310-cache";
83				reg = <0x40006000 0x1000>;
84				cache-unified;
85				cache-level = <2>;
86				arm,data-latency = <1 1 1>;
87				arm,tag-latency = <2 2 2>;
88			};
89
90			uart0: serial@40027000 {
91				compatible = "fsl,vf610-lpuart";
92				reg = <0x40027000 0x1000>;
93				interrupts = <0 61 0x00>;
94				clocks = <&clks VF610_CLK_UART0>;
95				clock-names = "ipg";
96				status = "disabled";
97			};
98
99			uart1: serial@40028000 {
100				compatible = "fsl,vf610-lpuart";
101				reg = <0x40028000 0x1000>;
102				interrupts = <0 62 0x04>;
103				clocks = <&clks VF610_CLK_UART1>;
104				clock-names = "ipg";
105				status = "disabled";
106			};
107
108			uart2: serial@40029000 {
109				compatible = "fsl,vf610-lpuart";
110				reg = <0x40029000 0x1000>;
111				interrupts = <0 63 0x04>;
112				clocks = <&clks VF610_CLK_UART2>;
113				clock-names = "ipg";
114				status = "disabled";
115			};
116
117			uart3: serial@4002a000 {
118				compatible = "fsl,vf610-lpuart";
119				reg = <0x4002a000 0x1000>;
120				interrupts = <0 64 0x04>;
121				clocks = <&clks VF610_CLK_UART3>;
122				clock-names = "ipg";
123				status = "disabled";
124			};
125
126			dspi0: dspi0@4002c000 {
127				#address-cells = <1>;
128				#size-cells = <0>;
129				compatible = "fsl,vf610-dspi";
130				reg = <0x4002c000 0x1000>;
131				interrupts = <0 67 0x04>;
132				clocks = <&clks VF610_CLK_DSPI0>;
133				clock-names = "dspi";
134				spi-num-chipselects = <5>;
135				status = "disabled";
136			};
137
138			sai2: sai@40031000 {
139				compatible = "fsl,vf610-sai";
140				reg = <0x40031000 0x1000>;
141				interrupts = <0 86 0x04>;
142				clocks = <&clks VF610_CLK_SAI2>;
143				clock-names = "sai";
144				status = "disabled";
145			};
146
147			pit: pit@40037000 {
148				compatible = "fsl,vf610-pit";
149				reg = <0x40037000 0x1000>;
150				interrupts = <0 39 0x04>;
151				clocks = <&clks VF610_CLK_PIT>;
152				clock-names = "pit";
153			};
154
155			wdog@4003e000 {
156				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
157				reg = <0x4003e000 0x1000>;
158				clocks = <&clks VF610_CLK_WDT>;
159				clock-names = "wdog";
160			};
161
162			qspi0: quadspi@40044000 {
163				#address-cells = <1>;
164				#size-cells = <0>;
165				compatible = "fsl,vf610-qspi";
166				reg = <0x40044000 0x1000>;
167				interrupts = <0 24 0x04>;
168				clocks = <&clks VF610_CLK_QSPI0_EN>,
169					<&clks VF610_CLK_QSPI0>;
170				clock-names = "qspi_en", "qspi";
171				status = "disabled";
172			};
173
174			iomuxc: iomuxc@40048000 {
175				compatible = "fsl,vf610-iomuxc";
176				reg = <0x40048000 0x1000>;
177				#gpio-range-cells = <3>;
178
179				/* functions and groups pins */
180
181				dcu0 {
182					pinctrl_dcu0_1: dcu0grp_1 {
183						fsl,pins = <
184						VF610_PAD_PTB8__GPIO_30		0x42
185						VF610_PAD_PTE0__DCU0_HSYNC	0x42
186						VF610_PAD_PTE1__DCU0_VSYNC	0x42
187						VF610_PAD_PTE2__DCU0_PCLK	0x42
188						VF610_PAD_PTE4__DCU0_DE		0x42
189						VF610_PAD_PTE5__DCU0_R0		0x42
190						VF610_PAD_PTE6__DCU0_R1		0x42
191						VF610_PAD_PTE7__DCU0_R2		0x42
192						VF610_PAD_PTE8__DCU0_R3		0x42
193						VF610_PAD_PTE9__DCU0_R4		0x42
194						VF610_PAD_PTE10__DCU0_R5	0x42
195						VF610_PAD_PTE11__DCU0_R6	0x42
196						VF610_PAD_PTE12__DCU0_R7	0x42
197						VF610_PAD_PTE13__DCU0_G0	0x42
198						VF610_PAD_PTE14__DCU0_G1	0x42
199						VF610_PAD_PTE15__DCU0_G2	0x42
200						VF610_PAD_PTE16__DCU0_G3	0x42
201						VF610_PAD_PTE17__DCU0_G4	0x42
202						VF610_PAD_PTE18__DCU0_G5	0x42
203						VF610_PAD_PTE19__DCU0_G6	0x42
204						VF610_PAD_PTE20__DCU0_G7	0x42
205						VF610_PAD_PTE21__DCU0_B0	0x42
206						VF610_PAD_PTE22__DCU0_B1	0x42
207						VF610_PAD_PTE23__DCU0_B2	0x42
208						VF610_PAD_PTE24__DCU0_B3	0x42
209						VF610_PAD_PTE25__DCU0_B4	0x42
210						VF610_PAD_PTE26__DCU0_B5	0x42
211						VF610_PAD_PTE27__DCU0_B6	0x42
212						VF610_PAD_PTE28__DCU0_B7	0x42
213						>;
214					};
215				};
216
217				dspi0 {
218					pinctrl_dspi0_1: dspi0grp_1 {
219						fsl,pins = <
220						VF610_PAD_PTB19__DSPI0_CS0	0x1182
221						VF610_PAD_PTB20__DSPI0_SIN	0x1181
222						VF610_PAD_PTB21__DSPI0_SOUT	0x1182
223						VF610_PAD_PTB22__DSPI0_SCK	0x1182
224						>;
225					};
226				};
227
228				esdhc1 {
229					pinctrl_esdhc1_1: esdhc1grp_1 {
230						fsl,pins = <
231						VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
232						VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
233						VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
234						VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
235						VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
236						VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
237						VF610_PAD_PTA7__GPIO_134	0x219d
238						>;
239					};
240				};
241
242				fec0 {
243					pinctrl_fec0_1: fec0grp_1 {
244						fsl,pins = <
245						VF610_PAD_PTA6__RMII_CLKIN	0x30d1
246						VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d3
247						VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d1
248						VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
249						VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
250						VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
251						VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
252						VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
253						VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
254						VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
255						>;
256					};
257				};
258
259				fec1 {
260					pinctrl_fec1_1: fec1grp_1 {
261						fsl,pins = <
262						VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
263						VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
264						VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
265						VF610_PAD_PTC12__ENET_RMII_RXD1		0x30d1
266						VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
267						VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
268						VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
269						VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
270						VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
271						>;
272					};
273				};
274
275				i2c0 {
276					pinctrl_i2c0_1: i2c0grp_1 {
277						fsl,pins = <
278						VF610_PAD_PTB14__I2C0_SCL	0x30d3
279						VF610_PAD_PTB15__I2C0_SDA	0x30d3
280						>;
281					};
282				};
283
284				pwm0 {
285					pinctrl_pwm0_1: pwm0grp_1 {
286						fsl,pins = <
287						VF610_PAD_PTB0__FTM0_CH0	0x1582
288						VF610_PAD_PTB1__FTM0_CH1	0x1582
289						VF610_PAD_PTB2__FTM0_CH2	0x1582
290						VF610_PAD_PTB3__FTM0_CH3	0x1582
291						VF610_PAD_PTB6__FTM0_CH6	0x1582
292						VF610_PAD_PTB7__FTM0_CH7	0x1582
293						>;
294					};
295				};
296
297				qspi0 {
298					pinctrl_qspi0_1: qspi0grp_1 {
299						fsl,pins = <
300						VF610_PAD_PTD0__QSPI0_A_QSCK	0x307b
301						VF610_PAD_PTD1__QSPI0_A_CS0	0x307f
302						VF610_PAD_PTD2__QSPI0_A_DATA3	0x3073
303						VF610_PAD_PTD3__QSPI0_A_DATA2	0x3073
304						VF610_PAD_PTD4__QSPI0_A_DATA1	0x3073
305						VF610_PAD_PTD5__QSPI0_A_DATA0	0x307b
306						VF610_PAD_PTD7__QSPI0_B_QSCK	0x307b
307						VF610_PAD_PTD8__QSPI0_B_CS0	0x307f
308						VF610_PAD_PTD9__QSPI0_B_DATA3	0x3073
309						VF610_PAD_PTD10__QSPI0_B_DATA2	0x3073
310						VF610_PAD_PTD11__QSPI0_B_DATA1	0x3073
311						VF610_PAD_PTD12__QSPI0_B_DATA0	0x307b
312						>;
313					};
314				};
315
316				sai2 {
317					pinctrl_sai2_1: sai2grp_1 {
318						fsl,pins = <
319						VF610_PAD_PTA16__SAI2_TX_BCLK	0x02ed
320						VF610_PAD_PTA18__SAI2_TX_DATA	0x02ee
321						VF610_PAD_PTA19__SAI2_TX_SYNC	0x02ed
322						VF610_PAD_PTA21__SAI2_RX_BCLK	0x02ed
323						VF610_PAD_PTA22__SAI2_RX_DATA	0x02ed
324						VF610_PAD_PTA23__SAI2_RX_SYNC	0x02ed
325						VF610_PAD_PTB18__EXT_AUDIO_MCLK	0x02ed
326						>;
327					};
328				};
329
330				uart1 {
331					pinctrl_uart1_1: uart1grp_1 {
332						fsl,pins = <
333						VF610_PAD_PTB4__UART1_TX	0x21a2
334						VF610_PAD_PTB5__UART1_RX	0x21a1
335						>;
336					};
337				};
338
339				usbvbus {
340					pinctrl_usbvbus_1: usbvbusgrp_1 {
341						fsl,pins = <
342						VF610_PAD_PTA24__USB1_VBUS_EN	0x219c
343						VF610_PAD_PTA16__USB0_VBUS_EN	0x219c
344						>;
345					};
346				};
347
348			};
349
350			gpio1: gpio@40049000 {
351				compatible = "fsl,vf610-gpio";
352				reg = <0x40049000 0x1000 0x400ff000 0x40>;
353				interrupts = <0 107 0x04>;
354				gpio-controller;
355				#gpio-cells = <2>;
356				interrupt-controller;
357				#interrupt-cells = <2>;
358				gpio-ranges = <&iomuxc 0 0 32>;
359			};
360
361			gpio2: gpio@4004a000 {
362				compatible = "fsl,vf610-gpio";
363				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
364				interrupts = <0 108 0x04>;
365				gpio-controller;
366				#gpio-cells = <2>;
367				interrupt-controller;
368				#interrupt-cells = <2>;
369				gpio-ranges = <&iomuxc 0 32 32>;
370			};
371
372			gpio3: gpio@4004b000 {
373				compatible = "fsl,vf610-gpio";
374				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
375				interrupts = <0 109 0x04>;
376				gpio-controller;
377				#gpio-cells = <2>;
378				interrupt-controller;
379				#interrupt-cells = <2>;
380				gpio-ranges = <&iomuxc 0 64 32>;
381			};
382
383			gpio4: gpio@4004c000 {
384				compatible = "fsl,vf610-gpio";
385				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
386				interrupts = <0 110 0x04>;
387				gpio-controller;
388				#gpio-cells = <2>;
389				interrupt-controller;
390				#interrupt-cells = <2>;
391				gpio-ranges = <&iomuxc 0 96 32>;
392			};
393
394			gpio5: gpio@4004d000 {
395				compatible = "fsl,vf610-gpio";
396				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
397				interrupts = <0 111 0x04>;
398				gpio-controller;
399				#gpio-cells = <2>;
400				interrupt-controller;
401				#interrupt-cells = <2>;
402				gpio-ranges = <&iomuxc 0 128 7>;
403			};
404
405			anatop@40050000 {
406				compatible = "fsl,vf610-anatop";
407				reg = <0x40050000 0x1000>;
408			};
409
410			i2c0: i2c@40066000 {
411				#address-cells = <1>;
412				#size-cells = <0>;
413				compatible = "fsl,vf610-i2c";
414				reg = <0x40066000 0x1000>;
415				interrupts =<0 71 0x04>;
416				clocks = <&clks VF610_CLK_I2C0>;
417				clock-names = "ipg";
418				status = "disabled";
419			};
420
421			clks: ccm@4006b000 {
422				compatible = "fsl,vf610-ccm";
423				reg = <0x4006b000 0x1000>;
424				#clock-cells = <1>;
425			};
426		};
427
428		aips1: aips-bus@40080000 {
429			compatible = "fsl,aips-bus", "simple-bus";
430			#address-cells = <1>;
431			#size-cells = <1>;
432			reg = <0x40080000 0x80000>;
433			ranges;
434
435			uart4: serial@400a9000 {
436				compatible = "fsl,vf610-lpuart";
437				reg = <0x400a9000 0x1000>;
438				interrupts = <0 65 0x04>;
439				clocks = <&clks VF610_CLK_UART4>;
440				clock-names = "ipg";
441				status = "disabled";
442			};
443
444			uart5: serial@400aa000 {
445				compatible = "fsl,vf610-lpuart";
446				reg = <0x400aa000 0x1000>;
447				interrupts = <0 66 0x04>;
448				clocks = <&clks VF610_CLK_UART5>;
449				clock-names = "ipg";
450				status = "disabled";
451			};
452
453			fec0: ethernet@400d0000 {
454				compatible = "fsl,mvf600-fec";
455				reg = <0x400d0000 0x1000>;
456				interrupts = <0 78 0x04>;
457				clocks = <&clks VF610_CLK_ENET0>,
458					<&clks VF610_CLK_ENET0>,
459					<&clks VF610_CLK_ENET>;
460				clock-names = "ipg", "ahb", "ptp";
461				status = "disabled";
462			};
463
464			fec1: ethernet@400d1000 {
465				compatible = "fsl,mvf600-fec";
466				reg = <0x400d1000 0x1000>;
467				interrupts = <0 79 0x04>;
468				clocks = <&clks VF610_CLK_ENET1>,
469					<&clks VF610_CLK_ENET1>,
470					<&clks VF610_CLK_ENET>;
471				clock-names = "ipg", "ahb", "ptp";
472				status = "disabled";
473			};
474		};
475	};
476};
477