sama5d3.dtsi revision 270864
1/* 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC 4 * 5 * Copyright (C) 2013 Atmel, 6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 8 * Licensed under GPLv2 or later. 9 */ 10 11#include "skeleton.dtsi" 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/pinctrl/at91.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/clock/at91.h> 17 18/ { 19 model = "Atmel SAMA5D3 family SoC"; 20 compatible = "atmel,sama5d3", "atmel,sama5"; 21 interrupt-parent = <&aic>; 22 23 aliases { 24 serial0 = &dbgu; 25 serial1 = &usart0; 26 serial2 = &usart1; 27 serial3 = &usart2; 28 serial4 = &usart3; 29 gpio0 = &pioA; 30 gpio1 = &pioB; 31 gpio2 = &pioC; 32 gpio3 = &pioD; 33 gpio4 = &pioE; 34 tcb0 = &tcb0; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 ssc0 = &ssc0; 39 ssc1 = &ssc1; 40 pwm0 = &pwm0; 41 }; 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a5"; 48 reg = <0x0>; 49 }; 50 }; 51 52 pmu { 53 compatible = "arm,cortex-a5-pmu"; 54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; 55 }; 56 57 memory { 58 reg = <0x20000000 0x8000000>; 59 }; 60 61 clocks { 62 slow_xtal: slow_xtal { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 68 main_xtal: main_xtal { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 }; 73 74 adc_op_clk: adc_op_clk{ 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <20000000>; 78 }; 79 }; 80 81 ahb { 82 compatible = "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges; 86 87 apb { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 93 mmc0: mmc@f0000000 { 94 compatible = "atmel,hsmci"; 95 reg = <0xf0000000 0x600>; 96 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 97 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; 98 dma-names = "rxtx"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; 101 status = "disabled"; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 clocks = <&mci0_clk>; 105 clock-names = "mci_clk"; 106 }; 107 108 spi0: spi@f0004000 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 compatible = "atmel,at91rm9200-spi"; 112 reg = <0xf0004000 0x100>; 113 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 114 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, 115 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; 116 dma-names = "tx", "rx"; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_spi0>; 119 clocks = <&spi0_clk>; 120 clock-names = "spi_clk"; 121 status = "disabled"; 122 }; 123 124 ssc0: ssc@f0008000 { 125 compatible = "atmel,at91sam9g45-ssc"; 126 reg = <0xf0008000 0x4000>; 127 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; 128 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, 129 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; 130 dma-names = "tx", "rx"; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 133 clocks = <&ssc0_clk>; 134 clock-names = "pclk"; 135 status = "disabled"; 136 }; 137 138 tcb0: timer@f0010000 { 139 compatible = "atmel,at91sam9x5-tcb"; 140 reg = <0xf0010000 0x100>; 141 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 142 clocks = <&tcb0_clk>; 143 clock-names = "t0_clk"; 144 }; 145 146 i2c0: i2c@f0014000 { 147 compatible = "atmel,at91sam9x5-i2c"; 148 reg = <0xf0014000 0x4000>; 149 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; 150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, 151 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; 152 dma-names = "tx", "rx"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_i2c0>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&twi0_clk>; 158 status = "disabled"; 159 }; 160 161 i2c1: i2c@f0018000 { 162 compatible = "atmel,at91sam9x5-i2c"; 163 reg = <0xf0018000 0x4000>; 164 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; 165 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, 166 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; 167 dma-names = "tx", "rx"; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_i2c1>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 clocks = <&twi1_clk>; 173 status = "disabled"; 174 }; 175 176 usart0: serial@f001c000 { 177 compatible = "atmel,at91sam9260-usart"; 178 reg = <0xf001c000 0x100>; 179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_usart0>; 182 clocks = <&usart0_clk>; 183 clock-names = "usart"; 184 status = "disabled"; 185 }; 186 187 usart1: serial@f0020000 { 188 compatible = "atmel,at91sam9260-usart"; 189 reg = <0xf0020000 0x100>; 190 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_usart1>; 193 clocks = <&usart1_clk>; 194 clock-names = "usart"; 195 status = "disabled"; 196 }; 197 198 pwm0: pwm@f002c000 { 199 compatible = "atmel,sama5d3-pwm"; 200 reg = <0xf002c000 0x300>; 201 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; 202 #pwm-cells = <3>; 203 clocks = <&pwm_clk>; 204 status = "disabled"; 205 }; 206 207 isi: isi@f0034000 { 208 compatible = "atmel,at91sam9g45-isi"; 209 reg = <0xf0034000 0x4000>; 210 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; 211 status = "disabled"; 212 }; 213 214 mmc1: mmc@f8000000 { 215 compatible = "atmel,hsmci"; 216 reg = <0xf8000000 0x600>; 217 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; 218 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; 219 dma-names = "rxtx"; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 222 status = "disabled"; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&mci1_clk>; 226 clock-names = "mci_clk"; 227 }; 228 229 spi1: spi@f8008000 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "atmel,at91rm9200-spi"; 233 reg = <0xf8008000 0x100>; 234 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 235 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, 236 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; 237 dma-names = "tx", "rx"; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_spi1>; 240 clocks = <&spi1_clk>; 241 clock-names = "spi_clk"; 242 status = "disabled"; 243 }; 244 245 ssc1: ssc@f800c000 { 246 compatible = "atmel,at91sam9g45-ssc"; 247 reg = <0xf800c000 0x4000>; 248 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; 249 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, 250 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; 251 dma-names = "tx", "rx"; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 254 clocks = <&ssc1_clk>; 255 clock-names = "pclk"; 256 status = "disabled"; 257 }; 258 259 adc0: adc@f8018000 { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 compatible = "atmel,at91sam9x5-adc"; 263 reg = <0xf8018000 0x100>; 264 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 265 pinctrl-names = "default"; 266 pinctrl-0 = < 267 &pinctrl_adc0_adtrg 268 &pinctrl_adc0_ad0 269 &pinctrl_adc0_ad1 270 &pinctrl_adc0_ad2 271 &pinctrl_adc0_ad3 272 &pinctrl_adc0_ad4 273 &pinctrl_adc0_ad5 274 &pinctrl_adc0_ad6 275 &pinctrl_adc0_ad7 276 &pinctrl_adc0_ad8 277 &pinctrl_adc0_ad9 278 &pinctrl_adc0_ad10 279 &pinctrl_adc0_ad11 280 >; 281 clocks = <&adc_clk>, 282 <&adc_op_clk>; 283 clock-names = "adc_clk", "adc_op_clk"; 284 atmel,adc-channels-used = <0xfff>; 285 atmel,adc-startup-time = <40>; 286 atmel,adc-use-external-triggers; 287 atmel,adc-vref = <3000>; 288 atmel,adc-res = <10 12>; 289 atmel,adc-res-names = "lowres", "highres"; 290 status = "disabled"; 291 292 trigger@0 { 293 reg = <0>; 294 trigger-name = "external-rising"; 295 trigger-value = <0x1>; 296 trigger-external; 297 }; 298 trigger@1 { 299 reg = <1>; 300 trigger-name = "external-falling"; 301 trigger-value = <0x2>; 302 trigger-external; 303 }; 304 trigger@2 { 305 reg = <2>; 306 trigger-name = "external-any"; 307 trigger-value = <0x3>; 308 trigger-external; 309 }; 310 trigger@3 { 311 reg = <3>; 312 trigger-name = "continuous"; 313 trigger-value = <0x6>; 314 }; 315 }; 316 317 i2c2: i2c@f801c000 { 318 compatible = "atmel,at91sam9x5-i2c"; 319 reg = <0xf801c000 0x4000>; 320 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; 321 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, 322 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; 323 dma-names = "tx", "rx"; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_i2c2>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&twi2_clk>; 329 status = "disabled"; 330 }; 331 332 usart2: serial@f8020000 { 333 compatible = "atmel,at91sam9260-usart"; 334 reg = <0xf8020000 0x100>; 335 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_usart2>; 338 clocks = <&usart2_clk>; 339 clock-names = "usart"; 340 status = "disabled"; 341 }; 342 343 usart3: serial@f8024000 { 344 compatible = "atmel,at91sam9260-usart"; 345 reg = <0xf8024000 0x100>; 346 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_usart3>; 349 clocks = <&usart3_clk>; 350 clock-names = "usart"; 351 status = "disabled"; 352 }; 353 354 sha@f8034000 { 355 compatible = "atmel,at91sam9g46-sha"; 356 reg = <0xf8034000 0x100>; 357 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 358 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; 359 dma-names = "tx"; 360 clocks = <&sha_clk>; 361 clock-names = "sha_clk"; 362 }; 363 364 aes@f8038000 { 365 compatible = "atmel,at91sam9g46-aes"; 366 reg = <0xf8038000 0x100>; 367 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; 368 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, 369 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; 370 dma-names = "tx", "rx"; 371 clocks = <&aes_clk>; 372 clock-names = "aes_clk"; 373 }; 374 375 tdes@f803c000 { 376 compatible = "atmel,at91sam9g46-tdes"; 377 reg = <0xf803c000 0x100>; 378 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; 379 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, 380 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; 381 dma-names = "tx", "rx"; 382 clocks = <&tdes_clk>; 383 clock-names = "tdes_clk"; 384 }; 385 386 dma0: dma-controller@ffffe600 { 387 compatible = "atmel,at91sam9g45-dma"; 388 reg = <0xffffe600 0x200>; 389 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; 390 #dma-cells = <2>; 391 clocks = <&dma0_clk>; 392 clock-names = "dma_clk"; 393 }; 394 395 dma1: dma-controller@ffffe800 { 396 compatible = "atmel,at91sam9g45-dma"; 397 reg = <0xffffe800 0x200>; 398 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 399 #dma-cells = <2>; 400 clocks = <&dma1_clk>; 401 clock-names = "dma_clk"; 402 }; 403 404 ramc0: ramc@ffffea00 { 405 compatible = "atmel,at91sam9g45-ddramc"; 406 reg = <0xffffea00 0x200>; 407 }; 408 409 dbgu: serial@ffffee00 { 410 compatible = "atmel,at91sam9260-usart"; 411 reg = <0xffffee00 0x200>; 412 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_dbgu>; 415 clocks = <&dbgu_clk>; 416 clock-names = "usart"; 417 status = "disabled"; 418 }; 419 420 aic: interrupt-controller@fffff000 { 421 #interrupt-cells = <3>; 422 compatible = "atmel,sama5d3-aic"; 423 interrupt-controller; 424 reg = <0xfffff000 0x200>; 425 atmel,external-irqs = <47>; 426 }; 427 428 pinctrl@fffff200 { 429 #address-cells = <1>; 430 #size-cells = <1>; 431 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 432 ranges = <0xfffff200 0xfffff200 0xa00>; 433 atmel,mux-mask = < 434 /* A B C */ 435 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ 436 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ 437 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ 438 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ 439 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ 440 >; 441 442 /* shared pinctrl settings */ 443 adc0 { 444 pinctrl_adc0_adtrg: adc0_adtrg { 445 atmel,pins = 446 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ 447 }; 448 pinctrl_adc0_ad0: adc0_ad0 { 449 atmel,pins = 450 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ 451 }; 452 pinctrl_adc0_ad1: adc0_ad1 { 453 atmel,pins = 454 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ 455 }; 456 pinctrl_adc0_ad2: adc0_ad2 { 457 atmel,pins = 458 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ 459 }; 460 pinctrl_adc0_ad3: adc0_ad3 { 461 atmel,pins = 462 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ 463 }; 464 pinctrl_adc0_ad4: adc0_ad4 { 465 atmel,pins = 466 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ 467 }; 468 pinctrl_adc0_ad5: adc0_ad5 { 469 atmel,pins = 470 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ 471 }; 472 pinctrl_adc0_ad6: adc0_ad6 { 473 atmel,pins = 474 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ 475 }; 476 pinctrl_adc0_ad7: adc0_ad7 { 477 atmel,pins = 478 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ 479 }; 480 pinctrl_adc0_ad8: adc0_ad8 { 481 atmel,pins = 482 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ 483 }; 484 pinctrl_adc0_ad9: adc0_ad9 { 485 atmel,pins = 486 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ 487 }; 488 pinctrl_adc0_ad10: adc0_ad10 { 489 atmel,pins = 490 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ 491 }; 492 pinctrl_adc0_ad11: adc0_ad11 { 493 atmel,pins = 494 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ 495 }; 496 }; 497 498 dbgu { 499 pinctrl_dbgu: dbgu-0 { 500 atmel,pins = 501 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ 502 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ 503 }; 504 }; 505 506 i2c0 { 507 pinctrl_i2c0: i2c0-0 { 508 atmel,pins = 509 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ 510 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ 511 }; 512 }; 513 514 i2c1 { 515 pinctrl_i2c1: i2c1-0 { 516 atmel,pins = 517 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ 518 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ 519 }; 520 }; 521 522 i2c2 { 523 pinctrl_i2c2: i2c2-0 { 524 atmel,pins = 525 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ 526 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ 527 }; 528 }; 529 530 isi { 531 pinctrl_isi: isi-0 { 532 atmel,pins = 533 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ 534 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ 535 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ 536 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ 537 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ 538 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ 539 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ 540 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ 541 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ 542 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ 543 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ 544 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ 545 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ 546 }; 547 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { 548 atmel,pins = 549 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ 550 }; 551 }; 552 553 mmc0 { 554 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 555 atmel,pins = 556 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ 557 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ 558 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ 559 }; 560 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 561 atmel,pins = 562 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ 563 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ 564 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ 565 }; 566 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 567 atmel,pins = 568 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ 569 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ 570 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ 571 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ 572 }; 573 }; 574 575 mmc1 { 576 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 577 atmel,pins = 578 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ 579 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ 580 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ 581 }; 582 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 583 atmel,pins = 584 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ 585 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ 586 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ 587 }; 588 }; 589 590 nand0 { 591 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 592 atmel,pins = 593 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ 594 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ 595 }; 596 }; 597 598 pwm0 { 599 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { 600 atmel,pins = 601 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ 602 }; 603 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { 604 atmel,pins = 605 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ 606 }; 607 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { 608 atmel,pins = 609 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ 610 }; 611 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { 612 atmel,pins = 613 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ 614 }; 615 616 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { 617 atmel,pins = 618 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ 619 }; 620 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { 621 atmel,pins = 622 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ 623 }; 624 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { 625 atmel,pins = 626 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ 627 }; 628 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { 629 atmel,pins = 630 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ 631 }; 632 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { 633 atmel,pins = 634 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ 635 }; 636 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { 637 atmel,pins = 638 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ 639 }; 640 641 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { 642 atmel,pins = 643 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ 644 }; 645 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { 646 atmel,pins = 647 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ 648 }; 649 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { 650 atmel,pins = 651 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ 652 }; 653 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { 654 atmel,pins = 655 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ 656 }; 657 658 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { 659 atmel,pins = 660 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ 661 }; 662 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { 663 atmel,pins = 664 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ 665 }; 666 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { 667 atmel,pins = 668 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ 669 }; 670 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { 671 atmel,pins = 672 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ 673 }; 674 }; 675 676 spi0 { 677 pinctrl_spi0: spi0-0 { 678 atmel,pins = 679 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ 680 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ 681 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ 682 }; 683 }; 684 685 spi1 { 686 pinctrl_spi1: spi1-0 { 687 atmel,pins = 688 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ 689 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ 690 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ 691 }; 692 }; 693 694 ssc0 { 695 pinctrl_ssc0_tx: ssc0_tx { 696 atmel,pins = 697 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ 698 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ 699 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ 700 }; 701 702 pinctrl_ssc0_rx: ssc0_rx { 703 atmel,pins = 704 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ 705 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ 706 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ 707 }; 708 }; 709 710 ssc1 { 711 pinctrl_ssc1_tx: ssc1_tx { 712 atmel,pins = 713 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ 714 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ 715 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ 716 }; 717 718 pinctrl_ssc1_rx: ssc1_rx { 719 atmel,pins = 720 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ 721 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ 722 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ 723 }; 724 }; 725 726 usart0 { 727 pinctrl_usart0: usart0-0 { 728 atmel,pins = 729 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ 730 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ 731 }; 732 733 pinctrl_usart0_rts_cts: usart0_rts_cts-0 { 734 atmel,pins = 735 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ 736 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ 737 }; 738 }; 739 740 usart1 { 741 pinctrl_usart1: usart1-0 { 742 atmel,pins = 743 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ 744 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ 745 }; 746 747 pinctrl_usart1_rts_cts: usart1_rts_cts-0 { 748 atmel,pins = 749 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ 750 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ 751 }; 752 }; 753 754 usart2 { 755 pinctrl_usart2: usart2-0 { 756 atmel,pins = 757 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ 758 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ 759 }; 760 761 pinctrl_usart2_rts_cts: usart2_rts_cts-0 { 762 atmel,pins = 763 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ 764 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ 765 }; 766 }; 767 768 usart3 { 769 pinctrl_usart3: usart3-0 { 770 atmel,pins = 771 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ 772 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ 773 }; 774 775 pinctrl_usart3_rts_cts: usart3_rts_cts-0 { 776 atmel,pins = 777 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ 778 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ 779 }; 780 }; 781 782 783 pioA: gpio@fffff200 { 784 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 785 reg = <0xfffff200 0x100>; 786 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; 787 #gpio-cells = <2>; 788 gpio-controller; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 clocks = <&pioA_clk>; 792 }; 793 794 pioB: gpio@fffff400 { 795 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 796 reg = <0xfffff400 0x100>; 797 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; 798 #gpio-cells = <2>; 799 gpio-controller; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 clocks = <&pioB_clk>; 803 }; 804 805 pioC: gpio@fffff600 { 806 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 807 reg = <0xfffff600 0x100>; 808 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; 809 #gpio-cells = <2>; 810 gpio-controller; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 clocks = <&pioC_clk>; 814 }; 815 816 pioD: gpio@fffff800 { 817 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 818 reg = <0xfffff800 0x100>; 819 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; 820 #gpio-cells = <2>; 821 gpio-controller; 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 clocks = <&pioD_clk>; 825 }; 826 827 pioE: gpio@fffffa00 { 828 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 829 reg = <0xfffffa00 0x100>; 830 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; 831 #gpio-cells = <2>; 832 gpio-controller; 833 interrupt-controller; 834 #interrupt-cells = <2>; 835 clocks = <&pioE_clk>; 836 }; 837 }; 838 839 pmc: pmc@fffffc00 { 840 compatible = "atmel,sama5d3-pmc"; 841 reg = <0xfffffc00 0x120>; 842 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 843 interrupt-controller; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 #interrupt-cells = <1>; 847 848 main_rc_osc: main_rc_osc { 849 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 850 #clock-cells = <0>; 851 interrupt-parent = <&pmc>; 852 interrupts = <AT91_PMC_MOSCRCS>; 853 clock-frequency = <12000000>; 854 clock-accuracy = <50000000>; 855 }; 856 857 main_osc: main_osc { 858 compatible = "atmel,at91rm9200-clk-main-osc"; 859 #clock-cells = <0>; 860 interrupt-parent = <&pmc>; 861 interrupts = <AT91_PMC_MOSCS>; 862 clocks = <&main_xtal>; 863 }; 864 865 main: mainck { 866 compatible = "atmel,at91sam9x5-clk-main"; 867 #clock-cells = <0>; 868 interrupt-parent = <&pmc>; 869 interrupts = <AT91_PMC_MOSCSELS>; 870 clocks = <&main_rc_osc &main_osc>; 871 }; 872 873 plla: pllack { 874 compatible = "atmel,sama5d3-clk-pll"; 875 #clock-cells = <0>; 876 interrupt-parent = <&pmc>; 877 interrupts = <AT91_PMC_LOCKA>; 878 clocks = <&main>; 879 reg = <0>; 880 atmel,clk-input-range = <8000000 50000000>; 881 #atmel,pll-clk-output-range-cells = <4>; 882 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; 883 }; 884 885 plladiv: plladivck { 886 compatible = "atmel,at91sam9x5-clk-plldiv"; 887 #clock-cells = <0>; 888 clocks = <&plla>; 889 }; 890 891 utmi: utmick { 892 compatible = "atmel,at91sam9x5-clk-utmi"; 893 #clock-cells = <0>; 894 interrupt-parent = <&pmc>; 895 interrupts = <AT91_PMC_LOCKU>; 896 clocks = <&main>; 897 }; 898 899 mck: masterck { 900 compatible = "atmel,at91sam9x5-clk-master"; 901 #clock-cells = <0>; 902 interrupt-parent = <&pmc>; 903 interrupts = <AT91_PMC_MCKRDY>; 904 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 905 atmel,clk-output-range = <0 166000000>; 906 atmel,clk-divisors = <1 2 4 3>; 907 }; 908 909 usb: usbck { 910 compatible = "atmel,at91sam9x5-clk-usb"; 911 #clock-cells = <0>; 912 clocks = <&plladiv>, <&utmi>; 913 }; 914 915 prog: progck { 916 compatible = "atmel,at91sam9x5-clk-programmable"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 interrupt-parent = <&pmc>; 920 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 921 922 prog0: prog0 { 923 #clock-cells = <0>; 924 reg = <0>; 925 interrupts = <AT91_PMC_PCKRDY(0)>; 926 }; 927 928 prog1: prog1 { 929 #clock-cells = <0>; 930 reg = <1>; 931 interrupts = <AT91_PMC_PCKRDY(1)>; 932 }; 933 934 prog2: prog2 { 935 #clock-cells = <0>; 936 reg = <2>; 937 interrupts = <AT91_PMC_PCKRDY(2)>; 938 }; 939 }; 940 941 smd: smdclk { 942 compatible = "atmel,at91sam9x5-clk-smd"; 943 #clock-cells = <0>; 944 clocks = <&plladiv>, <&utmi>; 945 }; 946 947 systemck { 948 compatible = "atmel,at91rm9200-clk-system"; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 952 ddrck: ddrck { 953 #clock-cells = <0>; 954 reg = <2>; 955 clocks = <&mck>; 956 }; 957 958 smdck: smdck { 959 #clock-cells = <0>; 960 reg = <4>; 961 clocks = <&smd>; 962 }; 963 964 uhpck: uhpck { 965 #clock-cells = <0>; 966 reg = <6>; 967 clocks = <&usb>; 968 }; 969 970 udpck: udpck { 971 #clock-cells = <0>; 972 reg = <7>; 973 clocks = <&usb>; 974 }; 975 976 pck0: pck0 { 977 #clock-cells = <0>; 978 reg = <8>; 979 clocks = <&prog0>; 980 }; 981 982 pck1: pck1 { 983 #clock-cells = <0>; 984 reg = <9>; 985 clocks = <&prog1>; 986 }; 987 988 pck2: pck2 { 989 #clock-cells = <0>; 990 reg = <10>; 991 clocks = <&prog2>; 992 }; 993 }; 994 995 periphck { 996 compatible = "atmel,at91sam9x5-clk-peripheral"; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 clocks = <&mck>; 1000 1001 dbgu_clk: dbgu_clk { 1002 #clock-cells = <0>; 1003 reg = <2>; 1004 }; 1005 1006 pioA_clk: pioA_clk { 1007 #clock-cells = <0>; 1008 reg = <6>; 1009 }; 1010 1011 pioB_clk: pioB_clk { 1012 #clock-cells = <0>; 1013 reg = <7>; 1014 }; 1015 1016 pioC_clk: pioC_clk { 1017 #clock-cells = <0>; 1018 reg = <8>; 1019 }; 1020 1021 pioD_clk: pioD_clk { 1022 #clock-cells = <0>; 1023 reg = <9>; 1024 }; 1025 1026 pioE_clk: pioE_clk { 1027 #clock-cells = <0>; 1028 reg = <10>; 1029 }; 1030 1031 usart0_clk: usart0_clk { 1032 #clock-cells = <0>; 1033 reg = <12>; 1034 atmel,clk-output-range = <0 66000000>; 1035 }; 1036 1037 usart1_clk: usart1_clk { 1038 #clock-cells = <0>; 1039 reg = <13>; 1040 atmel,clk-output-range = <0 66000000>; 1041 }; 1042 1043 usart2_clk: usart2_clk { 1044 #clock-cells = <0>; 1045 reg = <14>; 1046 atmel,clk-output-range = <0 66000000>; 1047 }; 1048 1049 usart3_clk: usart3_clk { 1050 #clock-cells = <0>; 1051 reg = <15>; 1052 atmel,clk-output-range = <0 66000000>; 1053 }; 1054 1055 twi0_clk: twi0_clk { 1056 reg = <18>; 1057 #clock-cells = <0>; 1058 atmel,clk-output-range = <0 16625000>; 1059 }; 1060 1061 twi1_clk: twi1_clk { 1062 #clock-cells = <0>; 1063 reg = <19>; 1064 atmel,clk-output-range = <0 16625000>; 1065 }; 1066 1067 twi2_clk: twi2_clk { 1068 #clock-cells = <0>; 1069 reg = <20>; 1070 atmel,clk-output-range = <0 16625000>; 1071 }; 1072 1073 mci0_clk: mci0_clk { 1074 #clock-cells = <0>; 1075 reg = <21>; 1076 }; 1077 1078 mci1_clk: mci1_clk { 1079 #clock-cells = <0>; 1080 reg = <22>; 1081 }; 1082 1083 spi0_clk: spi0_clk { 1084 #clock-cells = <0>; 1085 reg = <24>; 1086 atmel,clk-output-range = <0 133000000>; 1087 }; 1088 1089 spi1_clk: spi1_clk { 1090 #clock-cells = <0>; 1091 reg = <25>; 1092 atmel,clk-output-range = <0 133000000>; 1093 }; 1094 1095 tcb0_clk: tcb0_clk { 1096 #clock-cells = <0>; 1097 reg = <26>; 1098 atmel,clk-output-range = <0 133000000>; 1099 }; 1100 1101 pwm_clk: pwm_clk { 1102 #clock-cells = <0>; 1103 reg = <28>; 1104 }; 1105 1106 adc_clk: adc_clk { 1107 #clock-cells = <0>; 1108 reg = <29>; 1109 atmel,clk-output-range = <0 66000000>; 1110 }; 1111 1112 dma0_clk: dma0_clk { 1113 #clock-cells = <0>; 1114 reg = <30>; 1115 }; 1116 1117 dma1_clk: dma1_clk { 1118 #clock-cells = <0>; 1119 reg = <31>; 1120 }; 1121 1122 uhphs_clk: uhphs_clk { 1123 #clock-cells = <0>; 1124 reg = <32>; 1125 }; 1126 1127 udphs_clk: udphs_clk { 1128 #clock-cells = <0>; 1129 reg = <33>; 1130 }; 1131 1132 isi_clk: isi_clk { 1133 #clock-cells = <0>; 1134 reg = <37>; 1135 }; 1136 1137 ssc0_clk: ssc0_clk { 1138 #clock-cells = <0>; 1139 reg = <38>; 1140 atmel,clk-output-range = <0 66000000>; 1141 }; 1142 1143 ssc1_clk: ssc1_clk { 1144 #clock-cells = <0>; 1145 reg = <39>; 1146 atmel,clk-output-range = <0 66000000>; 1147 }; 1148 1149 sha_clk: sha_clk { 1150 #clock-cells = <0>; 1151 reg = <42>; 1152 }; 1153 1154 aes_clk: aes_clk { 1155 #clock-cells = <0>; 1156 reg = <43>; 1157 }; 1158 1159 tdes_clk: tdes_clk { 1160 #clock-cells = <0>; 1161 reg = <44>; 1162 }; 1163 1164 trng_clk: trng_clk { 1165 #clock-cells = <0>; 1166 reg = <45>; 1167 }; 1168 1169 fuse_clk: fuse_clk { 1170 #clock-cells = <0>; 1171 reg = <48>; 1172 }; 1173 }; 1174 }; 1175 1176 rstc@fffffe00 { 1177 compatible = "atmel,at91sam9g45-rstc"; 1178 reg = <0xfffffe00 0x10>; 1179 }; 1180 1181 pit: timer@fffffe30 { 1182 compatible = "atmel,at91sam9260-pit"; 1183 reg = <0xfffffe30 0xf>; 1184 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1185 clocks = <&mck>; 1186 }; 1187 1188 watchdog@fffffe40 { 1189 compatible = "atmel,at91sam9260-wdt"; 1190 reg = <0xfffffe40 0x10>; 1191 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 1192 atmel,watchdog-type = "hardware"; 1193 atmel,reset-type = "all"; 1194 atmel,dbg-halt; 1195 atmel,idle-halt; 1196 status = "disabled"; 1197 }; 1198 1199 sckc@fffffe50 { 1200 compatible = "atmel,at91sam9x5-sckc"; 1201 reg = <0xfffffe50 0x4>; 1202 1203 slow_rc_osc: slow_rc_osc { 1204 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1205 #clock-cells = <0>; 1206 clock-frequency = <32768>; 1207 clock-accuracy = <50000000>; 1208 atmel,startup-time-usec = <75>; 1209 }; 1210 1211 slow_osc: slow_osc { 1212 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1213 #clock-cells = <0>; 1214 clocks = <&slow_xtal>; 1215 atmel,startup-time-usec = <1200000>; 1216 }; 1217 1218 clk32k: slowck { 1219 compatible = "atmel,at91sam9x5-clk-slow"; 1220 #clock-cells = <0>; 1221 clocks = <&slow_rc_osc &slow_osc>; 1222 }; 1223 }; 1224 1225 rtc@fffffeb0 { 1226 compatible = "atmel,at91rm9200-rtc"; 1227 reg = <0xfffffeb0 0x30>; 1228 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1229 }; 1230 }; 1231 1232 usb0: gadget@00500000 { 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 compatible = "atmel,at91sam9rl-udc"; 1236 reg = <0x00500000 0x100000 1237 0xf8030000 0x4000>; 1238 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; 1239 clocks = <&udphs_clk>, <&utmi>; 1240 clock-names = "pclk", "hclk"; 1241 status = "disabled"; 1242 1243 ep0 { 1244 reg = <0>; 1245 atmel,fifo-size = <64>; 1246 atmel,nb-banks = <1>; 1247 }; 1248 1249 ep1 { 1250 reg = <1>; 1251 atmel,fifo-size = <1024>; 1252 atmel,nb-banks = <3>; 1253 atmel,can-dma; 1254 atmel,can-isoc; 1255 }; 1256 1257 ep2 { 1258 reg = <2>; 1259 atmel,fifo-size = <1024>; 1260 atmel,nb-banks = <3>; 1261 atmel,can-dma; 1262 atmel,can-isoc; 1263 }; 1264 1265 ep3 { 1266 reg = <3>; 1267 atmel,fifo-size = <1024>; 1268 atmel,nb-banks = <2>; 1269 atmel,can-dma; 1270 }; 1271 1272 ep4 { 1273 reg = <4>; 1274 atmel,fifo-size = <1024>; 1275 atmel,nb-banks = <2>; 1276 atmel,can-dma; 1277 }; 1278 1279 ep5 { 1280 reg = <5>; 1281 atmel,fifo-size = <1024>; 1282 atmel,nb-banks = <2>; 1283 atmel,can-dma; 1284 }; 1285 1286 ep6 { 1287 reg = <6>; 1288 atmel,fifo-size = <1024>; 1289 atmel,nb-banks = <2>; 1290 atmel,can-dma; 1291 }; 1292 1293 ep7 { 1294 reg = <7>; 1295 atmel,fifo-size = <1024>; 1296 atmel,nb-banks = <2>; 1297 atmel,can-dma; 1298 }; 1299 1300 ep8 { 1301 reg = <8>; 1302 atmel,fifo-size = <1024>; 1303 atmel,nb-banks = <2>; 1304 }; 1305 1306 ep9 { 1307 reg = <9>; 1308 atmel,fifo-size = <1024>; 1309 atmel,nb-banks = <2>; 1310 }; 1311 1312 ep10 { 1313 reg = <10>; 1314 atmel,fifo-size = <1024>; 1315 atmel,nb-banks = <2>; 1316 }; 1317 1318 ep11 { 1319 reg = <11>; 1320 atmel,fifo-size = <1024>; 1321 atmel,nb-banks = <2>; 1322 }; 1323 1324 ep12 { 1325 reg = <12>; 1326 atmel,fifo-size = <1024>; 1327 atmel,nb-banks = <2>; 1328 }; 1329 1330 ep13 { 1331 reg = <13>; 1332 atmel,fifo-size = <1024>; 1333 atmel,nb-banks = <2>; 1334 }; 1335 1336 ep14 { 1337 reg = <14>; 1338 atmel,fifo-size = <1024>; 1339 atmel,nb-banks = <2>; 1340 }; 1341 1342 ep15 { 1343 reg = <15>; 1344 atmel,fifo-size = <1024>; 1345 atmel,nb-banks = <2>; 1346 }; 1347 }; 1348 1349 usb1: ohci@00600000 { 1350 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1351 reg = <0x00600000 0x100000>; 1352 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1353 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, 1354 <&uhpck>; 1355 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; 1356 status = "disabled"; 1357 }; 1358 1359 usb2: ehci@00700000 { 1360 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1361 reg = <0x00700000 0x100000>; 1362 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1363 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1364 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1365 status = "disabled"; 1366 }; 1367 1368 nand0: nand@60000000 { 1369 compatible = "atmel,at91rm9200-nand"; 1370 #address-cells = <1>; 1371 #size-cells = <1>; 1372 ranges; 1373 reg = < 0x60000000 0x01000000 /* EBI CS3 */ 1374 0xffffc070 0x00000490 /* SMC PMECC regs */ 1375 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 1376 0x00110000 0x00018000 /* ROM code */ 1377 >; 1378 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1379 atmel,nand-addr-offset = <21>; 1380 atmel,nand-cmd-offset = <22>; 1381 atmel,nand-has-dma; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1384 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 1385 status = "disabled"; 1386 1387 nfc@70000000 { 1388 compatible = "atmel,sama5d3-nfc"; 1389 #address-cells = <1>; 1390 #size-cells = <1>; 1391 reg = < 1392 0x70000000 0x10000000 /* NFC Command Registers */ 1393 0xffffc000 0x00000070 /* NFC HSMC regs */ 1394 0x00200000 0x00100000 /* NFC SRAM banks */ 1395 >; 1396 }; 1397 }; 1398 }; 1399}; 1400