imx6qdl.dtsi revision 271143
1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include <dt-bindings/clock/imx6qdl-clock.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15 16#include "skeleton.dtsi" 17 18/ { 19 aliases { 20 ethernet0 = &fec; 21 can0 = &can1; 22 can1 = &can2; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 gpio5 = &gpio6; 29 gpio6 = &gpio7; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 mmc2 = &usdhc3; 36 mmc3 = &usdhc4; 37 serial0 = &uart1; 38 serial1 = &uart2; 39 serial2 = &uart3; 40 serial3 = &uart4; 41 serial4 = &uart5; 42 spi0 = &ecspi1; 43 spi1 = &ecspi2; 44 spi2 = &ecspi3; 45 spi3 = &ecspi4; 46 usbphy0 = &usbphy1; 47 usbphy1 = &usbphy2; 48 }; 49 50 intc: interrupt-controller@00a01000 { 51 compatible = "arm,cortex-a9-gic"; 52 #interrupt-cells = <3>; 53 interrupt-controller; 54 reg = <0x00a01000 0x1000>, 55 <0x00a00100 0x100>; 56 }; 57 58 clocks { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 ckil { 63 compatible = "fsl,imx-ckil", "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <32768>; 66 }; 67 68 ckih1 { 69 compatible = "fsl,imx-ckih1", "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 }; 73 74 osc { 75 compatible = "fsl,imx-osc", "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <24000000>; 78 }; 79 }; 80 81 soc { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 compatible = "simple-bus"; 85 interrupt-parent = <&intc>; 86 ranges; 87 88 dma_apbh: dma-apbh@00110000 { 89 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 90 reg = <0x00110000 0x2000>; 91 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 92 <0 13 IRQ_TYPE_LEVEL_HIGH>, 93 <0 13 IRQ_TYPE_LEVEL_HIGH>, 94 <0 13 IRQ_TYPE_LEVEL_HIGH>; 95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 96 #dma-cells = <1>; 97 dma-channels = <4>; 98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 99 }; 100 101 gpmi: gpmi-nand@00112000 { 102 compatible = "fsl,imx6q-gpmi-nand"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 106 reg-names = "gpmi-nand", "bch"; 107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-names = "bch"; 109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 110 <&clks IMX6QDL_CLK_GPMI_APB>, 111 <&clks IMX6QDL_CLK_GPMI_BCH>, 112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 113 <&clks IMX6QDL_CLK_PER1_BCH>; 114 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 115 "gpmi_bch_apb", "per1_bch"; 116 dmas = <&dma_apbh 0>; 117 dma-names = "rx-tx"; 118 status = "disabled"; 119 }; 120 121 timer@00a00600 { 122 compatible = "arm,cortex-a9-twd-timer"; 123 reg = <0x00a00600 0x20>; 124 interrupts = <1 13 0xf01>; 125 clocks = <&clks IMX6QDL_CLK_TWD>; 126 }; 127 128 L2: l2-cache@00a02000 { 129 compatible = "arm,pl310-cache"; 130 reg = <0x00a02000 0x1000>; 131 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 132 cache-unified; 133 cache-level = <2>; 134 arm,tag-latency = <4 2 3>; 135 arm,data-latency = <4 2 3>; 136 }; 137 138 pcie: pcie@0x01000000 { 139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 140 reg = <0x01ffc000 0x4000>; /* DBI */ 141 #address-cells = <3>; 142 #size-cells = <2>; 143 device_type = "pci"; 144 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ 145 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 146 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 147 num-lanes = <1>; 148 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-names = "msi"; 150 #interrupt-cells = <1>; 151 interrupt-map-mask = <0 0 0 0x7>; 152 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 153 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 154 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 155 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 157 <&clks IMX6QDL_CLK_LVDS1_GATE>, 158 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 159 clock-names = "pcie", "pcie_bus", "pcie_phy"; 160 status = "disabled"; 161 }; 162 163 pmu { 164 compatible = "arm,cortex-a9-pmu"; 165 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 168 aips-bus@02000000 { /* AIPS1 */ 169 compatible = "fsl,aips-bus", "simple-bus"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 reg = <0x02000000 0x100000>; 173 ranges; 174 175 spba-bus@02000000 { 176 compatible = "fsl,spba-bus", "simple-bus"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 reg = <0x02000000 0x40000>; 180 ranges; 181 182 spdif: spdif@02004000 { 183 compatible = "fsl,imx35-spdif"; 184 reg = <0x02004000 0x4000>; 185 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 186 dmas = <&sdma 14 18 0>, 187 <&sdma 15 18 0>; 188 dma-names = "rx", "tx"; 189 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, 190 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, 191 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, 192 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, 193 <&clks IMX6QDL_CLK_DUMMY>; 194 clock-names = "core", "rxtx0", 195 "rxtx1", "rxtx2", 196 "rxtx3", "rxtx4", 197 "rxtx5", "rxtx6", 198 "rxtx7"; 199 status = "disabled"; 200 }; 201 202 ecspi1: ecspi@02008000 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 206 reg = <0x02008000 0x4000>; 207 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&clks IMX6QDL_CLK_ECSPI1>, 209 <&clks IMX6QDL_CLK_ECSPI1>; 210 clock-names = "ipg", "per"; 211 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 212 dma-names = "rx", "tx"; 213 status = "disabled"; 214 }; 215 216 ecspi2: ecspi@0200c000 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 220 reg = <0x0200c000 0x4000>; 221 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clks IMX6QDL_CLK_ECSPI2>, 223 <&clks IMX6QDL_CLK_ECSPI2>; 224 clock-names = "ipg", "per"; 225 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 226 dma-names = "rx", "tx"; 227 status = "disabled"; 228 }; 229 230 ecspi3: ecspi@02010000 { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 234 reg = <0x02010000 0x4000>; 235 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&clks IMX6QDL_CLK_ECSPI3>, 237 <&clks IMX6QDL_CLK_ECSPI3>; 238 clock-names = "ipg", "per"; 239 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 240 dma-names = "rx", "tx"; 241 status = "disabled"; 242 }; 243 244 ecspi4: ecspi@02014000 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 248 reg = <0x02014000 0x4000>; 249 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clks IMX6QDL_CLK_ECSPI4>, 251 <&clks IMX6QDL_CLK_ECSPI4>; 252 clock-names = "ipg", "per"; 253 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 254 dma-names = "rx", "tx"; 255 status = "disabled"; 256 }; 257 258 uart1: serial@02020000 { 259 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 260 reg = <0x02020000 0x4000>; 261 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 263 <&clks IMX6QDL_CLK_UART_SERIAL>; 264 clock-names = "ipg", "per"; 265 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 266 dma-names = "rx", "tx"; 267 status = "disabled"; 268 }; 269 270 esai: esai@02024000 { 271 reg = <0x02024000 0x4000>; 272 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 273 }; 274 275 ssi1: ssi@02028000 { 276 compatible = "fsl,imx6q-ssi", 277 "fsl,imx51-ssi"; 278 reg = <0x02028000 0x4000>; 279 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; 281 dmas = <&sdma 37 1 0>, 282 <&sdma 38 1 0>; 283 dma-names = "rx", "tx"; 284 fsl,fifo-depth = <15>; 285 status = "disabled"; 286 }; 287 288 ssi2: ssi@0202c000 { 289 compatible = "fsl,imx6q-ssi", 290 "fsl,imx51-ssi"; 291 reg = <0x0202c000 0x4000>; 292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; 294 dmas = <&sdma 41 1 0>, 295 <&sdma 42 1 0>; 296 dma-names = "rx", "tx"; 297 fsl,fifo-depth = <15>; 298 status = "disabled"; 299 }; 300 301 ssi3: ssi@02030000 { 302 compatible = "fsl,imx6q-ssi", 303 "fsl,imx51-ssi"; 304 reg = <0x02030000 0x4000>; 305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; 307 dmas = <&sdma 45 1 0>, 308 <&sdma 46 1 0>; 309 dma-names = "rx", "tx"; 310 fsl,fifo-depth = <15>; 311 status = "disabled"; 312 }; 313 314 asrc: asrc@02034000 { 315 reg = <0x02034000 0x4000>; 316 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 spba@0203c000 { 320 reg = <0x0203c000 0x4000>; 321 }; 322 }; 323 324 vpu: vpu@02040000 { 325 reg = <0x02040000 0x3c000>; 326 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, 327 <0 12 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 aipstz@0207c000 { /* AIPSTZ1 */ 331 reg = <0x0207c000 0x4000>; 332 }; 333 334 pwm1: pwm@02080000 { 335 #pwm-cells = <2>; 336 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 337 reg = <0x02080000 0x4000>; 338 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&clks IMX6QDL_CLK_IPG>, 340 <&clks IMX6QDL_CLK_PWM1>; 341 clock-names = "ipg", "per"; 342 }; 343 344 pwm2: pwm@02084000 { 345 #pwm-cells = <2>; 346 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 347 reg = <0x02084000 0x4000>; 348 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clks IMX6QDL_CLK_IPG>, 350 <&clks IMX6QDL_CLK_PWM2>; 351 clock-names = "ipg", "per"; 352 }; 353 354 pwm3: pwm@02088000 { 355 #pwm-cells = <2>; 356 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 357 reg = <0x02088000 0x4000>; 358 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clks IMX6QDL_CLK_IPG>, 360 <&clks IMX6QDL_CLK_PWM3>; 361 clock-names = "ipg", "per"; 362 }; 363 364 pwm4: pwm@0208c000 { 365 #pwm-cells = <2>; 366 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 367 reg = <0x0208c000 0x4000>; 368 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clks IMX6QDL_CLK_IPG>, 370 <&clks IMX6QDL_CLK_PWM4>; 371 clock-names = "ipg", "per"; 372 }; 373 374 can1: flexcan@02090000 { 375 compatible = "fsl,imx6q-flexcan"; 376 reg = <0x02090000 0x4000>; 377 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 379 <&clks IMX6QDL_CLK_CAN1_SERIAL>; 380 clock-names = "ipg", "per"; 381 status = "disabled"; 382 }; 383 384 can2: flexcan@02094000 { 385 compatible = "fsl,imx6q-flexcan"; 386 reg = <0x02094000 0x4000>; 387 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 389 <&clks IMX6QDL_CLK_CAN2_SERIAL>; 390 clock-names = "ipg", "per"; 391 status = "disabled"; 392 }; 393 394 gpt: gpt@02098000 { 395 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 396 reg = <0x02098000 0x4000>; 397 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 399 <&clks IMX6QDL_CLK_GPT_IPG_PER>; 400 clock-names = "ipg", "per"; 401 }; 402 403 gpio1: gpio@0209c000 { 404 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 405 reg = <0x0209c000 0x4000>; 406 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 407 <0 67 IRQ_TYPE_LEVEL_HIGH>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 }; 413 414 gpio2: gpio@020a0000 { 415 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 416 reg = <0x020a0000 0x4000>; 417 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 418 <0 69 IRQ_TYPE_LEVEL_HIGH>; 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 }; 424 425 gpio3: gpio@020a4000 { 426 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 427 reg = <0x020a4000 0x4000>; 428 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 429 <0 71 IRQ_TYPE_LEVEL_HIGH>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 }; 435 436 gpio4: gpio@020a8000 { 437 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 438 reg = <0x020a8000 0x4000>; 439 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 440 <0 73 IRQ_TYPE_LEVEL_HIGH>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 }; 446 447 gpio5: gpio@020ac000 { 448 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 449 reg = <0x020ac000 0x4000>; 450 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 451 <0 75 IRQ_TYPE_LEVEL_HIGH>; 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 458 gpio6: gpio@020b0000 { 459 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 460 reg = <0x020b0000 0x4000>; 461 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 462 <0 77 IRQ_TYPE_LEVEL_HIGH>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 }; 468 469 gpio7: gpio@020b4000 { 470 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 471 reg = <0x020b4000 0x4000>; 472 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 473 <0 79 IRQ_TYPE_LEVEL_HIGH>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 }; 479 480 kpp: kpp@020b8000 { 481 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 482 reg = <0x020b8000 0x4000>; 483 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clks IMX6QDL_CLK_IPG>; 485 status = "disabled"; 486 }; 487 488 wdog1: wdog@020bc000 { 489 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 490 reg = <0x020bc000 0x4000>; 491 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clks IMX6QDL_CLK_DUMMY>; 493 }; 494 495 wdog2: wdog@020c0000 { 496 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 497 reg = <0x020c0000 0x4000>; 498 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clks IMX6QDL_CLK_DUMMY>; 500 status = "disabled"; 501 }; 502 503 clks: ccm@020c4000 { 504 compatible = "fsl,imx6q-ccm"; 505 reg = <0x020c4000 0x4000>; 506 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 507 <0 88 IRQ_TYPE_LEVEL_HIGH>; 508 #clock-cells = <1>; 509 }; 510 511 anatop: anatop@020c8000 { 512 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; 513 reg = <0x020c8000 0x1000>; 514 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 515 <0 54 IRQ_TYPE_LEVEL_HIGH>, 516 <0 127 IRQ_TYPE_LEVEL_HIGH>; 517 518 regulator-1p1@110 { 519 compatible = "fsl,anatop-regulator"; 520 regulator-name = "vdd1p1"; 521 regulator-min-microvolt = <800000>; 522 regulator-max-microvolt = <1375000>; 523 regulator-always-on; 524 anatop-reg-offset = <0x110>; 525 anatop-vol-bit-shift = <8>; 526 anatop-vol-bit-width = <5>; 527 anatop-min-bit-val = <4>; 528 anatop-min-voltage = <800000>; 529 anatop-max-voltage = <1375000>; 530 }; 531 532 regulator-3p0@120 { 533 compatible = "fsl,anatop-regulator"; 534 regulator-name = "vdd3p0"; 535 regulator-min-microvolt = <2800000>; 536 regulator-max-microvolt = <3150000>; 537 regulator-always-on; 538 anatop-reg-offset = <0x120>; 539 anatop-vol-bit-shift = <8>; 540 anatop-vol-bit-width = <5>; 541 anatop-min-bit-val = <0>; 542 anatop-min-voltage = <2625000>; 543 anatop-max-voltage = <3400000>; 544 }; 545 546 regulator-2p5@130 { 547 compatible = "fsl,anatop-regulator"; 548 regulator-name = "vdd2p5"; 549 regulator-min-microvolt = <2000000>; 550 regulator-max-microvolt = <2750000>; 551 regulator-always-on; 552 anatop-reg-offset = <0x130>; 553 anatop-vol-bit-shift = <8>; 554 anatop-vol-bit-width = <5>; 555 anatop-min-bit-val = <0>; 556 anatop-min-voltage = <2000000>; 557 anatop-max-voltage = <2750000>; 558 }; 559 560 reg_arm: regulator-vddcore@140 { 561 compatible = "fsl,anatop-regulator"; 562 regulator-name = "vddarm"; 563 regulator-min-microvolt = <725000>; 564 regulator-max-microvolt = <1450000>; 565 regulator-always-on; 566 anatop-reg-offset = <0x140>; 567 anatop-vol-bit-shift = <0>; 568 anatop-vol-bit-width = <5>; 569 anatop-delay-reg-offset = <0x170>; 570 anatop-delay-bit-shift = <24>; 571 anatop-delay-bit-width = <2>; 572 anatop-min-bit-val = <1>; 573 anatop-min-voltage = <725000>; 574 anatop-max-voltage = <1450000>; 575 }; 576 577 reg_pu: regulator-vddpu@140 { 578 compatible = "fsl,anatop-regulator"; 579 regulator-name = "vddpu"; 580 regulator-min-microvolt = <725000>; 581 regulator-max-microvolt = <1450000>; 582 regulator-always-on; 583 anatop-reg-offset = <0x140>; 584 anatop-vol-bit-shift = <9>; 585 anatop-vol-bit-width = <5>; 586 anatop-delay-reg-offset = <0x170>; 587 anatop-delay-bit-shift = <26>; 588 anatop-delay-bit-width = <2>; 589 anatop-min-bit-val = <1>; 590 anatop-min-voltage = <725000>; 591 anatop-max-voltage = <1450000>; 592 }; 593 594 reg_soc: regulator-vddsoc@140 { 595 compatible = "fsl,anatop-regulator"; 596 regulator-name = "vddsoc"; 597 regulator-min-microvolt = <725000>; 598 regulator-max-microvolt = <1450000>; 599 regulator-always-on; 600 anatop-reg-offset = <0x140>; 601 anatop-vol-bit-shift = <18>; 602 anatop-vol-bit-width = <5>; 603 anatop-delay-reg-offset = <0x170>; 604 anatop-delay-bit-shift = <28>; 605 anatop-delay-bit-width = <2>; 606 anatop-min-bit-val = <1>; 607 anatop-min-voltage = <725000>; 608 anatop-max-voltage = <1450000>; 609 }; 610 }; 611 612 tempmon: tempmon { 613 compatible = "fsl,imx6q-tempmon"; 614 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 615 fsl,tempmon = <&anatop>; 616 fsl,tempmon-data = <&ocotp>; 617 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 618 }; 619 620 usbphy1: usbphy@020c9000 { 621 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 622 reg = <0x020c9000 0x1000>; 623 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clks IMX6QDL_CLK_USBPHY1>; 625 fsl,anatop = <&anatop>; 626 }; 627 628 usbphy2: usbphy@020ca000 { 629 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 630 reg = <0x020ca000 0x1000>; 631 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&clks IMX6QDL_CLK_USBPHY2>; 633 fsl,anatop = <&anatop>; 634 }; 635 636 snvs@020cc000 { 637 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges = <0 0x020cc000 0x4000>; 641 642 snvs-rtc-lp@34 { 643 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 644 reg = <0x34 0x58>; 645 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 646 <0 20 IRQ_TYPE_LEVEL_HIGH>; 647 }; 648 }; 649 650 epit1: epit@020d0000 { /* EPIT1 */ 651 reg = <0x020d0000 0x4000>; 652 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 653 }; 654 655 epit2: epit@020d4000 { /* EPIT2 */ 656 reg = <0x020d4000 0x4000>; 657 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 658 }; 659 660 src: src@020d8000 { 661 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 662 reg = <0x020d8000 0x4000>; 663 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 664 <0 96 IRQ_TYPE_LEVEL_HIGH>; 665 #reset-cells = <1>; 666 }; 667 668 gpc: gpc@020dc000 { 669 compatible = "fsl,imx6q-gpc"; 670 reg = <0x020dc000 0x4000>; 671 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 672 <0 90 IRQ_TYPE_LEVEL_HIGH>; 673 }; 674 675 gpr: iomuxc-gpr@020e0000 { 676 compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; 677 reg = <0x020e0000 0x38>; 678 }; 679 680 iomuxc: iomuxc@020e0000 { 681 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 682 reg = <0x020e0000 0x4000>; 683 }; 684 685 ldb: ldb@020e0008 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 689 gpr = <&gpr>; 690 status = "disabled"; 691 692 lvds-channel@0 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0>; 696 status = "disabled"; 697 698 port@0 { 699 reg = <0>; 700 701 lvds0_mux_0: endpoint { 702 remote-endpoint = <&ipu1_di0_lvds0>; 703 }; 704 }; 705 706 port@1 { 707 reg = <1>; 708 709 lvds0_mux_1: endpoint { 710 remote-endpoint = <&ipu1_di1_lvds0>; 711 }; 712 }; 713 }; 714 715 lvds-channel@1 { 716 #address-cells = <1>; 717 #size-cells = <0>; 718 reg = <1>; 719 status = "disabled"; 720 721 port@0 { 722 reg = <0>; 723 724 lvds1_mux_0: endpoint { 725 remote-endpoint = <&ipu1_di0_lvds1>; 726 }; 727 }; 728 729 port@1 { 730 reg = <1>; 731 732 lvds1_mux_1: endpoint { 733 remote-endpoint = <&ipu1_di1_lvds1>; 734 }; 735 }; 736 }; 737 }; 738 739 hdmi: hdmi@0120000 { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 reg = <0x00120000 0x9000>; 743 interrupts = <0 115 0x04>; 744 gpr = <&gpr>; 745 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 746 <&clks IMX6QDL_CLK_HDMI_ISFR>; 747 clock-names = "iahb", "isfr"; 748 status = "disabled"; 749 750 port@0 { 751 reg = <0>; 752 753 hdmi_mux_0: endpoint { 754 remote-endpoint = <&ipu1_di0_hdmi>; 755 }; 756 }; 757 758 port@1 { 759 reg = <1>; 760 761 hdmi_mux_1: endpoint { 762 remote-endpoint = <&ipu1_di1_hdmi>; 763 }; 764 }; 765 }; 766 767 dcic1: dcic@020e4000 { 768 reg = <0x020e4000 0x4000>; 769 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 770 }; 771 772 dcic2: dcic@020e8000 { 773 reg = <0x020e8000 0x4000>; 774 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 777 sdma: sdma@020ec000 { 778 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 779 reg = <0x020ec000 0x4000>; 780 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clks IMX6QDL_CLK_SDMA>, 782 <&clks IMX6QDL_CLK_SDMA>; 783 clock-names = "ipg", "ahb"; 784 #dma-cells = <3>; 785 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 786 }; 787 }; 788 789 aips-bus@02100000 { /* AIPS2 */ 790 compatible = "fsl,aips-bus", "simple-bus"; 791 #address-cells = <1>; 792 #size-cells = <1>; 793 reg = <0x02100000 0x100000>; 794 ranges; 795 796 caam@02100000 { 797 reg = <0x02100000 0x40000>; 798 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, 799 <0 106 IRQ_TYPE_LEVEL_HIGH>; 800 }; 801 802 aipstz@0217c000 { /* AIPSTZ2 */ 803 reg = <0x0217c000 0x4000>; 804 }; 805 806 usbotg: usb@02184000 { 807 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 808 reg = <0x02184000 0x200>; 809 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&clks IMX6QDL_CLK_USBOH3>; 811 fsl,usbphy = <&usbphy1>; 812 fsl,usbmisc = <&usbmisc 0>; 813 status = "disabled"; 814 }; 815 816 usbh1: usb@02184200 { 817 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 818 reg = <0x02184200 0x200>; 819 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clks IMX6QDL_CLK_USBOH3>; 821 fsl,usbphy = <&usbphy2>; 822 fsl,usbmisc = <&usbmisc 1>; 823 status = "disabled"; 824 }; 825 826 usbh2: usb@02184400 { 827 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 828 reg = <0x02184400 0x200>; 829 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clks IMX6QDL_CLK_USBOH3>; 831 fsl,usbmisc = <&usbmisc 2>; 832 status = "disabled"; 833 }; 834 835 usbh3: usb@02184600 { 836 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 837 reg = <0x02184600 0x200>; 838 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&clks IMX6QDL_CLK_USBOH3>; 840 fsl,usbmisc = <&usbmisc 3>; 841 status = "disabled"; 842 }; 843 844 usbmisc: usbmisc@02184800 { 845 #index-cells = <1>; 846 compatible = "fsl,imx6q-usbmisc"; 847 reg = <0x02184800 0x200>; 848 clocks = <&clks IMX6QDL_CLK_USBOH3>; 849 }; 850 851 fec: ethernet@02188000 { 852 compatible = "fsl,imx6q-fec"; 853 reg = <0x02188000 0x4000>; 854 interrupts-extended = 855 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, 856 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&clks IMX6QDL_CLK_ENET>, 858 <&clks IMX6QDL_CLK_ENET>, 859 <&clks IMX6QDL_CLK_ENET_REF>; 860 clock-names = "ipg", "ahb", "ptp"; 861 status = "disabled"; 862 }; 863 864 mlb@0218c000 { 865 reg = <0x0218c000 0x4000>; 866 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 867 <0 117 IRQ_TYPE_LEVEL_HIGH>, 868 <0 126 IRQ_TYPE_LEVEL_HIGH>; 869 }; 870 871 usdhc1: usdhc@02190000 { 872 compatible = "fsl,imx6q-usdhc"; 873 reg = <0x02190000 0x4000>; 874 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clks IMX6QDL_CLK_USDHC1>, 876 <&clks IMX6QDL_CLK_USDHC1>, 877 <&clks IMX6QDL_CLK_USDHC1>; 878 clock-names = "ipg", "ahb", "per"; 879 bus-width = <4>; 880 status = "disabled"; 881 }; 882 883 usdhc2: usdhc@02194000 { 884 compatible = "fsl,imx6q-usdhc"; 885 reg = <0x02194000 0x4000>; 886 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&clks IMX6QDL_CLK_USDHC2>, 888 <&clks IMX6QDL_CLK_USDHC2>, 889 <&clks IMX6QDL_CLK_USDHC2>; 890 clock-names = "ipg", "ahb", "per"; 891 bus-width = <4>; 892 status = "disabled"; 893 }; 894 895 usdhc3: usdhc@02198000 { 896 compatible = "fsl,imx6q-usdhc"; 897 reg = <0x02198000 0x4000>; 898 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clks IMX6QDL_CLK_USDHC3>, 900 <&clks IMX6QDL_CLK_USDHC3>, 901 <&clks IMX6QDL_CLK_USDHC3>; 902 clock-names = "ipg", "ahb", "per"; 903 bus-width = <4>; 904 status = "disabled"; 905 }; 906 907 usdhc4: usdhc@0219c000 { 908 compatible = "fsl,imx6q-usdhc"; 909 reg = <0x0219c000 0x4000>; 910 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clks IMX6QDL_CLK_USDHC4>, 912 <&clks IMX6QDL_CLK_USDHC4>, 913 <&clks IMX6QDL_CLK_USDHC4>; 914 clock-names = "ipg", "ahb", "per"; 915 bus-width = <4>; 916 status = "disabled"; 917 }; 918 919 i2c1: i2c@021a0000 { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 923 reg = <0x021a0000 0x4000>; 924 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&clks IMX6QDL_CLK_I2C1>; 926 status = "disabled"; 927 }; 928 929 i2c2: i2c@021a4000 { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 933 reg = <0x021a4000 0x4000>; 934 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clks IMX6QDL_CLK_I2C2>; 936 status = "disabled"; 937 }; 938 939 i2c3: i2c@021a8000 { 940 #address-cells = <1>; 941 #size-cells = <0>; 942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 943 reg = <0x021a8000 0x4000>; 944 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clks IMX6QDL_CLK_I2C3>; 946 status = "disabled"; 947 }; 948 949 romcp@021ac000 { 950 reg = <0x021ac000 0x4000>; 951 }; 952 953 mmdc0: mmdc@021b0000 { /* MMDC0 */ 954 compatible = "fsl,imx6q-mmdc"; 955 reg = <0x021b0000 0x4000>; 956 }; 957 958 mmdc1: mmdc@021b4000 { /* MMDC1 */ 959 reg = <0x021b4000 0x4000>; 960 }; 961 962 weim: weim@021b8000 { 963 compatible = "fsl,imx6q-weim"; 964 reg = <0x021b8000 0x4000>; 965 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 967 }; 968 969 ocotp: ocotp@021bc000 { 970 compatible = "fsl,imx6q-ocotp", "syscon"; 971 reg = <0x021bc000 0x4000>; 972 }; 973 974 tzasc@021d0000 { /* TZASC1 */ 975 reg = <0x021d0000 0x4000>; 976 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 977 }; 978 979 tzasc@021d4000 { /* TZASC2 */ 980 reg = <0x021d4000 0x4000>; 981 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 982 }; 983 984 audmux: audmux@021d8000 { 985 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 986 reg = <0x021d8000 0x4000>; 987 status = "disabled"; 988 }; 989 990 mipi_csi: mipi@021dc000 { 991 reg = <0x021dc000 0x4000>; 992 }; 993 994 mipi_dsi: mipi@021e0000 { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 reg = <0x021e0000 0x4000>; 998 status = "disabled"; 999 1000 port@0 { 1001 reg = <0>; 1002 1003 mipi_mux_0: endpoint { 1004 remote-endpoint = <&ipu1_di0_mipi>; 1005 }; 1006 }; 1007 1008 port@1 { 1009 reg = <1>; 1010 1011 mipi_mux_1: endpoint { 1012 remote-endpoint = <&ipu1_di1_mipi>; 1013 }; 1014 }; 1015 }; 1016 1017 vdoa@021e4000 { 1018 reg = <0x021e4000 0x4000>; 1019 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1020 }; 1021 1022 uart2: serial@021e8000 { 1023 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1024 reg = <0x021e8000 0x4000>; 1025 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1027 <&clks IMX6QDL_CLK_UART_SERIAL>; 1028 clock-names = "ipg", "per"; 1029 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1030 dma-names = "rx", "tx"; 1031 status = "disabled"; 1032 }; 1033 1034 uart3: serial@021ec000 { 1035 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1036 reg = <0x021ec000 0x4000>; 1037 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1039 <&clks IMX6QDL_CLK_UART_SERIAL>; 1040 clock-names = "ipg", "per"; 1041 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1042 dma-names = "rx", "tx"; 1043 status = "disabled"; 1044 }; 1045 1046 uart4: serial@021f0000 { 1047 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1048 reg = <0x021f0000 0x4000>; 1049 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1051 <&clks IMX6QDL_CLK_UART_SERIAL>; 1052 clock-names = "ipg", "per"; 1053 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1054 dma-names = "rx", "tx"; 1055 status = "disabled"; 1056 }; 1057 1058 uart5: serial@021f4000 { 1059 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1060 reg = <0x021f4000 0x4000>; 1061 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1063 <&clks IMX6QDL_CLK_UART_SERIAL>; 1064 clock-names = "ipg", "per"; 1065 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1066 dma-names = "rx", "tx"; 1067 status = "disabled"; 1068 }; 1069 }; 1070 1071 ipu1: ipu@02400000 { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 compatible = "fsl,imx6q-ipu"; 1075 reg = <0x02400000 0x400000>; 1076 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1077 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&clks IMX6QDL_CLK_IPU1>, 1079 <&clks IMX6QDL_CLK_IPU1_DI0>, 1080 <&clks IMX6QDL_CLK_IPU1_DI1>; 1081 clock-names = "bus", "di0", "di1"; 1082 resets = <&src 2>; 1083 1084 ipu1_csi0: port@0 { 1085 reg = <0>; 1086 }; 1087 1088 ipu1_csi1: port@1 { 1089 reg = <1>; 1090 }; 1091 1092 ipu1_di0: port@2 { 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 reg = <2>; 1096 1097 ipu1_di0_disp0: endpoint@0 { 1098 }; 1099 1100 ipu1_di0_hdmi: endpoint@1 { 1101 remote-endpoint = <&hdmi_mux_0>; 1102 }; 1103 1104 ipu1_di0_mipi: endpoint@2 { 1105 remote-endpoint = <&mipi_mux_0>; 1106 }; 1107 1108 ipu1_di0_lvds0: endpoint@3 { 1109 remote-endpoint = <&lvds0_mux_0>; 1110 }; 1111 1112 ipu1_di0_lvds1: endpoint@4 { 1113 remote-endpoint = <&lvds1_mux_0>; 1114 }; 1115 }; 1116 1117 ipu1_di1: port@3 { 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 reg = <3>; 1121 1122 ipu1_di0_disp1: endpoint@0 { 1123 }; 1124 1125 ipu1_di1_hdmi: endpoint@1 { 1126 remote-endpoint = <&hdmi_mux_1>; 1127 }; 1128 1129 ipu1_di1_mipi: endpoint@2 { 1130 remote-endpoint = <&mipi_mux_1>; 1131 }; 1132 1133 ipu1_di1_lvds0: endpoint@3 { 1134 remote-endpoint = <&lvds0_mux_1>; 1135 }; 1136 1137 ipu1_di1_lvds1: endpoint@4 { 1138 remote-endpoint = <&lvds1_mux_1>; 1139 }; 1140 }; 1141 }; 1142 }; 1143}; 1144