imx6qdl-sabreauto.dtsi revision 262569 
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/ {
14	memory {
15		reg = <0x10000000 0x80000000>;
16	};
17};
18
19&ecspi1 {
20	fsl,spi-num-chipselects = <1>;
21	cs-gpios = <&gpio3 19 0>;
22	pinctrl-names = "default";
23	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
24	status = "disabled"; /* pin conflict with WEIM NOR */
25
26	flash: m25p80@0 {
27		#address-cells = <1>;
28		#size-cells = <1>;
29		compatible = "st,m25p32";
30		spi-max-frequency = <20000000>;
31		reg = <0>;
32	};
33};
34
35&fec {
36	pinctrl-names = "default";
37	pinctrl-0 = <&pinctrl_enet_2>;
38	phy-mode = "rgmii";
39	status = "okay";
40};
41
42&gpmi {
43	pinctrl-names = "default";
44	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
45	status = "okay";
46};
47
48&iomuxc {
49	pinctrl-names = "default";
50	pinctrl-0 = <&pinctrl_hog>;
51
52	hog {
53		pinctrl_hog: hoggrp {
54			fsl,pins = <
55				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
56				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
57				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
58			>;
59		};
60	};
61
62	ecspi1 {
63		pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
64			fsl,pins = <
65				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
66			>;
67		};
68	};
69};
70
71&uart4 {
72	pinctrl-names = "default";
73	pinctrl-0 = <&pinctrl_uart4_1>;
74	status = "okay";
75};
76
77&usdhc3 {
78	pinctrl-names = "default", "state_100mhz", "state_200mhz";
79	pinctrl-0 = <&pinctrl_usdhc3_1>;
80	pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
81	pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
82	cd-gpios = <&gpio6 15 0>;
83	wp-gpios = <&gpio1 13 0>;
84	status = "okay";
85};
86
87&weim {
88	pinctrl-names = "default";
89	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
90	#address-cells = <2>;
91	#size-cells = <1>;
92	ranges = <0 0 0x08000000 0x08000000>;
93	status = "disabled"; /* pin conflict with SPI NOR */
94
95	nor@0,0 {
96		compatible = "cfi-flash";
97		reg = <0 0 0x02000000>;
98		#address-cells = <1>;
99		#size-cells = <1>;
100		bank-width = <2>;
101		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
102				0x0000c000 0x1404a38e 0x00000000>;
103	};
104};
105