1262569Simp/* 2262569Simp * Copyright 2012 Freescale Semiconductor, Inc. 3262569Simp * Copyright 2011 Linaro Ltd. 4262569Simp * 5262569Simp * The code contained herein is licensed under the GNU General Public 6262569Simp * License. You may obtain a copy of the GNU General Public License 7262569Simp * Version 2 or later at the following locations: 8262569Simp * 9262569Simp * http://www.opensource.org/licenses/gpl-license.html 10262569Simp * http://www.gnu.org/copyleft/gpl.html 11262569Simp */ 12262569Simp 13270864Simp#include <dt-bindings/gpio/gpio.h> 14270864Simp 15262569Simp/ { 16262569Simp memory { 17262569Simp reg = <0x10000000 0x80000000>; 18262569Simp }; 19270864Simp 20270864Simp leds { 21270864Simp compatible = "gpio-leds"; 22270864Simp pinctrl-names = "default"; 23270864Simp pinctrl-0 = <&pinctrl_gpio_leds>; 24270864Simp 25270864Simp user { 26270864Simp label = "debug"; 27270864Simp gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 28270864Simp }; 29270864Simp }; 30270864Simp 31270864Simp sound-spdif { 32270864Simp compatible = "fsl,imx-audio-spdif", 33270864Simp "fsl,imx-sabreauto-spdif"; 34270864Simp model = "imx-spdif"; 35270864Simp spdif-controller = <&spdif>; 36270864Simp spdif-in; 37270864Simp }; 38270864Simp 39270864Simp backlight { 40270864Simp compatible = "pwm-backlight"; 41270864Simp pwms = <&pwm3 0 5000000>; 42270864Simp brightness-levels = <0 4 8 16 32 64 128 255>; 43270864Simp default-brightness-level = <7>; 44270864Simp status = "okay"; 45270864Simp }; 46262569Simp}; 47262569Simp 48262569Simp&ecspi1 { 49262569Simp fsl,spi-num-chipselects = <1>; 50262569Simp cs-gpios = <&gpio3 19 0>; 51262569Simp pinctrl-names = "default"; 52270864Simp pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 53262569Simp status = "disabled"; /* pin conflict with WEIM NOR */ 54262569Simp 55262569Simp flash: m25p80@0 { 56262569Simp #address-cells = <1>; 57262569Simp #size-cells = <1>; 58262569Simp compatible = "st,m25p32"; 59262569Simp spi-max-frequency = <20000000>; 60262569Simp reg = <0>; 61262569Simp }; 62262569Simp}; 63262569Simp 64262569Simp&fec { 65262569Simp pinctrl-names = "default"; 66270864Simp pinctrl-0 = <&pinctrl_enet>; 67262569Simp phy-mode = "rgmii"; 68270864Simp interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 69270864Simp <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 70262569Simp status = "okay"; 71262569Simp}; 72262569Simp 73262569Simp&gpmi { 74262569Simp pinctrl-names = "default"; 75270864Simp pinctrl-0 = <&pinctrl_gpmi_nand>; 76262569Simp status = "okay"; 77262569Simp}; 78262569Simp 79270864Simp&i2c2 { 80270864Simp clock-frequency = <100000>; 81270864Simp pinctrl-names = "default"; 82270864Simp pinctrl-0 = <&pinctrl_i2c2>; 83270864Simp status = "okay"; 84270864Simp 85270864Simp pmic: pfuze100@08 { 86270864Simp compatible = "fsl,pfuze100"; 87270864Simp reg = <0x08>; 88270864Simp 89270864Simp regulators { 90270864Simp sw1a_reg: sw1ab { 91270864Simp regulator-min-microvolt = <300000>; 92270864Simp regulator-max-microvolt = <1875000>; 93270864Simp regulator-boot-on; 94270864Simp regulator-always-on; 95270864Simp regulator-ramp-delay = <6250>; 96270864Simp }; 97270864Simp 98270864Simp sw1c_reg: sw1c { 99270864Simp regulator-min-microvolt = <300000>; 100270864Simp regulator-max-microvolt = <1875000>; 101270864Simp regulator-boot-on; 102270864Simp regulator-always-on; 103270864Simp regulator-ramp-delay = <6250>; 104270864Simp }; 105270864Simp 106270864Simp sw2_reg: sw2 { 107270864Simp regulator-min-microvolt = <800000>; 108270864Simp regulator-max-microvolt = <3300000>; 109270864Simp regulator-boot-on; 110270864Simp regulator-always-on; 111270864Simp }; 112270864Simp 113270864Simp sw3a_reg: sw3a { 114270864Simp regulator-min-microvolt = <400000>; 115270864Simp regulator-max-microvolt = <1975000>; 116270864Simp regulator-boot-on; 117270864Simp regulator-always-on; 118270864Simp }; 119270864Simp 120270864Simp sw3b_reg: sw3b { 121270864Simp regulator-min-microvolt = <400000>; 122270864Simp regulator-max-microvolt = <1975000>; 123270864Simp regulator-boot-on; 124270864Simp regulator-always-on; 125270864Simp }; 126270864Simp 127270864Simp sw4_reg: sw4 { 128270864Simp regulator-min-microvolt = <800000>; 129270864Simp regulator-max-microvolt = <3300000>; 130270864Simp }; 131270864Simp 132270864Simp swbst_reg: swbst { 133270864Simp regulator-min-microvolt = <5000000>; 134270864Simp regulator-max-microvolt = <5150000>; 135270864Simp }; 136270864Simp 137270864Simp snvs_reg: vsnvs { 138270864Simp regulator-min-microvolt = <1000000>; 139270864Simp regulator-max-microvolt = <3000000>; 140270864Simp regulator-boot-on; 141270864Simp regulator-always-on; 142270864Simp }; 143270864Simp 144270864Simp vref_reg: vrefddr { 145270864Simp regulator-boot-on; 146270864Simp regulator-always-on; 147270864Simp }; 148270864Simp 149270864Simp vgen1_reg: vgen1 { 150270864Simp regulator-min-microvolt = <800000>; 151270864Simp regulator-max-microvolt = <1550000>; 152270864Simp }; 153270864Simp 154270864Simp vgen2_reg: vgen2 { 155270864Simp regulator-min-microvolt = <800000>; 156270864Simp regulator-max-microvolt = <1550000>; 157270864Simp }; 158270864Simp 159270864Simp vgen3_reg: vgen3 { 160270864Simp regulator-min-microvolt = <1800000>; 161270864Simp regulator-max-microvolt = <3300000>; 162270864Simp }; 163270864Simp 164270864Simp vgen4_reg: vgen4 { 165270864Simp regulator-min-microvolt = <1800000>; 166270864Simp regulator-max-microvolt = <3300000>; 167270864Simp regulator-always-on; 168270864Simp }; 169270864Simp 170270864Simp vgen5_reg: vgen5 { 171270864Simp regulator-min-microvolt = <1800000>; 172270864Simp regulator-max-microvolt = <3300000>; 173270864Simp regulator-always-on; 174270864Simp }; 175270864Simp 176270864Simp vgen6_reg: vgen6 { 177270864Simp regulator-min-microvolt = <1800000>; 178270864Simp regulator-max-microvolt = <3300000>; 179270864Simp regulator-always-on; 180270864Simp }; 181270864Simp }; 182270864Simp }; 183270864Simp}; 184270864Simp 185262569Simp&iomuxc { 186262569Simp pinctrl-names = "default"; 187262569Simp pinctrl-0 = <&pinctrl_hog>; 188262569Simp 189270864Simp imx6qdl-sabreauto { 190262569Simp pinctrl_hog: hoggrp { 191262569Simp fsl,pins = < 192262569Simp MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 193262569Simp MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 194262569Simp MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 195262569Simp >; 196262569Simp }; 197262569Simp 198270864Simp pinctrl_ecspi1: ecspi1grp { 199262569Simp fsl,pins = < 200270864Simp MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 201270864Simp MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 202270864Simp MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 203270864Simp >; 204270864Simp }; 205270864Simp 206270864Simp pinctrl_ecspi1_cs: ecspi1cs { 207270864Simp fsl,pins = < 208262569Simp MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 209262569Simp >; 210262569Simp }; 211270864Simp 212270864Simp pinctrl_enet: enetgrp { 213270864Simp fsl,pins = < 214270864Simp MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 215270864Simp MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 216270864Simp MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 217270864Simp MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 218270864Simp MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 219270864Simp MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 220270864Simp MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 221270864Simp MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 222270864Simp MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 223270864Simp MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 224270864Simp MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 225270864Simp MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 226270864Simp MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 227270864Simp MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 228270864Simp MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 229270864Simp MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 230270864Simp >; 231270864Simp }; 232270864Simp 233270864Simp pinctrl_gpio_leds: gpioledsgrp { 234270864Simp fsl,pins = < 235270864Simp MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 236270864Simp >; 237270864Simp }; 238270864Simp 239270864Simp pinctrl_gpmi_nand: gpminandgrp { 240270864Simp fsl,pins = < 241270864Simp MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 242270864Simp MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 243270864Simp MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 244270864Simp MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 245270864Simp MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 246270864Simp MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 247270864Simp MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 248270864Simp MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 249270864Simp MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 250270864Simp MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 251270864Simp MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 252270864Simp MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 253270864Simp MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 254270864Simp MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 255270864Simp MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 256270864Simp MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 257270864Simp MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 258270864Simp >; 259270864Simp }; 260270864Simp 261270864Simp pinctrl_i2c2: i2c2grp { 262270864Simp fsl,pins = < 263270864Simp MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 264270864Simp MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 265270864Simp >; 266270864Simp }; 267270864Simp 268270864Simp pinctrl_pwm3: pwm1grp { 269270864Simp fsl,pins = < 270270864Simp MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 271270864Simp >; 272270864Simp }; 273270864Simp 274270864Simp pinctrl_spdif: spdifgrp { 275270864Simp fsl,pins = < 276270864Simp MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 277270864Simp >; 278270864Simp }; 279270864Simp 280270864Simp pinctrl_uart4: uart4grp { 281270864Simp fsl,pins = < 282270864Simp MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 283270864Simp MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 284270864Simp >; 285270864Simp }; 286270864Simp 287270864Simp pinctrl_usdhc3: usdhc3grp { 288270864Simp fsl,pins = < 289270864Simp MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 290270864Simp MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 291270864Simp MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 292270864Simp MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 293270864Simp MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 294270864Simp MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 295270864Simp MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 296270864Simp MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 297270864Simp MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 298270864Simp MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 299270864Simp >; 300270864Simp }; 301270864Simp 302270864Simp pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 303270864Simp fsl,pins = < 304270864Simp MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 305270864Simp MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 306270864Simp MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 307270864Simp MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 308270864Simp MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 309270864Simp MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 310270864Simp MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 311270864Simp MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 312270864Simp MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 313270864Simp MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 314270864Simp >; 315270864Simp }; 316270864Simp 317270864Simp pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 318270864Simp fsl,pins = < 319270864Simp MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 320270864Simp MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 321270864Simp MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 322270864Simp MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 323270864Simp MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 324270864Simp MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 325270864Simp MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 326270864Simp MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 327270864Simp MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 328270864Simp MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 329270864Simp >; 330270864Simp }; 331270864Simp 332270864Simp pinctrl_weim_cs0: weimcs0grp { 333270864Simp fsl,pins = < 334270864Simp MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 335270864Simp >; 336270864Simp }; 337270864Simp 338270864Simp pinctrl_weim_nor: weimnorgrp { 339270864Simp fsl,pins = < 340270864Simp MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 341270864Simp MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 342270864Simp MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 343270864Simp MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 344270864Simp MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 345270864Simp MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 346270864Simp MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 347270864Simp MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 348270864Simp MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 349270864Simp MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 350270864Simp MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 351270864Simp MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 352270864Simp MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 353270864Simp MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 354270864Simp MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 355270864Simp MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 356270864Simp MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 357270864Simp MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 358270864Simp MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 359270864Simp MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 360270864Simp MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 361270864Simp MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 362270864Simp MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 363270864Simp MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 364270864Simp MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 365270864Simp MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 366270864Simp MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 367270864Simp MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 368270864Simp MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 369270864Simp MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 370270864Simp MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 371270864Simp MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 372270864Simp MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 373270864Simp MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 374270864Simp MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 375270864Simp MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 376270864Simp MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 377270864Simp MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 378270864Simp MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 379270864Simp MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 380270864Simp MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 381270864Simp MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 382270864Simp MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 383270864Simp >; 384270864Simp }; 385262569Simp }; 386262569Simp}; 387262569Simp 388270864Simp&ldb { 389270864Simp status = "okay"; 390270864Simp 391270864Simp lvds-channel@0 { 392270864Simp fsl,data-mapping = "spwg"; 393270864Simp fsl,data-width = <18>; 394270864Simp status = "okay"; 395270864Simp 396270864Simp display-timings { 397270864Simp native-mode = <&timing0>; 398270864Simp timing0: hsd100pxn1 { 399270864Simp clock-frequency = <65000000>; 400270864Simp hactive = <1024>; 401270864Simp vactive = <768>; 402270864Simp hback-porch = <220>; 403270864Simp hfront-porch = <40>; 404270864Simp vback-porch = <21>; 405270864Simp vfront-porch = <7>; 406270864Simp hsync-len = <60>; 407270864Simp vsync-len = <10>; 408270864Simp }; 409270864Simp }; 410270864Simp }; 411270864Simp}; 412270864Simp 413270864Simp&pwm3 { 414270864Simp pinctrl-names = "default"; 415270864Simp pinctrl-0 = <&pinctrl_pwm3>; 416270864Simp status = "okay"; 417270864Simp}; 418270864Simp 419270864Simp&spdif { 420270864Simp pinctrl-names = "default"; 421270864Simp pinctrl-0 = <&pinctrl_spdif>; 422270864Simp status = "okay"; 423270864Simp}; 424270864Simp 425262569Simp&uart4 { 426262569Simp pinctrl-names = "default"; 427270864Simp pinctrl-0 = <&pinctrl_uart4>; 428262569Simp status = "okay"; 429262569Simp}; 430262569Simp 431262569Simp&usdhc3 { 432262569Simp pinctrl-names = "default", "state_100mhz", "state_200mhz"; 433270864Simp pinctrl-0 = <&pinctrl_usdhc3>; 434270864Simp pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 435270864Simp pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 436262569Simp cd-gpios = <&gpio6 15 0>; 437262569Simp wp-gpios = <&gpio1 13 0>; 438262569Simp status = "okay"; 439262569Simp}; 440262569Simp 441262569Simp&weim { 442262569Simp pinctrl-names = "default"; 443270864Simp pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; 444262569Simp #address-cells = <2>; 445262569Simp #size-cells = <1>; 446262569Simp ranges = <0 0 0x08000000 0x08000000>; 447262569Simp status = "disabled"; /* pin conflict with SPI NOR */ 448262569Simp 449262569Simp nor@0,0 { 450262569Simp compatible = "cfi-flash"; 451262569Simp reg = <0 0 0x02000000>; 452262569Simp #address-cells = <1>; 453262569Simp #size-cells = <1>; 454262569Simp bank-width = <2>; 455262569Simp fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 456262569Simp 0x0000c000 0x1404a38e 0x00000000>; 457262569Simp }; 458262569Simp}; 459