1262569Simp 2262569Simp/* 3262569Simp * Copyright 2013 Freescale Semiconductor, Inc. 4262569Simp * 5262569Simp * This program is free software; you can redistribute it and/or modify 6262569Simp * it under the terms of the GNU General Public License version 2 as 7262569Simp * published by the Free Software Foundation. 8262569Simp * 9262569Simp */ 10262569Simp 11270864Simp#include <dt-bindings/interrupt-controller/irq.h> 12262569Simp#include "imx6dl-pinfunc.h" 13262569Simp#include "imx6qdl.dtsi" 14262569Simp 15262569Simp/ { 16284090Sian aliases { 17284090Sian i2c3 = &i2c4; 18284090Sian }; 19284090Sian 20262569Simp cpus { 21262569Simp #address-cells = <1>; 22262569Simp #size-cells = <0>; 23262569Simp 24262569Simp cpu@0 { 25262569Simp compatible = "arm,cortex-a9"; 26262569Simp device_type = "cpu"; 27262569Simp reg = <0>; 28262569Simp next-level-cache = <&L2>; 29270864Simp operating-points = < 30270864Simp /* kHz uV */ 31284090Sian 996000 1250000 32270864Simp 792000 1175000 33270864Simp 396000 1075000 34270864Simp >; 35270864Simp fsl,soc-operating-points = < 36270864Simp /* ARM kHz SOC-PU uV */ 37270864Simp 996000 1175000 38270864Simp 792000 1175000 39270864Simp 396000 1175000 40270864Simp >; 41270864Simp clock-latency = <61036>; /* two CLK32 periods */ 42270864Simp clocks = <&clks IMX6QDL_CLK_ARM>, 43270864Simp <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, 44270864Simp <&clks IMX6QDL_CLK_STEP>, 45270864Simp <&clks IMX6QDL_CLK_PLL1_SW>, 46270864Simp <&clks IMX6QDL_CLK_PLL1_SYS>; 47270864Simp clock-names = "arm", "pll2_pfd2_396m", "step", 48270864Simp "pll1_sw", "pll1_sys"; 49270864Simp arm-supply = <®_arm>; 50270864Simp pu-supply = <®_pu>; 51270864Simp soc-supply = <®_soc>; 52262569Simp }; 53262569Simp 54262569Simp cpu@1 { 55262569Simp compatible = "arm,cortex-a9"; 56262569Simp device_type = "cpu"; 57262569Simp reg = <1>; 58262569Simp next-level-cache = <&L2>; 59262569Simp }; 60262569Simp }; 61262569Simp 62262569Simp soc { 63262569Simp ocram: sram@00900000 { 64262569Simp compatible = "mmio-sram"; 65262569Simp reg = <0x00900000 0x20000>; 66270864Simp clocks = <&clks IMX6QDL_CLK_OCRAM>; 67262569Simp }; 68262569Simp 69262569Simp aips1: aips-bus@02000000 { 70262569Simp iomuxc: iomuxc@020e0000 { 71262569Simp compatible = "fsl,imx6dl-iomuxc"; 72262569Simp }; 73262569Simp 74262569Simp pxp: pxp@020f0000 { 75262569Simp reg = <0x020f0000 0x4000>; 76270864Simp interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 77262569Simp }; 78262569Simp 79262569Simp epdc: epdc@020f4000 { 80262569Simp reg = <0x020f4000 0x4000>; 81270864Simp interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 82262569Simp }; 83262569Simp 84262569Simp lcdif: lcdif@020f8000 { 85262569Simp reg = <0x020f8000 0x4000>; 86270864Simp interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 87262569Simp }; 88262569Simp }; 89262569Simp 90262569Simp aips2: aips-bus@02100000 { 91262569Simp i2c4: i2c@021f8000 { 92262569Simp #address-cells = <1>; 93262569Simp #size-cells = <0>; 94270864Simp compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 95262569Simp reg = <0x021f8000 0x4000>; 96270864Simp interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 97270864Simp clocks = <&clks IMX6DL_CLK_I2C4>; 98262569Simp status = "disabled"; 99262569Simp }; 100262569Simp }; 101262569Simp }; 102270864Simp 103270864Simp display-subsystem { 104270864Simp compatible = "fsl,imx-display-subsystem"; 105270864Simp ports = <&ipu1_di0>, <&ipu1_di1>; 106270864Simp }; 107262569Simp}; 108262569Simp 109270864Simp&hdmi { 110270864Simp compatible = "fsl,imx6dl-hdmi"; 111270864Simp}; 112270864Simp 113262569Simp&ldb { 114270864Simp clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 115270864Simp <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, 116270864Simp <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; 117262569Simp clock-names = "di0_pll", "di1_pll", 118262569Simp "di0_sel", "di1_sel", 119262569Simp "di0", "di1"; 120262569Simp}; 121284090Sian 122284090Sian&vpu { 123284090Sian compatible = "fsl,imx6dl-vpu", "cnm,coda960"; 124284090Sian}; 125