imx53.dtsi revision 270864
1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "skeleton.dtsi" 14#include "imx53-pinfunc.h" 15#include <dt-bindings/clock/imx5-clock.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/input/input.h> 18 19/ { 20 aliases { 21 ethernet0 = &fec; 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 gpio4 = &gpio5; 27 gpio5 = &gpio6; 28 gpio6 = &gpio7; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 mmc0 = &esdhc1; 33 mmc1 = &esdhc2; 34 mmc2 = &esdhc3; 35 mmc3 = &esdhc4; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 serial4 = &uart5; 41 spi0 = &ecspi1; 42 spi1 = &ecspi2; 43 spi2 = &cspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a8"; 52 reg = <0x0>; 53 }; 54 }; 55 56 display-subsystem { 57 compatible = "fsl,imx-display-subsystem"; 58 ports = <&ipu_di0>, <&ipu_di1>; 59 }; 60 61 tzic: tz-interrupt-controller@0fffc000 { 62 compatible = "fsl,imx53-tzic", "fsl,tzic"; 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 reg = <0x0fffc000 0x4000>; 66 }; 67 68 clocks { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 ckil { 73 compatible = "fsl,imx-ckil", "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <32768>; 76 }; 77 78 ckih1 { 79 compatible = "fsl,imx-ckih1", "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <22579200>; 82 }; 83 84 ckih2 { 85 compatible = "fsl,imx-ckih2", "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <0>; 88 }; 89 90 osc { 91 compatible = "fsl,imx-osc", "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <24000000>; 94 }; 95 }; 96 97 soc { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 compatible = "simple-bus"; 101 interrupt-parent = <&tzic>; 102 ranges; 103 104 sata: sata@10000000 { 105 compatible = "fsl,imx53-ahci"; 106 reg = <0x10000000 0x1000>; 107 interrupts = <28>; 108 clocks = <&clks IMX5_CLK_SATA_GATE>, 109 <&clks IMX5_CLK_SATA_REF>, 110 <&clks IMX5_CLK_AHB>; 111 clock-names = "sata", "sata_ref", "ahb"; 112 status = "disabled"; 113 }; 114 115 ipu: ipu@18000000 { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 compatible = "fsl,imx53-ipu"; 119 reg = <0x18000000 0x08000000>; 120 interrupts = <11 10>; 121 clocks = <&clks IMX5_CLK_IPU_GATE>, 122 <&clks IMX5_CLK_IPU_DI0_GATE>, 123 <&clks IMX5_CLK_IPU_DI1_GATE>; 124 clock-names = "bus", "di0", "di1"; 125 resets = <&src 2>; 126 127 ipu_di0: port@2 { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 reg = <2>; 131 132 ipu_di0_disp0: endpoint@0 { 133 reg = <0>; 134 }; 135 136 ipu_di0_lvds0: endpoint@1 { 137 reg = <1>; 138 remote-endpoint = <&lvds0_in>; 139 }; 140 }; 141 142 ipu_di1: port@3 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 reg = <3>; 146 147 ipu_di1_disp1: endpoint@0 { 148 reg = <0>; 149 }; 150 151 ipu_di1_lvds1: endpoint@1 { 152 reg = <1>; 153 remote-endpoint = <&lvds1_in>; 154 }; 155 156 ipu_di1_tve: endpoint@2 { 157 reg = <2>; 158 remote-endpoint = <&tve_in>; 159 }; 160 }; 161 }; 162 163 aips@50000000 { /* AIPS1 */ 164 compatible = "fsl,aips-bus", "simple-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 reg = <0x50000000 0x10000000>; 168 ranges; 169 170 spba@50000000 { 171 compatible = "fsl,spba-bus", "simple-bus"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0x50000000 0x40000>; 175 ranges; 176 177 esdhc1: esdhc@50004000 { 178 compatible = "fsl,imx53-esdhc"; 179 reg = <0x50004000 0x4000>; 180 interrupts = <1>; 181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 182 <&clks IMX5_CLK_DUMMY>, 183 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 184 clock-names = "ipg", "ahb", "per"; 185 bus-width = <4>; 186 status = "disabled"; 187 }; 188 189 esdhc2: esdhc@50008000 { 190 compatible = "fsl,imx53-esdhc"; 191 reg = <0x50008000 0x4000>; 192 interrupts = <2>; 193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 194 <&clks IMX5_CLK_DUMMY>, 195 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 196 clock-names = "ipg", "ahb", "per"; 197 bus-width = <4>; 198 status = "disabled"; 199 }; 200 201 uart3: serial@5000c000 { 202 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 203 reg = <0x5000c000 0x4000>; 204 interrupts = <33>; 205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 206 <&clks IMX5_CLK_UART3_PER_GATE>; 207 clock-names = "ipg", "per"; 208 status = "disabled"; 209 }; 210 211 ecspi1: ecspi@50010000 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 215 reg = <0x50010000 0x4000>; 216 interrupts = <36>; 217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 218 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 219 clock-names = "ipg", "per"; 220 status = "disabled"; 221 }; 222 223 ssi2: ssi@50014000 { 224 compatible = "fsl,imx53-ssi", 225 "fsl,imx51-ssi", 226 "fsl,imx21-ssi"; 227 reg = <0x50014000 0x4000>; 228 interrupts = <30>; 229 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 230 dmas = <&sdma 24 1 0>, 231 <&sdma 25 1 0>; 232 dma-names = "rx", "tx"; 233 fsl,fifo-depth = <15>; 234 status = "disabled"; 235 }; 236 237 esdhc3: esdhc@50020000 { 238 compatible = "fsl,imx53-esdhc"; 239 reg = <0x50020000 0x4000>; 240 interrupts = <3>; 241 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 242 <&clks IMX5_CLK_DUMMY>, 243 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 244 clock-names = "ipg", "ahb", "per"; 245 bus-width = <4>; 246 status = "disabled"; 247 }; 248 249 esdhc4: esdhc@50024000 { 250 compatible = "fsl,imx53-esdhc"; 251 reg = <0x50024000 0x4000>; 252 interrupts = <4>; 253 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 254 <&clks IMX5_CLK_DUMMY>, 255 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 256 clock-names = "ipg", "ahb", "per"; 257 bus-width = <4>; 258 status = "disabled"; 259 }; 260 }; 261 262 aipstz1: bridge@53f00000 { 263 compatible = "fsl,imx53-aipstz"; 264 reg = <0x53f00000 0x60>; 265 }; 266 267 usbphy0: usbphy@0 { 268 compatible = "usb-nop-xceiv"; 269 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 270 clock-names = "main_clk"; 271 status = "okay"; 272 }; 273 274 usbphy1: usbphy@1 { 275 compatible = "usb-nop-xceiv"; 276 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 277 clock-names = "main_clk"; 278 status = "okay"; 279 }; 280 281 usbotg: usb@53f80000 { 282 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 283 reg = <0x53f80000 0x0200>; 284 interrupts = <18>; 285 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 286 fsl,usbmisc = <&usbmisc 0>; 287 fsl,usbphy = <&usbphy0>; 288 status = "disabled"; 289 }; 290 291 usbh1: usb@53f80200 { 292 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 293 reg = <0x53f80200 0x0200>; 294 interrupts = <14>; 295 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 296 fsl,usbmisc = <&usbmisc 1>; 297 fsl,usbphy = <&usbphy1>; 298 status = "disabled"; 299 }; 300 301 usbh2: usb@53f80400 { 302 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 303 reg = <0x53f80400 0x0200>; 304 interrupts = <16>; 305 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 306 fsl,usbmisc = <&usbmisc 2>; 307 status = "disabled"; 308 }; 309 310 usbh3: usb@53f80600 { 311 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 312 reg = <0x53f80600 0x0200>; 313 interrupts = <17>; 314 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 315 fsl,usbmisc = <&usbmisc 3>; 316 status = "disabled"; 317 }; 318 319 usbmisc: usbmisc@53f80800 { 320 #index-cells = <1>; 321 compatible = "fsl,imx53-usbmisc"; 322 reg = <0x53f80800 0x200>; 323 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 324 }; 325 326 gpio1: gpio@53f84000 { 327 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 328 reg = <0x53f84000 0x4000>; 329 interrupts = <50 51>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 gpio2: gpio@53f88000 { 337 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 338 reg = <0x53f88000 0x4000>; 339 interrupts = <52 53>; 340 gpio-controller; 341 #gpio-cells = <2>; 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 }; 345 346 gpio3: gpio@53f8c000 { 347 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 348 reg = <0x53f8c000 0x4000>; 349 interrupts = <54 55>; 350 gpio-controller; 351 #gpio-cells = <2>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 }; 355 356 gpio4: gpio@53f90000 { 357 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 358 reg = <0x53f90000 0x4000>; 359 interrupts = <56 57>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 }; 365 366 kpp: kpp@53f94000 { 367 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; 368 reg = <0x53f94000 0x4000>; 369 interrupts = <60>; 370 clocks = <&clks IMX5_CLK_DUMMY>; 371 status = "disabled"; 372 }; 373 374 wdog1: wdog@53f98000 { 375 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 376 reg = <0x53f98000 0x4000>; 377 interrupts = <58>; 378 clocks = <&clks IMX5_CLK_DUMMY>; 379 }; 380 381 wdog2: wdog@53f9c000 { 382 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 383 reg = <0x53f9c000 0x4000>; 384 interrupts = <59>; 385 clocks = <&clks IMX5_CLK_DUMMY>; 386 status = "disabled"; 387 }; 388 389 gpt: timer@53fa0000 { 390 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; 391 reg = <0x53fa0000 0x4000>; 392 interrupts = <39>; 393 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 394 <&clks IMX5_CLK_GPT_HF_GATE>; 395 clock-names = "ipg", "per"; 396 }; 397 398 iomuxc: iomuxc@53fa8000 { 399 compatible = "fsl,imx53-iomuxc"; 400 reg = <0x53fa8000 0x4000>; 401 }; 402 403 gpr: iomuxc-gpr@53fa8000 { 404 compatible = "fsl,imx53-iomuxc-gpr", "syscon"; 405 reg = <0x53fa8000 0xc>; 406 }; 407 408 ldb: ldb@53fa8008 { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 compatible = "fsl,imx53-ldb"; 412 reg = <0x53fa8008 0x4>; 413 gpr = <&gpr>; 414 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 415 <&clks IMX5_CLK_LDB_DI1_SEL>, 416 <&clks IMX5_CLK_IPU_DI0_SEL>, 417 <&clks IMX5_CLK_IPU_DI1_SEL>, 418 <&clks IMX5_CLK_LDB_DI0_GATE>, 419 <&clks IMX5_CLK_LDB_DI1_GATE>; 420 clock-names = "di0_pll", "di1_pll", 421 "di0_sel", "di1_sel", 422 "di0", "di1"; 423 status = "disabled"; 424 425 lvds-channel@0 { 426 reg = <0>; 427 status = "disabled"; 428 429 port { 430 lvds0_in: endpoint { 431 remote-endpoint = <&ipu_di0_lvds0>; 432 }; 433 }; 434 }; 435 436 lvds-channel@1 { 437 reg = <1>; 438 status = "disabled"; 439 440 port { 441 lvds1_in: endpoint { 442 remote-endpoint = <&ipu_di1_lvds1>; 443 }; 444 }; 445 }; 446 }; 447 448 pwm1: pwm@53fb4000 { 449 #pwm-cells = <2>; 450 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 451 reg = <0x53fb4000 0x4000>; 452 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 453 <&clks IMX5_CLK_PWM1_HF_GATE>; 454 clock-names = "ipg", "per"; 455 interrupts = <61>; 456 }; 457 458 pwm2: pwm@53fb8000 { 459 #pwm-cells = <2>; 460 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 461 reg = <0x53fb8000 0x4000>; 462 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 463 <&clks IMX5_CLK_PWM2_HF_GATE>; 464 clock-names = "ipg", "per"; 465 interrupts = <94>; 466 }; 467 468 uart1: serial@53fbc000 { 469 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 470 reg = <0x53fbc000 0x4000>; 471 interrupts = <31>; 472 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 473 <&clks IMX5_CLK_UART1_PER_GATE>; 474 clock-names = "ipg", "per"; 475 status = "disabled"; 476 }; 477 478 uart2: serial@53fc0000 { 479 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 480 reg = <0x53fc0000 0x4000>; 481 interrupts = <32>; 482 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 483 <&clks IMX5_CLK_UART2_PER_GATE>; 484 clock-names = "ipg", "per"; 485 status = "disabled"; 486 }; 487 488 can1: can@53fc8000 { 489 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 490 reg = <0x53fc8000 0x4000>; 491 interrupts = <82>; 492 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, 493 <&clks IMX5_CLK_CAN1_SERIAL_GATE>; 494 clock-names = "ipg", "per"; 495 status = "disabled"; 496 }; 497 498 can2: can@53fcc000 { 499 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 500 reg = <0x53fcc000 0x4000>; 501 interrupts = <83>; 502 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, 503 <&clks IMX5_CLK_CAN2_SERIAL_GATE>; 504 clock-names = "ipg", "per"; 505 status = "disabled"; 506 }; 507 508 src: src@53fd0000 { 509 compatible = "fsl,imx53-src", "fsl,imx51-src"; 510 reg = <0x53fd0000 0x4000>; 511 #reset-cells = <1>; 512 }; 513 514 clks: ccm@53fd4000{ 515 compatible = "fsl,imx53-ccm"; 516 reg = <0x53fd4000 0x4000>; 517 interrupts = <0 71 0x04 0 72 0x04>; 518 #clock-cells = <1>; 519 }; 520 521 gpio5: gpio@53fdc000 { 522 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 523 reg = <0x53fdc000 0x4000>; 524 interrupts = <103 104>; 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 531 gpio6: gpio@53fe0000 { 532 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 533 reg = <0x53fe0000 0x4000>; 534 interrupts = <105 106>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 }; 540 541 gpio7: gpio@53fe4000 { 542 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 543 reg = <0x53fe4000 0x4000>; 544 interrupts = <107 108>; 545 gpio-controller; 546 #gpio-cells = <2>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 }; 550 551 i2c3: i2c@53fec000 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 555 reg = <0x53fec000 0x4000>; 556 interrupts = <64>; 557 clocks = <&clks IMX5_CLK_I2C3_GATE>; 558 status = "disabled"; 559 }; 560 561 uart4: serial@53ff0000 { 562 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 563 reg = <0x53ff0000 0x4000>; 564 interrupts = <13>; 565 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, 566 <&clks IMX5_CLK_UART4_PER_GATE>; 567 clock-names = "ipg", "per"; 568 status = "disabled"; 569 }; 570 }; 571 572 aips@60000000 { /* AIPS2 */ 573 compatible = "fsl,aips-bus", "simple-bus"; 574 #address-cells = <1>; 575 #size-cells = <1>; 576 reg = <0x60000000 0x10000000>; 577 ranges; 578 579 aipstz2: bridge@63f00000 { 580 compatible = "fsl,imx53-aipstz"; 581 reg = <0x63f00000 0x60>; 582 }; 583 584 iim: iim@63f98000 { 585 compatible = "fsl,imx53-iim", "fsl,imx27-iim"; 586 reg = <0x63f98000 0x4000>; 587 interrupts = <69>; 588 clocks = <&clks IMX5_CLK_IIM_GATE>; 589 }; 590 591 uart5: serial@63f90000 { 592 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 593 reg = <0x63f90000 0x4000>; 594 interrupts = <86>; 595 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, 596 <&clks IMX5_CLK_UART5_PER_GATE>; 597 clock-names = "ipg", "per"; 598 status = "disabled"; 599 }; 600 601 owire: owire@63fa4000 { 602 compatible = "fsl,imx53-owire", "fsl,imx21-owire"; 603 reg = <0x63fa4000 0x4000>; 604 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 605 status = "disabled"; 606 }; 607 608 ecspi2: ecspi@63fac000 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 612 reg = <0x63fac000 0x4000>; 613 interrupts = <37>; 614 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 615 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 616 clock-names = "ipg", "per"; 617 status = "disabled"; 618 }; 619 620 sdma: sdma@63fb0000 { 621 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 622 reg = <0x63fb0000 0x4000>; 623 interrupts = <6>; 624 clocks = <&clks IMX5_CLK_SDMA_GATE>, 625 <&clks IMX5_CLK_SDMA_GATE>; 626 clock-names = "ipg", "ahb"; 627 #dma-cells = <3>; 628 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 629 }; 630 631 cspi: cspi@63fc0000 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 635 reg = <0x63fc0000 0x4000>; 636 interrupts = <38>; 637 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 638 <&clks IMX5_CLK_CSPI_IPG_GATE>; 639 clock-names = "ipg", "per"; 640 status = "disabled"; 641 }; 642 643 i2c2: i2c@63fc4000 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 647 reg = <0x63fc4000 0x4000>; 648 interrupts = <63>; 649 clocks = <&clks IMX5_CLK_I2C2_GATE>; 650 status = "disabled"; 651 }; 652 653 i2c1: i2c@63fc8000 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 657 reg = <0x63fc8000 0x4000>; 658 interrupts = <62>; 659 clocks = <&clks IMX5_CLK_I2C1_GATE>; 660 status = "disabled"; 661 }; 662 663 ssi1: ssi@63fcc000 { 664 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 665 "fsl,imx21-ssi"; 666 reg = <0x63fcc000 0x4000>; 667 interrupts = <29>; 668 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 669 dmas = <&sdma 28 0 0>, 670 <&sdma 29 0 0>; 671 dma-names = "rx", "tx"; 672 fsl,fifo-depth = <15>; 673 status = "disabled"; 674 }; 675 676 audmux: audmux@63fd0000 { 677 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 678 reg = <0x63fd0000 0x4000>; 679 status = "disabled"; 680 }; 681 682 nfc: nand@63fdb000 { 683 compatible = "fsl,imx53-nand"; 684 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 685 interrupts = <8>; 686 clocks = <&clks IMX5_CLK_NFC_GATE>; 687 status = "disabled"; 688 }; 689 690 ssi3: ssi@63fe8000 { 691 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 692 "fsl,imx21-ssi"; 693 reg = <0x63fe8000 0x4000>; 694 interrupts = <96>; 695 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; 696 dmas = <&sdma 46 0 0>, 697 <&sdma 47 0 0>; 698 dma-names = "rx", "tx"; 699 fsl,fifo-depth = <15>; 700 status = "disabled"; 701 }; 702 703 fec: ethernet@63fec000 { 704 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 705 reg = <0x63fec000 0x4000>; 706 interrupts = <87>; 707 clocks = <&clks IMX5_CLK_FEC_GATE>, 708 <&clks IMX5_CLK_FEC_GATE>, 709 <&clks IMX5_CLK_FEC_GATE>; 710 clock-names = "ipg", "ahb", "ptp"; 711 status = "disabled"; 712 }; 713 714 tve: tve@63ff0000 { 715 compatible = "fsl,imx53-tve"; 716 reg = <0x63ff0000 0x1000>; 717 interrupts = <92>; 718 clocks = <&clks IMX5_CLK_TVE_GATE>, 719 <&clks IMX5_CLK_IPU_DI1_SEL>; 720 clock-names = "tve", "di_sel"; 721 status = "disabled"; 722 723 port { 724 tve_in: endpoint { 725 remote-endpoint = <&ipu_di1_tve>; 726 }; 727 }; 728 }; 729 730 vpu: vpu@63ff4000 { 731 compatible = "fsl,imx53-vpu"; 732 reg = <0x63ff4000 0x1000>; 733 interrupts = <9>; 734 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 735 <&clks IMX5_CLK_VPU_GATE>; 736 clock-names = "per", "ahb"; 737 resets = <&src 1>; 738 iram = <&ocram>; 739 }; 740 }; 741 742 ocram: sram@f8000000 { 743 compatible = "mmio-sram"; 744 reg = <0xf8000000 0x20000>; 745 clocks = <&clks IMX5_CLK_OCRAM>; 746 }; 747 }; 748}; 749