1270866Simp/* 2270866Simp * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 3270866Simp * 4270866Simp * The code contained herein is licensed under the GNU General Public 5270866Simp * License. You may obtain a copy of the GNU General Public License 6270866Simp * Version 2 or later at the following locations: 7270866Simp * 8270866Simp * http://www.opensource.org/licenses/gpl-license.html 9270866Simp * http://www.gnu.org/copyleft/gpl.html 10270866Simp */ 11270866Simp 12270866Simp/dts-v1/; 13270866Simp#include "imx51.dtsi" 14270866Simp 15270866Simp/ { 16270866Simp model = "Digi ConnectCore CC(W)-MX51"; 17270866Simp compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; 18270866Simp 19270866Simp memory { 20270866Simp reg = <0x90000000 0x08000000>; 21270866Simp }; 22270866Simp}; 23270866Simp 24270866Simp&ecspi1 { 25270866Simp pinctrl-names = "default"; 26270866Simp pinctrl-0 = <&pinctrl_ecspi1>; 27270866Simp fsl,spi-num-chipselects = <1>; 28270866Simp cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 29270866Simp status = "okay"; 30270866Simp 31270866Simp pmic: mc13892@0 { 32270866Simp pinctrl-names = "default"; 33270866Simp pinctrl-0 = <&pinctrl_mc13892>; 34270866Simp compatible = "fsl,mc13892"; 35270866Simp spi-max-frequency = <16000000>; 36270866Simp spi-cs-high; 37270866Simp reg = <0>; 38270866Simp interrupt-parent = <&gpio1>; 39270866Simp interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 40270866Simp fsl,mc13xxx-uses-rtc; 41270866Simp 42270866Simp regulators { 43270866Simp sw1_reg: sw1 { 44270866Simp regulator-min-microvolt = <1000000>; 45270866Simp regulator-max-microvolt = <1100000>; 46270866Simp regulator-boot-on; 47270866Simp regulator-always-on; 48270866Simp }; 49270866Simp 50270866Simp sw2_reg: sw2 { 51270866Simp regulator-min-microvolt = <1225000>; 52270866Simp regulator-max-microvolt = <1225000>; 53270866Simp regulator-boot-on; 54270866Simp regulator-always-on; 55270866Simp }; 56270866Simp 57270866Simp sw3_reg: sw3 { 58270866Simp regulator-min-microvolt = <1200000>; 59270866Simp regulator-max-microvolt = <1200000>; 60270866Simp regulator-boot-on; 61270866Simp regulator-always-on; 62270866Simp }; 63270866Simp 64270866Simp swbst_reg: swbst { }; 65270866Simp 66270866Simp viohi_reg: viohi { 67270866Simp regulator-always-on; 68270866Simp }; 69270866Simp 70270866Simp vpll_reg: vpll { 71270866Simp regulator-min-microvolt = <1800000>; 72270866Simp regulator-max-microvolt = <1800000>; 73270866Simp regulator-always-on; 74270866Simp }; 75270866Simp 76270866Simp vdig_reg: vdig { 77270866Simp regulator-min-microvolt = <1250000>; 78270866Simp regulator-max-microvolt = <1250000>; 79270866Simp regulator-always-on; 80270866Simp }; 81270866Simp 82270866Simp vsd_reg: vsd { 83270866Simp regulator-min-microvolt = <3150000>; 84270866Simp regulator-max-microvolt = <3150000>; 85270866Simp regulator-always-on; 86270866Simp }; 87270866Simp 88270866Simp vusb2_reg: vusb2 { 89270866Simp regulator-min-microvolt = <2600000>; 90270866Simp regulator-max-microvolt = <2600000>; 91270866Simp regulator-always-on; 92270866Simp }; 93270866Simp 94270866Simp vvideo_reg: vvideo { 95270866Simp regulator-min-microvolt = <2775000>; 96270866Simp regulator-max-microvolt = <2775000>; 97270866Simp regulator-always-on; 98270866Simp }; 99270866Simp 100270866Simp vaudio_reg: vaudio { 101270866Simp regulator-min-microvolt = <3000000>; 102270866Simp regulator-max-microvolt = <3000000>; 103270866Simp regulator-always-on; 104270866Simp }; 105270866Simp 106270866Simp vcam_reg: vcam { 107270866Simp regulator-min-microvolt = <2750000>; 108270866Simp regulator-max-microvolt = <2750000>; 109270866Simp regulator-always-on; 110270866Simp }; 111270866Simp 112270866Simp vgen1_reg: vgen1 { 113270866Simp regulator-min-microvolt = <1200000>; 114270866Simp regulator-max-microvolt = <1200000>; 115270866Simp regulator-always-on; 116270866Simp }; 117270866Simp 118270866Simp vgen2_reg: vgen2 { 119270866Simp regulator-min-microvolt = <3150000>; 120270866Simp regulator-max-microvolt = <3150000>; 121270866Simp regulator-always-on; 122270866Simp }; 123270866Simp 124270866Simp vgen3_reg: vgen3 { 125270866Simp regulator-min-microvolt = <1800000>; 126270866Simp regulator-max-microvolt = <1800000>; 127270866Simp regulator-always-on; 128270866Simp }; 129270866Simp 130270866Simp vusb_reg: vusb { 131270866Simp regulator-always-on; 132270866Simp }; 133270866Simp 134270866Simp gpo1_reg: gpo1 { }; 135270866Simp 136270866Simp gpo2_reg: gpo2 { }; 137270866Simp 138270866Simp gpo3_reg: gpo3 { }; 139270866Simp 140270866Simp gpo4_reg: gpo4 { }; 141270866Simp 142270866Simp pwgt2spi_reg: pwgt2spi { 143270866Simp regulator-always-on; 144270866Simp }; 145270866Simp 146270866Simp vcoincell_reg: vcoincell { 147270866Simp regulator-min-microvolt = <3000000>; 148270866Simp regulator-max-microvolt = <3000000>; 149270866Simp regulator-always-on; 150270866Simp }; 151270866Simp }; 152270866Simp }; 153270866Simp}; 154270866Simp 155270866Simp&esdhc2 { 156270866Simp pinctrl-names = "default"; 157270866Simp pinctrl-0 = <&pinctrl_esdhc2>; 158270866Simp cap-sdio-irq; 159270866Simp enable-sdio-wakeup; 160270866Simp keep-power-in-suspend; 161270866Simp max-frequency = <50000000>; 162270866Simp no-1-8-v; 163270866Simp non-removable; 164270866Simp vmmc-supply = <&gpo4_reg>; 165270866Simp status = "okay"; 166270866Simp}; 167270866Simp 168270866Simp&fec { 169270866Simp pinctrl-names = "default"; 170270866Simp pinctrl-0 = <&pinctrl_fec>; 171270866Simp phy-mode = "mii"; 172270866Simp phy-supply = <&gpo3_reg>; 173270866Simp /* Pins shared with LCD2, keep status disabled */ 174270866Simp}; 175270866Simp 176270866Simp&i2c2 { 177270866Simp pinctrl-names = "default"; 178270866Simp pinctrl-0 = <&pinctrl_i2c2>; 179270866Simp clock-frequency = <400000>; 180270866Simp status = "okay"; 181270866Simp 182270866Simp mma7455l@1d { 183270866Simp pinctrl-names = "default"; 184270866Simp pinctrl-0 = <&pinctrl_mma7455l>; 185270866Simp compatible = "fsl,mma7455l"; 186270866Simp reg = <0x1d>; 187270866Simp interrupt-parent = <&gpio1>; 188270866Simp interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; 189270866Simp }; 190270866Simp}; 191270866Simp 192270866Simp&nfc { 193270866Simp pinctrl-names = "default"; 194270866Simp pinctrl-0 = <&pinctrl_nfc>; 195270866Simp nand-bus-width = <8>; 196270866Simp nand-ecc-mode = "hw"; 197270866Simp nand-on-flash-bbt; 198270866Simp status = "okay"; 199270866Simp}; 200270866Simp 201270866Simp&usbotg { 202270866Simp phy_type = "utmi_wide"; 203270866Simp disable-over-current; 204270866Simp /* Device role is not known, keep status disabled */ 205270866Simp}; 206270866Simp 207270866Simp&weim { 208270866Simp pinctrl-names = "default"; 209270866Simp pinctrl-0 = <&pinctrl_weim>; 210270866Simp status = "okay"; 211270866Simp 212270866Simp lan9221: lan9221@5,0 { 213270866Simp pinctrl-names = "default"; 214270866Simp pinctrl-0 = <&pinctrl_lan9221>; 215270866Simp compatible = "smsc,lan9221", "smsc,lan9115"; 216270866Simp reg = <5 0x00000000 0x1000>; 217270866Simp fsl,weim-cs-timing = < 218270866Simp 0x00420081 0x00000000 219270866Simp 0x32260000 0x00000000 220270866Simp 0x72080f00 0x00000000 221270866Simp >; 222270866Simp clocks = <&clks IMX5_CLK_DUMMY>; 223270866Simp interrupt-parent = <&gpio1>; 224270866Simp interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 225270866Simp phy-mode = "mii"; 226270866Simp reg-io-width = <2>; 227270866Simp smsc,irq-push-pull; 228270866Simp vdd33a-supply = <&gpo2_reg>; 229270866Simp vddvario-supply = <&gpo2_reg>; 230270866Simp }; 231270866Simp}; 232270866Simp 233270866Simp&iomuxc { 234270866Simp imx51-digi-connectcore-som { 235270866Simp pinctrl_ecspi1: ecspi1grp { 236270866Simp fsl,pins = < 237270866Simp MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 238270866Simp MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 239270866Simp MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 240270866Simp MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 241270866Simp >; 242270866Simp }; 243270866Simp 244270866Simp pinctrl_esdhc2: esdhc2grp { 245270866Simp fsl,pins = < 246270866Simp MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 247270866Simp MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 248270866Simp MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 249270866Simp MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 250270866Simp MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 251270866Simp MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 252270866Simp >; 253270866Simp }; 254270866Simp 255270866Simp pinctrl_fec: fecgrp { 256270866Simp fsl,pins = < 257270866Simp MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 258270866Simp MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 259270866Simp MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 260270866Simp MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 261270866Simp MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 262270866Simp MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 263270866Simp MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 264270866Simp MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 265270866Simp MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 266270866Simp MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 267270866Simp MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 268270866Simp MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 269270866Simp MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 270270866Simp MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 271270866Simp MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 272270866Simp MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 273270866Simp MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 274270866Simp MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 275270866Simp >; 276270866Simp }; 277270866Simp 278270866Simp pinctrl_i2c2: i2c2grp { 279270866Simp fsl,pins = < 280270866Simp MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed 281270866Simp MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed 282270866Simp >; 283270866Simp }; 284270866Simp 285270866Simp pinctrl_nfc: nfcgrp { 286270866Simp fsl,pins = < 287270866Simp MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 288270866Simp MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 289270866Simp MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 290270866Simp MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 291270866Simp MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 292270866Simp MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 293270866Simp MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 294270866Simp MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 295270866Simp MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 296270866Simp MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 297270866Simp MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 298270866Simp MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 299270866Simp MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 300270866Simp MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 301270866Simp MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 302270866Simp >; 303270866Simp }; 304270866Simp 305270866Simp pinctrl_lan9221: lan9221grp { 306270866Simp fsl,pins = < 307270866Simp MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ 308270866Simp >; 309270866Simp }; 310270866Simp 311270866Simp pinctrl_mc13892: mc13892grp { 312270866Simp fsl,pins = < 313270866Simp MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ 314270866Simp >; 315270866Simp }; 316270866Simp 317270866Simp pinctrl_mma7455l: mma7455lgrp { 318270866Simp fsl,pins = < 319270866Simp MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ 320270866Simp MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ 321270866Simp >; 322270866Simp }; 323270866Simp 324270866Simp pinctrl_weim: weimgrp { 325270866Simp fsl,pins = < 326270866Simp MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 327270866Simp MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 328270866Simp MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 329270866Simp MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 330270866Simp MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 331270866Simp MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 332270866Simp MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 333270866Simp MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 334270866Simp MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 335270866Simp MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 336270866Simp MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 337270866Simp MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 338270866Simp MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 339270866Simp MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 340270866Simp MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 341270866Simp MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 342270866Simp MX51_PAD_EIM_A16__EIM_A16 0x80000000 343270866Simp MX51_PAD_EIM_A17__EIM_A17 0x80000000 344270866Simp MX51_PAD_EIM_A18__EIM_A18 0x80000000 345270866Simp MX51_PAD_EIM_A19__EIM_A19 0x80000000 346270866Simp MX51_PAD_EIM_A20__EIM_A20 0x80000000 347270866Simp MX51_PAD_EIM_A21__EIM_A21 0x80000000 348270866Simp MX51_PAD_EIM_A22__EIM_A22 0x80000000 349270866Simp MX51_PAD_EIM_A23__EIM_A23 0x80000000 350270866Simp MX51_PAD_EIM_A24__EIM_A24 0x80000000 351270866Simp MX51_PAD_EIM_A25__EIM_A25 0x80000000 352270866Simp MX51_PAD_EIM_A26__EIM_A26 0x80000000 353270866Simp MX51_PAD_EIM_A27__EIM_A27 0x80000000 354270866Simp MX51_PAD_EIM_D16__EIM_D16 0x80000000 355270866Simp MX51_PAD_EIM_D17__EIM_D17 0x80000000 356270866Simp MX51_PAD_EIM_D18__EIM_D18 0x80000000 357270866Simp MX51_PAD_EIM_D19__EIM_D19 0x80000000 358270866Simp MX51_PAD_EIM_D20__EIM_D20 0x80000000 359270866Simp MX51_PAD_EIM_D21__EIM_D21 0x80000000 360270866Simp MX51_PAD_EIM_D22__EIM_D22 0x80000000 361270866Simp MX51_PAD_EIM_D23__EIM_D23 0x80000000 362270866Simp MX51_PAD_EIM_D24__EIM_D24 0x80000000 363270866Simp MX51_PAD_EIM_D25__EIM_D25 0x80000000 364270866Simp MX51_PAD_EIM_D26__EIM_D26 0x80000000 365270866Simp MX51_PAD_EIM_D27__EIM_D27 0x80000000 366270866Simp MX51_PAD_EIM_D28__EIM_D28 0x80000000 367270866Simp MX51_PAD_EIM_D29__EIM_D29 0x80000000 368270866Simp MX51_PAD_EIM_D30__EIM_D30 0x80000000 369270866Simp MX51_PAD_EIM_D31__EIM_D31 0x80000000 370270866Simp MX51_PAD_EIM_OE__EIM_OE 0x80000000 371270866Simp MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 372270866Simp MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 373270866Simp MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ 374270866Simp >; 375270866Simp }; 376270866Simp }; 377270866Simp}; 378