1270866Simp/*
2270866Simp * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3270866Simp *
4270866Simp * The code contained herein is licensed under the GNU General Public
5270866Simp * License. You may obtain a copy of the GNU General Public License
6270866Simp * Version 2 or later at the following locations:
7270866Simp *
8270866Simp * http://www.opensource.org/licenses/gpl-license.html
9270866Simp * http://www.gnu.org/copyleft/gpl.html
10270866Simp */
11270866Simp
12270866Simp#include "imx51-digi-connectcore-som.dtsi"
13270866Simp
14270866Simp/ {
15270866Simp	model = "Digi ConnectCore CC(W)-MX51 JSK";
16270866Simp	compatible = "digi,connectcore-ccxmx51-jsk",
17270866Simp		     "digi,connectcore-ccxmx51-som", "fsl,imx51";
18270866Simp
19270866Simp	chosen {
20270866Simp		linux,stdout-path = &uart1;
21270866Simp	};
22270866Simp};
23270866Simp
24270866Simp&owire {
25270866Simp	pinctrl-names = "default";
26270866Simp	pinctrl-0 = <&pinctrl_owire>;
27270866Simp	status = "okay";
28270866Simp};
29270866Simp
30270866Simp&uart1 {
31270866Simp	pinctrl-names = "default";
32270866Simp	pinctrl-0 = <&pinctrl_uart1>;
33270866Simp	status = "okay";
34270866Simp};
35270866Simp
36270866Simp&uart2 {
37270866Simp	pinctrl-names = "default";
38270866Simp	pinctrl-0 = <&pinctrl_uart2>;
39270866Simp	status = "okay";
40270866Simp};
41270866Simp
42270866Simp&uart3 {
43270866Simp	pinctrl-names = "default";
44270866Simp	pinctrl-0 = <&pinctrl_uart3>;
45270866Simp	status = "okay";
46270866Simp};
47270866Simp
48270866Simp&usbotg {
49270866Simp	dr_mode = "otg";
50270866Simp	status = "okay";
51270866Simp};
52270866Simp
53270866Simp&usbh1 {
54270866Simp	pinctrl-names = "default";
55270866Simp	pinctrl-0 = <&pinctrl_usbh1>;
56270866Simp	dr_mode = "host";
57270866Simp	phy_type = "ulpi";
58270866Simp	disable-over-current;
59270866Simp	status = "okay";
60270866Simp};
61270866Simp
62270866Simp&iomuxc {
63270866Simp	imx51-digi-connectcore-jsk {
64270866Simp		pinctrl_owire: owiregrp {
65270866Simp			fsl,pins = <
66270866Simp				MX51_PAD_OWIRE_LINE__OWIRE_LINE		0x40000000
67270866Simp			>;
68270866Simp		};
69270866Simp
70270866Simp		pinctrl_uart1: uart1grp {
71270866Simp			fsl,pins = <
72270866Simp				MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
73270866Simp				MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
74270866Simp			>;
75270866Simp		};
76270866Simp
77270866Simp		pinctrl_uart2: uart2grp {
78270866Simp			fsl,pins = <
79270866Simp				MX51_PAD_UART2_RXD__UART2_RXD		0x1c5
80270866Simp				MX51_PAD_UART2_TXD__UART2_TXD		0x1c5
81270866Simp			>;
82270866Simp		};
83270866Simp
84270866Simp		pinctrl_uart3: uart3grp {
85270866Simp			fsl,pins = <
86270866Simp				MX51_PAD_UART3_RXD__UART3_RXD		0x1c5
87270866Simp				MX51_PAD_UART3_TXD__UART3_TXD		0x1c5
88270866Simp			>;
89270866Simp		};
90270866Simp
91270866Simp		pinctrl_usbh1: usbh1grp {
92270866Simp			fsl,pins = <
93270866Simp				MX51_PAD_USBH1_DATA0__USBH1_DATA0	0x1e5
94270866Simp				MX51_PAD_USBH1_DATA1__USBH1_DATA1	0x1e5
95270866Simp				MX51_PAD_USBH1_DATA2__USBH1_DATA2	0x1e5
96270866Simp				MX51_PAD_USBH1_DATA3__USBH1_DATA3	0x1e5
97270866Simp				MX51_PAD_USBH1_DATA4__USBH1_DATA4	0x1e5
98270866Simp				MX51_PAD_USBH1_DATA5__USBH1_DATA5	0x1e5
99270866Simp				MX51_PAD_USBH1_DATA6__USBH1_DATA6	0x1e5
100270866Simp				MX51_PAD_USBH1_DATA7__USBH1_DATA7	0x1e5
101270866Simp				MX51_PAD_USBH1_CLK__USBH1_CLK		0x1e5
102270866Simp				MX51_PAD_USBH1_DIR__USBH1_DIR		0x1e5
103270866Simp				MX51_PAD_USBH1_NXT__USBH1_NXT		0x1e5
104270866Simp				MX51_PAD_USBH1_STP__USBH1_STP		0x1e5
105270866Simp			>;
106270866Simp		};
107270866Simp	};
108270866Simp};
109