imx51-apf51dev.dts revision 270864 
1/*
2 * Copyright 2013 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/* APF51Dev is a docking board for the APF51 SOM */
13#include "imx51-apf51.dts"
14
15/ {
16	model = "Armadeus Systems APF51Dev docking/development board";
17	compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18
19	display@di1 {
20		compatible = "fsl,imx-parallel-display";
21		interface-pix-fmt = "bgr666";
22		pinctrl-names = "default";
23		pinctrl-0 = <&pinctrl_ipu_disp1>;
24
25		display-timings {
26			lw700 {
27				native-mode;
28				clock-frequency = <33000033>;
29				hactive = <800>;
30				vactive = <480>;
31				hback-porch = <96>;
32				hfront-porch = <96>;
33				vback-porch = <20>;
34				vfront-porch = <21>;
35				hsync-len = <64>;
36				vsync-len = <4>;
37				hsync-active = <1>;
38				vsync-active = <1>;
39				de-active = <1>;
40				pixelclk-active = <0>;
41			};
42		};
43
44		port {
45			display_in: endpoint {
46				remote-endpoint = <&ipu_di0_disp0>;
47			};
48		};
49	};
50
51	gpio-keys {
52		compatible = "gpio-keys";
53
54		user-key {
55			label = "user";
56			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
57			linux,code = <256>; /* BTN_0 */
58		};
59	};
60
61	leds {
62		compatible = "gpio-leds";
63
64		user {
65			label = "Heartbeat";
66			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
67			linux,default-trigger = "heartbeat";
68		};
69	};
70};
71
72&ecspi1 {
73	pinctrl-names = "default";
74	pinctrl-0 = <&pinctrl_ecspi1>;
75	fsl,spi-num-chipselects = <2>;
76	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
77		   <&gpio4 25 GPIO_ACTIVE_HIGH>;
78	status = "okay";
79};
80
81&ecspi2 {
82	pinctrl-names = "default";
83	pinctrl-0 = <&pinctrl_ecspi2>;
84	fsl,spi-num-chipselects = <2>;
85	cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
86		   <&gpio3 27 GPIO_ACTIVE_LOW>;
87	status = "okay";
88};
89
90&esdhc1 {
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_esdhc1>;
93	cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
94	bus-width = <4>;
95	status = "okay";
96};
97
98&esdhc2 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_esdhc2>;
101	bus-width = <4>;
102	non-removable;
103	status = "okay";
104};
105
106&i2c2 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_i2c2>;
109	status = "okay";
110};
111
112&iomuxc {
113	pinctrl-names = "default";
114	pinctrl-0 = <&pinctrl_hog>;
115
116	imx51-apf51dev {
117		pinctrl_hog: hoggrp {
118			fsl,pins = <
119				MX51_PAD_EIM_EB2__GPIO2_22   0x0C5
120				MX51_PAD_EIM_EB3__GPIO2_23   0x0C5
121				MX51_PAD_EIM_CS4__GPIO2_29   0x100
122				MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
123				MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
124				MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
125				MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
126				MX51_PAD_GPIO1_2__GPIO1_2    0x0C5
127				MX51_PAD_GPIO1_3__GPIO1_3    0x0C5
128			>;
129		};
130
131		pinctrl_ecspi1: ecspi1grp {
132			fsl,pins = <
133				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
134				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
135				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
136			>;
137		};
138
139		pinctrl_ecspi2: ecspi2grp {
140			fsl,pins = <
141				MX51_PAD_NANDF_RB3__ECSPI2_MISO		0x185
142				MX51_PAD_NANDF_D15__ECSPI2_MOSI		0x185
143				MX51_PAD_NANDF_RB2__ECSPI2_SCLK		0x185
144			>;
145		};
146
147		pinctrl_esdhc1: esdhc1grp {
148			fsl,pins = <
149				MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
150				MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
151				MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
152				MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
153				MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
154				MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
155			>;
156		};
157
158		pinctrl_esdhc2: esdhc2grp {
159			fsl,pins = <
160				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
161				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
162				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
163				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
164				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
165				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
166			>;
167		};
168
169		pinctrl_i2c2: i2c2grp {
170			fsl,pins = <
171				MX51_PAD_EIM_D27__I2C2_SCL		0x400001ed
172				MX51_PAD_EIM_D24__I2C2_SDA		0x400001ed
173			>;
174		};
175
176		pinctrl_ipu_disp1: ipudisp1grp {
177			fsl,pins = <
178				MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
179				MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
180				MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
181				MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
182				MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
183				MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
184				MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
185				MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
186				MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
187				MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
188				MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
189				MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
190				MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
191				MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
192				MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
193				MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
194				MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
195				MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
196				MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
197				MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
198				MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
199				MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
200				MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
201				MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
202				MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
203				MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
204			>;
205		};
206	};
207};
208
209&ipu_di0_disp0 {
210	remote-endpoint = <&display_in>;
211};
212