1262569Simp/* 2262569Simp * Copyright 2012 Armadeus Systems - <support@armadeus.com> 3262569Simp * Copyright 2012 Laurent Cans <laurent.cans@gmail.com> 4262569Simp * 5262569Simp * Based on mx51-babbage.dts 6262569Simp * Copyright 2011 Freescale Semiconductor, Inc. 7262569Simp * Copyright 2011 Linaro Ltd. 8262569Simp * 9262569Simp * The code contained herein is licensed under the GNU General Public 10262569Simp * License. You may obtain a copy of the GNU General Public License 11262569Simp * Version 2 or later at the following locations: 12262569Simp * 13262569Simp * http://www.opensource.org/licenses/gpl-license.html 14262569Simp * http://www.gnu.org/copyleft/gpl.html 15262569Simp */ 16262569Simp 17262569Simp/dts-v1/; 18262569Simp#include "imx51.dtsi" 19262569Simp 20262569Simp/ { 21262569Simp model = "Armadeus Systems APF51 module"; 22262569Simp compatible = "armadeus,imx51-apf51", "fsl,imx51"; 23262569Simp 24262569Simp memory { 25262569Simp reg = <0x90000000 0x20000000>; 26262569Simp }; 27262569Simp 28262569Simp clocks { 29262569Simp osc { 30262569Simp clock-frequency = <33554432>; 31262569Simp }; 32262569Simp }; 33262569Simp}; 34262569Simp 35262569Simp&fec { 36262569Simp pinctrl-names = "default"; 37270864Simp pinctrl-0 = <&pinctrl_fec>; 38262569Simp phy-mode = "mii"; 39270864Simp phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 40262569Simp phy-reset-duration = <1>; 41262569Simp status = "okay"; 42262569Simp}; 43262569Simp 44270864Simp&iomuxc { 45270864Simp imx51-apf51 { 46270864Simp pinctrl_fec: fecgrp { 47270864Simp fsl,pins = < 48270864Simp MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 49270864Simp MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 50270864Simp MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 51270864Simp MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 52270864Simp MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 53270864Simp MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 54270864Simp MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 55270864Simp MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 56270864Simp MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 57270864Simp MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 58270864Simp MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 59270864Simp MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 60270864Simp MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 61270864Simp MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 62270864Simp MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 63270864Simp MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 64270864Simp MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 65270864Simp MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 66270864Simp >; 67270864Simp }; 68270864Simp 69270864Simp pinctrl_uart3: uart3grp { 70270864Simp fsl,pins = < 71270864Simp MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 72270864Simp MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 73270864Simp >; 74270864Simp }; 75270864Simp }; 76270864Simp}; 77270864Simp 78262569Simp&nfc { 79262569Simp nand-bus-width = <8>; 80262569Simp nand-ecc-mode = "hw"; 81262569Simp nand-on-flash-bbt; 82262569Simp status = "okay"; 83262569Simp}; 84262569Simp 85262569Simp&uart3 { 86262569Simp pinctrl-names = "default"; 87270864Simp pinctrl-0 = <&pinctrl_uart3>; 88262569Simp status = "okay"; 89262569Simp}; 90