at91sam9g20.dtsi revision 270864
1262569Simp/* 2262569Simp * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC 3262569Simp * 4262569Simp * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5262569Simp * 6262569Simp * Licensed under GPLv2. 7262569Simp */ 8262569Simp 9262569Simp#include "at91sam9260.dtsi" 10262569Simp 11262569Simp/ { 12262569Simp model = "Atmel AT91SAM9G20 family SoC"; 13262569Simp compatible = "atmel,at91sam9g20"; 14262569Simp 15262569Simp memory { 16262569Simp reg = <0x20000000 0x08000000>; 17262569Simp }; 18262569Simp 19262569Simp ahb { 20262569Simp apb { 21262569Simp i2c0: i2c@fffac000 { 22262569Simp compatible = "atmel,at91sam9g20-i2c"; 23262569Simp }; 24262569Simp 25262569Simp adc0: adc@fffe0000 { 26262569Simp atmel,adc-startup-time = <40>; 27262569Simp }; 28270864Simp 29270864Simp pmc: pmc@fffffc00 { 30270864Simp plla: pllack { 31270864Simp atmel,clk-input-range = <2000000 32000000>; 32270864Simp atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, 33270864Simp <695000000 750000000 1 0>, 34270864Simp <645000000 700000000 2 0>, 35270864Simp <595000000 650000000 3 0>, 36270864Simp <545000000 600000000 0 1>, 37270864Simp <495000000 550000000 1 1>, 38270864Simp <445000000 500000000 2 1>, 39270864Simp <400000000 450000000 3 1>; 40270864Simp }; 41270864Simp 42270864Simp pllb: pllbck { 43270864Simp atmel,clk-input-range = <2000000 32000000>; 44270864Simp atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; 45270864Simp }; 46270864Simp 47270864Simp mck: masterck { 48270864Simp atmel,clk-output-range = <0 133000000>; 49270864Simp atmel,clk-divisors = <1 2 4 6>; 50270864Simp }; 51270864Simp }; 52262569Simp }; 53262569Simp }; 54262569Simp}; 55