1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD: releng/10.3/sys/dev/vxge/vxgehal/vxgehal-regs.h 221167 2011-04-28 14:33:15Z gnn $*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_REGS_H 34221167Sgnn#define VXGE_HAL_REGS_H 35221167Sgnn 36221167Sgnn__EXTERN_BEGIN_DECLS 37221167Sgnn 38221167Sgnn#pragma pack(1) 39221167Sgnn/* Using this strcture to calculate offsets */ 40221167Sgnntypedef struct vxge_hal_pci_config_le_t { 41221167Sgnn u16 vendor_id; /* 0x00 */ 42221167Sgnn u16 device_id; /* 0x02 */ 43221167Sgnn 44221167Sgnn u16 command; /* 0x04 */ 45221167Sgnn u16 status; /* 0x06 */ 46221167Sgnn 47221167Sgnn u8 revision; /* 0x08 */ 48221167Sgnn u8 pciClass[3]; /* 0x09 */ 49221167Sgnn 50221167Sgnn u8 cache_line_size; /* 0x0c */ 51221167Sgnn u8 latency_timer; /* 0x0d */ 52221167Sgnn u8 header_type; /* 0x0e */ 53221167Sgnn u8 bist; /* 0x0f */ 54221167Sgnn 55221167Sgnn u32 base_addr0_lo; /* 0x10 */ 56221167Sgnn u32 base_addr0_hi; /* 0x14 */ 57221167Sgnn 58221167Sgnn u32 base_addr1_lo; /* 0x18 */ 59221167Sgnn u32 base_addr1_hi; /* 0x1C */ 60221167Sgnn 61221167Sgnn u32 base_addr2_lo; /* 0x20 */ 62221167Sgnn u32 base_addr2_hi; /* 0x24 */ 63221167Sgnn 64221167Sgnn u32 cardbus_cis_pointer; /* 0x28 */ 65221167Sgnn 66221167Sgnn u16 subsystem_vendor_id; /* 0x2c */ 67221167Sgnn u16 subsystem_id; /* 0x2e */ 68221167Sgnn 69221167Sgnn u32 rom_base; /* 0x30 */ 70221167Sgnn u8 capabilities_pointer; /* 0x34 */ 71221167Sgnn u8 rsvd_35[3]; /* 0x35 */ 72221167Sgnn u32 rsvd_38; /* 0x38 */ 73221167Sgnn 74221167Sgnn u8 interrupt_line; /* 0x3c */ 75221167Sgnn u8 interrupt_pin; /* 0x3d */ 76221167Sgnn u8 min_grant; /* 0x3e */ 77221167Sgnn u8 max_latency; /* 0x3f */ 78221167Sgnn 79221167Sgnn u8 rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40]; 80221167Sgnn} vxge_hal_pci_config_le_t; /* 0x100 */ 81221167Sgnn 82221167Sgnntypedef struct vxge_hal_pci_config_t { 83221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 84221167Sgnn u16 device_id; /* 0x02 */ 85221167Sgnn u16 vendor_id; /* 0x00 */ 86221167Sgnn 87221167Sgnn u16 status; /* 0x06 */ 88221167Sgnn u16 command; /* 0x04 */ 89221167Sgnn 90221167Sgnn u8 pciClass[3]; /* 0x09 */ 91221167Sgnn u8 revision; /* 0x08 */ 92221167Sgnn 93221167Sgnn u8 bist; /* 0x0f */ 94221167Sgnn u8 header_type; /* 0x0e */ 95221167Sgnn u8 latency_timer; /* 0x0d */ 96221167Sgnn u8 cache_line_size; /* 0x0c */ 97221167Sgnn 98221167Sgnn u32 base_addr0_lo; /* 0x10 */ 99221167Sgnn u32 base_addr0_hi; /* 0x14 */ 100221167Sgnn 101221167Sgnn u32 base_addr1_lo; /* 0x18 */ 102221167Sgnn u32 base_addr1_hi; /* 0x1C */ 103221167Sgnn 104221167Sgnn u32 not_Implemented1; /* 0x20 */ 105221167Sgnn u32 not_Implemented2; /* 0x24 */ 106221167Sgnn 107221167Sgnn u32 cardbus_cis_pointer; /* 0x28 */ 108221167Sgnn 109221167Sgnn u16 subsystem_id; /* 0x2e */ 110221167Sgnn u16 subsystem_vendor_id; /* 0x2c */ 111221167Sgnn 112221167Sgnn u32 rom_base; /* 0x30 */ 113221167Sgnn u8 rsvd_35[3]; /* 0x35 */ 114221167Sgnn u8 capabilities_pointer; /* 0x34 */ 115221167Sgnn u32 rsvd_38; /* 0x38 */ 116221167Sgnn 117221167Sgnn u8 max_latency; /* 0x3f */ 118221167Sgnn u8 min_grant; /* 0x3e */ 119221167Sgnn u8 interrupt_pin; /* 0x3d */ 120221167Sgnn u8 interrupt_line; /* 0x3c */ 121221167Sgnn#else 122221167Sgnn u16 vendor_id; /* 0x00 */ 123221167Sgnn u16 device_id; /* 0x02 */ 124221167Sgnn 125221167Sgnn u16 command; /* 0x04 */ 126221167Sgnn u16 status; /* 0x06 */ 127221167Sgnn 128221167Sgnn u8 revision; /* 0x08 */ 129221167Sgnn u8 pciClass[3]; /* 0x09 */ 130221167Sgnn 131221167Sgnn u8 cache_line_size; /* 0x0c */ 132221167Sgnn u8 latency_timer; /* 0x0d */ 133221167Sgnn u8 header_type; /* 0x0e */ 134221167Sgnn u8 bist; /* 0x0f */ 135221167Sgnn 136221167Sgnn u32 base_addr0_lo; /* 0x10 */ 137221167Sgnn u32 base_addr0_hi; /* 0x14 */ 138221167Sgnn 139221167Sgnn u32 base_addr1_lo; /* 0x18 */ 140221167Sgnn u32 base_addr1_hi; /* 0x1C */ 141221167Sgnn 142221167Sgnn u32 not_Implemented1; /* 0x20 */ 143221167Sgnn u32 not_Implemented2; /* 0x24 */ 144221167Sgnn 145221167Sgnn u32 cardbus_cis_pointer; /* 0x28 */ 146221167Sgnn 147221167Sgnn u16 subsystem_vendor_id; /* 0x2c */ 148221167Sgnn u16 subsystem_id; /* 0x2e */ 149221167Sgnn 150221167Sgnn u32 rom_base; /* 0x30 */ 151221167Sgnn u8 capabilities_pointer; /* 0x34 */ 152221167Sgnn u8 rsvd_35[3]; /* 0x35 */ 153221167Sgnn u32 rsvd_38; /* 0x38 */ 154221167Sgnn 155221167Sgnn u8 interrupt_line; /* 0x3c */ 156221167Sgnn u8 interrupt_pin; /* 0x3d */ 157221167Sgnn u8 min_grant; /* 0x3e */ 158221167Sgnn u8 max_latency; /* 0x3f */ 159221167Sgnn 160221167Sgnn#endif 161221167Sgnn u8 rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40]; 162221167Sgnn} vxge_hal_pci_config_t; /* 0x100 */ 163221167Sgnn 164221167Sgnn#define VXGE_HAL_EEPROM_SIZE (0x01 << 11) 165221167Sgnn 166221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 167221167Sgnn#define VXGE_HAL_PCI_CAP_ID(ptr) *((ptr) + 3) 168221167Sgnn#define VXGE_HAL_PCI_CAP_NEXT(ptr) *((ptr) + 2) 169221167Sgnn#else 170221167Sgnn#define VXGE_HAL_PCI_CAP_ID(ptr) *(ptr) 171221167Sgnn#define VXGE_HAL_PCI_CAP_NEXT(ptr) *((ptr) + 1) 172221167Sgnn#endif 173221167Sgnn 174221167Sgnn/* Capability lists */ 175221167Sgnn 176221167Sgnn#define VXGE_HAL_PCI_CAP_LIST_ID 0 /* Capability ID */ 177221167Sgnn#define VXGE_HAL_PCI_CAP_ID_PM 0x01 /* Power Management */ 178221167Sgnn#define VXGE_HAL_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 179221167Sgnn#define VXGE_HAL_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 180221167Sgnn#define VXGE_HAL_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 181221167Sgnn#define VXGE_HAL_PCI_CAP_ID_MSI 0x05 /* Message Signalled Intr */ 182221167Sgnn#define VXGE_HAL_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 183221167Sgnn#define VXGE_HAL_PCI_CAP_ID_PCIX 0x07 /* PCIX */ 184221167Sgnn#define VXGE_HAL_PCI_CAP_ID_HT 0x08 /* Hypertransport */ 185221167Sgnn#define VXGE_HAL_PCI_CAP_ID_VS 0x09 /* Vendor Specific */ 186221167Sgnn#define VXGE_HAL_PCI_CAP_ID_DBGPORT 0x0A /* Debug Port */ 187221167Sgnn#define VXGE_HAL_PCI_CAP_ID_CPCICSR 0x0B /* CompPCI central res ctrl */ 188221167Sgnn#define VXGE_HAL_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Ctrl */ 189221167Sgnn#define VXGE_HAL_PCI_CAP_ID_PCIBSVID 0x0D /* PCI Bridge Subsys Vendr Id */ 190221167Sgnn#define VXGE_HAL_PCI_CAP_ID_AGP8X 0x0E /* AGP 8x */ 191221167Sgnn#define VXGE_HAL_PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 192221167Sgnn#define VXGE_HAL_PCI_CAP_ID_PCIE 0x10 /* PCI Express */ 193221167Sgnn#define VXGE_HAL_PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 194221167Sgnn#define VXGE_HAL_PCI_CAP_LIST_NEXT 1 /* Next cap in the list */ 195221167Sgnn#define VXGE_HAL_PCI_CAP_FLAGS 2 /* Cap defined flags(16 bits) */ 196221167Sgnn 197221167Sgnntypedef struct vxge_hal_pm_capability_le_t { 198221167Sgnn u8 capability_id; 199221167Sgnn u8 next_capability_ptr; 200221167Sgnn u16 capabilities_reg; 201221167Sgnn#define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 202221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 203221167Sgnn#define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 204221167Sgnn#define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Device specific init */ 205221167Sgnn#define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary current reqs */ 206221167Sgnn#define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 207221167Sgnn#define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 208221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */ 209221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */ 210221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */ 211221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */ 212221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */ 213221167Sgnn u16 pm_ctrl; 214221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr power state(D0 to D3) */ 215221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* trans from D3hot to D0 */ 216221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 217221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 218221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 219221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 220221167Sgnn u8 pm_ppb_ext; 221221167Sgnn#define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */ 222221167Sgnn#define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */ 223221167Sgnn u8 pm_data_reg; 224221167Sgnn} vxge_hal_pm_capability_le_t; 225221167Sgnn 226221167Sgnntypedef struct vxge_hal_pm_capability_t { 227221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 228221167Sgnn u16 capabilities_reg; 229221167Sgnn#define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 230221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 231221167Sgnn#define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 232221167Sgnn#define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Dev specific init */ 233221167Sgnn#define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary current reqs */ 234221167Sgnn#define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 235221167Sgnn#define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 236221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */ 237221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */ 238221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */ 239221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */ 240221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */ 241221167Sgnn u8 next_capability_ptr; 242221167Sgnn u8 capability_id; 243221167Sgnn u8 pm_data_reg; 244221167Sgnn u8 pm_ppb_ext; 245221167Sgnn#define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */ 246221167Sgnn#define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */ 247221167Sgnn u16 pm_ctrl; 248221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr pwr state (D0 to D3) */ 249221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* dev trans D3hot to D0 */ 250221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 251221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 252221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 253221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 254221167Sgnn#else 255221167Sgnn u8 capability_id; 256221167Sgnn u8 next_capability_ptr; 257221167Sgnn u16 capabilities_reg; 258221167Sgnn#define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 259221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 260221167Sgnn#define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 261221167Sgnn#define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Dev specific init */ 262221167Sgnn#define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary curr reqs */ 263221167Sgnn#define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 264221167Sgnn#define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 265221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */ 266221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */ 267221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */ 268221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */ 269221167Sgnn#define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */ 270221167Sgnn u16 pm_ctrl; 271221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr pwr state (D0 to D3) */ 272221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* dev trans D3hot to D0 */ 273221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 274221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 275221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 276221167Sgnn#define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 277221167Sgnn u8 pm_ppb_ext; 278221167Sgnn#define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */ 279221167Sgnn#define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */ 280221167Sgnn u8 pm_data_reg; 281221167Sgnn#endif 282221167Sgnn} vxge_hal_pm_capability_t; 283221167Sgnn 284221167Sgnntypedef struct vxge_hal_vpid_capability_le_t { 285221167Sgnn u8 capability_id; 286221167Sgnn u8 next_capability_ptr; 287221167Sgnn u16 vpd_address; 288221167Sgnn#define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */ 289221167Sgnn u32 vpd_data; 290221167Sgnn} vxge_hal_vpid_capability_le_t; 291221167Sgnn 292221167Sgnntypedef struct vxge_hal_vpid_capability_t { 293221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 294221167Sgnn u16 vpd_address; 295221167Sgnn#define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */ 296221167Sgnn u8 next_capability_ptr; 297221167Sgnn u8 capability_id; 298221167Sgnn u32 vpd_data; 299221167Sgnn#else 300221167Sgnn u8 capability_id; 301221167Sgnn u8 next_capability_ptr; 302221167Sgnn u16 vpd_address; 303221167Sgnn#define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */ 304221167Sgnn u32 vpd_data; 305221167Sgnn#endif 306221167Sgnn} vxge_hal_vpid_capability_t; 307221167Sgnn 308221167Sgnntypedef struct vxge_hal_sid_capability_le_t { 309221167Sgnn u8 capability_id; 310221167Sgnn u8 next_capability_ptr; 311221167Sgnn u8 sid_esr; 312221167Sgnn#define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */ 313221167Sgnn#define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 314221167Sgnn u8 sid_chasis_nr; 315221167Sgnn} vxge_hal_sid_capability_le_t; 316221167Sgnn 317221167Sgnntypedef struct vxge_hal_sid_capability_t { 318221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 319221167Sgnn u8 sid_chasis_nr; 320221167Sgnn u8 sid_esr; 321221167Sgnn#define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */ 322221167Sgnn#define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 323221167Sgnn u8 next_capability_ptr; 324221167Sgnn u8 capability_id; 325221167Sgnn#else 326221167Sgnn u8 capability_id; 327221167Sgnn u8 next_capability_ptr; 328221167Sgnn u8 sid_esr; 329221167Sgnn#define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */ 330221167Sgnn#define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 331221167Sgnn u8 sid_chasis_nr; 332221167Sgnn#endif 333221167Sgnn} vxge_hal_sid_capability_t; 334221167Sgnn 335221167Sgnntypedef struct vxge_hal_msi_capability_le_t { 336221167Sgnn u8 capability_id; 337221167Sgnn u8 next_capability_ptr; 338221167Sgnn u16 msi_control; 339221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */ 340221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 341221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */ 342221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */ 343221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 344221167Sgnn union { 345221167Sgnn struct { 346221167Sgnn u32 msi_addr; 347221167Sgnn u16 msi_data; 348221167Sgnn u16 msi_unused; 349221167Sgnn } ma32_no_pvm; 350221167Sgnn struct { 351221167Sgnn u32 msi_addr; 352221167Sgnn u16 msi_data; 353221167Sgnn u16 msi_unused; 354221167Sgnn u32 msi_mask; 355221167Sgnn u32 msi_pending; 356221167Sgnn } ma32_pvm; 357221167Sgnn struct { 358221167Sgnn u32 msi_addr_lo; 359221167Sgnn u32 msi_addr_hi; 360221167Sgnn u16 msi_data; 361221167Sgnn u16 msi_unused; 362221167Sgnn } ma64_no_pvm; 363221167Sgnn struct { 364221167Sgnn u32 msi_addr_lo; 365221167Sgnn u32 msi_addr_hi; 366221167Sgnn u16 msi_data; 367221167Sgnn u16 msi_unused; 368221167Sgnn u32 msi_mask; 369221167Sgnn u32 msi_pending; 370221167Sgnn } ma64_pvm; 371221167Sgnn } au; 372221167Sgnn} vxge_hal_msi_capability_le_t; 373221167Sgnn 374221167Sgnntypedef struct vxge_hal_msi_capability_t { 375221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 376221167Sgnn u16 msi_control; 377221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */ 378221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 379221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */ 380221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */ 381221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 382221167Sgnn u8 next_capability_ptr; 383221167Sgnn u8 capability_id; 384221167Sgnn union { 385221167Sgnn struct { 386221167Sgnn u32 msi_addr; 387221167Sgnn u16 msi_unused; 388221167Sgnn u16 msi_data; 389221167Sgnn } ma32_no_pvm; 390221167Sgnn struct { 391221167Sgnn u32 msi_addr; 392221167Sgnn u16 msi_unused; 393221167Sgnn u16 msi_data; 394221167Sgnn u32 msi_mask; 395221167Sgnn u32 msi_pending; 396221167Sgnn } ma32_pvm; 397221167Sgnn struct { 398221167Sgnn u32 msi_addr_lo; 399221167Sgnn u32 msi_addr_hi; 400221167Sgnn u16 msi_unused; 401221167Sgnn u16 msi_data; 402221167Sgnn } ma64_no_pvm; 403221167Sgnn struct { 404221167Sgnn u32 msi_addr_lo; 405221167Sgnn u32 msi_addr_hi; 406221167Sgnn u16 msi_unused; 407221167Sgnn u16 msi_data; 408221167Sgnn u32 msi_mask; 409221167Sgnn u32 msi_pending; 410221167Sgnn } ma64_pvm; 411221167Sgnn } au; 412221167Sgnn#else 413221167Sgnn u8 capability_id; 414221167Sgnn u8 next_capability_ptr; 415221167Sgnn u16 msi_control; 416221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */ 417221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 418221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */ 419221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */ 420221167Sgnn#define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 421221167Sgnn union { 422221167Sgnn struct { 423221167Sgnn u32 msi_addr; 424221167Sgnn u16 msi_data; 425221167Sgnn u16 msi_unused; 426221167Sgnn } ma32_no_pvm; 427221167Sgnn struct { 428221167Sgnn u32 msi_addr; 429221167Sgnn u16 msi_data; 430221167Sgnn u16 msi_unused; 431221167Sgnn u32 msi_mask; 432221167Sgnn u32 msi_pending; 433221167Sgnn } ma32_pvm; 434221167Sgnn struct { 435221167Sgnn u32 msi_addr_lo; 436221167Sgnn u32 msi_addr_hi; 437221167Sgnn u16 msi_data; 438221167Sgnn u16 msi_unused; 439221167Sgnn } ma64_no_pvm; 440221167Sgnn struct { 441221167Sgnn u32 msi_addr_lo; 442221167Sgnn u32 msi_addr_hi; 443221167Sgnn u16 msi_data; 444221167Sgnn u16 msi_unused; 445221167Sgnn u32 msi_mask; 446221167Sgnn u32 msi_pending; 447221167Sgnn } ma64_pvm; 448221167Sgnn } au; 449221167Sgnn#endif 450221167Sgnn} vxge_hal_msi_capability_t; 451221167Sgnn 452221167Sgnntypedef struct vxge_hal_chswp_capability_le_t { 453221167Sgnn u8 capability_id; 454221167Sgnn u8 next_capability_ptr; 455221167Sgnn u8 chswp_csr; 456221167Sgnn#define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 457221167Sgnn#define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 458221167Sgnn#define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 459221167Sgnn#define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */ 460221167Sgnn#define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */ 461221167Sgnn#define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 462221167Sgnn#define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 463221167Sgnn} vxge_hal_chswp_capability_le_t; 464221167Sgnn 465221167Sgnntypedef struct vxge_hal_chswp_capability_t { 466221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 467221167Sgnn u8 chswp_csr; 468221167Sgnn#define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 469221167Sgnn#define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 470221167Sgnn#define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 471221167Sgnn#define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */ 472221167Sgnn#define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */ 473221167Sgnn#define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 474221167Sgnn#define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 475221167Sgnn u8 next_capability_ptr; 476221167Sgnn u8 capability_id; 477221167Sgnn#else 478221167Sgnn u8 capability_id; 479221167Sgnn u8 next_capability_ptr; 480221167Sgnn u8 chswp_csr; 481221167Sgnn#define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 482221167Sgnn#define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 483221167Sgnn#define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 484221167Sgnn#define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */ 485221167Sgnn#define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */ 486221167Sgnn#define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 487221167Sgnn#define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 488221167Sgnn#endif 489221167Sgnn} vxge_hal_chswp_capability_t; 490221167Sgnn 491221167Sgnntypedef struct vxge_hal_shpc_capability_le_t { 492221167Sgnn u8 capability_id; 493221167Sgnn u8 next_capability_ptr; 494221167Sgnn} vxge_hal_shpc_capability_le_t; 495221167Sgnn 496221167Sgnntypedef struct vxge_hal_shpc_capability_t { 497221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 498221167Sgnn u8 next_capability_ptr; 499221167Sgnn u8 capability_id; 500221167Sgnn#else 501221167Sgnn u8 capability_id; 502221167Sgnn u8 next_capability_ptr; 503221167Sgnn#endif 504221167Sgnn} vxge_hal_shpc_capability_t; 505221167Sgnn 506221167Sgnntypedef struct vxge_hal_msix_capability_le_t { 507221167Sgnn u8 capability_id; 508221167Sgnn u8 next_capability_ptr; 509221167Sgnn u16 msix_control; 510221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */ 511221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */ 512221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */ 513221167Sgnn u32 table_offset; 514221167Sgnn#define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */ 515221167Sgnn#define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */ 516221167Sgnn u32 pba_offset; 517221167Sgnn#define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */ 518221167Sgnn#define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */ 519221167Sgnn} vxge_hal_msix_capability_le_t; 520221167Sgnn 521221167Sgnntypedef struct vxge_hal_msix_capability_t { 522221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 523221167Sgnn u16 msix_control; 524221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */ 525221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */ 526221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */ 527221167Sgnn u8 next_capability_ptr; 528221167Sgnn u8 capability_id; 529221167Sgnn u32 table_offset; 530221167Sgnn#define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */ 531221167Sgnn#define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */ 532221167Sgnn u32 pba_offset; 533221167Sgnn#define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */ 534221167Sgnn#define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */ 535221167Sgnn#else 536221167Sgnn u8 capability_id; 537221167Sgnn u8 next_capability_ptr; 538221167Sgnn u16 msix_control; 539221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */ 540221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */ 541221167Sgnn#define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */ 542221167Sgnn u32 table_offset; 543221167Sgnn#define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */ 544221167Sgnn#define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */ 545221167Sgnn u32 pba_offset; 546221167Sgnn#define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */ 547221167Sgnn#define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */ 548221167Sgnn#endif 549221167Sgnn} vxge_hal_msix_capability_t; 550221167Sgnn 551221167Sgnntypedef struct vxge_hal_pci_caps_offset_t { 552221167Sgnn u32 pm_cap_offset; 553221167Sgnn u32 vpd_cap_offset; 554221167Sgnn u32 sid_cap_offset; 555221167Sgnn u32 msi_cap_offset; 556221167Sgnn u32 vs_cap_offset; 557221167Sgnn u32 shpc_cap_offset; 558221167Sgnn u32 msix_cap_offset; 559221167Sgnn} vxge_hal_pci_caps_offset_t; 560221167Sgnn 561221167Sgnntypedef struct vxge_hal_pci_e_capability_le_t { 562221167Sgnn u8 capability_id; 563221167Sgnn u8 next_capability_ptr; 564221167Sgnn u16 pci_e_flags; 565221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 566221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 567221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 568221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 569221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 570221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 571221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 572221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ 573221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 574221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt msg number */ 575221167Sgnn u32 pci_e_devcap; 576221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ 577221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ 578221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ 579221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ 580221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ 581221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 582221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */ 583221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 584221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 585221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 586221167Sgnn u16 pci_e_devctl; 587221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Err Report En. */ 588221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Report En */ 589221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Report En */ 590221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Req Report En. */ 591221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 592221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 593221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 594221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 595221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 596221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 597221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 598221167Sgnn u16 pci_e_devsta; 599221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ 600221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ 601221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ 602221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Req Detected */ 603221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 604221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 605221167Sgnn u32 pci_e_lnkcap; 606221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */ 607221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */ 608221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */ 609221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ 610221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */ 611221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */ 612221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */ 613221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */ 614221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */ 615221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */ 616221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */ 617221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */ 618221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */ 619221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */ 620221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */ 621221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */ 622221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */ 623221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */ 624221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64ns. */ 625221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64ns to less than 128ns. */ 626221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */ 627221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256ns to less than 512ns. */ 628221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512ns to less than 1s. */ 629221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1s to less than 2s. */ 630221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2s-4s. */ 631221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4s. */ 632221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */ 633221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */ 634221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */ 635221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */ 636221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */ 637221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */ 638221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */ 639221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64us. */ 640221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */ 641221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clk power management. */ 642221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */ 643221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */ 644221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw reporting cap. */ 645221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */ 646221167Sgnn u16 pci_e_lnkctl; 647221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */ 648221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */ 649221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */ 650221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */ 651221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */ 652221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Completion Boundary. */ 653221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */ 654221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */ 655221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */ 656221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */ 657221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */ 658221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */ 659221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clk pwr mgmt. */ 660221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* Hw autonomous with dis */ 661221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgt interrupt enable */ 662221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW intr en */ 663221167Sgnn u16 pci_e_lnksta; 664221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */ 665221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */ 666221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */ 667221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ 668221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */ 669221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */ 670221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */ 671221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */ 672221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */ 673221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */ 674221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */ 675221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */ 676221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */ 677221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */ 678221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */ 679221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt intr enable */ 680221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */ 681221167Sgnn u32 pci_e_stlcap; 682221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */ 683221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */ 684221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */ 685221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */ 686221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 /* Power Indicator Present */ 687221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */ 688221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */ 689221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */ 690221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 /* 250 W Slot Power Limit */ 691221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 /* 275 W Slot Power Limit */ 692221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 /* 300 W Slot Power Limit */ 693221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */ 694221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */ 695221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */ 696221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */ 697221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */ 698221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */ 699221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Cmd Compl Support */ 700221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phys Slot Number */ 701221167Sgnn u16 pci_e_stlctl; 702221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Btn pressed enable */ 703221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Power Fault Detected En */ 704221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed Enable */ 705221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Change En */ 706221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmd Compl Intr Enable */ 707221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */ 708221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Attention Ind Control */ 709221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */ 710221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */ 711221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */ 712221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */ 713221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* POwer Indicator Control */ 714221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */ 715221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */ 716221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */ 717221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */ 718221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */ 719221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */ 720221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */ 721221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Interlock Crl */ 722221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL Layer State Ch En */ 723221167Sgnn u16 pci_e_stlsta; 724221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */ 725221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */ 726221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */ 727221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */ 728221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */ 729221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */ 730221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */ 731221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */ 732221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */ 733221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */ 734221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */ 735221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 /* Ele-mec Intrlock Control */ 736221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */ 737221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */ 738221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 /* DL Layer State Changed */ 739221167Sgnn u16 pci_e_rtctl; 740221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */ 741221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */ 742221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */ 743221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ 744221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */ 745221167Sgnn u16 pci_e_rtcap; 746221167Sgnn#define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS SW Visibility */ 747221167Sgnn u32 pci_e_rtsta; 748221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */ 749221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */ 750221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */ 751221167Sgnn} vxge_hal_pci_e_capability_le_t; 752221167Sgnn 753221167Sgnntypedef struct vxge_hal_pci_e_capability_t { 754221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 755221167Sgnn u16 pci_e_flags; 756221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 757221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 758221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 759221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 760221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 761221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 762221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 763221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ 764221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 765221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 766221167Sgnn u8 next_capability_ptr; 767221167Sgnn u8 capability_id; 768221167Sgnn u32 pci_e_devcap; 769221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ 770221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ 771221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ 772221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ 773221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ 774221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 775221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */ 776221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 777221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 778221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 779221167Sgnn u16 pci_e_devsta; 780221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Err Detected */ 781221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ 782221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ 783221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Req Detected */ 784221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 785221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 786221167Sgnn u16 pci_e_devctl; 787221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Corr'ble Err Reporting En. */ 788221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Reporting En */ 789221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting En */ 790221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupp Req Reporting En. */ 791221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 792221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 793221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 794221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 795221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 796221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 797221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 798221167Sgnn u32 pci_e_lnkcap; 799221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */ 800221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */ 801221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 2.5 Gb/s supported. */ 802221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ 803221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */ 804221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */ 805221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */ 806221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */ 807221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */ 808221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */ 809221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */ 810221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */ 811221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */ 812221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */ 813221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */ 814221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */ 815221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */ 816221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */ 817221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64 ns. */ 818221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64 ns to less than 128 ns. */ 819221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128 ns to less than 256 ns. */ 820221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256 ns to less than 512 ns. */ 821221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512 ns to less than 1us. */ 822221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1us to less than 2us. */ 823221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2us-4us. */ 824221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4us. */ 825221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */ 826221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */ 827221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */ 828221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */ 829221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */ 830221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */ 831221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */ 832221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64s. */ 833221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */ 834221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clk power management. */ 835221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */ 836221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */ 837221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw rep cap. */ 838221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */ 839221167Sgnn u16 pci_e_lnksta; 840221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */ 841221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */ 842221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */ 843221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ 844221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */ 845221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */ 846221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */ 847221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */ 848221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */ 849221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */ 850221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */ 851221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */ 852221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */ 853221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */ 854221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */ 855221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt interrupt enable */ 856221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */ 857221167Sgnn u16 pci_e_lnkctl; 858221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */ 859221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */ 860221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */ 861221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */ 862221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */ 863221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Compl Boundary. */ 864221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */ 865221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */ 866221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */ 867221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */ 868221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */ 869221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */ 870221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clk pwr mgmt. */ 871221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* Hw autonomous w/dis */ 872221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgmt intr enable */ 873221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW int en */ 874221167Sgnn u32 pci_e_stlcap; 875221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */ 876221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */ 877221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */ 878221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */ 879221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 /* Power Indicator Present */ 880221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */ 881221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */ 882221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */ 883221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 /* 250 W Slot Power Limit */ 884221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 /* 275 W Slot Power Limit */ 885221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 /* 300 W Slot Power Limit */ 886221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */ 887221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */ 888221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */ 889221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */ 890221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */ 891221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */ 892221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Command Compl Supp */ 893221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phy Slot Number */ 894221167Sgnn u16 pci_e_stlsta; 895221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */ 896221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */ 897221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */ 898221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */ 899221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */ 900221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */ 901221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */ 902221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */ 903221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */ 904221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */ 905221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */ 906221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 /* Ele-mec Intrlock Ctrl */ 907221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */ 908221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */ 909221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 /* DL State Changed */ 910221167Sgnn u16 pci_e_stlctl; 911221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Btn pressed en */ 912221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Pwr Fault Detected En */ 913221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed En */ 914221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Changed En */ 915221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmmd Completed Intr En */ 916221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */ 917221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Attention Ind Ctrl */ 918221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */ 919221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */ 920221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */ 921221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */ 922221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* POwer Ind Control */ 923221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */ 924221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */ 925221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */ 926221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */ 927221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */ 928221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */ 929221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */ 930221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Intrlock Ctrl */ 931221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL State Changed En */ 932221167Sgnn u16 pci_e_rtcap; 933221167Sgnn#define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS Software Visibility */ 934221167Sgnn u16 pci_e_rtctl; 935221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */ 936221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */ 937221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */ 938221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Intr Enable */ 939221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */ 940221167Sgnn u32 pci_e_rtsta; 941221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */ 942221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */ 943221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */ 944221167Sgnn#else 945221167Sgnn u8 capability_id; 946221167Sgnn u8 next_capability_ptr; 947221167Sgnn u16 pci_e_flags; 948221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 949221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 950221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 951221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 952221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 953221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 954221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 955221167Sgnn#define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ 956221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 957221167Sgnn#define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 958221167Sgnn u32 pci_e_devcap; 959221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ 960221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ 961221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ 962221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ 963221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ 964221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 965221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */ 966221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 967221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 968221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 969221167Sgnn u16 pci_e_devctl; 970221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Corr'ble Err Reporting En. */ 971221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Reporting En */ 972221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Err Reporting En */ 973221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupp Req Reporting En. */ 974221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 975221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 976221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 977221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 978221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 979221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 980221167Sgnn#define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 981221167Sgnn u16 pci_e_devsta; 982221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ 983221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ 984221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ 985221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupp Request Detected */ 986221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 987221167Sgnn#define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 988221167Sgnn u32 pci_e_lnkcap; 989221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */ 990221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */ 991221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */ 992221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ 993221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */ 994221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */ 995221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */ 996221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */ 997221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */ 998221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */ 999221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */ 1000221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */ 1001221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */ 1002221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */ 1003221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */ 1004221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */ 1005221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */ 1006221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */ 1007221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64 ns. */ 1008221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64ns to less than 128ns. */ 1009221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */ 1010221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256ns to less than 512ns. */ 1011221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512ns to less than 1us. */ 1012221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1us to less than 2us. */ 1013221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2us-4us. */ 1014221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4us. */ 1015221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */ 1016221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */ 1017221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */ 1018221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */ 1019221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */ 1020221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */ 1021221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */ 1022221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64us. */ 1023221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */ 1024221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clock power mgmt */ 1025221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */ 1026221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */ 1027221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw rep cap. */ 1028221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */ 1029221167Sgnn u16 pci_e_lnkctl; 1030221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */ 1031221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */ 1032221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */ 1033221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */ 1034221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */ 1035221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Completion Boundary. */ 1036221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */ 1037221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */ 1038221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */ 1039221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */ 1040221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */ 1041221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */ 1042221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clock power mgmt */ 1043221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* HW autonomous with dis */ 1044221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgmt interrupt enable */ 1045221167Sgnn#define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW int enable */ 1046221167Sgnn u16 pci_e_lnksta; 1047221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */ 1048221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */ 1049221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 and 2.5 Gb/s supported */ 1050221167Sgnn /* Supported Link speeds. */ 1051221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 1052221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */ 1053221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */ 1054221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */ 1055221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */ 1056221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */ 1057221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */ 1058221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */ 1059221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */ 1060221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */ 1061221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */ 1062221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */ 1063221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt intr enable */ 1064221167Sgnn#define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */ 1065221167Sgnn u32 pci_e_stlcap; 1066221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */ 1067221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */ 1068221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */ 1069221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */ 1070221167Sgnn /* Power Indicator Present */ 1071221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 1072221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */ 1073221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */ 1074221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */ 1075221167Sgnn /* 250 W Slot Power Limit */ 1076221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 1077221167Sgnn /* 275 W Slot Power Limit */ 1078221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 1079221167Sgnn /* 300 W Slot Power Limit */ 1080221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 1081221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */ 1082221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */ 1083221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */ 1084221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */ 1085221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */ 1086221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */ 1087221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Cmd Completed Supp */ 1088221167Sgnn#define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phys Slot Number */ 1089221167Sgnn u16 pci_e_stlctl; 1090221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Bttn pressed en */ 1091221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Power Fault Detected En */ 1092221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed Enable */ 1093221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Changed En */ 1094221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmd Compl Intr Enable */ 1095221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */ 1096221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Atten Ind Control */ 1097221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */ 1098221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */ 1099221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */ 1100221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */ 1101221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* Power Ind Control */ 1102221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */ 1103221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */ 1104221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */ 1105221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */ 1106221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */ 1107221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */ 1108221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */ 1109221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Intrlock Ctrl */ 1110221167Sgnn#define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL State Changed En */ 1111221167Sgnn u16 pci_e_stlsta; 1112221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */ 1113221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */ 1114221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */ 1115221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */ 1116221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */ 1117221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */ 1118221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */ 1119221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */ 1120221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */ 1121221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */ 1122221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */ 1123221167Sgnn /* Ele-mec Interlock Control */ 1124221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 1125221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */ 1126221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */ 1127221167Sgnn /* DL Layer State Changed */ 1128221167Sgnn#define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 1129221167Sgnn u16 pci_e_rtctl; 1130221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */ 1131221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */ 1132221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */ 1133221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ 1134221167Sgnn#define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */ 1135221167Sgnn u16 pci_e_rtcap; 1136221167Sgnn#define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS SW Visibility */ 1137221167Sgnn u32 pci_e_rtsta; 1138221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */ 1139221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */ 1140221167Sgnn#define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */ 1141221167Sgnn#endif 1142221167Sgnn} vxge_hal_pci_e_capability_t; 1143221167Sgnn 1144221167Sgnntypedef u32 vxge_hal_pci_e_caps_offset_t; 1145221167Sgnn 1146221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 1147221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 1148221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 1149221167Sgnn 1150221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_ID_ERR 1 1151221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_ID_VC 2 1152221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_ID_DSN 3 1153221167Sgnn#define VXGE_HAL_PCI_EXT_CAP_ID_PWR 4 1154221167Sgnn 1155221167Sgnntypedef struct vxge_hal_err_capability_t { 1156221167Sgnn u32 pci_err_header; 1157221167Sgnn u32 pci_err_uncor_status; 1158221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 1159221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 1160221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 1161221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 1162221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 1163221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 1164221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 1165221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 1166221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 1167221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 1168221167Sgnn#define VXGE_HAL_PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 1169221167Sgnn u32 pci_err_uncor_mask; 1170221167Sgnn u32 pci_err_uncor_server; 1171221167Sgnn u32 pci_err_cor_status; 1172221167Sgnn#define VXGE_HAL_PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 1173221167Sgnn#define VXGE_HAL_PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 1174221167Sgnn#define VXGE_HAL_PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 1175221167Sgnn#define VXGE_HAL_PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 1176221167Sgnn#define VXGE_HAL_PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 1177221167Sgnn#define VXGE_HAL_PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 1178221167Sgnn u32 pci_err_cap; 1179221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 1180221167Sgnn /* ECRC Generation Capable */ 1181221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_ECRC_GENC 0x00000020 1182221167Sgnn 1183221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 1184221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 1185221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 1186221167Sgnn u32 err_header_log; 1187221167Sgnn#define VXGE_HAL_PCI_ERR_HEADER_LOG(x) ((x) >> 31) /* Error Header Log */ 1188221167Sgnn u32 unused2[3]; 1189221167Sgnn u32 pci_err_root_command; 1190221167Sgnn u32 pci_err_root_status; 1191221167Sgnn u32 pci_err_root_cor_src; 1192221167Sgnn u32 pci_err_root_src; 1193221167Sgnn} vxge_hal_err_capability_t; 1194221167Sgnn 1195221167Sgnntypedef struct vxge_hal_vc_capability_t { 1196221167Sgnn u32 pci_vc_header; 1197221167Sgnn u32 pci_vc_port_reg1; 1198221167Sgnn u32 pci_vc_port_reg2; 1199221167Sgnn u32 pci_vc_port_ctrl; 1200221167Sgnn u32 pci_vc_port_status; 1201221167Sgnn u32 pci_vc_res_cap; 1202221167Sgnn u32 pci_vc_res_ctrl; 1203221167Sgnn u32 pci_vc_res_status; 1204221167Sgnn} vxge_hal_vc_capability_t; 1205221167Sgnn 1206221167Sgnntypedef struct vxge_hal_pwr_budget_capability_t { 1207221167Sgnn u32 pci_pwr_header; 1208221167Sgnn u32 pci_pwr_dsr; 1209221167Sgnn u32 pci_pwr_data; 1210221167Sgnn#define VXGE_HAL_PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 1211221167Sgnn#define VXGE_HAL_PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 1212221167Sgnn#define VXGE_HAL_PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 1213221167Sgnn#define VXGE_HAL_PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 1214221167Sgnn#define VXGE_HAL_PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 1215221167Sgnn#define VXGE_HAL_PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 1216221167Sgnn u32 pci_pwr_cap; 1217221167Sgnn#define VXGE_HAL_PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Include in sys budget */ 1218221167Sgnn} vxge_hal_pwr_budget_capability_t; 1219221167Sgnn 1220221167Sgnntypedef struct vxge_hal_pci_e_ext_caps_offset_t { 1221221167Sgnn u32 err_cap_offset; 1222221167Sgnn u32 vc_cap_offset; 1223221167Sgnn u32 dsn_cap_offset; 1224221167Sgnn u32 pwr_budget_cap_offset; 1225221167Sgnn} vxge_hal_pci_e_ext_caps_offset_t; 1226221167Sgnn 1227221167Sgnn#pragma pack() 1228221167Sgnn 1229221167Sgnn__EXTERN_END_DECLS 1230221167Sgnn 1231221167Sgnn#endif /* VXGE_HAL_REGS_H */ 1232