1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD: releng/10.3/sys/dev/vxge/include/vxgehal-status.h 221167 2011-04-28 14:33:15Z gnn $*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_STATUS_H 34221167Sgnn#define VXGE_HAL_STATUS_H 35221167Sgnn 36221167Sgnn__EXTERN_BEGIN_DECLS 37221167Sgnn 38221167Sgnn#define VXGE_HAL_EVENT_BASE 0 39221167Sgnn#define VXGE_LL_EVENT_BASE 100 40221167Sgnn 41221167Sgnn/* 42221167Sgnn * enum vxge_hal_event_e - Enumerates slow-path HAL events. 43221167Sgnn * @VXGE_HAL_EVENT_UNKNOWN: Unknown (and invalid) event. 44221167Sgnn * @VXGE_HAL_EVENT_SERR: Serious hardware error event. 45221167Sgnn * @VXGE_HAL_EVENT_CRITICAL: Critical vpath hardware error event. 46221167Sgnn * @VXGE_HAL_EVENT_ECCERR: vpath ECC error event. 47221167Sgnn * @VXGE_HAL_EVENT_KDFCCTL: FIFO Doorbell fifo error. 48221167Sgnn * @VXGE_HAL_EVENT_SRPCIM_CRITICAL: srpcim hardware error event. 49221167Sgnn * @VXGE_HAL_EVENT_MRPCIM_CRITICAL: mrpcim hardware error event. 50221167Sgnn * @VXGE_HAL_EVENT_MRPCIM_ECCERR: mrpcim ecc error event. 51221167Sgnn * @VXGE_HAL_EVENT_DEVICE_RESET_START: Privileged entity starting device reset 52221167Sgnn * @VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE: Device reset has been completed 53221167Sgnn * @VXGE_HAL_EVENT_VPATH_RESET_START: A function is starting vpath reset 54221167Sgnn * @VXGE_HAL_EVENT_VPATH_RESET_COMPLETE: vpath reset has been completed 55221167Sgnn * @VXGE_HAL_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish 56221167Sgnn * slot-freeze from the rest critical events (e.g. ECC) when it is 57221167Sgnn * impossible to PIO read "through" the bus, i.e. when getting all-foxes. 58221167Sgnn * 59221167Sgnn * vxge_hal_event_e enumerates slow-path HAL eventis. 60221167Sgnn * 61221167Sgnn * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_up_f {}, 62221167Sgnn * vxge_uld_link_down_f {}. 63221167Sgnn */ 64221167Sgnntypedef enum vxge_hal_event_e { 65221167Sgnn VXGE_HAL_EVENT_UNKNOWN = 0, 66221167Sgnn /* HAL events */ 67221167Sgnn VXGE_HAL_EVENT_SERR = VXGE_HAL_EVENT_BASE + 1, 68221167Sgnn VXGE_HAL_EVENT_CRITICAL = VXGE_HAL_EVENT_BASE + 2, 69221167Sgnn VXGE_HAL_EVENT_ECCERR = VXGE_HAL_EVENT_BASE + 3, 70221167Sgnn VXGE_HAL_EVENT_KDFCCTL = VXGE_HAL_EVENT_BASE + 4, 71221167Sgnn VXGE_HAL_EVENT_SRPCIM_CRITICAL = VXGE_HAL_EVENT_BASE + 5, 72221167Sgnn VXGE_HAL_EVENT_MRPCIM_CRITICAL = VXGE_HAL_EVENT_BASE + 6, 73221167Sgnn VXGE_HAL_EVENT_MRPCIM_ECCERR = VXGE_HAL_EVENT_BASE + 7, 74221167Sgnn VXGE_HAL_EVENT_DEVICE_RESET_START = VXGE_HAL_EVENT_BASE + 8, 75221167Sgnn VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE = VXGE_HAL_EVENT_BASE + 9, 76221167Sgnn VXGE_HAL_EVENT_VPATH_RESET_START = VXGE_HAL_EVENT_BASE + 10, 77221167Sgnn VXGE_HAL_EVENT_VPATH_RESET_COMPLETE = VXGE_HAL_EVENT_BASE + 11, 78221167Sgnn VXGE_HAL_EVENT_SLOT_FREEZE = VXGE_HAL_EVENT_BASE + 12 79221167Sgnn} vxge_hal_event_e; 80221167Sgnn 81221167Sgnn#define VXGE_HAL_BASE_INF 100 82221167Sgnn#define VXGE_HAL_BASE_ERR 200 83221167Sgnn#define VXGE_HAL_BASE_BADCFG 300 84221167Sgnn 85221167Sgnn/* 86221167Sgnn * enum vxge_hal_status_e - HAL return codes. 87221167Sgnn * @VXGE_HAL_OK: Success. 88221167Sgnn * @VXGE_HAL_FAIL: Failure. 89221167Sgnn * @VXGE_HAL_PENDING: Opearation is pending 90221167Sgnn * @VXGE_HAL_CONTINUE: Continue processing 91221167Sgnn * @VXGE_HAL_RETURN: Stop processing and return 92221167Sgnn * @VXGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 93221167Sgnn * (specific to polling mode completion processing). 94221167Sgnn * @VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 95221167Sgnn * descriptors. See vxge_hal_fifo_txdl_next_completed(). 96221167Sgnn * @VXGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 97221167Sgnn * descriptors 98221167Sgnn * are reserved (via vxge_hal_fifo_txdl_reserve(), 99221167Sgnn * vxge_hal_ring_rxd_reserve()) 100221167Sgnn * and not yet freed (via vxge_hal_fifo_txdl_free(), 101221167Sgnn * vxge_hal_ring_rxd_free()). 102221167Sgnn * @VXGE_HAL_INF_QUEUE_IS_NOT_READY: A descriptor was reserved and not posted 103221167Sgnn * @VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 104221167Sgnn * poll until PIO is executed. 105221167Sgnn * @VXGE_HAL_INF_STATS_IS_NOT_READY: Queue is not ready for 106221167Sgnn * operation. 107221167Sgnn * @VXGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 108221167Sgnn * reserve. Internal use only. 109221167Sgnn * @VXGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 110221167Sgnn * callback when instructed to exit descriptor processing loop 111221167Sgnn * prematurely. Typical usage: polling mode of processing completed 112221167Sgnn * descriptors. 113221167Sgnn * Upon getting LRO_ISED, ll driver shall 114221167Sgnn * 1) initialise lro struct with mbuf if sg_num == 1. 115221167Sgnn * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 116221167Sgnn * append the new mbuf to the tail of mbuf chain in lro struct. 117221167Sgnn * @VXGE_HAL_INF_SW_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 118221167Sgnn * being initiated. 119221167Sgnn * @VXGE_HAL_INF_SW_LRO_CONT: Returned by ULD LRO module, when new frame 120221167Sgnn * is appended at the end of existing LRO. 121221167Sgnn * @VXGE_HAL_INF_SW_LRO_UNCAPABLE: Returned by ULD LRO module, when new 122221167Sgnn * frame is not LRO capable. 123221167Sgnn * @VXGE_HAL_INF_SW_LRO_FLUSH_SESSION: Returned by ULD LRO module, 124221167Sgnn * when new frame triggers LRO flush. 125221167Sgnn * @VXGE_HAL_INF_SW_LRO_FLUSH_BOTH: Returned by ULD LRO module, when new 126221167Sgnn * frame triggers LRO flush. Lro frame should be flushed first then 127221167Sgnn * new frame should be flushed next. 128221167Sgnn * @VXGE_HAL_INF_SW_LRO_END_3: Returned by ULD LRO module, when new 129221167Sgnn * frame triggers close of current LRO session and opening of new LRO session 130221167Sgnn * with the frame. 131221167Sgnn * @VXGE_HAL_INF_SW_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 132221167Sgnn * more LRO sessions can be added. 133221167Sgnn * @VXGE_HAL_INF_NOT_ENOUGH_HW_CQES: Enough CQEs are available 134221167Sgnn * @VXGE_HAL_INF_LINK_UP_DOWN: Link up down indication received 135221167Sgnn * @VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 136221167Sgnn * @VXGE_HAL_ERR_INVALID_HANDLE: The handle passed is invalid. 137221167Sgnn * @VXGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 138221167Sgnn * allocating descriptors). 139221167Sgnn * @VXGE_HAL_ERR_VPATH_NOT_AVAILABLE: Vpath is not allocated to this 140221167Sgnn * function 141221167Sgnn * @VXGE_HAL_ERR_VPATH_NOT_OPEN: Vpath is not opened i.e put in service. 142221167Sgnn * @VXGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 143221167Sgnn * invoked not because of the X3100-generated interrupt. 144221167Sgnn * @VXGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 145221167Sgnn * configure more than VXGE_HAL_MAX_MAC_ADDRESSES mac addresses. 146221167Sgnn * @VXGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 147221167Sgnn * to set X3100 byte swapper in accordnace with the host 148221167Sgnn * endian-ness. 149221167Sgnn * @VXGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 150221167Sgnn * a "quiescent" state. 151221167Sgnn * @VXGE_HAL_ERR_INVALID_MTU_SIZE:Returned when MTU size specified by 152221167Sgnn * caller is not in the (64, 9600) range. 153221167Sgnn * @VXGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 154221167Sgnn * @VXGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 155221167Sgnn * check for zero/non-zero only.) 156221167Sgnn * @VXGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. X3100 supports two Base 157221167Sgnn * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 158221167Sgnn * @VXGE_HAL_ERR_INVALID_INDEX: Invalid index. Example, attempt to read 159221167Sgnn * register value from the register section that is out of range. 160221167Sgnn * @VXGE_HAL_ERR_INVALID_TYPE: Invalid register section. 161221167Sgnn * @VXGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 162221167Sgnn * register value (with offset) outside of the register section range 163221167Sgnn * @VXGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 164221167Sgnn * (passed by ULD) is invalid. 165221167Sgnn * @VXGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 166221167Sgnn * management "get" routines when the retrieved information does 167221167Sgnn * not fit into the provided buffer. 168221167Sgnn * @VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 169221167Sgnn * @VXGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 170221167Sgnn * are not compatible. 171221167Sgnn * @VXGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 172221167Sgnn * @VXGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 173221167Sgnn * @VXGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 174221167Sgnn * in a scatter-gather list. 175221167Sgnn * @VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 176221167Sgnn * Typically means wrong sequence of API calls. 177221167Sgnn * @VXGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 178221167Sgnn * @VXGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 179221167Sgnn * @VXGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 180221167Sgnn * @VXGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 181221167Sgnn * SPDM table. 182221167Sgnn * @VXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 183221167Sgnn * synch ith the actual one. 184221167Sgnn * @VXGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI parameters. 185221167Sgnn * @VXGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 186221167Sgnn * (including vxge_hal_fifo_handle_tcode() and vxge_hal_ring_handle_tcode()) 187221167Sgnn * on: ECC, parity, SERR. 188221167Sgnn * Also returned when PIO read does not go through ("all-foxes") 189221167Sgnn * because of "slot-freeze". 190221167Sgnn * @VXGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 191221167Sgnn * Returned by vxge_hal_device_reset(). One circumstance when it could 192221167Sgnn * happen: slot freeze by the system (see @VXGE_HAL_ERR_CRITICAL). 193221167Sgnn * @VXGE_HAL_ERR_TOO_MANY: This error is returned if there were laready 194221167Sgnn * maximum number of sessions or queues allocated 195221167Sgnn * @VXGE_HAL_ERR_PKT_DROP: Packet got dropped 196221167Sgnn * @VXGE_HAL_ERR_INVALID_BLOCK_SIZE: Invalid block size 197221167Sgnn * @VXGE_HAL_ERR_INVALID_STATE: Invalid state 198221167Sgnn * @VXGE_HAL_ERR_PRIVILAGED_OPEARATION: A previleged operation is attempted 199221167Sgnn * @VXGE_HAL_ERR_RESET_IN_PROGRESS: Reset is currently in progress 200221167Sgnn * @VXGE_HAL_ERR_MAC_TABLE_FULL: DA table is full 201221167Sgnn * @VXGE_HAL_ERR_MAC_TABLE_EMPTY: DA table is empty 202221167Sgnn * @VXGE_HAL_ERR_MAC_TABLE_NO_MORE_ENTRIES: There are no more entries in the 203221167Sgnn * DA table 204221167Sgnn * @VXGE_HAL_ERR_RTDMA_RTDMA_READY: RTDMA is ready 205221167Sgnn * @VXGE_HAL_ERR_WRDMA_WRDMA_READY: WRDMA is ready 206221167Sgnn * @VXGE_HAL_ERR_KDFC_KDFC_READY: Kernel mode doorbell controller ready 207221167Sgnn * @VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY: Transmit Protocol Assist TMAC buffer empty 208221167Sgnn * @VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT: PIC block is quiescent 209221167Sgnn * @VXGE_HAL_ERR_XGMAC_NETWORK_FAULT: Network Fault 210221167Sgnn * @VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT: ROCRC offload quiescent 211221167Sgnn * @VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY: G3DDR Interface FB Ready 212221167Sgnn * @VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY: G3DDR Interface CM Ready 213221167Sgnn * @VXGE_HAL_ERR_RIC_RIC_RUNNING: Adapter RIC is still programming flash 214221167Sgnn * settings to device 215221167Sgnn * @VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK: CMG C PLL in lock 216221167Sgnn * @VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK: XGMAC X PLL in Lock 217221167Sgnn * @VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK: FBUF M PLL in Lock 218221167Sgnn * @VXGE_HAL_ERR_PCC_PCC_IDLE: PCC is idle 219221167Sgnn * @VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT: ROCRC RC PCC quiescent 220221167Sgnn * @VXGE_HAL_ERR_SLOT_FREEZE: PCI Slot frozen 221221167Sgnn * @VXGE_HAL_ERR_INVALID_TCODE: The t-code returned is invalid 222221167Sgnn * @VXGE_HAL_ERR_INVALID_PORT: The port number specified is invalid 223221167Sgnn * @VXGE_HAL_ERR_INVALID_PRIORITY: Proiority specified is invalid 224221167Sgnn * @VXGE_HAL_ERR_INVALID_MIN_BANDWIDTH: Minimum bandwidth specified is invalid 225221167Sgnn * @VXGE_HAL_ERR_INVALID_MAX_BANDWIDTH: Maximum bandwidth specified is invalid 226221167Sgnn * @VXGE_HAL_ERR_INVALID_BANDWIDTH_LIMIT: Bandwidth limit specified is invalid 227221167Sgnn * @VXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTH: Total bandwidth specified is invalid 228221167Sgnn * @VXGE_HAL_ERR_MANAGER_NOT_FOUND: The Function 0 driver or MRPCIM manager is 229221167Sgnn * down 230221167Sgnn * @VXGE_HAL_ERR_TIME_OUT: Timeout occurred 231221167Sgnn * @VXGE_HAL_ERR_EVENT_UNKNOWN: Unknown alarm 232221167Sgnn * @VXGE_HAL_ERR_EVENT_SERR: Serious error on device 233221167Sgnn * @VXGE_HAL_ERR_EVENT_CRITICAL: Critical error in the vpath 234221167Sgnn * @VXGE_HAL_ERR_EVENT_ECCERR: Ecc Error returned in t-code 235221167Sgnn * @VXGE_HAL_ERR_EVENT_KDFCCTL: Kdfcctl error on the device 236221167Sgnn * @VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL: Critical error in SRPCIM 237221167Sgnn * @VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL: Critical error in MRPCIM 238221167Sgnn * @VXGE_HAL_ERR_EVENT_MRPCIM_ECCERR: ECC error in MRPCIM 239221167Sgnn * @VXGE_HAL_ERR_EVENT_RESET_START: Device is going to be reset 240221167Sgnn * @VXGE_HAL_ERR_EVENT_RESET_COMPLETE: Device reset is complete 241221167Sgnn * @VXGE_HAL_ERR_EVENT_SLOT_FREEZE: PCI Slot freeze 242221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID: Invalid port id in config 243221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA: Invalid media type in config 244221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU: Invalid initial MTU size 245221167Sgnn * in config 246221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE: Invalid autonegotiation mode 247221167Sgnn * in config 248221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE: Invalid autonegotiation rate 249221167Sgnn * in config 250221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM: Invalid fixed use fsm in config 251221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM: Invalid ANTP use FSM in config 252221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM: Invalid ANBE use FSM in config 253221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD: Invalid link stability 254221167Sgnn * period in config 255221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD: Invalid port stability 256221167Sgnn * period in config 257221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN: Invalid Transmit MAC enable setting 258221167Sgnn * in config 259221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN: Invalid Receive MAC enable setting 260221167Sgnn * in config 261221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD: Invalid Transmit MAC PAD enable setting 262221167Sgnn * in config 263221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE: Invalid Transmit MAC PAD Byte 264221167Sgnn * setting in config 265221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD: Invalid Transmit MAC utilization 266221167Sgnn * period in config 267221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS: Invalid Receive MAC strip FCS 268221167Sgnn * setting in config 269221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN: Invalid Receive MAC PROM enable 270221167Sgnn * in config 271221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM: Invalid Receive MAC discard 272221167Sgnn * pfrm setting in config 273221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD: Invalid Receive MAC utilization 274221167Sgnn * period in config 275221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN: Invalid Receive MAC pause 276221167Sgnn * generation enable setting in config 277221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN: Invalid Receive MAC pause 278221167Sgnn * receive enable setting in config 279221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME: Invalid Receive MAC high ptime 280221167Sgnn * setting in config 281221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN: Invalid Receive MAC pause 282221167Sgnn * limitter enable setting in config 283221167Sgnn * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT: Invalid Receive MAC max limit 284221167Sgnn * setting in config 285221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU: Invalid initial MTU size 286221167Sgnn * in config 287221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN: Invalid Transmit MAC enable setting 288221167Sgnn * in config 289221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN: Invalid Receive MAC enable setting 290221167Sgnn * in config 291221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD: Invalid Transmit MAC PAD enable 292221167Sgnn * setting in config 293221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE: Invalid Transmit MAC PAD Byte 294221167Sgnn * setting in config 295221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD: Invalid Transmit MAC 296221167Sgnn * utilization period in config 297221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS: Invalid Receive MAC strip FCS 298221167Sgnn * setting in config 299221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN: Invalid Receive MAC PROM enable 300221167Sgnn * in config 301221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM: Invalid Receive MAC discard 302221167Sgnn * pfrm setting in config 303221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD: Invalid Receive MAC 304221167Sgnn * utilization period in config 305221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN: Invalid Receive MAC 306221167Sgnn * pause generation enable setting in config 307221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN: Invalid Receive MAC 308221167Sgnn * pause receive enable setting in config 309221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME: Invalid Receive MAC 310221167Sgnn * high ptime setting in config 311221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN: Invalid Receive MAC pause 312221167Sgnn * limitter enable setting in config 313221167Sgnn * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT: Invalid Receive MAC 314221167Sgnn * max limit setting in config 315221167Sgnn * @VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD: Invalid network 316221167Sgnn * stability period setting in config 317221167Sgnn * @VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD: Invalid MC pause threshold 318221167Sgnn * setting in config 319221167Sgnn * @VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN: Invalid perma stop enable setting 320221167Sgnn * in config 321221167Sgnn * @VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS: Invalid Transmit MAC 322221167Sgnn * tx switch disable in config 323221167Sgnn * @VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN: Invalid Transmit MAC 324221167Sgnn * lossy switch enable in config 325221167Sgnn * @VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN: Invalid Transmit MAC 326221167Sgnn * lossy wire enable in config 327221167Sgnn * @VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS: Invalid Transmit 328221167Sgnn * MAC broadcast to wire disable in config 329221167Sgnn * @VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS: Invalid Transmit 330221167Sgnn * MAC broadcast to switch disable in config 331221167Sgnn * @VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN: Invalid Transmit MAC 332221167Sgnn * host append fcs in config 333221167Sgnn * @VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N: Invalid Transmit Protocol 334221167Sgnn * Assist support SNAP AB N setting in config 335221167Sgnn * @VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N: Invalid Transmit Protocol 336221167Sgnn * Assist ecc enable N setting in config 337221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR: Invalid Receive Protocol 338221167Sgnn * Assist ignore frame error in config 339221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N: Invalid Receive Protocol Assist 340221167Sgnn * SNAP AB N in config 341221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO: Invalid Receive Protocol 342221167Sgnn * Assist search for HAO in config 343221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS: Invalid Receive 344221167Sgnn * Protocol support ipv6 mobile headers in config 345221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING: Invalid Receive Protocol 346221167Sgnn * Assist ipv6 stop searching in config 347221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN: Invalid Receive Protocol 348221167Sgnn * Assist no ps if unknown in config 349221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE: Invalid Receive Protocol 350221167Sgnn * Assist search for etype in config 351221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM: Invalid Receive Protocol 352221167Sgnn * Assist replication setting in config 353221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF: Invalid Receive Protocol Assist 354221167Sgnn * replication setting in config 355221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM: Invalid Receive Protocol Assist 356221167Sgnn * replication setting in config 357221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH: Invalid Receive Protocol 358221167Sgnn * Assist replication setting in config 359221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH: Invalid Receive Protocol 360221167Sgnn * Assist replication setting in config 361221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH: Invalid Receive Protocol 362221167Sgnn * Assist replication setting in config 363221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH: Invalid Receive Protocol 364221167Sgnn * Assist replication setting in config 365221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF: Invalid Receive Protocol Assist 366221167Sgnn * replication setting in config 367221167Sgnn * @VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG: Invalid Receive Protocol 368221167Sgnn * Assist replication setting in config 369221167Sgnn * @VXGE_HAL_BADCFG_LAG_LAG_EN: Invalid option for lag_en in config 370221167Sgnn * @VXGE_HAL_BADCFG_LAG_LAG_MODE: Invalid option for lag_mode in config 371221167Sgnn * @VXGE_HAL_BADCFG_LAG_TX_DISCARD: Invalid option for tx_discard in config 372221167Sgnn * @VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS: Invalid option for incr_tx_aggr_stats 373221167Sgnn * in config 374221167Sgnn * @VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL: Invalid option for distrib_alg_sel 375221167Sgnn * in config 376221167Sgnn * @VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL: Invalid option for 377221167Sgnn * distrib_remap_if_fail in config 378221167Sgnn * @VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY: Invalid Collector Max Delay in config 379221167Sgnn * @VXGE_HAL_BADCFG_LAG_RX_DISCARD: Invalid option for rx_discard in config 380221167Sgnn * @VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT: Invalid option for pref_indiv_port 381221167Sgnn * in config 382221167Sgnn * @VXGE_HAL_BADCFG_LAG_HOT_STANDBY: Invalid option for hot_standby in config 383221167Sgnn * @VXGE_HAL_BADCFG_LAG_LACP_DECIDES: Invalid option for lacp_decides in config 384221167Sgnn * @VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT: Invalid option for pref_active_port 385221167Sgnn * in config 386221167Sgnn * @VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK: Invalid option for auto_failback 387221167Sgnn * in config 388221167Sgnn * @VXGE_HAL_BADCFG_LAG_FAILBACK_EN: Invalid option for failback_en in config 389221167Sgnn * @VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT: Invalid cold_failover_timeout 390221167Sgnn * in config 391221167Sgnn * @VXGE_HAL_BADCFG_LAG_LACP_EN: Invalid option for lacp_en in config 392221167Sgnn * @VXGE_HAL_BADCFG_LAG_LACP_BEGIN: Invalid option for lacp_begin in config 393221167Sgnn * @VXGE_HAL_BADCFG_LAG_DISCARD_LACP: Invalid option for discard_lacp in config 394221167Sgnn * @VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK: Invalid option for liberal_len_chk 395221167Sgnn * in config 396221167Sgnn * @VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN: Invalid option for 397221167Sgnn * marker_gen_recv_en in config 398221167Sgnn * @VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN: Invalid option for marker_resp_en 399221167Sgnn * in config 400221167Sgnn * @VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT: Invalid option for 401221167Sgnn * marker_resp_timeout in config 402221167Sgnn * @VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL: Invalid option for 403221167Sgnn * slow_proto_mrkr_min_interval in config 404221167Sgnn * @VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP: Invalid option for 405221167Sgnn * throttle_mrkr_resp in config 406221167Sgnn * @VXGE_HAL_BADCFG_LAG_SYS_PRI: Invalid system priority in config 407221167Sgnn * @VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR: Invalid option for 408221167Sgnn * use_port_mac_addr in config 409221167Sgnn * @VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL: Invalid option for mac_addr_sel in config 410221167Sgnn * @VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY: Invalid alterneate admin key in config 411221167Sgnn * @VXGE_HAL_BADCFG_LAG_ALT_AGGR: Invalid option for alt_aggr in config 412221167Sgnn * @VXGE_HAL_BADCFG_LAG_FAST_PER_TIME: Invalid fast periodic time in config 413221167Sgnn * @VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME: Invalid slow periodic time in config 414221167Sgnn * @VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT: Invalid short timeout in config 415221167Sgnn * @VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT: Invalid long timeout in config 416221167Sgnn * @VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME: Invalid churn detection time in config 417221167Sgnn * @VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME: Invalid Aggregator wait time in config 418221167Sgnn * @VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE: Invalid short timer scale in config 419221167Sgnn * @VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE: Invalid long timer scale in config 420221167Sgnn * @VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID: Invalid Aggregator Id in config 421221167Sgnn * @VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR: Invalid option for 422221167Sgnn * use_port_mac_addr in config 423221167Sgnn * @VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL: Invalid option for mac_addr_sel 424221167Sgnn * in config 425221167Sgnn * @VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY: Invalid admin key in config 426221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PORT_ID: Invalid port id in config 427221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_LAG_EN: Invalid option for lag_en in config 428221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO: Invalid option for 429221167Sgnn * discard_slow_proto in config 430221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR: Invalid option for 431221167Sgnn * host_chosen_aggr in config 432221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO: Invalid option 433221167Sgnn * for discard unknown slow proto in config 434221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM: Invalid Actor port number in config 435221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY: Invalid Actor port priority 436221167Sgnn * in config 437221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G: Invalid Actor 10G key in config 438221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G: Invalid Actor 1G key in config 439221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY: Invalid option for 440221167Sgnn * actor_lacp_activity in config 441221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT: Invalid option for 442221167Sgnn * actor_lacp_timeout in config 443221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION: Invalid option for 444221167Sgnn * actor_aggregation in config 445221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION: Invalid option 446221167Sgnn * for actor_synchronization in config 447221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING: Invalid option for 448221167Sgnn * actor_collecting in config 449221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING: Invalid option for 450221167Sgnn * actor_distributing in config 451221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED: Invalid option for 452221167Sgnn * actor_defaulted in config 453221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED: Invalid option for 454221167Sgnn * actor_expired in config 455221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI: Invalid option for 456221167Sgnn * partner_sys_pri in config 457221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY: Invalid option for 458221167Sgnn * partner_key in config 459221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM: Invalid option for 460221167Sgnn * partner_port_num in config 461221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY: Invalid option for 462221167Sgnn * partner_port_pri in config 463221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY: Invalid option for 464221167Sgnn * partner_lacp_activity in config 465221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT: Invalid option for 466221167Sgnn * partner_lacp_timeout in config 467221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION: Invalid option for 468221167Sgnn * partner_aggregation in config 469221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION: Invalid option for 470221167Sgnn * partner_synchronization in config 471221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING: Invalid option for 472221167Sgnn * partner_collecting in config 473221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING: Invalid option for 474221167Sgnn * partner_distributing in config 475221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED: Invalid option for 476221167Sgnn * partner_defaulted in config 477221167Sgnn * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED: Invalid option for 478221167Sgnn * partner_expired in config 479221167Sgnn * @VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY: Invalid vpath priority 480221167Sgnn * @VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH: Invalid minimum bandwidth 481221167Sgnn * @VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH: Invalid maximum bandwidth 482221167Sgnn * @VXGE_HAL_BADCFG_LOG_LEVEL: Invalid option for partner_mac_addr in config 483221167Sgnn * @VXGE_HAL_BADCFG_RING_ENABLE: Invalid option for ring enable in config 484221167Sgnn * @VXGE_HAL_BADCFG_RING_LENGTH: Invalid ring length in config in config 485221167Sgnn * @VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE: Invalid receive buffer mode in config 486221167Sgnn * @VXGE_HAL_BADCFG_RING_SCATTER_MODE: Invalid scatter mode setting in config 487221167Sgnn * @VXGE_HAL_BADCFG_RING_POST_MODE: Invalid post mode setting in config 488221167Sgnn * @VXGE_HAL_BADCFG_RING_MAX_FRM_LEN: Invalid max frame length setting in config 489221167Sgnn * @VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL: Invalid no snoop all setting in config 490221167Sgnn * @VXGE_HAL_BADCFG_RING_TIMER_VAL: Invalid timer value setting in config 491221167Sgnn * @VXGE_HAL_BADCFG_RING_GREEDY_RETURN: Invalid grredy return setting in config 492221167Sgnn * @VXGE_HAL_BADCFG_RING_TIMER_CI: Invalid timer ci setting in config 493221167Sgnn * @VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US: Invalid backoff interval 494221167Sgnn * in microseconds setting in config 495221167Sgnn * @VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid indicate maximum packets 496221167Sgnn * setting in config 497221167Sgnn * @VXGE_HAL_BADCFG_FIFO_ENABLE: Invalid option for FIFO enable in config 498221167Sgnn * @VXGE_HAL_BADCFG_FIFO_LENGTH: Invalid FIFO length in config 499221167Sgnn * @VXGE_HAL_BADCFG_FIFO_FRAGS: Invalid number of transmit frame fragments 500221167Sgnn * in config 501221167Sgnn * @VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE: Invalid alignment size in config 502221167Sgnn * @VXGE_HAL_BADCFG_FIFO_MAX_FRAGS: Invalid maximum number of transmit frame 503221167Sgnn * fragments in config 504221167Sgnn * @VXGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid FIFO queue interrupt setting 505221167Sgnn * in config 506221167Sgnn * @VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL: Invalid FIFO no snoop all setting 507221167Sgnn * in config 508221167Sgnn * @VXGE_HAL_BADCFG_DMQ_LENGTH: Invalid DMQ length setting in config 509221167Sgnn * @VXGE_HAL_BADCFG_DMQ_IMMED_EN: Invalid DMQ immediate enable setting in config 510221167Sgnn * @VXGE_HAL_BADCFG_DMQ_EVENT_EN: Invalid DMQ event enable setting in config 511221167Sgnn * @VXGE_HAL_BADCFG_DMQ_INTR_CTRL: Invalid DMQ interrupt control setting 512221167Sgnn * in config 513221167Sgnn * @VXGE_HAL_BADCFG_DMQ_GEN_COMPL: Invalid DMQ general completion setting 514221167Sgnn * in config 515221167Sgnn * @VXGE_HAL_BADCFG_UMQ_LENGTH: Invalid UMQ length setting in config 516221167Sgnn * @VXGE_HAL_BADCFG_UMQ_IMMED_EN: Invalid UMQ immediate enable setting in config 517221167Sgnn * @VXGE_HAL_BADCFG_UMQ_EVENT_EN: Invalid UMQ event enable setting in config 518221167Sgnn * @VXGE_HAL_BADCFG_UMQ_INTR_CTRL: Invalid UMQ interrupt control setting 519221167Sgnn * in config 520221167Sgnn * @VXGE_HAL_BADCFG_UMQ_GEN_COMPL: Invalid UMQ general completion setting 521221167Sgnn * in config 522221167Sgnn * @VXGE_HAL_BADCFG_SW_LRO_SESSIONS: Invalid number of SW LRO sessions 523221167Sgnn * setting in config 524221167Sgnn * @VXGE_HAL_BADCFG_SW_LRO_SG_SIZE: Invalid SW LRO Segment size 525221167Sgnn * @VXGE_HAL_BADCFG_SW_LRO_FRM_LEN: Invalid SW LRO Frame Length 526221167Sgnn * @VXGE_HAL_BADCFG_SW_LRO_MODE: Invalid SW LRO mode setting in config 527221167Sgnn * @VXGE_HAL_BADCFG_LRO_SESSIONS_MAX: Invalid maximum number of LRO sessions 528221167Sgnn * setting in config 529221167Sgnn * @VXGE_HAL_BADCFG_LRO_SESSIONS_THRESHOLD: Invalid sessions number threshold 530221167Sgnn * setting in config 531221167Sgnn * @VXGE_HAL_BADCFG_LRO_SESSIONS_TIMEOUT: Invalid sessions timeout setting 532221167Sgnn * in config 533221167Sgnn * @VXGE_HAL_BADCFG_LRO_NO_WQE_THRESHOLD: Invalid lower limit for number 534221167Sgnn * of WQEs in config 535221167Sgnn * @VXGE_HAL_BADCFG_LRO_DUPACK_DETECTION: Invalid option for 536221167Sgnn * dupack_detection_enabled in config 537221167Sgnn * @VXGE_HAL_BADCFG_LRO_DATA_MERGING: Invalid option for 538221167Sgnn * data_merging_enabled in config 539221167Sgnn * @VXGE_HAL_BADCFG_LRO_ACK_MERGING: Invalid option for 540221167Sgnn * ack_merging_enabled in config 541221167Sgnn * @VXGE_HAL_BADCFG_LRO_LLC_HDR_MODE: Invalid LLC Header Mode 542221167Sgnn * @VXGE_HAL_BADCFG_LRO_SNAP_HDR_MODE: Invalid SNAP Header Mode 543221167Sgnn * @VXGE_HAL_BADCFG_LRO_SESSION_ECN: Invalid option for session_ecn_enabled 544221167Sgnn * @VXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCE: Invalid option for 545221167Sgnn * session_ecn_enabled_nonce 546221167Sgnn * @VXGE_HAL_BADCFG_LRO_RXD_BUFFER_MODE: Invalid buffer mode 547221167Sgnn * @VXGE_HAL_BADCFG_LRO_SCATTER_MODE: Invalid scatter mode 548221167Sgnn * @VXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZE: Invalid IP Datagram size 549221167Sgnn * @VXGE_HAL_BADCFG_LRO_FRAME_THRESHOLD: Invalid Frame Threshold 550221167Sgnn * @VXGE_HAL_BADCFG_LRO_PSH_THRESHOLD: Invalid push Threshold 551221167Sgnn * @VXGE_HAL_BADCFG_LRO_MTU_THRESHOLD: Invalid MTU Threshold 552221167Sgnn * @VXGE_HAL_BADCFG_LRO_MSS_THRESHOLD: Invalid MSS Threshold 553221167Sgnn * @VXGE_HAL_BADCFG_LRO_TCP_TSVAL_DELTA: Invalid TXP TSVAL DELTA 554221167Sgnn * @VXGE_HAL_BADCFG_LRO_ACK_NBR_DELTA: Invalid Acknowledgement delta 555221167Sgnn * @VXGE_HAL_BADCFG_LRO_SPARE_WQE_CAPACITY: Invalid Spare WQE Capacity 556221167Sgnn * @VXGE_HAL_BADCFG_TIM_INTR_ENABLE: Invalid TIM interrupt enable setting 557221167Sgnn * in config 558221167Sgnn * @VXGE_HAL_BADCFG_TIM_BTIMER_VAL: Invalid TIM btimer value setting in config 559221167Sgnn * @VXGE_HAL_BADCFG_TIM_TIMER_AC_EN: Invalid TIM timer ac enable setting 560221167Sgnn * in config 561221167Sgnn * @VXGE_HAL_BADCFG_TIM_TIMER_CI_EN: Invalid Tx timer continuous interrupt 562221167Sgnn * enable. See the structure vxge_hal_tim_intr_config_t {} for valid values. 563221167Sgnn * @VXGE_HAL_BADCFG_TIM_TIMER_RI_EN: Invalid TIM timer ri enable setting 564221167Sgnn * in config 565221167Sgnn * @VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF: Invalid TIM btimer event sf seting 566221167Sgnn * in config 567221167Sgnn * @VXGE_HAL_BADCFG_TIM_RTIMER_VAL: Invalid TIM rtimer setting in config 568221167Sgnn * @VXGE_HAL_BADCFG_TIM_UTIL_SEL: Invalid TIM utilization setting in config 569221167Sgnn * @VXGE_HAL_BADCFG_TIM_LTIMER_VAL: Invalid TIM ltimer value setting in config 570221167Sgnn * @VXGE_HAL_BADCFG_TXFRM_CNT_EN: Invalid transmit frame count enable in config 571221167Sgnn * @VXGE_HAL_BADCFG_TXD_CNT_EN: Invalid transmit count enable in config 572221167Sgnn * @VXGE_HAL_BADCFG_TIM_URANGE_A: Invalid link utilization range A. See 573221167Sgnn * the structure vxge_hal_tim_intr_config_t {} for valid values. 574221167Sgnn * @VXGE_HAL_BADCFG_TIM_UEC_A: Invalid frame count for link utilization 575221167Sgnn * range A. See the structure vxge_hal_tim_intr_config_t {} for valid values. 576221167Sgnn * @VXGE_HAL_BADCFG_TIM_URANGE_B: Invalid link utilization range B. See 577221167Sgnn * the structure vxge_hal_tim_intr_config_t {} for valid values. 578221167Sgnn * @VXGE_HAL_BADCFG_TIM_UEC_B: Invalid frame count for link utilization 579221167Sgnn * range B. See the strucuture vxge_hal_tim_intr_config_t {} for valid values. 580221167Sgnn * @VXGE_HAL_BADCFG_TIM_URANGE_C: Invalid link utilization range C. See 581221167Sgnn * the structure vxge_hal_tim_intr_config_t {} for valid values. 582221167Sgnn * @VXGE_HAL_BADCFG_TIM_UEC_C: Invalid frame count for link utilization 583221167Sgnn * range C. See the structure vxge_hal_tim_intr_config_t {} for valid values. 584221167Sgnn * @VXGE_HAL_BADCFG_TIM_UEC_D: Invalid frame count for link utilization 585221167Sgnn * range D. See the structure vxge_hal_tim_intr_config_t {} for valid values. 586221167Sgnn * @VXGE_HAL_BADCFG_VPATH_ID: Invalid vpath id in config 587221167Sgnn * @VXGE_HAL_BADCFG_VPATH_WIRE_PORT: Invalid wire port to be used 588221167Sgnn * @VXGE_HAL_BADCFG_VPATH_NO_SNOOP: Invalid vpath no snoop setting in config 589221167Sgnn * @VXGE_HAL_BADCFG_VPATH_MTU: Invalid vpath mtu size setting in config 590221167Sgnn * @VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN: Invalid vpath transmit protocol assist 591221167Sgnn * lso v2 en setting in config 592221167Sgnn * @VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR: Invalid vpath transmit 593221167Sgnn * protocol assist ignore frame error setting in config 594221167Sgnn * @VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING: Invalid vpath transmit 595221167Sgnn * protocol assist ipv6 keep searching setting in config 596221167Sgnn * @VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT: Invalid vpath transmit protocol 597221167Sgnn * assist L4 pseudo header present setting in config 598221167Sgnn * @VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS: Invalid vpath transmit 599221167Sgnn * protocol assist support mobile ipv6 headers setting in config 600221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH: Invalid vpath receive protocol 601221167Sgnn * assist ipv4 tcp include pseudo header setting in config 602221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH: Invalid vpath receive protocol 603221167Sgnn * assist ipv6 tcp include pseudo header setting in config 604221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH: Invalid vpath receive protocol 605221167Sgnn * assist ipv4 udp include pseudo header setting in config 606221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_IPV6_UDP_INCL_PH: Invalid vpath receive protocol 607221167Sgnn * assist ipv6 udp include pseudo header setting in config 608221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF: Invalid vpath receive protocol assist 609221167Sgnn * layer 4 include cf setting in config 610221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG: Invalid vpath receive protocol 611221167Sgnn * assist strip vlan tag setting in config 612221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM: Invalid vpath receive protocol 613221167Sgnn * assist layer 4 compute check sum setting in config 614221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF: Invalid vpath receive protocol 615221167Sgnn * assist layer 3 include cf setting in config 616221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM: Invalid vpath receive protocol 617221167Sgnn * assist layer 3 compute check sum setting in config 618221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN: Invalid vpath receive protocol 619221167Sgnn * assist unicast all address enable setting in config 620221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN: Invalid vpath receive protocol 621221167Sgnn * assist multi-icast all address enable setting in config 622221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN: Invalid vpath receive protocol assist 623221167Sgnn * cast enable setting in config 624221167Sgnn * @VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN: Invalid vpath receive protocol 625221167Sgnn * assist all vlan ids enable setting in config 626221167Sgnn * @VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW: Invalid Q l2 flow setting in config 627221167Sgnn * @VXGE_HAL_BADCFG_VPATH_VP_STATS_READ_METHOD: Invalid Stats read method 628221167Sgnn * @VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT: Invalid bandwidth limit 629221167Sgnn * @VXGE_HAL_BADCFG_BLOCKPOOL_MIN: Invalid minimum number of block pool blocks 630221167Sgnn * setting in config 631221167Sgnn * @VXGE_HAL_BADCFG_BLOCKPOOL_INITIAL: Invalid initial number of block pool 632221167Sgnn * blocks setting in config 633221167Sgnn * @VXGE_HAL_BADCFG_BLOCKPOOL_INCR: Invalid number of block pool blocks 634221167Sgnn * increment setting in config 635221167Sgnn * @VXGE_HAL_BADCFG_BLOCKPOOL_MAX: Invalid maximum number of block pool 636221167Sgnn * blocks setting in config 637221167Sgnn * @VXGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count setting in config 638221167Sgnn * @VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE: Invalid maximum payload size setting 639221167Sgnn * in config 640221167Sgnn * @VXGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count setting in config 641221167Sgnn * @VXGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid stats refresh time setting 642221167Sgnn * in config 643221167Sgnn * @VXGE_HAL_BADCFG_DUMP_ON_SERR: Invalid dump on serr setting in config 644221167Sgnn * @VXGE_HAL_BADCFG_DUMP_ON_CRITICAL: Invalid dump on critical error setting 645221167Sgnn * config 646221167Sgnn * @VXGE_HAL_BADCFG_DUMP_ON_ECCERR: Invalid dump on ecc error setting config 647221167Sgnn * @VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN: Invalid dump on unknown alarm setting 648221167Sgnn * config 649221167Sgnn * @VXGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode setting in config 650221167Sgnn * @VXGE_HAL_BADCFG_RTH_EN: Invalid rth enable setting in config 651221167Sgnn * @VXGE_HAL_BADCFG_RTH_IT_TYPE: Invalid rth it type setting in config 652221167Sgnn * @VXGE_HAL_BADCFG_UFCA_INTR_THRES: Invalid rxufca interrupt threshold 653221167Sgnn * setting in config 654221167Sgnn * @VXGE_HAL_BADCFG_UFCA_LO_LIM: Invalid rxufca low limit setting in config 655221167Sgnn * @VXGE_HAL_BADCFG_UFCA_HI_LIM: Invalid rxufca high limit setting in config 656221167Sgnn * @VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD: Invalid rxufca lbolt period in config 657221167Sgnn * @VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll timeout 658221167Sgnn * in milliseconds setting in config 659221167Sgnn * @VXGE_HAL_BADCFG_RTS_MAC_EN: Invalid rts mac enable setting in config 660221167Sgnn * @VXGE_HAL_BADCFG_RTS_QOS_EN: Invalid rts qos enable setting in config 661221167Sgnn * @VXGE_HAL_BADCFG_RTS_PORT_EN: Invalid rts port enable setting in config 662221167Sgnn * @VXGE_HAL_BADCFG_MAX_CQE_GROUPS: Invalid maximum number of CQE groups 663221167Sgnn * in config 664221167Sgnn * @VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS: Invalid maximum number of OD groups 665221167Sgnn * in config 666221167Sgnn * @VXGE_HAL_BADCFG_NO_WQE_THRESHOLD: Invalid no wqe threshold setting 667221167Sgnn * in config 668221167Sgnn * @VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH: Invalid refill threshold setting 669221167Sgnn * in config 670221167Sgnn * @VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW: Invalid refill threshold setting 671221167Sgnn * in config 672221167Sgnn * @VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT: Invalid acknowledgement block setting 673221167Sgnn * in config 674221167Sgnn * @VXGE_HAL_BADCFG_STATS_READ_METHOD: Invalid stats read method 675221167Sgnn * @VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL: Invalid poll or doorbell setting 676221167Sgnn * in config 677221167Sgnn * @VXGE_HAL_BADCFG_MSIX_ID: Invalid MSIX Id 678221167Sgnn * @VXGE_HAL_EOF_TRACE_BUF: Invalid end of trace buffer setting in config 679221167Sgnn * 680221167Sgnn */ 681221167Sgnntypedef enum vxge_hal_status_e { 682221167Sgnn VXGE_HAL_OK = 0, 683221167Sgnn VXGE_HAL_FAIL = 1, 684221167Sgnn VXGE_HAL_PENDING = 2, 685221167Sgnn VXGE_HAL_CONTINUE = 3, 686221167Sgnn VXGE_HAL_RETURN = 4, 687221167Sgnn VXGE_HAL_COMPLETIONS_REMAIN = 5, 688221167Sgnn VXGE_HAL_TRAFFIC_INTERRUPT = 6, 689221167Sgnn 690221167Sgnn VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HAL_BASE_INF + 1, 691221167Sgnn VXGE_HAL_INF_OUT_OF_DESCRIPTORS = VXGE_HAL_BASE_INF + 2, 692221167Sgnn VXGE_HAL_INF_QUEUE_IS_NOT_READY = VXGE_HAL_BASE_INF + 4, 693221167Sgnn VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = VXGE_HAL_BASE_INF + 5, 694221167Sgnn VXGE_HAL_INF_STATS_IS_NOT_READY = VXGE_HAL_BASE_INF + 6, 695221167Sgnn VXGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = VXGE_HAL_BASE_INF + 7, 696221167Sgnn VXGE_HAL_INF_IRQ_POLLING_CONTINUE = VXGE_HAL_BASE_INF + 8, 697221167Sgnn VXGE_HAL_INF_SW_LRO_BEGIN = VXGE_HAL_BASE_INF + 9, 698221167Sgnn VXGE_HAL_INF_SW_LRO_CONT = VXGE_HAL_BASE_INF + 10, 699221167Sgnn VXGE_HAL_INF_SW_LRO_UNCAPABLE = VXGE_HAL_BASE_INF + 11, 700221167Sgnn VXGE_HAL_INF_SW_LRO_FLUSH_SESSION = VXGE_HAL_BASE_INF + 12, 701221167Sgnn VXGE_HAL_INF_SW_LRO_FLUSH_BOTH = VXGE_HAL_BASE_INF + 13, 702221167Sgnn VXGE_HAL_INF_SW_LRO_END_3 = VXGE_HAL_BASE_INF + 14, 703221167Sgnn VXGE_HAL_INF_SW_LRO_SESSIONS_XCDED = VXGE_HAL_BASE_INF + 15, 704221167Sgnn VXGE_HAL_INF_NOT_ENOUGH_HW_CQES = VXGE_HAL_BASE_INF + 16, 705221167Sgnn VXGE_HAL_INF_LINK_UP_DOWN = VXGE_HAL_BASE_INF + 17, 706221167Sgnn 707221167Sgnn VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED = VXGE_HAL_BASE_ERR + 1, 708221167Sgnn VXGE_HAL_ERR_INVALID_HANDLE = VXGE_HAL_BASE_ERR + 2, 709221167Sgnn VXGE_HAL_ERR_OUT_OF_MEMORY = VXGE_HAL_BASE_ERR + 3, 710221167Sgnn VXGE_HAL_ERR_VPATH_NOT_AVAILABLE = VXGE_HAL_BASE_ERR + 4, 711221167Sgnn VXGE_HAL_ERR_VPATH_NOT_OPEN = VXGE_HAL_BASE_ERR + 5, 712221167Sgnn VXGE_HAL_ERR_WRONG_IRQ = VXGE_HAL_BASE_ERR + 6, 713221167Sgnn VXGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = VXGE_HAL_BASE_ERR + 7, 714221167Sgnn VXGE_HAL_ERR_SWAPPER_CTRL = VXGE_HAL_BASE_ERR + 8, 715221167Sgnn VXGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = VXGE_HAL_BASE_ERR + 9, 716221167Sgnn VXGE_HAL_ERR_INVALID_MTU_SIZE = VXGE_HAL_BASE_ERR + 10, 717221167Sgnn VXGE_HAL_ERR_OUT_OF_MAPPING = VXGE_HAL_BASE_ERR + 11, 718221167Sgnn VXGE_HAL_ERR_BAD_SUBSYSTEM_ID = VXGE_HAL_BASE_ERR + 12, 719221167Sgnn VXGE_HAL_ERR_INVALID_BAR_ID = VXGE_HAL_BASE_ERR + 13, 720221167Sgnn VXGE_HAL_ERR_INVALID_INDEX = VXGE_HAL_BASE_ERR + 14, 721221167Sgnn VXGE_HAL_ERR_INVALID_TYPE = VXGE_HAL_BASE_ERR + 15, 722221167Sgnn VXGE_HAL_ERR_INVALID_OFFSET = VXGE_HAL_BASE_ERR + 16, 723221167Sgnn VXGE_HAL_ERR_INVALID_DEVICE = VXGE_HAL_BASE_ERR + 17, 724221167Sgnn VXGE_HAL_ERR_OUT_OF_SPACE = VXGE_HAL_BASE_ERR + 18, 725221167Sgnn VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = VXGE_HAL_BASE_ERR + 19, 726221167Sgnn VXGE_HAL_ERR_VERSION_CONFLICT = VXGE_HAL_BASE_ERR + 20, 727221167Sgnn VXGE_HAL_ERR_INVALID_MAC_ADDRESS = VXGE_HAL_BASE_ERR + 21, 728221167Sgnn VXGE_HAL_ERR_BAD_DEVICE_ID = VXGE_HAL_BASE_ERR + 22, 729221167Sgnn VXGE_HAL_ERR_OUT_ALIGNED_FRAGS = VXGE_HAL_BASE_ERR + 23, 730221167Sgnn VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED = VXGE_HAL_BASE_ERR + 24, 731221167Sgnn VXGE_HAL_ERR_SPDM_NOT_ENABLED = VXGE_HAL_BASE_ERR + 25, 732221167Sgnn VXGE_HAL_ERR_SPDM_TABLE_FULL = VXGE_HAL_BASE_ERR + 26, 733221167Sgnn VXGE_HAL_ERR_SPDM_INVALID_ENTRY = VXGE_HAL_BASE_ERR + 27, 734221167Sgnn VXGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = VXGE_HAL_BASE_ERR + 28, 735221167Sgnn VXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT = VXGE_HAL_BASE_ERR + 29, 736221167Sgnn VXGE_HAL_ERR_INVALID_PCI_INFO = VXGE_HAL_BASE_ERR + 30, 737221167Sgnn VXGE_HAL_ERR_CRITICAL = VXGE_HAL_BASE_ERR + 31, 738221167Sgnn VXGE_HAL_ERR_RESET_FAILED = VXGE_HAL_BASE_ERR + 32, 739221167Sgnn VXGE_HAL_ERR_TOO_MANY = VXGE_HAL_BASE_ERR + 33, 740221167Sgnn VXGE_HAL_ERR_PKT_DROP = VXGE_HAL_BASE_ERR + 34, 741221167Sgnn VXGE_HAL_ERR_INVALID_BLOCK_SIZE = VXGE_HAL_BASE_ERR + 35, 742221167Sgnn VXGE_HAL_ERR_INVALID_STATE = VXGE_HAL_BASE_ERR + 36, 743221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION = VXGE_HAL_BASE_ERR + 37, 744221167Sgnn VXGE_HAL_ERR_RESET_IN_PROGRESS = VXGE_HAL_BASE_ERR + 38, 745221167Sgnn VXGE_HAL_ERR_MAC_TABLE_FULL = VXGE_HAL_BASE_ERR + 39, 746221167Sgnn VXGE_HAL_ERR_MAC_TABLE_EMPTY = VXGE_HAL_BASE_ERR + 40, 747221167Sgnn VXGE_HAL_ERR_MAC_TABLE_NO_MORE_ENTRIES = VXGE_HAL_BASE_ERR + 41, 748221167Sgnn VXGE_HAL_ERR_RTDMA_RTDMA_READY = VXGE_HAL_BASE_ERR + 42, 749221167Sgnn VXGE_HAL_ERR_WRDMA_WRDMA_READY = VXGE_HAL_BASE_ERR + 43, 750221167Sgnn VXGE_HAL_ERR_KDFC_KDFC_READY = VXGE_HAL_BASE_ERR + 44, 751221167Sgnn VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY = VXGE_HAL_BASE_ERR + 45, 752221167Sgnn VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT = VXGE_HAL_BASE_ERR + 46, 753221167Sgnn VXGE_HAL_ERR_XGMAC_NETWORK_FAULT = VXGE_HAL_BASE_ERR + 47, 754221167Sgnn VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT = VXGE_HAL_BASE_ERR + 48, 755221167Sgnn VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY = VXGE_HAL_BASE_ERR + 49, 756221167Sgnn VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY = VXGE_HAL_BASE_ERR + 50, 757221167Sgnn VXGE_HAL_ERR_RIC_RIC_RUNNING = VXGE_HAL_BASE_ERR + 51, 758221167Sgnn VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK = VXGE_HAL_BASE_ERR + 52, 759221167Sgnn VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK = VXGE_HAL_BASE_ERR + 53, 760221167Sgnn VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK = VXGE_HAL_BASE_ERR + 54, 761221167Sgnn VXGE_HAL_ERR_PCC_PCC_IDLE = VXGE_HAL_BASE_ERR + 55, 762221167Sgnn VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT = VXGE_HAL_BASE_ERR + 56, 763221167Sgnn VXGE_HAL_ERR_SLOT_FREEZE = VXGE_HAL_BASE_ERR + 57, 764221167Sgnn VXGE_HAL_ERR_INVALID_TCODE = VXGE_HAL_BASE_ERR + 58, 765221167Sgnn VXGE_HAL_ERR_INVALID_PORT = VXGE_HAL_BASE_ERR + 59, 766221167Sgnn VXGE_HAL_ERR_INVALID_WIRE_PORT = VXGE_HAL_BASE_ERR + 60, 767221167Sgnn VXGE_HAL_ERR_INVALID_PRIORITY = VXGE_HAL_BASE_ERR + 61, 768221167Sgnn VXGE_HAL_ERR_INVALID_MIN_BANDWIDTH = VXGE_HAL_BASE_ERR + 62, 769221167Sgnn VXGE_HAL_ERR_INVALID_MAX_BANDWIDTH = VXGE_HAL_BASE_ERR + 63, 770221167Sgnn VXGE_HAL_ERR_INVALID_BANDWIDTH_LIMIT = VXGE_HAL_BASE_ERR + 64, 771221167Sgnn VXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTH = VXGE_HAL_BASE_ERR + 65, 772221167Sgnn VXGE_HAL_ERR_MANAGER_NOT_FOUND = VXGE_HAL_BASE_ERR + 66, 773221167Sgnn VXGE_HAL_ERR_TIME_OUT = VXGE_HAL_BASE_ERR + 67, 774221167Sgnn VXGE_HAL_ERR_EVENT_UNKNOWN = VXGE_HAL_BASE_ERR + 68, 775221167Sgnn VXGE_HAL_ERR_EVENT_SERR = VXGE_HAL_BASE_ERR + 69, 776221167Sgnn VXGE_HAL_ERR_EVENT_CRITICAL = VXGE_HAL_BASE_ERR + 70, 777221167Sgnn VXGE_HAL_ERR_EVENT_ECCERR = VXGE_HAL_BASE_ERR + 71, 778221167Sgnn VXGE_HAL_ERR_EVENT_KDFCCTL = VXGE_HAL_BASE_ERR + 72, 779221167Sgnn VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL = VXGE_HAL_BASE_ERR + 73, 780221167Sgnn VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL = VXGE_HAL_BASE_ERR + 74, 781221167Sgnn VXGE_HAL_ERR_EVENT_MRPCIM_ECCERR = VXGE_HAL_BASE_ERR + 75, 782221167Sgnn VXGE_HAL_ERR_EVENT_RESET_START = VXGE_HAL_BASE_ERR + 76, 783221167Sgnn VXGE_HAL_ERR_EVENT_RESET_COMPLETE = VXGE_HAL_BASE_ERR + 77, 784221167Sgnn VXGE_HAL_ERR_EVENT_SLOT_FREEZE = VXGE_HAL_BASE_ERR + 78, 785221167Sgnn VXGE_HAL_ERR_INVALID_DP_MODE = VXGE_HAL_BASE_ERR + 79, 786221167Sgnn VXGE_HAL_ERR_INVALID_L2_SWITCH_STATE = VXGE_HAL_BASE_ERR + 79, 787221167Sgnn 788221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID = VXGE_HAL_BASE_BADCFG + 1, 789221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA = VXGE_HAL_BASE_BADCFG + 2, 790221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU = VXGE_HAL_BASE_BADCFG + 3, 791221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE = VXGE_HAL_BASE_BADCFG + 4, 792221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE = VXGE_HAL_BASE_BADCFG + 5, 793221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM = VXGE_HAL_BASE_BADCFG + 6, 794221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM = VXGE_HAL_BASE_BADCFG + 7, 795221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM = VXGE_HAL_BASE_BADCFG + 8, 796221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD = 797221167Sgnn VXGE_HAL_BASE_BADCFG + 9, 798221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD = 799221167Sgnn VXGE_HAL_BASE_BADCFG + 10, 800221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN = VXGE_HAL_BASE_BADCFG + 11, 801221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN = VXGE_HAL_BASE_BADCFG + 12, 802221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD = VXGE_HAL_BASE_BADCFG + 13, 803221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE = VXGE_HAL_BASE_BADCFG + 14, 804221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD = VXGE_HAL_BASE_BADCFG + 15, 805221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS = VXGE_HAL_BASE_BADCFG + 16, 806221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN = VXGE_HAL_BASE_BADCFG + 18, 807221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM = VXGE_HAL_BASE_BADCFG + 19, 808221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD = VXGE_HAL_BASE_BADCFG + 20, 809221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN = VXGE_HAL_BASE_BADCFG + 21, 810221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN = VXGE_HAL_BASE_BADCFG + 22, 811221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME = VXGE_HAL_BASE_BADCFG + 23, 812221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN = 813221167Sgnn VXGE_HAL_BASE_BADCFG + 24, 814221167Sgnn VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT = VXGE_HAL_BASE_BADCFG + 25, 815221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU = VXGE_HAL_BASE_BADCFG + 26, 816221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN = VXGE_HAL_BASE_BADCFG + 27, 817221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN = VXGE_HAL_BASE_BADCFG + 28, 818221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD = VXGE_HAL_BASE_BADCFG + 29, 819221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE = VXGE_HAL_BASE_BADCFG + 30, 820221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD = 821221167Sgnn VXGE_HAL_BASE_BADCFG + 31, 822221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS = VXGE_HAL_BASE_BADCFG + 32, 823221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN = VXGE_HAL_BASE_BADCFG + 33, 824221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM = 825221167Sgnn VXGE_HAL_BASE_BADCFG + 34, 826221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD = 827221167Sgnn VXGE_HAL_BASE_BADCFG + 35, 828221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN = 829221167Sgnn VXGE_HAL_BASE_BADCFG + 36, 830221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN = 831221167Sgnn VXGE_HAL_BASE_BADCFG + 37, 832221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME = VXGE_HAL_BASE_BADCFG + 38, 833221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN = 834221167Sgnn VXGE_HAL_BASE_BADCFG + 39, 835221167Sgnn VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT = VXGE_HAL_BASE_BADCFG + 40, 836221167Sgnn VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD = 837221167Sgnn VXGE_HAL_BASE_BADCFG + 41, 838221167Sgnn VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD = VXGE_HAL_BASE_BADCFG + 42, 839221167Sgnn VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN = VXGE_HAL_BASE_BADCFG + 43, 840221167Sgnn VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS = VXGE_HAL_BASE_BADCFG + 44, 841221167Sgnn VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN = VXGE_HAL_BASE_BADCFG + 45, 842221167Sgnn VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN = VXGE_HAL_BASE_BADCFG + 46, 843221167Sgnn VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS = VXGE_HAL_BASE_BADCFG + 47, 844221167Sgnn VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS = 845221167Sgnn VXGE_HAL_BASE_BADCFG + 48, 846221167Sgnn VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN = VXGE_HAL_BASE_BADCFG + 49, 847221167Sgnn VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N = VXGE_HAL_BASE_BADCFG + 50, 848221167Sgnn VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N = VXGE_HAL_BASE_BADCFG + 51, 849221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR = VXGE_HAL_BASE_BADCFG + 52, 850221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N = VXGE_HAL_BASE_BADCFG + 53, 851221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO = VXGE_HAL_BASE_BADCFG + 54, 852221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS = 853221167Sgnn VXGE_HAL_BASE_BADCFG + 55, 854221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING = VXGE_HAL_BASE_BADCFG + 56, 855221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN = VXGE_HAL_BASE_BADCFG + 57, 856221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE = VXGE_HAL_BASE_BADCFG + 58, 857221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 59, 858221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF = VXGE_HAL_BASE_BADCFG + 60, 859221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 61, 860221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH = 861221167Sgnn VXGE_HAL_BASE_BADCFG + 62, 862221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH = 863221167Sgnn VXGE_HAL_BASE_BADCFG + 63, 864221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH = 865221167Sgnn VXGE_HAL_BASE_BADCFG + 64, 866221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH = 867221167Sgnn VXGE_HAL_BASE_BADCFG + 65, 868221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF = VXGE_HAL_BASE_BADCFG + 66, 869221167Sgnn VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG = VXGE_HAL_BASE_BADCFG + 67, 870221167Sgnn 871221167Sgnn VXGE_HAL_BADCFG_LAG_LAG_EN = VXGE_HAL_BASE_BADCFG + 101, 872221167Sgnn VXGE_HAL_BADCFG_LAG_LAG_MODE = VXGE_HAL_BASE_BADCFG + 102, 873221167Sgnn VXGE_HAL_BADCFG_LAG_TX_DISCARD = VXGE_HAL_BASE_BADCFG + 103, 874221167Sgnn VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS = VXGE_HAL_BASE_BADCFG + 104, 875221167Sgnn VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL = VXGE_HAL_BASE_BADCFG + 105, 876221167Sgnn VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL = VXGE_HAL_BASE_BADCFG + 106, 877221167Sgnn VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY = VXGE_HAL_BASE_BADCFG + 107, 878221167Sgnn VXGE_HAL_BADCFG_LAG_RX_DISCARD = VXGE_HAL_BASE_BADCFG + 108, 879221167Sgnn VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT = VXGE_HAL_BASE_BADCFG + 109, 880221167Sgnn VXGE_HAL_BADCFG_LAG_HOT_STANDBY = VXGE_HAL_BASE_BADCFG + 110, 881221167Sgnn VXGE_HAL_BADCFG_LAG_LACP_DECIDES = VXGE_HAL_BASE_BADCFG + 111, 882221167Sgnn VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT = VXGE_HAL_BASE_BADCFG + 112, 883221167Sgnn VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK = VXGE_HAL_BASE_BADCFG + 113, 884221167Sgnn VXGE_HAL_BADCFG_LAG_FAILBACK_EN = VXGE_HAL_BASE_BADCFG + 114, 885221167Sgnn VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT = VXGE_HAL_BASE_BADCFG + 115, 886221167Sgnn VXGE_HAL_BADCFG_LAG_LACP_EN = VXGE_HAL_BASE_BADCFG + 116, 887221167Sgnn VXGE_HAL_BADCFG_LAG_LACP_BEGIN = VXGE_HAL_BASE_BADCFG + 117, 888221167Sgnn VXGE_HAL_BADCFG_LAG_DISCARD_LACP = VXGE_HAL_BASE_BADCFG + 118, 889221167Sgnn VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK = VXGE_HAL_BASE_BADCFG + 119, 890221167Sgnn VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN = VXGE_HAL_BASE_BADCFG + 120, 891221167Sgnn VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN = VXGE_HAL_BASE_BADCFG + 121, 892221167Sgnn VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT = VXGE_HAL_BASE_BADCFG + 122, 893221167Sgnn VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL = 894221167Sgnn VXGE_HAL_BASE_BADCFG + 123, 895221167Sgnn VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP = VXGE_HAL_BASE_BADCFG + 124, 896221167Sgnn VXGE_HAL_BADCFG_LAG_SYS_PRI = VXGE_HAL_BASE_BADCFG + 125, 897221167Sgnn VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR = VXGE_HAL_BASE_BADCFG + 126, 898221167Sgnn VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL = VXGE_HAL_BASE_BADCFG + 127, 899221167Sgnn VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY = VXGE_HAL_BASE_BADCFG + 128, 900221167Sgnn VXGE_HAL_BADCFG_LAG_ALT_AGGR = VXGE_HAL_BASE_BADCFG + 129, 901221167Sgnn VXGE_HAL_BADCFG_LAG_FAST_PER_TIME = VXGE_HAL_BASE_BADCFG + 130, 902221167Sgnn VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME = VXGE_HAL_BASE_BADCFG + 131, 903221167Sgnn VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT = VXGE_HAL_BASE_BADCFG + 132, 904221167Sgnn VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT = VXGE_HAL_BASE_BADCFG + 133, 905221167Sgnn VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME = VXGE_HAL_BASE_BADCFG + 134, 906221167Sgnn VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME = VXGE_HAL_BASE_BADCFG + 135, 907221167Sgnn VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE = VXGE_HAL_BASE_BADCFG + 136, 908221167Sgnn VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE = VXGE_HAL_BASE_BADCFG + 137, 909221167Sgnn VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID = VXGE_HAL_BASE_BADCFG + 138, 910221167Sgnn VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR = VXGE_HAL_BASE_BADCFG + 139, 911221167Sgnn VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL = VXGE_HAL_BASE_BADCFG + 140, 912221167Sgnn VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY = VXGE_HAL_BASE_BADCFG + 141, 913221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PORT_ID = VXGE_HAL_BASE_BADCFG + 142, 914221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_LAG_EN = VXGE_HAL_BASE_BADCFG + 143, 915221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO = 916221167Sgnn VXGE_HAL_BASE_BADCFG + 144, 917221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR = VXGE_HAL_BASE_BADCFG + 145, 918221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO = 919221167Sgnn VXGE_HAL_BASE_BADCFG + 146, 920221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM = VXGE_HAL_BASE_BADCFG + 147, 921221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY = 922221167Sgnn VXGE_HAL_BASE_BADCFG + 148, 923221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G = VXGE_HAL_BASE_BADCFG + 149, 924221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G = VXGE_HAL_BASE_BADCFG + 150, 925221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY = 926221167Sgnn VXGE_HAL_BASE_BADCFG + 151, 927221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT = 928221167Sgnn VXGE_HAL_BASE_BADCFG + 152, 929221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION = VXGE_HAL_BASE_BADCFG + 153, 930221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION = 931221167Sgnn VXGE_HAL_BASE_BADCFG + 154, 932221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING = VXGE_HAL_BASE_BADCFG + 155, 933221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING = 934221167Sgnn VXGE_HAL_BASE_BADCFG + 156, 935221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED = VXGE_HAL_BASE_BADCFG + 157, 936221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED = VXGE_HAL_BASE_BADCFG + 158, 937221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI = VXGE_HAL_BASE_BADCFG + 159, 938221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY = VXGE_HAL_BASE_BADCFG + 160, 939221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM = VXGE_HAL_BASE_BADCFG + 161, 940221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY = 941221167Sgnn VXGE_HAL_BASE_BADCFG + 162, 942221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY = 943221167Sgnn VXGE_HAL_BASE_BADCFG + 163, 944221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT = 945221167Sgnn VXGE_HAL_BASE_BADCFG + 164, 946221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION = 947221167Sgnn VXGE_HAL_BASE_BADCFG + 165, 948221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION = 949221167Sgnn VXGE_HAL_BASE_BADCFG + 166, 950221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING = 951221167Sgnn VXGE_HAL_BASE_BADCFG + 167, 952221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING = 953221167Sgnn VXGE_HAL_BASE_BADCFG + 168, 954221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED = 955221167Sgnn VXGE_HAL_BASE_BADCFG + 169, 956221167Sgnn VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED = 957221167Sgnn VXGE_HAL_BASE_BADCFG + 170, 958221167Sgnn VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY = VXGE_HAL_BASE_BADCFG + 171, 959221167Sgnn VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH = VXGE_HAL_BASE_BADCFG + 172, 960221167Sgnn VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH = VXGE_HAL_BASE_BADCFG + 173, 961221167Sgnn 962221167Sgnn VXGE_HAL_BADCFG_LOG_LEVEL = VXGE_HAL_BASE_BADCFG + 202, 963221167Sgnn VXGE_HAL_BADCFG_RING_ENABLE = VXGE_HAL_BASE_BADCFG + 203, 964221167Sgnn VXGE_HAL_BADCFG_RING_LENGTH = VXGE_HAL_BASE_BADCFG + 204, 965221167Sgnn VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE = VXGE_HAL_BASE_BADCFG + 205, 966221167Sgnn VXGE_HAL_BADCFG_RING_SCATTER_MODE = VXGE_HAL_BASE_BADCFG + 206, 967221167Sgnn VXGE_HAL_BADCFG_RING_POST_MODE = VXGE_HAL_BASE_BADCFG + 207, 968221167Sgnn VXGE_HAL_BADCFG_RING_MAX_FRM_LEN = VXGE_HAL_BASE_BADCFG + 208, 969221167Sgnn VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL = VXGE_HAL_BASE_BADCFG + 209, 970221167Sgnn VXGE_HAL_BADCFG_RING_TIMER_VAL = VXGE_HAL_BASE_BADCFG + 210, 971221167Sgnn VXGE_HAL_BADCFG_RING_GREEDY_RETURN = VXGE_HAL_BASE_BADCFG + 211, 972221167Sgnn VXGE_HAL_BADCFG_RING_TIMER_CI = VXGE_HAL_BASE_BADCFG + 212, 973221167Sgnn VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US = VXGE_HAL_BASE_BADCFG + 213, 974221167Sgnn VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = VXGE_HAL_BASE_BADCFG + 214, 975221167Sgnn VXGE_HAL_BADCFG_FIFO_ENABLE = VXGE_HAL_BASE_BADCFG + 215, 976221167Sgnn VXGE_HAL_BADCFG_FIFO_LENGTH = VXGE_HAL_BASE_BADCFG + 216, 977221167Sgnn VXGE_HAL_BADCFG_FIFO_FRAGS = VXGE_HAL_BASE_BADCFG + 217, 978221167Sgnn VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE = VXGE_HAL_BASE_BADCFG + 218, 979221167Sgnn VXGE_HAL_BADCFG_FIFO_MAX_FRAGS = VXGE_HAL_BASE_BADCFG + 219, 980221167Sgnn VXGE_HAL_BADCFG_FIFO_QUEUE_INTR = VXGE_HAL_BASE_BADCFG + 220, 981221167Sgnn VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL = VXGE_HAL_BASE_BADCFG + 221, 982221167Sgnn VXGE_HAL_BADCFG_DMQ_LENGTH = VXGE_HAL_BASE_BADCFG + 222, 983221167Sgnn VXGE_HAL_BADCFG_DMQ_IMMED_EN = VXGE_HAL_BASE_BADCFG + 223, 984221167Sgnn VXGE_HAL_BADCFG_DMQ_EVENT_EN = VXGE_HAL_BASE_BADCFG + 224, 985221167Sgnn VXGE_HAL_BADCFG_DMQ_INTR_CTRL = VXGE_HAL_BASE_BADCFG + 225, 986221167Sgnn VXGE_HAL_BADCFG_DMQ_GEN_COMPL = VXGE_HAL_BASE_BADCFG + 226, 987221167Sgnn VXGE_HAL_BADCFG_UMQ_LENGTH = VXGE_HAL_BASE_BADCFG + 227, 988221167Sgnn VXGE_HAL_BADCFG_UMQ_IMMED_EN = VXGE_HAL_BASE_BADCFG + 228, 989221167Sgnn VXGE_HAL_BADCFG_UMQ_EVENT_EN = VXGE_HAL_BASE_BADCFG + 229, 990221167Sgnn VXGE_HAL_BADCFG_UMQ_INTR_CTRL = VXGE_HAL_BASE_BADCFG + 230, 991221167Sgnn VXGE_HAL_BADCFG_UMQ_GEN_COMPL = VXGE_HAL_BASE_BADCFG + 231, 992221167Sgnn VXGE_HAL_BADCFG_SW_LRO_SESSIONS = VXGE_HAL_BASE_BADCFG + 232, 993221167Sgnn VXGE_HAL_BADCFG_SW_LRO_SG_SIZE = VXGE_HAL_BASE_BADCFG + 333, 994221167Sgnn VXGE_HAL_BADCFG_SW_LRO_FRM_LEN = VXGE_HAL_BASE_BADCFG + 334, 995221167Sgnn VXGE_HAL_BADCFG_SW_LRO_MODE = VXGE_HAL_BASE_BADCFG + 235, 996221167Sgnn VXGE_HAL_BADCFG_LRO_SESSIONS_MAX = VXGE_HAL_BASE_BADCFG + 236, 997221167Sgnn VXGE_HAL_BADCFG_LRO_SESSIONS_THRESHOLD = VXGE_HAL_BASE_BADCFG + 237, 998221167Sgnn VXGE_HAL_BADCFG_LRO_SESSIONS_TIMEOUT = VXGE_HAL_BASE_BADCFG + 238, 999221167Sgnn VXGE_HAL_BADCFG_LRO_NO_WQE_THRESHOLD = VXGE_HAL_BASE_BADCFG + 239, 1000221167Sgnn VXGE_HAL_BADCFG_LRO_DUPACK_DETECTION = VXGE_HAL_BASE_BADCFG + 242, 1001221167Sgnn VXGE_HAL_BADCFG_LRO_DATA_MERGING = VXGE_HAL_BASE_BADCFG + 243, 1002221167Sgnn VXGE_HAL_BADCFG_LRO_ACK_MERGING = VXGE_HAL_BASE_BADCFG + 244, 1003221167Sgnn VXGE_HAL_BADCFG_LRO_LLC_HDR_MODE = VXGE_HAL_BASE_BADCFG + 245, 1004221167Sgnn VXGE_HAL_BADCFG_LRO_SNAP_HDR_MODE = VXGE_HAL_BASE_BADCFG + 246, 1005221167Sgnn VXGE_HAL_BADCFG_LRO_SESSION_ECN = VXGE_HAL_BASE_BADCFG + 247, 1006221167Sgnn VXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCE = VXGE_HAL_BASE_BADCFG + 248, 1007221167Sgnn VXGE_HAL_BADCFG_LRO_RXD_BUFFER_MODE = VXGE_HAL_BASE_BADCFG + 249, 1008221167Sgnn VXGE_HAL_BADCFG_LRO_SCATTER_MODE = VXGE_HAL_BASE_BADCFG + 250, 1009221167Sgnn VXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZE = VXGE_HAL_BASE_BADCFG + 251, 1010221167Sgnn VXGE_HAL_BADCFG_LRO_FRAME_THRESHOLD = VXGE_HAL_BASE_BADCFG + 252, 1011221167Sgnn VXGE_HAL_BADCFG_LRO_PSH_THRESHOLD = VXGE_HAL_BASE_BADCFG + 253, 1012221167Sgnn VXGE_HAL_BADCFG_LRO_MTU_THRESHOLD = VXGE_HAL_BASE_BADCFG + 254, 1013221167Sgnn VXGE_HAL_BADCFG_LRO_MSS_THRESHOLD = VXGE_HAL_BASE_BADCFG + 255, 1014221167Sgnn VXGE_HAL_BADCFG_LRO_TCP_TSVAL_DELTA = VXGE_HAL_BASE_BADCFG + 256, 1015221167Sgnn VXGE_HAL_BADCFG_LRO_ACK_NBR_DELTA = VXGE_HAL_BASE_BADCFG + 257, 1016221167Sgnn VXGE_HAL_BADCFG_LRO_SPARE_WQE_CAPACITY = VXGE_HAL_BASE_BADCFG + 258, 1017221167Sgnn VXGE_HAL_BADCFG_TIM_INTR_ENABLE = VXGE_HAL_BASE_BADCFG + 259, 1018221167Sgnn VXGE_HAL_BADCFG_TIM_BTIMER_VAL = VXGE_HAL_BASE_BADCFG + 261, 1019221167Sgnn VXGE_HAL_BADCFG_TIM_TIMER_AC_EN = VXGE_HAL_BASE_BADCFG + 262, 1020221167Sgnn VXGE_HAL_BADCFG_TIM_TIMER_CI_EN = VXGE_HAL_BASE_BADCFG + 263, 1021221167Sgnn VXGE_HAL_BADCFG_TIM_TIMER_RI_EN = VXGE_HAL_BASE_BADCFG + 264, 1022221167Sgnn VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF = VXGE_HAL_BASE_BADCFG + 265, 1023221167Sgnn VXGE_HAL_BADCFG_TIM_RTIMER_VAL = VXGE_HAL_BASE_BADCFG + 266, 1024221167Sgnn VXGE_HAL_BADCFG_TIM_UTIL_SEL = VXGE_HAL_BASE_BADCFG + 267, 1025221167Sgnn VXGE_HAL_BADCFG_TIM_LTIMER_VAL = VXGE_HAL_BASE_BADCFG + 268, 1026221167Sgnn VXGE_HAL_BADCFG_TXFRM_CNT_EN = VXGE_HAL_BASE_BADCFG + 269, 1027221167Sgnn VXGE_HAL_BADCFG_TXD_CNT_EN = VXGE_HAL_BASE_BADCFG + 270, 1028221167Sgnn VXGE_HAL_BADCFG_TIM_URANGE_A = VXGE_HAL_BASE_BADCFG + 271, 1029221167Sgnn VXGE_HAL_BADCFG_TIM_UEC_A = VXGE_HAL_BASE_BADCFG + 272, 1030221167Sgnn VXGE_HAL_BADCFG_TIM_URANGE_B = VXGE_HAL_BASE_BADCFG + 273, 1031221167Sgnn VXGE_HAL_BADCFG_TIM_UEC_B = VXGE_HAL_BASE_BADCFG + 274, 1032221167Sgnn VXGE_HAL_BADCFG_TIM_URANGE_C = VXGE_HAL_BASE_BADCFG + 275, 1033221167Sgnn VXGE_HAL_BADCFG_TIM_UEC_C = VXGE_HAL_BASE_BADCFG + 276, 1034221167Sgnn VXGE_HAL_BADCFG_TIM_UEC_D = VXGE_HAL_BASE_BADCFG + 277, 1035221167Sgnn VXGE_HAL_BADCFG_VPATH_ID = VXGE_HAL_BASE_BADCFG + 278, 1036221167Sgnn VXGE_HAL_BADCFG_VPATH_WIRE_PORT = VXGE_HAL_BASE_BADCFG + 279, 1037221167Sgnn VXGE_HAL_BADCFG_VPATH_NO_SNOOP = VXGE_HAL_BASE_BADCFG + 281, 1038221167Sgnn VXGE_HAL_BADCFG_VPATH_MTU = VXGE_HAL_BASE_BADCFG + 282, 1039221167Sgnn VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN = VXGE_HAL_BASE_BADCFG + 283, 1040221167Sgnn VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR = 1041221167Sgnn VXGE_HAL_BASE_BADCFG + 284, 1042221167Sgnn VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING = 1043221167Sgnn VXGE_HAL_BASE_BADCFG + 285, 1044221167Sgnn VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT = VXGE_HAL_BASE_BADCFG + 286, 1045221167Sgnn VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS = 1046221167Sgnn VXGE_HAL_BASE_BADCFG + 287, 1047221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH = VXGE_HAL_BASE_BADCFG + 288, 1048221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH = VXGE_HAL_BASE_BADCFG + 289, 1049221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH = VXGE_HAL_BASE_BADCFG + 290, 1050221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_IPV6_UDP_INCL_PH = VXGE_HAL_BASE_BADCFG + 291, 1051221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF = VXGE_HAL_BASE_BADCFG + 292, 1052221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG = VXGE_HAL_BASE_BADCFG + 293, 1053221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 294, 1054221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF = VXGE_HAL_BASE_BADCFG + 295, 1055221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM = VXGE_HAL_BASE_BADCFG + 296, 1056221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN = 1057221167Sgnn VXGE_HAL_BASE_BADCFG + 297, 1058221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN = 1059221167Sgnn VXGE_HAL_BASE_BADCFG + 298, 1060221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN = VXGE_HAL_BASE_BADCFG + 299, 1061221167Sgnn VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN = VXGE_HAL_BASE_BADCFG + 300, 1062221167Sgnn VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW = VXGE_HAL_BASE_BADCFG + 301, 1063221167Sgnn VXGE_HAL_BADCFG_VPATH_VP_STATS_READ_METHOD = VXGE_HAL_BASE_BADCFG + 302, 1064221167Sgnn VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT = VXGE_HAL_BASE_BADCFG + 305, 1065221167Sgnn VXGE_HAL_BADCFG_BLOCKPOOL_MIN = VXGE_HAL_BASE_BADCFG + 306, 1066221167Sgnn VXGE_HAL_BADCFG_BLOCKPOOL_INITIAL = VXGE_HAL_BASE_BADCFG + 307, 1067221167Sgnn VXGE_HAL_BADCFG_BLOCKPOOL_INCR = VXGE_HAL_BASE_BADCFG + 308, 1068221167Sgnn VXGE_HAL_BADCFG_BLOCKPOOL_MAX = VXGE_HAL_BASE_BADCFG + 309, 1069221167Sgnn VXGE_HAL_BADCFG_ISR_POLLING_CNT = VXGE_HAL_BASE_BADCFG + 310, 1070221167Sgnn VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE = VXGE_HAL_BASE_BADCFG + 312, 1071221167Sgnn VXGE_HAL_BADCFG_MMRB_COUNT = VXGE_HAL_BASE_BADCFG + 313, 1072221167Sgnn VXGE_HAL_BADCFG_STATS_REFRESH_TIME = VXGE_HAL_BASE_BADCFG + 314, 1073221167Sgnn VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN = VXGE_HAL_BASE_BADCFG + 315, 1074221167Sgnn VXGE_HAL_BADCFG_DUMP_ON_SERR = VXGE_HAL_BASE_BADCFG + 316, 1075221167Sgnn VXGE_HAL_BADCFG_DUMP_ON_CRITICAL = VXGE_HAL_BASE_BADCFG + 317, 1076221167Sgnn VXGE_HAL_BADCFG_DUMP_ON_ECCERR = VXGE_HAL_BASE_BADCFG + 318, 1077221167Sgnn VXGE_HAL_BADCFG_INTR_MODE = VXGE_HAL_BASE_BADCFG + 319, 1078221167Sgnn VXGE_HAL_BADCFG_RTH_EN = VXGE_HAL_BASE_BADCFG + 320, 1079221167Sgnn VXGE_HAL_BADCFG_RTH_IT_TYPE = VXGE_HAL_BASE_BADCFG + 321, 1080221167Sgnn VXGE_HAL_BADCFG_UFCA_INTR_THRES = VXGE_HAL_BASE_BADCFG + 323, 1081221167Sgnn VXGE_HAL_BADCFG_UFCA_LO_LIM = VXGE_HAL_BASE_BADCFG + 324, 1082221167Sgnn VXGE_HAL_BADCFG_UFCA_HI_LIM = VXGE_HAL_BASE_BADCFG + 325, 1083221167Sgnn VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD = VXGE_HAL_BASE_BADCFG + 326, 1084221167Sgnn VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS = VXGE_HAL_BASE_BADCFG + 327, 1085221167Sgnn VXGE_HAL_BADCFG_RTS_MAC_EN = VXGE_HAL_BASE_BADCFG + 330, 1086221167Sgnn VXGE_HAL_BADCFG_RTS_QOS_EN = VXGE_HAL_BASE_BADCFG + 331, 1087221167Sgnn VXGE_HAL_BADCFG_RTS_PORT_EN = VXGE_HAL_BASE_BADCFG + 332, 1088221167Sgnn VXGE_HAL_BADCFG_MAX_CQE_GROUPS = VXGE_HAL_BASE_BADCFG + 333, 1089221167Sgnn VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS = VXGE_HAL_BASE_BADCFG + 334, 1090221167Sgnn VXGE_HAL_BADCFG_NO_WQE_THRESHOLD = VXGE_HAL_BASE_BADCFG + 335, 1091221167Sgnn VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH = VXGE_HAL_BASE_BADCFG + 336, 1092221167Sgnn VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW = VXGE_HAL_BASE_BADCFG + 337, 1093221167Sgnn VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT = VXGE_HAL_BASE_BADCFG + 338, 1094221167Sgnn VXGE_HAL_BADCFG_STATS_READ_METHOD = VXGE_HAL_BASE_BADCFG + 339, 1095221167Sgnn VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL = VXGE_HAL_BASE_BADCFG + 340, 1096221167Sgnn VXGE_HAL_BADCFG_MSIX_ID = VXGE_HAL_BASE_BADCFG + 341, 1097221167Sgnn VXGE_HAL_BADCFG_VPATH_PRIORITY = VXGE_HAL_BASE_BADCFG + 342, 1098221167Sgnn VXGE_HAL_EOF_TRACE_BUF = -1 1099221167Sgnn 1100221167Sgnn} vxge_hal_status_e; 1101221167Sgnn 1102221167Sgnn/* 1103221167Sgnn * enum vxge_hal_result_e - HAL Up Message result codes. 1104221167Sgnn * @VXGE_HAL_RESULT_OK: Success 1105221167Sgnn */ 1106221167Sgnntypedef enum vxge_hal_result_e { 1107221167Sgnn VXGE_HAL_RESULT_OK = 0 1108221167Sgnn} vxge_hal_result_e; 1109221167Sgnn 1110221167Sgnn__EXTERN_END_DECLS 1111221167Sgnn 1112221167Sgnn#endif /* VXGE_HAL_STATUS_H */ 1113