1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD: releng/10.3/sys/dev/vxge/include/vxgehal-mgmt.h 221167 2011-04-28 14:33:15Z gnn $*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_MGMT_H 34221167Sgnn#define VXGE_HAL_MGMT_H 35221167Sgnn 36221167Sgnn__EXTERN_BEGIN_DECLS 37221167Sgnn 38221167Sgnn/* 39221167Sgnn * struct vxge_hal_mgmt_about_info_t - About info. 40221167Sgnn * @vendor: PCI Vendor ID. 41221167Sgnn * @device: PCI Device ID. 42221167Sgnn * @subsys_vendor: PCI Subsystem Vendor ID. 43221167Sgnn * @subsys_device: PCI Subsystem Device ID. 44221167Sgnn * @board_rev: PCI Board revision, e.g. 3 - for Xena 3. 45221167Sgnn * @vendor_name: Exar Corp. 46221167Sgnn * @chip_name: X3100. 47221167Sgnn * @media: Fiber, copper. 48221167Sgnn * @hal_major: HAL major version number. 49221167Sgnn * @hal_minor: HAL minor version number. 50221167Sgnn * @hal_fix: HAL fix number. 51221167Sgnn * @hal_build: HAL build number. 52221167Sgnn * @ll_major: Link-layer ULD major version number. 53221167Sgnn * @ll_minor: Link-layer ULD minor version number. 54221167Sgnn * @ll_fix: Link-layer ULD fix version number. 55221167Sgnn * @ll_build: Link-layer ULD build number. 56221167Sgnn */ 57221167Sgnntypedef struct vxge_hal_mgmt_about_info_t { 58221167Sgnn u16 vendor; 59221167Sgnn u16 device; 60221167Sgnn u16 subsys_vendor; 61221167Sgnn u16 subsys_device; 62221167Sgnn u8 board_rev; 63221167Sgnn char vendor_name[16]; 64221167Sgnn char chip_name[16]; 65221167Sgnn char media[16]; 66221167Sgnn char hal_major[4]; 67221167Sgnn char hal_minor[4]; 68221167Sgnn char hal_fix[4]; 69221167Sgnn char hal_build[16]; 70221167Sgnn char ll_major[4]; 71221167Sgnn char ll_minor[4]; 72221167Sgnn char ll_fix[4]; 73221167Sgnn char ll_build[16]; 74221167Sgnn} vxge_hal_mgmt_about_info_t; 75221167Sgnn 76221167Sgnn 77221167Sgnn/* 78221167Sgnn * vxge_hal_mgmt_about - Retrieve about info. 79221167Sgnn * @devh: HAL device handle. 80221167Sgnn * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}. 81221167Sgnn * @size: Pointer to buffer containing the Size of the @buffer_info. 82221167Sgnn * HAL will return an error if the size is smaller than 83221167Sgnn * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field 84221167Sgnn * 85221167Sgnn * Retrieve information such as PCI device and vendor IDs, board 86221167Sgnn * revision number, HAL version number, etc. 87221167Sgnn * 88221167Sgnn * Returns: VXGE_HAL_OK - success; 89221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 90221167Sgnn * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 91221167Sgnn * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 92221167Sgnn * VXGE_HAL_FAIL - Failed to retrieve the information. 93221167Sgnn * 94221167Sgnn * See also: vxge_hal_mgmt_about_info_t {}. 95221167Sgnn */ 96221167Sgnnvxge_hal_status_e 97221167Sgnnvxge_hal_mgmt_about(vxge_hal_device_h devh, 98221167Sgnn vxge_hal_mgmt_about_info_t *about_info, 99221167Sgnn u32 *size); 100221167Sgnn 101221167Sgnn/* 102221167Sgnn * vxge_hal_mgmt_pci_config - Retrieve PCI configuration. 103221167Sgnn * @devh: HAL device handle. 104221167Sgnn * @buffer: Buffer for PCI configuration space. 105221167Sgnn * @size: Pointer to buffer containing the Size of the @buffer. 106221167Sgnn * HAL will return an error if the size is smaller than 107221167Sgnn * sizeof(vxge_hal_pci_config_t) and returns required size in this field 108221167Sgnn * 109221167Sgnn * Get PCI configuration. Permits to retrieve at run-time configuration 110221167Sgnn * values that were used to configure the device at load-time. 111221167Sgnn * 112221167Sgnn * Returns: VXGE_HAL_OK - success. 113221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 114221167Sgnn * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 115221167Sgnn * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 116221167Sgnn * 117221167Sgnn */ 118221167Sgnnvxge_hal_status_e 119221167Sgnnvxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size); 120221167Sgnn 121221167Sgnn/* 122221167Sgnn * struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities 123221167Sgnn * @pm_cap_ver: Version 124221167Sgnn * @pm_cap_pme_clock: PME clock required 125221167Sgnn * @pm_cap_aux_power: Auxilliary power support 126221167Sgnn * @pm_cap_dsi: Device specific initialization 127221167Sgnn * @pm_cap_aux_current: auxiliary current requirements 128221167Sgnn * @pm_cap_cap_d0: D1 power state support 129221167Sgnn * @pm_cap_cap_d1: D2 power state support 130221167Sgnn * @pm_cap_pme_d0: PME# can be asserted from D3hot 131221167Sgnn * @pm_cap_pme_d1: PME# can be asserted from D3hot 132221167Sgnn * @pm_cap_pme_d2: PME# can be asserted from D3hot 133221167Sgnn * @pm_cap_pme_d3_hot: PME# can be asserted from D3hot 134221167Sgnn * @pm_cap_pme_d3_cold: PME# can be asserted from D3cold 135221167Sgnn * @pm_ctrl_state: Current power state (D0 to D3) 136221167Sgnn * @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0 137221167Sgnn * @pm_ctrl_pme_enable: PME pin enable 138221167Sgnn * @pm_ctrl_pme_data_sel: Data select 139221167Sgnn * @pm_ctrl_pme_data_scale: Data scale 140221167Sgnn * @pm_ctrl_pme_status: PME pin status 141221167Sgnn * @pm_ppb_ext_b2_b3: Stop clock when in D3hot 142221167Sgnn * @pm_ppb_ext_ecc_en: Bus power/clock control enable 143221167Sgnn * @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel 144221167Sgnn * 145221167Sgnn * Power Management Capabilities structure 146221167Sgnn */ 147221167Sgnntypedef struct vxge_hal_mgmt_pm_cap_t { 148221167Sgnn u32 pm_cap_ver; 149221167Sgnn u32 pm_cap_pme_clock; 150221167Sgnn u32 pm_cap_aux_power; 151221167Sgnn u32 pm_cap_dsi; 152221167Sgnn u32 pm_cap_aux_current; 153221167Sgnn u32 pm_cap_cap_d0; 154221167Sgnn u32 pm_cap_cap_d1; 155221167Sgnn u32 pm_cap_pme_d0; 156221167Sgnn u32 pm_cap_pme_d1; 157221167Sgnn u32 pm_cap_pme_d2; 158221167Sgnn u32 pm_cap_pme_d3_hot; 159221167Sgnn u32 pm_cap_pme_d3_cold; 160221167Sgnn u32 pm_ctrl_state; 161221167Sgnn u32 pm_ctrl_no_soft_reset; 162221167Sgnn u32 pm_ctrl_pme_enable; 163221167Sgnn u32 pm_ctrl_pme_data_sel; 164221167Sgnn u32 pm_ctrl_pme_data_scale; 165221167Sgnn u32 pm_ctrl_pme_status; 166221167Sgnn u32 pm_ppb_ext_b2_b3; 167221167Sgnn u32 pm_ppb_ext_ecc_en; 168221167Sgnn u32 pm_data_reg; 169221167Sgnn} vxge_hal_mgmt_pm_cap_t; 170221167Sgnn 171221167Sgnn/* 172221167Sgnn * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities 173221167Sgnn * @devh: HAL device handle. 174221167Sgnn * @pm_cap: Power Management Capabilities 175221167Sgnn * 176221167Sgnn * Return the pm capabilities 177221167Sgnn */ 178221167Sgnnvxge_hal_status_e 179221167Sgnnvxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh, 180221167Sgnn vxge_hal_mgmt_pm_cap_t *pm_cap); 181221167Sgnn 182221167Sgnn/* 183221167Sgnn * struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities 184221167Sgnn * @sid_number_of_slots: Number of solts 185221167Sgnn * @sid_first_in_chasis: First in chasis flag 186221167Sgnn * @sid_chasis_number: Chasis Number 187221167Sgnn * 188221167Sgnn * Slot ID Capabilities structure 189221167Sgnn */ 190221167Sgnntypedef struct vxge_hal_mgmt_sid_cap_t { 191221167Sgnn u32 sid_number_of_slots; 192221167Sgnn u32 sid_first_in_chasis; 193221167Sgnn u32 sid_chasis_number; 194221167Sgnn} vxge_hal_mgmt_sid_cap_t; 195221167Sgnn 196221167Sgnn/* 197221167Sgnn * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities 198221167Sgnn * @devh: HAL device handle. 199221167Sgnn * @sid_cap: Slot Id Capabilities 200221167Sgnn * 201221167Sgnn * Return the pm capabilities 202221167Sgnn */ 203221167Sgnnvxge_hal_status_e 204221167Sgnnvxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh, 205221167Sgnn vxge_hal_mgmt_sid_cap_t *sid_cap); 206221167Sgnn 207221167Sgnn/* 208221167Sgnn * struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities 209221167Sgnn * @enable: 1 - MSI enabled, 0 - MSI not enabled 210221167Sgnn * @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only) 211221167Sgnn * @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only 212221167Sgnn * (valid for get only) 213221167Sgnn * @vectors_allocated: Number of vectors allocated 214221167Sgnn * 000-1 vectors 215221167Sgnn * 001-2 vectors 216221167Sgnn * 010-4 vectors 217221167Sgnn * 011-8 vectors 218221167Sgnn * 100-16 vectors 219221167Sgnn * 101-32 vectors 220221167Sgnn * @max_vectors_capable: Maximum number of vectors that can be allocated 221221167Sgnn * (valid for get only) 222221167Sgnn * 000-1 vectors 223221167Sgnn * 001-2 vectors 224221167Sgnn * 010-4 vectors 225221167Sgnn * 011-8 vectors 226221167Sgnn * 100-16 vectors 227221167Sgnn * 101-32 vectors 228221167Sgnn * @address: MSI address 229221167Sgnn * @data: MSI Data 230221167Sgnn * @mask_bits: For each Mask bit that is set, the function is prohibited from 231221167Sgnn * sending the associated message 232221167Sgnn * @pending_bits: For each Pending bit that is set, the function has a 233221167Sgnn * pending associated message. 234221167Sgnn * 235221167Sgnn * MSI Capabilities structure 236221167Sgnn */ 237221167Sgnntypedef struct vxge_hal_mgmt_msi_cap_t { 238221167Sgnn u32 enable; 239221167Sgnn u32 is_pvm_capable; 240221167Sgnn u32 is_64bit_addr_capable; 241221167Sgnn u32 vectors_allocated; 242221167Sgnn u32 max_vectors_capable; 243221167Sgnn#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_1 0 244221167Sgnn#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_2 1 245221167Sgnn#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_4 2 246221167Sgnn#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_8 3 247221167Sgnn#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_16 4 248221167Sgnn#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_32 5 249221167Sgnn u64 address; 250221167Sgnn u16 data; 251221167Sgnn u32 mask_bits; 252221167Sgnn u32 pending_bits; 253221167Sgnn} vxge_hal_mgmt_msi_cap_t; 254221167Sgnn 255221167Sgnn/* 256221167Sgnn * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities 257221167Sgnn * @devh: HAL device handle. 258221167Sgnn * @msi_cap: MSI Capabilities 259221167Sgnn * 260221167Sgnn * Return the msi capabilities 261221167Sgnn */ 262221167Sgnnvxge_hal_status_e 263221167Sgnnvxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh, 264221167Sgnn vxge_hal_mgmt_msi_cap_t *msi_cap); 265221167Sgnn 266221167Sgnn/* 267221167Sgnn * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities 268221167Sgnn * @devh: HAL device handle. 269221167Sgnn * @msi_cap: MSI Capabilities 270221167Sgnn * 271221167Sgnn * Sets the msi capabilities 272221167Sgnn */ 273221167Sgnnvxge_hal_status_e 274221167Sgnnvxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh, 275221167Sgnn vxge_hal_mgmt_msi_cap_t *msi_cap); 276221167Sgnn 277221167Sgnn/* 278221167Sgnn * struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities 279221167Sgnn * @enable: 1 - MSIX enabled, 0 - MSIX not enabled 280221167Sgnn * @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors 281221167Sgnn * @table_size: MSIX Table Size-1 282221167Sgnn * @table_offset: Offset of the table from the table_bir 283221167Sgnn * @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2 284221167Sgnn * @pba_offset: Offset of the PBA from the pba_bir 285221167Sgnn * @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2 286221167Sgnn * 287221167Sgnn * MSIS Capabilities structure 288221167Sgnn */ 289221167Sgnntypedef struct vxge_hal_mgmt_msix_cap_t { 290221167Sgnn u32 enable; 291221167Sgnn u32 mask_all_vect; 292221167Sgnn u32 table_size; 293221167Sgnn u32 table_offset; 294221167Sgnn u32 table_bir; 295221167Sgnn#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0 0 296221167Sgnn#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1 2 297221167Sgnn#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2 4 298221167Sgnn u32 pba_offset; 299221167Sgnn u32 pba_bir; 300221167Sgnn#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0 0 301221167Sgnn#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1 2 302221167Sgnn#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2 4 303221167Sgnn} vxge_hal_mgmt_msix_cap_t; 304221167Sgnn 305221167Sgnn/* 306221167Sgnn * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities 307221167Sgnn * @devh: HAL device handle. 308221167Sgnn * @msix_cap: MSIX Capabilities 309221167Sgnn * 310221167Sgnn * Return the msix capabilities 311221167Sgnn */ 312221167Sgnnvxge_hal_status_e 313221167Sgnnvxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh, 314221167Sgnn vxge_hal_mgmt_msix_cap_t *msix_cap); 315221167Sgnn 316221167Sgnn/* 317221167Sgnn * struct vxge_hal_pci_err_cap_t - PCI Error Capabilities 318221167Sgnn * @pci_err_header: Error header 319221167Sgnn * @pci_err_uncor_status: Uncorrectable error status 320221167Sgnn * 0x00000001 - Training 321221167Sgnn * 0x00000010 - Data Link Protocol 322221167Sgnn * 0x00001000 - Poisoned TLP 323221167Sgnn * 0x00002000 - Flow Control Protocol 324221167Sgnn * 0x00004000 - Completion Timeout 325221167Sgnn * 0x00008000 - Completer Abort 326221167Sgnn * 0x00010000 - Unexpected Completion 327221167Sgnn * 0x00020000 - Receiver Overflow 328221167Sgnn * 0x00040000 - Malformed TLP 329221167Sgnn * 0x00080000 - ECRC Error Status 330221167Sgnn * 0x00100000 - Unsupported Request 331221167Sgnn * @pci_err_uncor_mask: Uncorrectable mask 332221167Sgnn * @pci_err_uncor_server: Uncorrectable server 333221167Sgnn * @pci_err_cor_status: Correctable status 334221167Sgnn * 0x00000001 - Receiver Error Status 335221167Sgnn * 0x00000040 - Bad TLP Status 336221167Sgnn * 0x00000080 - Bad DLLP Status 337221167Sgnn * 0x00000100 - REPLAY_NUM Rollover 338221167Sgnn * 0x00001000 - Replay Timer Timeout 339221167Sgnn * VXGE_HAL_PCI_ERR_COR_MASK 20 340221167Sgnn * @pci_err_cap: Error capability 341221167Sgnn * 0x00000020 - ECRC Generation Capable 342221167Sgnn * 0x00000040 - ECRC Generation Enable 343221167Sgnn * 0x00000080 - ECRC Check Capable 344221167Sgnn * 0x00000100 - ECRC Check Enable 345221167Sgnn * @err_header_log: Error header log 346221167Sgnn * @unused: Reserved 347221167Sgnn * @pci_err_root_command: Error root command 348221167Sgnn * @pci_err_root_status: Error root status 349221167Sgnn * @pci_err_root_cor_src: Error root correctible source 350221167Sgnn * @pci_err_root_src: Error root source 351221167Sgnn * 352221167Sgnn * MSIS Capabilities structure 353221167Sgnn */ 354221167Sgnntypedef struct vxge_hal_pci_err_cap_t { 355221167Sgnn u32 pci_err_header; 356221167Sgnn u32 pci_err_uncor_status; 357221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN 0x00000001 /* Training */ 358221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_DLP 0x00000010 /* Data Link Protocol */ 359221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 360221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_FCP 0x00002000 /* Flow Ctrl Protocol */ 361221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 362221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 363221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP 0x00010000 /* Unexpected Compl */ 364221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 365221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 366221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_ECRC 0x00080000 /* ECRC Error Status */ 367221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP 0x00100000 /* Unsupported Request */ 368221167Sgnn u32 pci_err_uncor_mask; 369221167Sgnn u32 pci_err_uncor_server; 370221167Sgnn u32 pci_err_cor_status; 371221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_COR_RCVR 0x00000001 /* Recv Err Status */ 372221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 373221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 374221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL 0x00000100 /* REPLAY Rollover */ 375221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER 0x00001000 /* Replay Timeout */ 376221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_COR_MASK 20 /* Corrble Err Mask */ 377221167Sgnn u32 pci_err_cap; 378221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */ 379221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC 0x00000020 /* ECRC Gen Capable */ 380221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE 0x00000040 /* ECRC Gen Enable */ 381221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC 0x00000080 /* ECRC Chk Capable */ 382221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE 0x00000100 /* ECRC Chk Enable */ 383221167Sgnn u32 err_header_log; 384221167Sgnn#define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */ 385221167Sgnn u32 unused[3]; 386221167Sgnn u32 pci_err_root_command; 387221167Sgnn u32 pci_err_root_status; 388221167Sgnn u32 pci_err_root_cor_src; 389221167Sgnn u32 pci_err_root_src; 390221167Sgnn} vxge_hal_pci_err_cap_t; 391221167Sgnn 392221167Sgnn/* 393221167Sgnn * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities 394221167Sgnn * @devh: HAL device handle. 395221167Sgnn * @err_cap: PCI-E Extended Error Capabilities 396221167Sgnn * 397221167Sgnn * Return the PCI-E Extended Error capabilities 398221167Sgnn */ 399221167Sgnnvxge_hal_status_e 400221167Sgnnvxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh, 401221167Sgnn vxge_hal_pci_err_cap_t *err_cap); 402221167Sgnn 403221167Sgnn/* 404221167Sgnn * vxge_hal_mgmt_driver_config - Retrieve driver configuration. 405221167Sgnn * @drv_config: Device configuration, see vxge_hal_driver_config_t {}. 406221167Sgnn * @size: Pointer to buffer containing the Size of the @drv_config. 407221167Sgnn * HAL will return an error if the size is smaller than 408221167Sgnn * sizeof(vxge_hal_driver_config_t) and returns required size in this field 409221167Sgnn * 410221167Sgnn * Get driver configuration. Permits to retrieve at run-time configuration 411221167Sgnn * values that were used to configure the device at load-time. 412221167Sgnn * 413221167Sgnn * Returns: VXGE_HAL_OK - success. 414221167Sgnn * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized. 415221167Sgnn * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching. 416221167Sgnn * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 417221167Sgnn * 418221167Sgnn * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config(). 419221167Sgnn */ 420221167Sgnnvxge_hal_status_e 421221167Sgnnvxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size); 422221167Sgnn 423221167Sgnn#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 424221167Sgnn 425221167Sgnn/* 426221167Sgnn * vxge_hal_mgmt_trace_read - Read trace buffer contents. 427221167Sgnn * @buffer: Buffer to store the trace buffer contents. 428221167Sgnn * @buf_size: Size of the buffer. 429221167Sgnn * @offset: Offset in the internal trace buffer to read data. 430221167Sgnn * @read_length: Size of the valid data in the buffer. 431221167Sgnn * 432221167Sgnn * Read HAL trace buffer contents starting from the offset 433221167Sgnn * upto the size of the buffer or till EOF is reached. 434221167Sgnn * 435221167Sgnn * Returns: VXGE_HAL_OK - success. 436221167Sgnn * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer. 437221167Sgnn * 438221167Sgnn */ 439221167Sgnnvxge_hal_status_e 440221167Sgnnvxge_hal_mgmt_trace_read(char *buffer, 441221167Sgnn unsigned buf_size, 442221167Sgnn unsigned *offset, 443221167Sgnn unsigned *read_length); 444221167Sgnn 445221167Sgnn#endif 446221167Sgnn 447221167Sgnn/* 448221167Sgnn * vxge_hal_mgmt_device_config - Retrieve device configuration. 449221167Sgnn * @devh: HAL device handle. 450221167Sgnn * @dev_config: Device configuration, see vxge_hal_device_config_t {}. 451221167Sgnn * @size: Pointer to buffer containing the Size of the @dev_config. 452221167Sgnn * HAL will return an error if the size is smaller than 453221167Sgnn * sizeof(vxge_hal_device_config_t) and returns required size in this field 454221167Sgnn * 455221167Sgnn * Get device configuration. Permits to retrieve at run-time configuration 456221167Sgnn * values that were used to initialize and configure the device. 457221167Sgnn * 458221167Sgnn * Returns: VXGE_HAL_OK - success. 459221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 460221167Sgnn * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 461221167Sgnn * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 462221167Sgnn * 463221167Sgnn * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config(). 464221167Sgnn */ 465221167Sgnnvxge_hal_status_e 466221167Sgnnvxge_hal_mgmt_device_config(vxge_hal_device_h devh, 467221167Sgnn vxge_hal_device_config_t *dev_config, u32 *size); 468221167Sgnn 469221167Sgnn 470221167Sgnn/* 471221167Sgnn * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified 472221167Sgnn * offset. 473221167Sgnn * @devh: HAL device handle. 474221167Sgnn * @offset: Offset in the 256 byte PCI configuration space. 475221167Sgnn * @value_bits: 8, 16, or 32 (bits) to read. 476221167Sgnn * @value: Value returned by HAL. 477221167Sgnn * 478221167Sgnn * Read PCI configuration, given device and offset in the PCI space. 479221167Sgnn * 480221167Sgnn * Returns: VXGE_HAL_OK - success. 481221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 482221167Sgnn * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not 483221167Sgnn * valid. 484221167Sgnn * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid 485221167Sgnn * values(8/16/32). 486221167Sgnn * 487221167Sgnn */ 488221167Sgnnvxge_hal_status_e 489221167Sgnnvxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset, 490221167Sgnn int value_bits, u32 *value); 491221167Sgnn 492221167Sgnn/* 493221167Sgnn * enum vxge_hal_mgmt_reg_type_e - Register types. 494221167Sgnn * 495221167Sgnn * @vxge_hal_mgmt_reg_type_legacy: Legacy registers 496221167Sgnn * @vxge_hal_mgmt_reg_type_toc: TOC Registers 497221167Sgnn * @vxge_hal_mgmt_reg_type_common: Common Registers 498221167Sgnn * @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers 499221167Sgnn * @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers 500221167Sgnn * @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers 501221167Sgnn * @vxge_hal_mgmt_reg_type_srpcim: srpcim registers 502221167Sgnn * @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers 503221167Sgnn * @vxge_hal_mgmt_reg_type_vpath: vpath registers 504221167Sgnn * 505221167Sgnn * Register type enumaration 506221167Sgnn */ 507221167Sgnntypedef enum vxge_hal_mgmt_reg_type_e { 508221167Sgnn vxge_hal_mgmt_reg_type_legacy = 0, 509221167Sgnn vxge_hal_mgmt_reg_type_toc = 1, 510221167Sgnn vxge_hal_mgmt_reg_type_common = 2, 511221167Sgnn vxge_hal_mgmt_reg_type_memrepair = 3, 512221167Sgnn vxge_hal_mgmt_reg_type_pcicfgmgmt = 4, 513221167Sgnn vxge_hal_mgmt_reg_type_mrpcim = 5, 514221167Sgnn vxge_hal_mgmt_reg_type_srpcim = 6, 515221167Sgnn vxge_hal_mgmt_reg_type_vpmgmt = 7, 516221167Sgnn vxge_hal_mgmt_reg_type_vpath = 8 517221167Sgnn} vxge_hal_mgmt_reg_type_e; 518221167Sgnn 519221167Sgnn/* 520221167Sgnn * vxge_hal_mgmt_reg_read - Read X3100 register. 521221167Sgnn * @devh: HAL device handle. 522221167Sgnn * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 523221167Sgnn * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 524221167Sgnn * ignored for others 525221167Sgnn * @offset: Register offset in the register space qualified by the type and 526221167Sgnn * index. 527221167Sgnn * @value: Register value. Returned by HAL. 528221167Sgnn * Read X3100 register. 529221167Sgnn * 530221167Sgnn * Returns: VXGE_HAL_OK - success. 531221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 532221167Sgnn * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 533221167Sgnn * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 534221167Sgnn * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 535221167Sgnn * 536221167Sgnn */ 537221167Sgnnvxge_hal_status_e 538221167Sgnnvxge_hal_mgmt_reg_read(vxge_hal_device_h devh, 539221167Sgnn vxge_hal_mgmt_reg_type_e type, 540221167Sgnn u32 index, 541221167Sgnn u32 offset, 542221167Sgnn u64 *value); 543221167Sgnn 544221167Sgnn/* 545221167Sgnn * vxge_hal_mgmt_reg_Write - Write X3100 register. 546221167Sgnn * @devh: HAL device handle. 547221167Sgnn * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 548221167Sgnn * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 549221167Sgnn * ignored for others 550221167Sgnn * @offset: Register offset in the register space qualified by the type and 551221167Sgnn * index. 552221167Sgnn * @value: Register value to be written. 553221167Sgnn * Write X3100 register. 554221167Sgnn * 555221167Sgnn * Returns: VXGE_HAL_OK - success. 556221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 557221167Sgnn * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 558221167Sgnn * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 559221167Sgnn * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 560221167Sgnn * 561221167Sgnn */ 562221167Sgnnvxge_hal_status_e 563221167Sgnnvxge_hal_mgmt_reg_write(vxge_hal_device_h devh, 564221167Sgnn vxge_hal_mgmt_reg_type_e type, 565221167Sgnn u32 index, 566221167Sgnn u32 offset, 567221167Sgnn u64 value); 568221167Sgnn 569221167Sgnn/* 570221167Sgnn * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset 571221167Sgnn * from bar0. 572221167Sgnn * @devh: HAL device handle. 573221167Sgnn * @offset: Register offset from bar0 574221167Sgnn * @value: Register value. Returned by HAL. 575221167Sgnn * Read X3100 register. 576221167Sgnn * 577221167Sgnn * Returns: VXGE_HAL_OK - success. 578221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 579221167Sgnn * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 580221167Sgnn * 581221167Sgnn */ 582221167Sgnnvxge_hal_status_e 583221167Sgnnvxge_hal_mgmt_bar0_read(vxge_hal_device_h devh, 584221167Sgnn u32 offset, 585221167Sgnn u64 *value); 586221167Sgnn 587221167Sgnn/* 588221167Sgnn * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset 589221167Sgnn * from bar1. 590221167Sgnn * @devh: HAL device handle. 591221167Sgnn * @offset: Register offset from bar1 592221167Sgnn * @value: Register value. Returned by HAL. 593221167Sgnn * Read X3100 register. 594221167Sgnn * 595221167Sgnn * Returns: VXGE_HAL_OK - success. 596221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 597221167Sgnn * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 598221167Sgnn * 599221167Sgnn */ 600221167Sgnnvxge_hal_status_e 601221167Sgnnvxge_hal_mgmt_bar1_read(vxge_hal_device_h devh, 602221167Sgnn u32 offset, 603221167Sgnn u64 *value); 604221167Sgnn 605221167Sgnn/* 606221167Sgnn * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset 607221167Sgnn * from bar0. 608221167Sgnn * @devh: HAL device handle. 609221167Sgnn * @offset: Register offset from bar0 610221167Sgnn * @value: Register value to be written. 611221167Sgnn * Write X3100 register. 612221167Sgnn * 613221167Sgnn * Returns: VXGE_HAL_OK - success. 614221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 615221167Sgnn * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 616221167Sgnn * 617221167Sgnn */ 618221167Sgnnvxge_hal_status_e 619221167Sgnnvxge_hal_mgmt_bar0_write(vxge_hal_device_h devh, 620221167Sgnn u32 offset, 621221167Sgnn u64 value); 622221167Sgnn 623221167Sgnn/* 624221167Sgnn * vxge_hal_mgmt_register_config - Retrieve register configuration. 625221167Sgnn * @devh: HAL device handle. 626221167Sgnn * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 627221167Sgnn * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 628221167Sgnn * ignored for others 629221167Sgnn * @config: Device configuration, see vxge_hal_device_config_t {}. 630221167Sgnn * @size: Pointer to buffer containing the Size of the @reg_config. 631221167Sgnn * HAL will return an error if the size is smaller than 632221167Sgnn * requested register space and returns required size in this field 633221167Sgnn * 634221167Sgnn * Get register configuration. Permits to retrieve register values. 635221167Sgnn * 636221167Sgnn * Returns: VXGE_HAL_OK - success. 637221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 638221167Sgnn * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 639221167Sgnn * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 640221167Sgnn * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 641221167Sgnn * 642221167Sgnn */ 643221167Sgnnvxge_hal_status_e 644221167Sgnnvxge_hal_mgmt_register_config(vxge_hal_device_h devh, 645221167Sgnn vxge_hal_mgmt_reg_type_e type, 646221167Sgnn u32 vp_id, 647221167Sgnn u8 *config, 648221167Sgnn u32 *size); 649221167Sgnn 650221167Sgnn/* 651221167Sgnn * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port 652221167Sgnn * @devh: HAL device handle. 653221167Sgnn * @port: Port number 654221167Sgnn * 655221167Sgnn * This routine only gets the temperature for XFP modules. Also, updating of the 656221167Sgnn * NVRAM can sometimes fail and so the reading we might get may not be uptodate. 657221167Sgnn */ 658221167Sgnnu32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port); 659221167Sgnn 660221167Sgnn/* 661221167Sgnn * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback 662221167Sgnn * @devh: HAL device handle. 663221167Sgnn * @port: Port number 664221167Sgnn * @enable:Boolean set to 1 to enable and 0 to disable. 665221167Sgnn * 666221167Sgnn * Enable or disable PMA loopback. 667221167Sgnn * Return value: 668221167Sgnn * 0 on success. 669221167Sgnn */ 670221167Sgnnvxge_hal_status_e 671221167Sgnnvxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable); 672221167Sgnn 673221167Sgnn/* 674221167Sgnn * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback 675221167Sgnn * @devh: HAL device handle. 676221167Sgnn * @port: Port number 677221167Sgnn * @enable:Boolean set to 1 to enable and 0 to disable. 678221167Sgnn * 679221167Sgnn * Enable or disable xgmii loopback. 680221167Sgnn * Return value: 681221167Sgnn * 0 on success. 682221167Sgnn */ 683221167Sgnnvxge_hal_status_e 684221167Sgnnvxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable); 685221167Sgnn 686221167Sgnn__EXTERN_END_DECLS 687221167Sgnn 688221167Sgnn#endif /* VXGE_HAL_MGMT_H */ 689