1216829Syongari/*- 2216829Syongari * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 3216829Syongari * All rights reserved. 4216829Syongari * 5216829Syongari * Redistribution and use in source and binary forms, with or without 6216829Syongari * modification, are permitted provided that the following conditions 7216829Syongari * are met: 8216829Syongari * 1. Redistributions of source code must retain the above copyright 9216829Syongari * notice unmodified, this list of conditions, and the following 10216829Syongari * disclaimer. 11216829Syongari * 2. Redistributions in binary form must reproduce the above copyright 12216829Syongari * notice, this list of conditions and the following disclaimer in the 13216829Syongari * documentation and/or other materials provided with the distribution. 14216829Syongari * 15216829Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16216829Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17216829Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18216829Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19216829Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20216829Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21216829Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22216829Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23216829Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24216829Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25216829Syongari * SUCH DAMAGE. 26216829Syongari * 27216829Syongari * $FreeBSD: releng/10.3/sys/dev/vte/if_vtereg.h 219787 2011-03-19 22:36:59Z yongari $ 28216829Syongari */ 29216829Syongari 30216829Syongari#ifndef _IF_VTEREG_H 31216829Syongari#define _IF_VTEREG_H 32216829Syongari 33216829Syongari/* 34216829Syongari * RDC Semiconductor PCI vendor ID 35216829Syongari */ 36216829Syongari#define VENDORID_RDC 0x17F3 37216829Syongari 38216829Syongari/* 39216829Syongari * Vortex86 RDC R6040 FastEthernet device ID 40216829Syongari */ 41216829Syongari#define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */ 42216829Syongari 43216829Syongari/* MAC control register 0 */ 44216829Syongari#define VTE_MCR0 0x00 45216829Syongari#define MCR0_ACCPT_ERR 0x0001 46216829Syongari#define MCR0_RX_ENB 0x0002 47216829Syongari#define MCR0_ACCPT_RUNT 0x0004 48216829Syongari#define MCR0_ACCPT_LONG_PKT 0x0008 49216829Syongari#define MCR0_ACCPT_DRIBBLE 0x0010 50216829Syongari#define MCR0_PROMISC 0x0020 51219787Syongari#define MCR0_BROADCAST_DIS 0x0040 52216829Syongari#define MCR0_RX_EARLY_INTR 0x0080 53216829Syongari#define MCR0_MULTICAST 0x0100 54216829Syongari#define MCR0_FC_ENB 0x0200 55216829Syongari#define MCR0_TX_ENB 0x1000 56216829Syongari#define MCR0_TX_EARLY_INTR 0x4000 57216829Syongari#define MCR0_FULL_DUPLEX 0x8000 58216829Syongari 59216829Syongari/* MAC control register 1 */ 60216829Syongari#define VTE_MCR1 0x04 61216829Syongari#define MCR1_MAC_RESET 0x0001 62216829Syongari#define MCR1_MAC_LOOPBACK 0x0002 63216829Syongari#define MCR1_EXCESS_COL_RETRANS_DIS 0x0004 64216829Syongari#define MCR1_AUTO_CHG_DUPLEX 0x0008 65216829Syongari#define MCR1_PKT_LENGTH_1518 0x0010 66216829Syongari#define MCR1_PKT_LENGTH_1522 0x0020 67216829Syongari#define MCR1_PKT_LENGTH_1534 0x0030 68216829Syongari#define MCR1_PKT_LENGTH_1537 0x0000 69216829Syongari#define MCR1_EARLY_INTR_THRESH_1129 0x0000 70216829Syongari#define MCR1_EARLY_INTR_THRESH_1257 0x0040 71216829Syongari#define MCR1_EARLY_INTR_THRESH_1385 0x0080 72216829Syongari#define MCR1_EARLY_INTR_THRESH_1513 0x00C0 73216829Syongari#define MCR1_EXCESS_COL_RETRY_16 0x0000 74216829Syongari#define MCR1_EXCESS_COL_RETRY_32 0x0100 75216829Syongari#define MCR1_FC_ACTIVE 0x0200 76216829Syongari#define MCR1_RX_DESC_HASH_IDX 0x4000 77216829Syongari#define MCR1_RX_UNICAST_HASH 0x8000 78216829Syongari 79216829Syongari#define MCR1_PKT_LENGTH_MASK 0x0030 80216829Syongari#define MCR1_EARLY_INTR_THRESH_MASK 0x00C0 81216829Syongari 82216829Syongari/* MAC bus control register */ 83216829Syongari#define VTE_MBCR 0x08 84216829Syongari#define MBCR_FIFO_XFER_LENGTH_4 0x0000 85216829Syongari#define MBCR_FIFO_XFER_LENGTH_8 0x0001 86216829Syongari#define MBCR_FIFO_XFER_LENGTH_16 0x0002 87216829Syongari#define MBCR_FIFO_XFER_LENGTH_32 0x0003 88216829Syongari#define MBCR_TX_FIFO_THRESH_16 0x0000 89216829Syongari#define MBCR_TX_FIFO_THRESH_32 0x0004 90216829Syongari#define MBCR_TX_FIFO_THRESH_64 0x0008 91216829Syongari#define MBCR_TX_FIFO_THRESH_96 0x000C 92216829Syongari#define MBCR_RX_FIFO_THRESH_8 0x0000 93216829Syongari#define MBCR_RX_FIFO_THRESH_16 0x0010 94216829Syongari#define MBCR_RX_FIFO_THRESH_32 0x0020 95216829Syongari#define MBCR_RX_FIFO_THRESH_64 0x0030 96216829Syongari#define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00 97216829Syongari#define MBCR_SDRAM_BUS_REQ_TIMER_SHIFT 8 98216829Syongari#define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00 99216829Syongari 100216829Syongari/* MAC TX interrupt control register */ 101216829Syongari#define VTE_MTICR 0x0C 102216829Syongari#define MTICR_TX_TIMER_MASK 0x001F 103216829Syongari#define MTICR_TX_BUNDLE_MASK 0x0F00 104216829Syongari#define VTE_IM_TX_TIMER_DEFAULT 0x7F 105216829Syongari#define VTE_IM_TX_BUNDLE_DEFAULT 15 106216829Syongari 107216829Syongari#define VTE_IM_TIMER_MIN 0 108216829Syongari#define VTE_IM_TIMER_MAX 82 109216829Syongari#define VTE_IM_TIMER_MASK 0x001F 110216829Syongari#define VTE_IM_TIMER_SHIFT 0 111216829Syongari#define VTE_IM_BUNDLE_MIN 1 112216829Syongari#define VTE_IM_BUNDLE_MAX 15 113216829Syongari#define VTE_IM_BUNDLE_SHIFT 8 114216829Syongari 115216829Syongari/* MAC RX interrupt control register */ 116216829Syongari#define VTE_MRICR 0x10 117216829Syongari#define MRICR_RX_TIMER_MASK 0x001F 118216829Syongari#define MRICR_RX_BUNDLE_MASK 0x0F00 119216829Syongari#define VTE_IM_RX_TIMER_DEFAULT 0x7F 120216829Syongari#define VTE_IM_RX_BUNDLE_DEFAULT 15 121216829Syongari 122216829Syongari/* MAC TX poll command register */ 123216829Syongari#define VTE_TX_POLL 0x14 124216829Syongari#define TX_POLL_START 0x0001 125216829Syongari 126216829Syongari/* MAC RX buffer size register */ 127216829Syongari#define VTE_MRBSR 0x18 128216829Syongari#define VTE_MRBSR_SIZE_MASK 0x03FF 129216829Syongari 130216829Syongari/* MAC RX descriptor control register */ 131216829Syongari#define VTE_MRDCR 0x1A 132216829Syongari#define VTE_MRDCR_RESIDUE_MASK 0x00FF 133216829Syongari#define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00 134216829Syongari#define VTE_MRDCR_RX_PAUSE_THRESH_SHIFT 8 135216829Syongari 136216829Syongari/* MAC Last status register */ 137216829Syongari#define VTE_MLSR 0x1C 138216829Syongari#define MLSR_MULTICAST 0x0001 139216829Syongari#define MLSR_BROADCAST 0x0002 140216829Syongari#define MLSR_CRC_ERR 0x0004 141216829Syongari#define MLSR_RUNT 0x0008 142216829Syongari#define MLSR_LONG_PKT 0x0010 143216829Syongari#define MLSR_TRUNC 0x0020 144216829Syongari#define MLSR_DRIBBLE 0x0040 145216829Syongari#define MLSR_PHY_ERR 0x0080 146216829Syongari#define MLSR_TX_FIFO_UNDERRUN 0x0200 147216829Syongari#define MLSR_RX_DESC_UNAVAIL 0x0400 148216829Syongari#define MLSR_TX_EXCESS_COL 0x2000 149216829Syongari#define MLSR_TX_LATE_COL 0x4000 150216829Syongari#define MLSR_RX_FIFO_OVERRUN 0x8000 151216829Syongari 152216829Syongari/* MAC MDIO control register */ 153216829Syongari#define VTE_MMDIO 0x20 154216829Syongari#define MMDIO_REG_ADDR_MASK 0x001F 155216829Syongari#define MMDIO_PHY_ADDR_MASK 0x1F00 156216829Syongari#define MMDIO_READ 0x2000 157216829Syongari#define MMDIO_WRITE 0x4000 158216829Syongari#define MMDIO_REG_ADDR_SHIFT 0 159216829Syongari#define MMDIO_PHY_ADDR_SHIFT 8 160216829Syongari 161216829Syongari/* MAC MDIO read data register */ 162216829Syongari#define VTE_MMRD 0x24 163216829Syongari#define MMRD_DATA_MASK 0xFFFF 164216829Syongari 165216829Syongari/* MAC MDIO write data register */ 166216829Syongari#define VTE_MMWD 0x28 167216829Syongari#define MMWD_DATA_MASK 0xFFFF 168216829Syongari 169216829Syongari/* MAC TX descriptor start address 0 */ 170216829Syongari#define VTE_MTDSA0 0x2C 171216829Syongari 172216829Syongari/* MAC TX descriptor start address 1 */ 173216829Syongari#define VTE_MTDSA1 0x30 174216829Syongari 175216829Syongari/* MAC RX descriptor start address 0 */ 176216829Syongari#define VTE_MRDSA0 0x34 177216829Syongari 178216829Syongari/* MAC RX descriptor start address 1 */ 179216829Syongari#define VTE_MRDSA1 0x38 180216829Syongari 181216829Syongari/* MAC Interrupt status register */ 182216829Syongari#define VTE_MISR 0x3C 183216829Syongari#define MISR_RX_DONE 0x0001 184216829Syongari#define MISR_RX_DESC_UNAVAIL 0x0002 185216829Syongari#define MISR_RX_FIFO_FULL 0x0004 186216829Syongari#define MISR_RX_EARLY_INTR 0x0008 187216829Syongari#define MISR_TX_DONE 0x0010 188216829Syongari#define MISR_TX_EARLY_INTR 0x0080 189216829Syongari#define MISR_EVENT_CNT_OFLOW 0x0100 190216829Syongari#define MISR_PHY_MEDIA_CHG 0x0200 191216829Syongari 192216829Syongari/* MAC Interrupt enable register */ 193216829Syongari#define VTE_MIER 0x40 194216829Syongari 195216829Syongari#define VTE_INTRS \ 196216829Syongari (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | MISR_RX_FIFO_FULL | \ 197216829Syongari MISR_TX_DONE | MISR_EVENT_CNT_OFLOW) 198216829Syongari 199216829Syongari/* MAC Event counter interrupt status register */ 200216829Syongari#define VTE_MECISR 0x44 201216829Syongari#define MECISR_EC_RX_DONE 0x0001 202216829Syongari#define MECISR_EC_MULTICAST 0x0002 203216829Syongari#define MECISR_EC_BROADCAST 0x0004 204216829Syongari#define MECISR_EC_CRC_ERR 0x0008 205216829Syongari#define MECISR_EC_RUNT 0x0010 206216829Syongari#define MESCIR_EC_LONG_PKT 0x0020 207216829Syongari#define MESCIR_EC_RX_DESC_UNAVAIL 0x0080 208216829Syongari#define MESCIR_EC_RX_FIFO_FULL 0x0100 209216829Syongari#define MESCIR_EC_TX_DONE 0x0200 210216829Syongari#define MESCIR_EC_LATE_COL 0x0400 211216829Syongari#define MESCIR_EC_TX_UNDERRUN 0x0800 212216829Syongari 213216829Syongari/* MAC Event counter interrupt enable register */ 214216829Syongari#define VTE_MECIER 0x48 215216829Syongari#define VTE_MECIER_INTRS \ 216216829Syongari (MECISR_EC_RX_DONE | MECISR_EC_MULTICAST | MECISR_EC_BROADCAST | \ 217216829Syongari MECISR_EC_CRC_ERR | MECISR_EC_RUNT | MESCIR_EC_LONG_PKT | \ 218216829Syongari MESCIR_EC_RX_DESC_UNAVAIL | MESCIR_EC_RX_FIFO_FULL | \ 219216829Syongari MESCIR_EC_TX_DONE | MESCIR_EC_LATE_COL | MESCIR_EC_TX_UNDERRUN) 220216829Syongari 221216829Syongari#define VTE_CNT_RX_DONE 0x50 222216829Syongari 223216829Syongari#define VTE_CNT_MECNT0 0x52 224216829Syongari 225216829Syongari#define VTE_CNT_MECNT1 0x54 226216829Syongari 227216829Syongari#define VTE_CNT_MECNT2 0x56 228216829Syongari 229216829Syongari#define VTE_CNT_MECNT3 0x58 230216829Syongari 231216829Syongari#define VTE_CNT_TX_DONE 0x5A 232216829Syongari 233216829Syongari#define VTE_CNT_MECNT4 0x5C 234216829Syongari 235216829Syongari#define VTE_CNT_PAUSE 0x5E 236216829Syongari 237216829Syongari/* MAC Hash table register */ 238216829Syongari#define VTE_MAR0 0x60 239216829Syongari#define VTE_MAR1 0x62 240216829Syongari#define VTE_MAR2 0x64 241216829Syongari#define VTE_MAR3 0x66 242216829Syongari 243216829Syongari/* MAC station address and multicast address register */ 244216829Syongari#define VTE_MID0L 0x68 245216829Syongari#define VTE_MID0M 0x6A 246216829Syongari#define VTE_MID0H 0x6C 247216829Syongari#define VTE_MID1L 0x70 248216829Syongari#define VTE_MID1M 0x72 249216829Syongari#define VTE_MID1H 0x74 250216829Syongari#define VTE_MID2L 0x78 251216829Syongari#define VTE_MID2M 0x7A 252216829Syongari#define VTE_MID2H 0x7C 253216829Syongari#define VTE_MID3L 0x80 254216829Syongari#define VTE_MID3M 0x82 255216829Syongari#define VTE_MID3H 0x84 256216829Syongari 257216829Syongari#define VTE_RXFILTER_PEEFECT_BASE VTE_MID1L 258216829Syongari#define VTE_RXFILT_PERFECT_CNT 3 259216829Syongari 260216829Syongari/* MAC PHY status change configuration register */ 261216829Syongari#define VTE_MPSCCR 0x88 262216829Syongari#define MPSCCR_TIMER_DIVIDER_MASK 0x0007 263216829Syongari#define MPSCCR_PHY_ADDR_MASK 0x1F00 264216829Syongari#define MPSCCR_PHY_STS_CHG_ENB 0x8000 265216829Syongari#define MPSCCR_PHY_ADDR_SHIFT 8 266216829Syongari 267216829Syongari/* MAC PHY status register2 */ 268216829Syongari#define VTE_MPSR 0x8A 269216829Syongari#define MPSR_LINK_UP 0x0001 270216829Syongari#define MPSR_SPEED_100 0x0002 271216829Syongari#define MPSR_FULL_DUPLEX 0x0004 272216829Syongari 273216829Syongari/* MAC Status machine(undocumented). */ 274216829Syongari#define VTE_MACSM 0xAC 275216829Syongari 276216829Syongari/* MDC Speed control register */ 277216829Syongari#define VTE_MDCSC 0xB6 278216829Syongari#define MDCSC_DEFAULT 0x0030 279216829Syongari 280216829Syongari/* MAC Identifier and revision register */ 281216829Syongari#define VTE_MACID_REV 0xBC 282216829Syongari#define VTE_MACID_REV_MASK 0x00FF 283216829Syongari#define VTE_MACID_MASK 0xFF00 284216829Syongari#define VTE_MACID_REV_SHIFT 0 285216829Syongari#define VTE_MACID_SHIFT 8 286216829Syongari 287216829Syongari/* MAC Identifier register */ 288216829Syongari#define VTE_MACID 0xBE 289216829Syongari 290216829Syongari/* 291216829Syongari * RX descriptor 292216829Syongari * - Added one more uint16_t member to align it 4 on bytes boundary. 293216829Syongari * This does not affect operation of controller since it includes 294216829Syongari * next pointer address. 295216829Syongari */ 296216829Syongaristruct vte_rx_desc { 297216829Syongari uint16_t drst; 298216829Syongari uint16_t drlen; 299216829Syongari uint32_t drbp; 300216829Syongari uint32_t drnp; 301216829Syongari uint16_t hidx; 302216829Syongari uint16_t rsvd2; 303216829Syongari uint16_t rsvd3; 304216829Syongari uint16_t __pad; /* Not actual descriptor member. */ 305216829Syongari}; 306216829Syongari 307216829Syongari#define VTE_DRST_MID_MASK 0x0003 308216829Syongari#define VTE_DRST_MID_HIT 0x0004 309216829Syongari#define VTE_DRST_MULTICAST_HIT 0x0008 310216829Syongari#define VTE_DRST_MULTICAST 0x0010 311216829Syongari#define VTE_DRST_BROADCAST 0x0020 312216829Syongari#define VTE_DRST_CRC_ERR 0x0040 313216829Syongari#define VTE_DRST_RUNT 0x0080 314216829Syongari#define VTE_DRST_LONG 0x0100 315216829Syongari#define VTE_DRST_TRUNC 0x0200 316216829Syongari#define VTE_DRST_DRIBBLE 0x0400 317216829Syongari#define VTE_DRST_PHY_ERR 0x0800 318216829Syongari#define VTE_DRST_RX_OK 0x4000 319216829Syongari#define VTE_DRST_RX_OWN 0x8000 320216829Syongari 321216829Syongari#define VTE_RX_LEN(x) ((x) & 0x7FF) 322216829Syongari 323216829Syongari#define VTE_RX_HIDX(x) ((x) & 0x3F) 324216829Syongari 325216829Syongari/* 326216829Syongari * TX descriptor 327216829Syongari * - Added one more uint32_t member to align it on 16 bytes boundary. 328216829Syongari */ 329216829Syongaristruct vte_tx_desc { 330216829Syongari uint16_t dtst; 331216829Syongari uint16_t dtlen; 332216829Syongari uint32_t dtbp; 333216829Syongari uint32_t dtnp; 334216829Syongari uint32_t __pad; /* Not actual descriptor member. */ 335216829Syongari}; 336216829Syongari 337216829Syongari#define VTE_DTST_EXCESS_COL 0x0010 338216829Syongari#define VTE_DTST_LATE_COL 0x0020 339216829Syongari#define VTE_DTST_UNDERRUN 0x0040 340216829Syongari#define VTE_DTST_NO_CRC 0x2000 341216829Syongari#define VTE_DTST_TX_OK 0x4000 342216829Syongari#define VTE_DTST_TX_OWN 0x8000 343216829Syongari 344216829Syongari#define VTE_TX_LEN(x) ((x) & 0x7FF) 345216829Syongari 346216829Syongari#endif /* _IF_VTEREG_H */ 347