if_vgereg.h revision 225440
197403Sobrien/*- 297403Sobrien * Copyright (c) 2004 3169691Skan * Bill Paul <wpaul@windriver.com>. All rights reserved. 4169691Skan * 597403Sobrien * Redistribution and use in source and binary forms, with or without 697403Sobrien * modification, are permitted provided that the following conditions 797403Sobrien * are met: 897403Sobrien * 1. Redistributions of source code must retain the above copyright 997403Sobrien * notice, this list of conditions and the following disclaimer. 1097403Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1197403Sobrien * notice, this list of conditions and the following disclaimer in the 1297403Sobrien * documentation and/or other materials provided with the distribution. 1397403Sobrien * 3. All advertising materials mentioning features or use of this software 1497403Sobrien * must display the following acknowledgement: 1597403Sobrien * This product includes software developed by Bill Paul. 1697403Sobrien * 4. Neither the name of the author nor the names of any co-contributors 1797403Sobrien * may be used to endorse or promote products derived from this software 1897403Sobrien * without specific prior written permission. 19169691Skan * 2097403Sobrien * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2197403Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2297403Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2397403Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2497403Sobrien * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2597403Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2697403Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2797403Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2897403Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2997403Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3097403Sobrien * THE POSSIBILITY OF SUCH DAMAGE. 3197403Sobrien * 3297403Sobrien * $FreeBSD: head/sys/dev/vge/if_vgereg.h 225440 2011-09-07 16:57:43Z yongari $ 3397403Sobrien */ 3497403Sobrien 3597403Sobrien/* 3697403Sobrien * Register definitions for the VIA VT6122 gigabit ethernet controller. 3797403Sobrien * Definitions for the built-in copper PHY can be found in vgphy.h. 3897403Sobrien * 3997403Sobrien * The VT612x controllers have 256 bytes of register space. The 4097403Sobrien * manual seems to imply that the registers should all be accessed 4197403Sobrien * using 32-bit I/O cycles, but some of them are less than 32 bits 4297403Sobrien * wide. Go figure. 4397403Sobrien */ 4497403Sobrien 4597403Sobrien#ifndef _IF_VGEREG_H_ 4697403Sobrien#define _IF_VGEREG_H_ 4797403Sobrien 4897403Sobrien#define VIA_VENDORID 0x1106 4997403Sobrien#define VIA_DEVICEID_61XX 0x3119 5097403Sobrien 5197403Sobrien#define VGE_PAR0 0x00 /* physical address register */ 5297403Sobrien#define VGE_PAR1 0x02 5397403Sobrien#define VGE_PAR2 0x04 5497403Sobrien#define VGE_RXCTL 0x06 /* RX control register */ 5597403Sobrien#define VGE_TXCTL 0x07 /* TX control register */ 5697403Sobrien#define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */ 5797403Sobrien#define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */ 5897403Sobrien#define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */ 5997403Sobrien#define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */ 6097403Sobrien#define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */ 6197403Sobrien#define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */ 6297403Sobrien#define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */ 6397403Sobrien#define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */ 64132720Skan#define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */ 65132720Skan#define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */ 6697403Sobrien#define VGE_CAM0 0x10 67258429Spfg#define VGE_CAM1 0x11 68258429Spfg#define VGE_CAM2 0x12 6997403Sobrien#define VGE_CAM3 0x13 70132720Skan#define VGE_CAM4 0x14 7197403Sobrien#define VGE_CAM5 0x15 7297403Sobrien#define VGE_CAM6 0x16 73132720Skan#define VGE_CAM7 0x17 7497403Sobrien#define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */ 75169691Skan#define VGE_DATABUF_HIADDR 0x1D /* Hi part of 64bit data buffer addr */ 76169691Skan#define VGE_INTCTL0 0x20 /* interrupt control register */ 77132720Skan#define VGE_RXSUPPTHR 0x20 78132720Skan#define VGE_TXSUPPTHR 0x20 79132720Skan#define VGE_INTHOLDOFF 0x20 80132720Skan#define VGE_INTCTL1 0x21 /* interrupt control register */ 81132720Skan#define VGE_TXHOSTERR 0x22 /* TX host error status */ 82132720Skan#define VGE_RXHOSTERR 0x23 /* RX host error status */ 83132720Skan#define VGE_ISR 0x24 /* Interrupt status register */ 84132720Skan#define VGE_IMR 0x28 /* Interrupt mask register */ 85132720Skan#define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */ 86132720Skan#define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */ 87132720Skan#define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */ 88132720Skan#define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */ 89132720Skan#define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */ 90132720Skan#define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */ 91132720Skan#define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */ 9297403Sobrien#define VGE_TXQTIMER 0x3E /* TX queue timer pend register */ 93132720Skan#define VGE_RXQTIMER 0x3F /* RX queue timer pend register */ 94132720Skan#define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */ 9597403Sobrien#define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */ 9697403Sobrien#define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */ 9797403Sobrien#define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */ 98132720Skan#define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */ 99132720Skan#define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */ 100132720Skan#define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */ 101132720Skan#define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */ 102132720Skan#define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */ 103132720Skan#define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */ 104132720Skan#define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */ 105132720Skan#define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */ 10697403Sobrien#define VGE_FIFOTEST0 0x60 /* FIFO test register */ 10797403Sobrien#define VGE_FIFOTEST1 0x64 /* FIFO test register */ 10897403Sobrien#define VGE_CAMADDR 0x68 /* CAM address register */ 10997403Sobrien#define VGE_CAMCTL 0x69 /* CAM control register */ 11097403Sobrien#define VGE_GFTEST 0x6A 11197403Sobrien#define VGE_FTSCMD 0x6B 112132720Skan#define VGE_MIICFG 0x6C /* MII port config register */ 113132720Skan#define VGE_MIISTS 0x6D /* MII port status register */ 114132720Skan#define VGE_PHYSTS0 0x6E /* PHY status register */ 115132720Skan#define VGE_PHYSTS1 0x6F /* PHY status register */ 116132720Skan#define VGE_MIICMD 0x70 /* MII command register */ 117132720Skan#define VGE_MIIADDR 0x71 /* MII address register */ 118132720Skan#define VGE_MIIDATA 0x72 /* MII data register */ 119132720Skan#define VGE_SSTIMER 0x74 /* single-shot timer */ 12097403Sobrien#define VGE_PTIMER 0x76 /* periodic timer */ 12197403Sobrien#define VGE_CHIPCFG0 0x78 /* chip config A */ 12297403Sobrien#define VGE_CHIPCFG1 0x79 /* chip config B */ 12397403Sobrien#define VGE_CHIPCFG2 0x7A /* chip config C */ 12497403Sobrien#define VGE_CHIPCFG3 0x7B /* chip config D */ 125132720Skan#define VGE_DMACFG0 0x7C /* DMA config 0 */ 126132720Skan#define VGE_DMACFG1 0x7D /* DMA config 1 */ 127132720Skan#define VGE_RXCFG 0x7E /* MAC RX config */ 128132720Skan#define VGE_TXCFG 0x7F /* MAC TX config */ 129132720Skan#define VGE_PWRMGMT 0x82 /* power management shadow register */ 130132720Skan#define VGE_PWRSTAT 0x83 /* power state shadow register */ 131132720Skan#define VGE_MIBCSR 0x84 /* MIB control/status register */ 13297403Sobrien#define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */ 13397403Sobrien#define VGE_MIBDATA 0x88 /* MIB data register */ 13497403Sobrien#define VGE_EEWRDAT 0x8C /* EEPROM embedded write */ 13597403Sobrien#define VGE_EECSUM 0x92 /* EEPROM checksum */ 13697403Sobrien#define VGE_EECSR 0x93 /* EEPROM control/status */ 13797403Sobrien#define VGE_EERDDAT 0x94 /* EEPROM embedded read */ 13897403Sobrien#define VGE_EEADDR 0x96 /* EEPROM address */ 13997403Sobrien#define VGE_EECMD 0x97 /* EEPROM embedded command */ 14097403Sobrien#define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */ 141132720Skan#define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */ 142132720Skan#define VGE_DIAGSTS 0x9C /* Chip diagnostic status */ 14397403Sobrien#define VGE_DBGCTL 0x9E /* Chip debug control */ 144132720Skan#define VGE_DIAGCTL 0x9F /* Chip diagnostic control */ 145132720Skan#define VGE_WOLCR0S 0xA0 /* WOL0 event set */ 14697403Sobrien#define VGE_WOLCR1S 0xA1 /* WOL1 event set */ 147132720Skan#define VGE_PWRCFGS 0xA2 /* Power management config set */ 148132720Skan#define VGE_WOLCFGS 0xA3 /* WOL config set */ 14997403Sobrien#define VGE_WOLCR0C 0xA4 /* WOL0 event clear */ 150132720Skan#define VGE_WOLCR1C 0xA5 /* WOL1 event clear */ 151132720Skan#define VGE_PWRCFGC 0xA6 /* Power management config clear */ 152132720Skan#define VGE_WOLCFGC 0xA7 /* WOL config clear */ 153132720Skan#define VGE_WOLSR0S 0xA8 /* WOL status set */ 154132720Skan#define VGE_WOLSR1S 0xA9 /* WOL status set */ 15597403Sobrien#define VGE_WOLSR0C 0xAC /* WOL status clear */ 156132720Skan#define VGE_WOLSR1C 0xAD /* WOL status clear */ 157132720Skan#define VGE_WAKEPAT_CRC0 0xB0 158132720Skan#define VGE_WAKEPAT_CRC1 0xB2 15997403Sobrien#define VGE_WAKEPAT_CRC2 0xB4 160132720Skan#define VGE_WAKEPAT_CRC3 0xB6 161132720Skan#define VGE_WAKEPAT_CRC4 0xB8 16297403Sobrien#define VGE_WAKEPAT_CRC5 0xBA 163132720Skan#define VGE_WAKEPAT_CRC6 0xBC 164132720Skan#define VGE_WAKEPAT_CRC7 0xBE 165132720Skan#define VGE_WAKEPAT_MSK0_0 0xC0 16697403Sobrien#define VGE_WAKEPAT_MSK0_1 0xC4 167146897Skan#define VGE_WAKEPAT_MSK0_2 0xC8 168146897Skan#define VGE_WAKEPAT_MSK0_3 0xCC 169132720Skan#define VGE_WAKEPAT_MSK1_0 0xD0 170169691Skan#define VGE_WAKEPAT_MSK1_1 0xD4 171132720Skan#define VGE_WAKEPAT_MSK1_2 0xD8 172132720Skan#define VGE_WAKEPAT_MSK1_3 0xDC 173132720Skan#define VGE_WAKEPAT_MSK2_0 0xE0 174132720Skan#define VGE_WAKEPAT_MSK2_1 0xE4 175132720Skan#define VGE_WAKEPAT_MSK2_2 0xE8 176132720Skan#define VGE_WAKEPAT_MSK2_3 0xEC 177132720Skan#define VGE_WAKEPAT_MSK3_0 0xF0 178132720Skan#define VGE_WAKEPAT_MSK3_1 0xF4 179132720Skan#define VGE_WAKEPAT_MSK3_2 0xF8 180132720Skan#define VGE_WAKEPAT_MSK3_3 0xFC 181132720Skan 182132720Skan/* Receive control register */ 183132720Skan 184132720Skan#define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */ 185132720Skan#define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */ 186132720Skan#define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */ 18797403Sobrien#define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */ 18897403Sobrien#define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */ 189132720Skan#define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */ 190132720Skan#define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */ 19197403Sobrien#define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */ 19297403Sobrien 193132720Skan/* Transmit control register */ 19497403Sobrien 19597403Sobrien#define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */ 19697403Sobrien#define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */ 197132720Skan 198132720Skan#define VGE_TXLOOPCTL_OFF 0x00 19997403Sobrien#define VGE_TXLOOPCTL_MAC_INTERNAL 0x01 200132720Skan#define VGE_TXLOOPCTL_EXTERNAL 0x02 201132720Skan 202132720Skan#define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */ 203132720Skan#define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */ 204132720Skan#define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */ 205132720Skan#define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */ 206132720Skan 20797403Sobrien/* Global command register 0 */ 208132720Skan 20997403Sobrien#define VGE_CR0_START 0x01 /* start NIC */ 21097403Sobrien#define VGE_CR0_STOP 0x02 /* stop NIC */ 211132720Skan#define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */ 212132720Skan#define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */ 213132720Skan 214132720Skan/* Global command register 1 */ 215132720Skan 216132720Skan#define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */ 217132720Skan#define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */ 218132720Skan#define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */ 219132720Skan#define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */ 220132720Skan#define VGE_CR1_SOFTRESET 0x80 /* software reset */ 22197403Sobrien 22297403Sobrien/* Global command register 2 */ 223132720Skan 224132720Skan#define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */ 225132720Skan#define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */ 226132720Skan#define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */ 227132720Skan#define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */ 228132720Skan#define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */ 22997403Sobrien#define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */ 230132720Skan 23197403Sobrien/* Global command register 3 */ 232132720Skan 233132720Skan#define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */ 23497403Sobrien#define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */ 235132720Skan#define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */ 236132720Skan#define VGE_CR3_DIAG 0x10 /* diagnostic enabled */ 237132720Skan#define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */ 23897403Sobrien#define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */ 239146897Skan 240146897Skan/* Interrupt control register */ 24197403Sobrien 242169691Skan#define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */ 243132720Skan#define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */ 244132720Skan#define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */ 24597403Sobrien#define VGE_INTCTL_MASK 0x18 /* multilayer int mask */ 246132720Skan#define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */ 247132720Skan#define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */ 24897403Sobrien#define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */ 249132720Skan 250132720Skan#define VGE_INTMASK_LAYER0 0x00 251132720Skan#define VGE_INTMASK_LAYER1 0x08 25297403Sobrien#define VGE_INTMASK_ALL 0x10 253132720Skan#define VGE_INTMASK_ALL2 0x18 254132720Skan 255132720Skan/* Transmit host error status register */ 25697403Sobrien 257132720Skan#define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */ 258132720Skan#define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */ 25997403Sobrien#define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */ 260132720Skan#define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */ 261132720Skan 26297403Sobrien/* Receive host error status register */ 26397403Sobrien 264132720Skan#define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */ 265132720Skan#define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */ 26697403Sobrien#define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */ 267132720Skan#define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */ 268132720Skan 269132720Skan/* Interrupt status register */ 27097403Sobrien 271132720Skan#define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ 272132720Skan#define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ 273132720Skan#define VGE_ISR_RXOK 0x00000004 /* normal RX done */ 274132720Skan#define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */ 275132720Skan#define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */ 276132720Skan#define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */ 27797403Sobrien#define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */ 278132720Skan#define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */ 279132720Skan#define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ 280132720Skan#define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */ 281132720Skan#define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */ 282132720Skan#define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */ 283132720Skan#define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ 284132720Skan#define VGE_ISR_LINKSTS 0x00008000 /* link status change */ 28597403Sobrien#define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */ 28697403Sobrien#define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */ 287132720Skan#define VGE_ISR_PWR 0x00040000 /* wake up power event */ 288132720Skan#define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */ 289132720Skan#define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */ 29097403Sobrien#define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ 291132720Skan#define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */ 292132720Skan#define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ 293132720Skan#define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */ 29497403Sobrien#define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ 295132720Skan#define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */ 296132720Skan#define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */ 29797403Sobrien#define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */ 298132720Skan#define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */ 299132720Skan 300132720Skan#define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \ 301132720Skan VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \ 302132720Skan VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \ 30397403Sobrien VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL) 304132720Skan 305132720Skan#define VGE_INTRS_POLLING (VGE_ISR_PHYINT|VGE_ISR_LINKSTS) 306132720Skan 307132720Skan/* Interrupt mask register */ 308132720Skan 30997403Sobrien#define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ 310132720Skan#define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ 311132720Skan#define VGE_IMR_RXOK 0x00000004 /* normal RX done */ 312132720Skan#define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */ 31397403Sobrien#define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */ 314132720Skan#define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */ 315132720Skan#define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */ 316132720Skan#define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */ 31797403Sobrien#define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ 318132720Skan#define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */ 319132720Skan#define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */ 320132720Skan#define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */ 321132720Skan#define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ 322132720Skan#define VGE_IMR_LINKSTS 0x00008000 /* link status change */ 32397403Sobrien#define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */ 324132720Skan#define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */ 325132720Skan#define VGE_IMR_PWR 0x00040000 /* wake up power event */ 326132720Skan#define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */ 32797403Sobrien#define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */ 32897403Sobrien#define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ 329132720Skan#define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */ 330132720Skan#define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ 331132720Skan#define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */ 33297403Sobrien#define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ 333132720Skan#define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */ 334132720Skan#define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */ 33597403Sobrien#define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */ 33697403Sobrien#define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */ 33797403Sobrien 338132720Skan/* TX descriptor queue control/status register */ 33997403Sobrien 340132720Skan#define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */ 34197403Sobrien#define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */ 34297403Sobrien#define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */ 34397403Sobrien#define VGE_TXQCSR_DEAD0 0x0008 /* queue 0 dead indicator */ 34497403Sobrien#define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */ 34597403Sobrien#define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */ 34697403Sobrien#define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */ 34797403Sobrien#define VGE_TXQCSR_DEAD1 0x0080 /* queue 1 dead indicator */ 34897403Sobrien#define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */ 349132720Skan#define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */ 35097403Sobrien#define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */ 35197403Sobrien#define VGE_TXQCSR_DEAD2 0x0800 /* queue 2 dead indicator */ 352132720Skan#define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */ 353132720Skan#define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */ 354169691Skan#define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */ 355169691Skan#define VGE_TXQCSR_DEAD3 0x8000 /* queue 3 dead indicator */ 356169691Skan 357169691Skan/* RX descriptor queue control/status register */ 358169691Skan 359169691Skan#define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */ 360132720Skan#define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */ 361132720Skan#define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */ 362169691Skan#define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */ 363169691Skan 364169691Skan/* RX/TX queue empty interrupt delay timer register */ 365169691Skan 36697403Sobrien#define VGE_QTIMER_PENDCNT 0x3F 367132720Skan#define VGE_QTIMER_RESOLUTION 0xC0 368132720Skan 369132720Skan#define VGE_QTIMER_RES_1US 0x00 370132720Skan#define VGE_QTIMER_RES_4US 0x40 371132720Skan#define VGE_QTIMER_RES_16US 0x80 372132720Skan#define VGE_QTIMER_RES_64US 0xC0 373132720Skan 374132720Skan/* CAM address register */ 37597403Sobrien 37697403Sobrien#define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */ 37797403Sobrien#define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */ 37897403Sobrien#define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */ 379132720Skan 380169691Skan#define VGE_CAM_MAXADDRS 64 38197403Sobrien 38297403Sobrien/* 383132720Skan * CAM command register 384132720Skan * Note that the page select bits in this register affect three 38597403Sobrien * different things: 38697403Sobrien * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the 38797403Sobrien * page select bits control whether the MAR0/MAR1 registers affect 388132720Skan * the multicast hash filter or the CAM table) 389132720Skan * - The behavior of the interrupt holdoff timer register at offset 390132720Skan * 0x20 (the page select bits allow you to set the interrupt 39197403Sobrien * holdoff timer, the TX interrupt supression count or the 39297403Sobrien * RX interrupt supression count) 39397403Sobrien * - The behavior the WOL pattern programming registers at offset 39497403Sobrien * 0xC0 (controls which pattern is set) 39597403Sobrien */ 39697403Sobrien 39797403Sobrien 39897403Sobrien#define VGE_CAMCTL_WRITE 0x04 /* CAM write command */ 39997403Sobrien#define VGE_CAMCTL_READ 0x08 /* CAM read command */ 400169691Skan#define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */ 40197403Sobrien#define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */ 402169691Skan#define VGE_CAMCTL_PAGESEL 0xC0 /* page select */ 40397403Sobrien 40497403Sobrien#define VGE_PAGESEL_MAR 0x00 40597403Sobrien#define VGE_PAGESEL_CAMMASK 0x40 406132720Skan#define VGE_PAGESEL_CAMDATA 0x80 407132720Skan 408169691Skan#define VGE_PAGESEL_INTHLDOFF 0x00 409132720Skan#define VGE_PAGESEL_TXSUPPTHR 0x40 410132720Skan#define VGE_PAGESEL_RXSUPPTHR 0x80 411132720Skan 412132720Skan#define VGE_PAGESEL_WOLPAT0 0x00 413132720Skan#define VGE_PAGESEL_WOLPAT1 0x40 41497403Sobrien 415236829Spfg/* MII port config register */ 416236829Spfg 417169691Skan#define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */ 418236829Spfg#define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */ 419236829Spfg#define VGE_MIICFG_POLLINT 0xC0 /* polling interval */ 420236829Spfg 421236829Spfg#define VGE_MIIPOLLINT_1024 0x00 422236829Spfg#define VGE_MIIPOLLINT_512 0x40 423236829Spfg#define VGE_MIIPOLLINT_128 0x80 424236829Spfg#define VGE_MIIPOLLINT_64 0xC0 425236829Spfg 426236829Spfg/* MII port status register */ 427236829Spfg 428132720Skan#define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */ 429132720Skan 430132720Skan/* PHY status register */ 431132720Skan 432132720Skan#define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */ 433132720Skan#define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */ 434132720Skan#define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */ 43597403Sobrien#define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */ 436132720Skan#define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */ 437132720Skan#define VGE_PHYSTS_LINK 0x40 /* link status */ 438132720Skan#define VGE_PHYSTS_RESETSTS 0x80 /* reset status */ 439132720Skan 440132720Skan/* MII management command register */ 441132720Skan 442132720Skan#define VGE_MIICMD_MDC 0x01 /* clock pin */ 443132720Skan#define VGE_MIICMD_MDI 0x02 /* data in pin */ 44497403Sobrien#define VGE_MIICMD_MDO 0x04 /* data out pin */ 445236829Spfg#define VGE_MIICMD_MOUT 0x08 /* data out pin enable */ 446236829Spfg#define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */ 447236829Spfg#define VGE_MIICMD_WCMD 0x20 /* embedded mode write */ 448236829Spfg#define VGE_MIICMD_RCMD 0x40 /* embadded mode read */ 449236829Spfg#define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */ 450236829Spfg 451169691Skan/* MII address register */ 452169691Skan 453236829Spfg#define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */ 454236829Spfg 455236829Spfg/* Chip config register A */ 456236829Spfg 457236829Spfg#define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */ 458236829Spfg#define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */ 459132720Skan#define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */ 460132720Skan#define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */ 461132720Skan#define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */ 462132720Skan 463132720Skan/* Chip config register B */ 464132720Skan/* Note: some of these bits are not documented in the manual! */ 46597403Sobrien 466132720Skan#define VGE_CHIPCFG1_BAKOPT 0x01 46797403Sobrien#define VGE_CHIPCFG1_MBA 0x02 468132720Skan#define VGE_CHIPCFG1_CAP 0x04 469132720Skan#define VGE_CHIPCFG1_CRANDOM 0x08 470132720Skan#define VGE_CHIPCFG1_OFSET 0x10 471132720Skan#define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */ 47297403Sobrien#define VGE_CHIPCFG1_MIIOPT 0x40 473132720Skan#define VGE_CHIPCFG1_GTCKOPT 0x80 474132720Skan 475132720Skan/* Chip config register C */ 47697403Sobrien 477132720Skan#define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */ 478132720Skan 479132720Skan/* Chip config register D */ 48097403Sobrien 481132720Skan#define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */ 482132720Skan#define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */ 483132720Skan 48497403Sobrien/* DMA config register 0 */ 485132720Skan 486132720Skan#define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */ 487132720Skan 48897403Sobrien#define VGE_DMABURST_8 0x00 489132720Skan#define VGE_DMABURST_16 0x01 490132720Skan#define VGE_DMABURST_32 0x02 491132720Skan#define VGE_DMABURST_64 0x03 49297403Sobrien#define VGE_DMABURST_128 0x04 493132720Skan#define VGE_DMABURST_256 0x05 494132720Skan#define VGE_DMABURST_STRFWD 0x07 495132720Skan 49697403Sobrien/* DMA config register 1 */ 497132720Skan 498132720Skan#define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */ 499169691Skan#define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */ 500169691Skan#define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */ 501169691Skan#define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */ 502169691Skan#define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */ 50397403Sobrien#define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */ 504132720Skan 505132720Skan/* RX MAC config register */ 506132720Skan 50797403Sobrien#define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */ 508132720Skan#define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */ 509132720Skan#define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */ 510132720Skan#define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */ 51197403Sobrien#define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */ 512132720Skan 513132720Skan#define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion 514132720Skan RX: rx all, no tag extraction */ 51597403Sobrien 516132720Skan#define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion 517132720Skan RX: rx only tagged pkts, no 518132720Skan extraction */ 51997403Sobrien 520132720Skan#define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion, 521132720Skan RX: rx all, extract tags */ 522132720Skan 52397403Sobrien#define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion, 524132720Skan RX: rx only tagged pkts, 525132720Skan with extraction */ 526132720Skan 527132720Skan#define VGE_RXFIFOTHR_128BYTES 0x00 528132720Skan#define VGE_RXFIFOTHR_512BYTES 0x10 529132720Skan#define VGE_RXFIFOTHR_1024BYTES 0x20 530132720Skan#define VGE_RXFIFOTHR_STRNFWD 0x30 531132720Skan 532132720Skan/* TX MAC config register */ 533132720Skan 534132720Skan#define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at 535132720Skan 13th byte 536132720Skan 0 == insert VLANM tag after 537132720Skan SNAP header (21st byte) */ 538132720Skan#define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */ 539132720Skan#define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */ 540132720Skan#define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */ 541132720Skan 542132720Skan#define VGE_TXBLOCK_64PKTS 0x00 543132720Skan#define VGE_TXBLOCK_32PKTS 0x04 544132720Skan#define VGE_TXBLOCK_128PKTS 0x08 545132720Skan#define VGE_TXBLOCK_8PKTS 0x0C 546132720Skan 547132720Skan/* MIB control/status register */ 548132720Skan#define VGE_MIBCSR_CLR 0x01 549132720Skan#define VGE_MIBCSR_RINI 0x02 550132720Skan#define VGE_MIBCSR_FLUSH 0x04 551132720Skan#define VGE_MIBCSR_FREEZE 0x08 552132720Skan#define VGE_MIBCSR_HI_80 0x00 553132720Skan#define VGE_MIBCSR_HI_C0 0x10 554132720Skan#define VGE_MIBCSR_BISTGO 0x40 555132720Skan#define VGE_MIBCSR_BISTOK 0x80 556132720Skan 557132720Skan/* MIB data index. */ 558132720Skan#define VGE_MIB_RX_FRAMES 0 559132720Skan#define VGE_MIB_RX_GOOD_FRAMES 1 56097403Sobrien#define VGE_MIB_TX_GOOD_FRAMES 2 561132720Skan#define VGE_MIB_RX_FIFO_OVERRUNS 3 562132720Skan#define VGE_MIB_RX_RUNTS 4 56397403Sobrien#define VGE_MIB_RX_RUNTS_ERRS 5 564132720Skan#define VGE_MIB_RX_PKTS_64 6 565117397Skan#define VGE_MIB_TX_PKTS_64 7 56697403Sobrien#define VGE_MIB_RX_PKTS_65_127 8 56797403Sobrien#define VGE_MIB_TX_PKTS_65_127 9 568132720Skan#define VGE_MIB_RX_PKTS_128_255 10 56997403Sobrien#define VGE_MIB_TX_PKTS_128_255 11 57097403Sobrien#define VGE_MIB_RX_PKTS_256_511 12 571169691Skan#define VGE_MIB_TX_PKTS_256_511 13 572169691Skan#define VGE_MIB_RX_PKTS_512_1023 14 573169691Skan#define VGE_MIB_TX_PKTS_512_1023 15 574169691Skan#define VGE_MIB_RX_PKTS_1024_1518 16 575169691Skan#define VGE_MIB_TX_PKTS_1024_1518 17 576169691Skan#define VGE_MIB_TX_COLLS 18 577169691Skan#define VGE_MIB_RX_CRCERRS 19 578169691Skan#define VGE_MIB_RX_JUMBOS 20 579169691Skan#define VGE_MIB_TX_JUMBOS 21 580132720Skan#define VGE_MIB_RX_PAUSE 22 581132720Skan#define VGE_MIB_TX_PAUSE 23 58297403Sobrien#define VGE_MIB_RX_ALIGNERRS 24 583132720Skan#define VGE_MIB_RX_PKTS_1519_MAX 25 58497403Sobrien#define VGE_MIB_RX_PKTS_1519_MAX_ERRS 26 58597403Sobrien#define VGE_MIB_TX_SQEERRS 27 58697403Sobrien#define VGE_MIB_RX_NOBUFS 28 58797403Sobrien#define VGE_MIB_RX_SYMERRS 29 58897403Sobrien#define VGE_MIB_RX_LENERRS 30 589132720Skan#define VGE_MIB_TX_LATECOLLS 31 59097403Sobrien 591236829Spfg#define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1) 592236829Spfg#define VGE_MIB_DATA_MASK 0x00FFFFFF 593236829Spfg#define VGE_MIB_DATA_IDX(x) ((x) >> 24) 594132720Skan 59597403Sobrien/* Sticky bit shadow register */ 596236829Spfg 597236829Spfg#define VGE_STICKHW_DS0 0x01 598132720Skan#define VGE_STICKHW_DS1 0x02 599132720Skan#define VGE_STICKHW_WOL_ENB 0x04 60097403Sobrien#define VGE_STICKHW_WOL_STS 0x08 601132720Skan#define VGE_STICKHW_SWPTAG 0x10 60297403Sobrien 60397403Sobrien/* WOL pattern control */ 604132720Skan#define VGE_WOLCR0_PATTERN0 0x01 60597403Sobrien#define VGE_WOLCR0_PATTERN1 0x02 60697403Sobrien#define VGE_WOLCR0_PATTERN2 0x04 60797403Sobrien#define VGE_WOLCR0_PATTERN3 0x08 608132720Skan#define VGE_WOLCR0_PATTERN4 0x10 609132720Skan#define VGE_WOLCR0_PATTERN5 0x20 61097403Sobrien#define VGE_WOLCR0_PATTERN6 0x40 611236829Spfg#define VGE_WOLCR0_PATTERN7 0x80 612236829Spfg#define VGE_WOLCR0_PATTERN_ALL 0xFF 61397403Sobrien 61497403Sobrien/* WOL event control */ 615132720Skan#define VGE_WOLCR1_UCAST 0x01 616132720Skan#define VGE_WOLCR1_MAGIC 0x02 617132720Skan#define VGE_WOLCR1_LINKON 0x04 61897403Sobrien#define VGE_WOLCR1_LINKOFF 0x08 619132720Skan 620132720Skan/* Poweer management config */ 621169691Skan#define VGE_PWRCFG_LEGACY_WOLEN 0x01 622169691Skan#define VGE_PWRCFG_WOL_PULSE 0x20 623169691Skan#define VGE_PWRCFG_WOL_BUTTON 0x00 624169691Skan 62597403Sobrien/* WOL config register */ 626132720Skan#define VGE_WOLCFG_PHYINT_ENB 0x01 627132720Skan#define VGE_WOLCFG_SAB 0x10 628169691Skan#define VGE_WOLCFG_SAM 0x20 629169691Skan#define VGE_WOLCFG_PMEOVR 0x80 630169691Skan 631169691Skan/* EEPROM control/status register */ 63297403Sobrien 633132720Skan#define VGE_EECSR_EDO 0x01 /* data out pin */ 634132720Skan#define VGE_EECSR_EDI 0x02 /* data in pin */ 635169691Skan#define VGE_EECSR_ECK 0x04 /* clock pin */ 63697403Sobrien#define VGE_EECSR_ECS 0x08 /* chip select pin */ 637132720Skan#define VGE_EECSR_DPM 0x10 /* direct program mode enable */ 638132720Skan#define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */ 639169691Skan#define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */ 640169691Skan 641169691Skan/* EEPROM embedded command register */ 642169691Skan 64397403Sobrien#define VGE_EECMD_ERD 0x01 /* EEPROM read command */ 644132720Skan#define VGE_EECMD_EWR 0x02 /* EEPROM write command */ 645132720Skan#define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */ 646132720Skan#define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */ 64797403Sobrien#define VGE_EECMD_EDONE 0x80 /* read/write done */ 648132720Skan 649132720Skan/* Chip operation and diagnostic control register */ 650132720Skan 65197403Sobrien#define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */ 652132720Skan#define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */ 653132720Skan#define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */ 654132720Skan#define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */ 65597403Sobrien#define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */ 656132720Skan#define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */ 657132720Skan#define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */ 658132720Skan#define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */ 65997403Sobrien 660132720Skan/* Location of station address in EEPROM */ 661132720Skan#define VGE_EE_EADDR 0 662132720Skan 66397403Sobrien/* DMA descriptor structures */ 664132720Skan 665132720Skan/* 666132720Skan * Each TX DMA descriptor has a control and status word, and 7 66797403Sobrien * fragment address/length words. If a transmitted packet spans 668132720Skan * more than 7 fragments, it has to be coalesced. 669132720Skan */ 670169691Skan 671132720Skan#define VGE_TX_FRAGS 7 672132720Skan 673236829Spfgstruct vge_tx_frag { 674132720Skan uint32_t vge_addrlo; 67597403Sobrien uint32_t vge_addrhi; 676169691Skan}; 677169691Skan 67897403Sobrien/* 679132720Skan * The high bit in the buflen field of fragment #0 has special meaning. 680169691Skan * Normally, the chip requires the driver to issue a TX poll command 68197403Sobrien * for every packet that gets put in the TX DMA queue. Sometimes though, 682169691Skan * the driver might want to queue up several packets at once and just 683169691Skan * issue one transmit command to have all of them processed. In order 684132720Skan * to obtain this behavior, the special 'queue' bit must be set. 685169691Skan */ 68697403Sobrien 687132720Skan#define VGE_TXDESC_Q 0x80000000 688169691Skan 68997403Sobrienstruct vge_tx_desc { 690169691Skan uint32_t vge_sts; 691169691Skan uint32_t vge_ctl; 692169691Skan struct vge_tx_frag vge_frag[VGE_TX_FRAGS]; 693169691Skan}; 694169691Skan 695169691Skan#define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */ 696169691Skan#define VGE_TDSTS_COLL 0x00000010 /* collision seen */ 697169691Skan#define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */ 698169691Skan#define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */ 69997403Sobrien#define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */ 700169691Skan#define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */ 701169691Skan#define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */ 70297403Sobrien#define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */ 70397403Sobrien#define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */ 704169691Skan#define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */ 705169691Skan#define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */ 70697403Sobrien#define VGE_TDSTS_TXERR 0x00008000 /* error occurred */ 707132720Skan#define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */ 70897403Sobrien#define VGE_TDSTS_OWN 0x80000000 /* own bit */ 70997403Sobrien 710169691Skan#define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */ 711169691Skan#define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */ 712169691Skan#define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */ 713132720Skan#define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */ 71497403Sobrien#define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */ 71597403Sobrien#define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */ 716132720Skan#define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */ 71797403Sobrien#define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */ 71897403Sobrien#define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */ 719132720Skan#define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */ 720169691Skan#define VGE_TDCTL_TIC 0x00800000 /* transfer int request */ 721169691Skan#define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */ 722169691Skan#define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */ 72397403Sobrien 72497403Sobrien#define VGE_TD_LS_MOF 0x00000000 /* middle of large send */ 725132720Skan#define VGE_TD_LS_SOF 0x01000000 /* start of large send */ 726132720Skan#define VGE_TD_LS_EOF 0x02000000 /* end of large send */ 72797403Sobrien#define VGE_TD_LS_NORM 0x03000000 /* normal frame */ 728132720Skan 729132720Skan/* Receive DMA descriptors have a single fragment pointer. */ 730132720Skan 731132720Skanstruct vge_rx_desc { 732132720Skan uint32_t vge_sts; 733132720Skan uint32_t vge_ctl; 73497403Sobrien uint32_t vge_addrlo; 73597403Sobrien uint32_t vge_addrhi; 736132720Skan}; 73797403Sobrien 73897403Sobrien/* 739132720Skan * Like the TX descriptor, the high bit in the buflen field in the 74097403Sobrien * RX descriptor has special meaning. This bit controls whether or 74197403Sobrien * not interrupts are generated for this descriptor. 742132720Skan */ 74397403Sobrien 74497403Sobrien#define VGE_RXDESC_I 0x80000000 745132720Skan 74697403Sobrien#define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */ 74797403Sobrien#define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */ 748132720Skan#define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */ 74997403Sobrien#define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */ 75097403Sobrien#define VGE_RDSTS_RLERR 0x00000010 /* RX length error */ 751132720Skan#define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */ 75297403Sobrien#define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */ 75397403Sobrien#define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */ 754132720Skan#define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */ 75597403Sobrien#define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */ 75697403Sobrien#define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */ 757132720Skan#define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */ 75897403Sobrien#define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */ 75997403Sobrien#define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */ 760132720Skan#define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */ 76197403Sobrien#define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */ 76297403Sobrien#define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */ 76397403Sobrien#define VGE_RDSTS_OWN 0x80000000 /* own bit. */ 764132720Skan 76597403Sobrien#define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */ 76697403Sobrien#define VGE_RXPKT_EOF 0x00000100 /* last frag in frame */ 76797403Sobrien#define VGE_RXPKT_SOF 0x00000200 /* first frag in frame */ 768132720Skan#define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */ 76997403Sobrien 770132720Skan#define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */ 771169691Skan#define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */ 772169691Skan#define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */ 77397403Sobrien#define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */ 774132720Skan#define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */ 775146897Skan#define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */ 77697403Sobrien#define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */ 77797403Sobrien#define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */ 778132720Skan#define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */ 77997403Sobrien 780132720Skan#endif /* _IF_VGEREG_H_ */ 781169691Skan