if_vgereg.h revision 200696
1226584Sdim/*- 2226584Sdim * Copyright (c) 2004 3226584Sdim * Bill Paul <wpaul@windriver.com>. All rights reserved. 4226584Sdim * 5226584Sdim * Redistribution and use in source and binary forms, with or without 6226584Sdim * modification, are permitted provided that the following conditions 7226584Sdim * are met: 8226584Sdim * 1. Redistributions of source code must retain the above copyright 9226584Sdim * notice, this list of conditions and the following disclaimer. 10226584Sdim * 2. Redistributions in binary form must reproduce the above copyright 11226584Sdim * notice, this list of conditions and the following disclaimer in the 12226584Sdim * documentation and/or other materials provided with the distribution. 13226584Sdim * 3. All advertising materials mentioning features or use of this software 14226584Sdim * must display the following acknowledgement: 15226584Sdim * This product includes software developed by Bill Paul. 16226584Sdim * 4. Neither the name of the author nor the names of any co-contributors 17226584Sdim * may be used to endorse or promote products derived from this software 18226584Sdim * without specific prior written permission. 19226584Sdim * 20226584Sdim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21226584Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22226584Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23226584Sdim * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24226584Sdim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25226584Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26226584Sdim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27226584Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28226584Sdim * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29226584Sdim * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30226584Sdim * THE POSSIBILITY OF SUCH DAMAGE. 31226584Sdim * 32226584Sdim * $FreeBSD: head/sys/dev/vge/if_vgereg.h 200696 2009-12-18 22:14:28Z yongari $ 33226584Sdim */ 34226584Sdim 35226584Sdim/* 36226584Sdim * Register definitions for the VIA VT6122 gigabit ethernet controller. 37226584Sdim * Definitions for the built-in copper PHY can be found in vgphy.h. 38226584Sdim * 39226584Sdim * The VT612x controllers have 256 bytes of register space. The 40226584Sdim * manual seems to imply that the registers should all be accessed 41226584Sdim * using 32-bit I/O cycles, but some of them are less than 32 bits 42226584Sdim * wide. Go figure. 43226584Sdim */ 44226584Sdim 45226584Sdim#ifndef _IF_VGEREG_H_ 46226584Sdim#define _IF_VGEREG_H_ 47226584Sdim 48226584Sdim#define VIA_VENDORID 0x1106 49226584Sdim#define VIA_DEVICEID_61XX 0x3119 50226584Sdim 51226584Sdim#define VGE_PAR0 0x00 /* physical address register */ 52226584Sdim#define VGE_PAR1 0x02 53226584Sdim#define VGE_PAR2 0x04 54226584Sdim#define VGE_RXCTL 0x06 /* RX control register */ 55226584Sdim#define VGE_TXCTL 0x07 /* TX control register */ 56226584Sdim#define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */ 57226584Sdim#define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */ 58226584Sdim#define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */ 59226584Sdim#define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */ 60226584Sdim#define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */ 61226584Sdim#define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */ 62226584Sdim#define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */ 63226584Sdim#define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */ 64226584Sdim#define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */ 65226584Sdim#define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */ 66226584Sdim#define VGE_CAM0 0x10 67226584Sdim#define VGE_CAM1 0x11 68226584Sdim#define VGE_CAM2 0x12 69226584Sdim#define VGE_CAM3 0x13 70226584Sdim#define VGE_CAM4 0x14 71226584Sdim#define VGE_CAM5 0x15 72226584Sdim#define VGE_CAM6 0x16 73226584Sdim#define VGE_CAM7 0x17 74226584Sdim#define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */ 75226584Sdim#define VGE_DATABUF_HIADDR 0x1D /* Hi part of 64bit data buffer addr */ 76226584Sdim#define VGE_INTCTL0 0x20 /* interrupt control register */ 77226584Sdim#define VGE_RXSUPPTHR 0x20 78226584Sdim#define VGE_TXSUPPTHR 0x20 79226584Sdim#define VGE_INTHOLDOFF 0x20 80226584Sdim#define VGE_INTCTL1 0x21 /* interrupt control register */ 81226584Sdim#define VGE_TXHOSTERR 0x22 /* TX host error status */ 82226584Sdim#define VGE_RXHOSTERR 0x23 /* RX host error status */ 83226584Sdim#define VGE_ISR 0x24 /* Interrupt status register */ 84226584Sdim#define VGE_IMR 0x28 /* Interrupt mask register */ 85226584Sdim#define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */ 86226584Sdim#define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */ 87226584Sdim#define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */ 88226584Sdim#define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */ 89226584Sdim#define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */ 90226584Sdim#define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */ 91226584Sdim#define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */ 92226584Sdim#define VGE_RXQTIMER 0x3E /* RX queue timer pend register */ 93226584Sdim#define VGE_TXQTIMER 0x3F /* TX queue timer pend register */ 94226584Sdim#define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */ 95226584Sdim#define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */ 96226584Sdim#define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */ 97226584Sdim#define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */ 98226584Sdim#define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */ 99226584Sdim#define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */ 100226584Sdim#define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */ 101226584Sdim#define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */ 102226584Sdim#define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */ 103226584Sdim#define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */ 104226584Sdim#define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */ 105226584Sdim#define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */ 106226584Sdim#define VGE_FIFOTEST0 0x60 /* FIFO test register */ 107226584Sdim#define VGE_FIFOTEST1 0x64 /* FIFO test register */ 108226584Sdim#define VGE_CAMADDR 0x68 /* CAM address register */ 109226584Sdim#define VGE_CAMCTL 0x69 /* CAM control register */ 110226584Sdim#define VGE_GFTEST 0x6A 111226584Sdim#define VGE_FTSCMD 0x6B 112226584Sdim#define VGE_MIICFG 0x6C /* MII port config register */ 113226584Sdim#define VGE_MIISTS 0x6D /* MII port status register */ 114226584Sdim#define VGE_PHYSTS0 0x6E /* PHY status register */ 115226584Sdim#define VGE_PHYSTS1 0x6F /* PHY status register */ 116226584Sdim#define VGE_MIICMD 0x70 /* MII command register */ 117226584Sdim#define VGE_MIIADDR 0x71 /* MII address register */ 118226584Sdim#define VGE_MIIDATA 0x72 /* MII data register */ 119226584Sdim#define VGE_SSTIMER 0x74 /* single-shot timer */ 120226584Sdim#define VGE_PTIMER 0x76 /* periodic timer */ 121226584Sdim#define VGE_CHIPCFG0 0x78 /* chip config A */ 122226584Sdim#define VGE_CHIPCFG1 0x79 /* chip config B */ 123226584Sdim#define VGE_CHIPCFG2 0x7A /* chip config C */ 124226584Sdim#define VGE_CHIPCFG3 0x7B /* chip config D */ 125226584Sdim#define VGE_DMACFG0 0x7C /* DMA config 0 */ 126226584Sdim#define VGE_DMACFG1 0x7D /* DMA config 1 */ 127226584Sdim#define VGE_RXCFG 0x7E /* MAC RX config */ 128226584Sdim#define VGE_TXCFG 0x7F /* MAC TX config */ 129226584Sdim#define VGE_PWRMGMT 0x82 /* power management shadow register */ 130226584Sdim#define VGE_PWRSTAT 0x83 /* power state shadow register */ 131226584Sdim#define VGE_MIBCSR 0x84 /* MIB control/status register */ 132226584Sdim#define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */ 133226584Sdim#define VGE_MIBDATA 0x88 /* MIB data register */ 134226584Sdim#define VGE_EEWRDAT 0x8C /* EEPROM embedded write */ 135226584Sdim#define VGE_EECSUM 0x92 /* EEPROM checksum */ 136226584Sdim#define VGE_EECSR 0x93 /* EEPROM control/status */ 137226584Sdim#define VGE_EERDDAT 0x94 /* EEPROM embedded read */ 138226584Sdim#define VGE_EEADDR 0x96 /* EEPROM address */ 139226584Sdim#define VGE_EECMD 0x97 /* EEPROM embedded command */ 140226584Sdim#define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */ 141226584Sdim#define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */ 142226584Sdim#define VGE_DIAGSTS 0x9C /* Chip diagnostic status */ 143226584Sdim#define VGE_DBGCTL 0x9E /* Chip debug control */ 144226584Sdim#define VGE_DIAGCTL 0x9F /* Chip diagnostic control */ 145226584Sdim#define VGE_WOLCR0S 0xA0 /* WOL0 event set */ 146226584Sdim#define VGE_WOLCR1S 0xA1 /* WOL1 event set */ 147226584Sdim#define VGE_PWRCFGS 0xA2 /* Power management config set */ 148226584Sdim#define VGE_WOLCFGS 0xA3 /* WOL config set */ 149226584Sdim#define VGE_WOLCR0C 0xA4 /* WOL0 event clear */ 150226584Sdim#define VGE_WOLCR1C 0xA5 /* WOL1 event clear */ 151226584Sdim#define VGE_PWRCFGC 0xA6 /* Power management config clear */ 152226584Sdim#define VGE_WOLCFGC 0xA7 /* WOL config clear */ 153226584Sdim#define VGE_WOLSR0S 0xA8 /* WOL status set */ 154226584Sdim#define VGE_WOLSR1S 0xA9 /* WOL status set */ 155226584Sdim#define VGE_WOLSR0C 0xAC /* WOL status clear */ 156226584Sdim#define VGE_WOLSR1C 0xAD /* WOL status clear */ 157226584Sdim#define VGE_WAKEPAT_CRC0 0xB0 158226584Sdim#define VGE_WAKEPAT_CRC1 0xB2 159226584Sdim#define VGE_WAKEPAT_CRC2 0xB4 160226584Sdim#define VGE_WAKEPAT_CRC3 0xB6 161226584Sdim#define VGE_WAKEPAT_CRC4 0xB8 162226584Sdim#define VGE_WAKEPAT_CRC5 0xBA 163226584Sdim#define VGE_WAKEPAT_CRC6 0xBC 164226584Sdim#define VGE_WAKEPAT_CRC7 0xBE 165226584Sdim#define VGE_WAKEPAT_MSK0_0 0xC0 166226584Sdim#define VGE_WAKEPAT_MSK0_1 0xC4 167226584Sdim#define VGE_WAKEPAT_MSK0_2 0xC8 168226584Sdim#define VGE_WAKEPAT_MSK0_3 0xCC 169226584Sdim#define VGE_WAKEPAT_MSK1_0 0xD0 170226584Sdim#define VGE_WAKEPAT_MSK1_1 0xD4 171226584Sdim#define VGE_WAKEPAT_MSK1_2 0xD8 172226584Sdim#define VGE_WAKEPAT_MSK1_3 0xDC 173226584Sdim#define VGE_WAKEPAT_MSK2_0 0xE0 174226584Sdim#define VGE_WAKEPAT_MSK2_1 0xE4 175226584Sdim#define VGE_WAKEPAT_MSK2_2 0xE8 176226584Sdim#define VGE_WAKEPAT_MSK2_3 0xEC 177226584Sdim#define VGE_WAKEPAT_MSK3_0 0xF0 178226584Sdim#define VGE_WAKEPAT_MSK3_1 0xF4 179226584Sdim#define VGE_WAKEPAT_MSK3_2 0xF8 180226584Sdim#define VGE_WAKEPAT_MSK3_3 0xFC 181226584Sdim 182226584Sdim/* Receive control register */ 183226584Sdim 184226584Sdim#define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */ 185226584Sdim#define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */ 186226584Sdim#define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */ 187226584Sdim#define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */ 188226584Sdim#define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */ 189226584Sdim#define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */ 190226584Sdim#define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */ 191226584Sdim#define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */ 192226584Sdim 193226584Sdim/* Transmit control register */ 194226584Sdim 195226584Sdim#define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */ 196226584Sdim#define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */ 197226584Sdim 198226584Sdim#define VGE_TXLOOPCTL_OFF 0x00 199226584Sdim#define VGE_TXLOOPCTL_MAC_INTERNAL 0x01 200226584Sdim#define VGE_TXLOOPCTL_EXTERNAL 0x02 201226584Sdim 202226584Sdim#define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */ 203226584Sdim#define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */ 204226584Sdim#define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */ 205226584Sdim#define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */ 206226584Sdim 207226584Sdim/* Global command register 0 */ 208226584Sdim 209226584Sdim#define VGE_CR0_START 0x01 /* start NIC */ 210226584Sdim#define VGE_CR0_STOP 0x02 /* stop NIC */ 211226584Sdim#define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */ 212226584Sdim#define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */ 213226584Sdim 214226584Sdim/* Global command register 1 */ 215226584Sdim 216226584Sdim#define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */ 217226584Sdim#define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */ 218226584Sdim#define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */ 219226584Sdim#define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */ 220226584Sdim#define VGE_CR1_SOFTRESET 0x80 /* software reset */ 221226584Sdim 222226584Sdim/* Global command register 2 */ 223226584Sdim 224226584Sdim#define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */ 225226584Sdim#define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */ 226226584Sdim#define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */ 227226584Sdim#define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */ 228226584Sdim#define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */ 229226584Sdim#define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */ 230226584Sdim 231226584Sdim/* Global command register 3 */ 232226584Sdim 233226584Sdim#define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */ 234226584Sdim#define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */ 235226584Sdim#define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */ 236226584Sdim#define VGE_CR3_DIAG 0x10 /* diagnostic enabled */ 237226584Sdim#define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */ 238226584Sdim#define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */ 239226584Sdim 240226584Sdim/* Interrupt control register */ 241226584Sdim 242226584Sdim#define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */ 243226584Sdim#define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */ 244226584Sdim#define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */ 245226584Sdim#define VGE_INTCTL_MASK 0x18 /* multilayer int mask */ 246226584Sdim#define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */ 247226584Sdim#define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */ 248226584Sdim#define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */ 249226584Sdim 250226584Sdim#define VGE_INTMASK_LAYER0 0x00 251226584Sdim#define VGE_INTMASK_LAYER1 0x08 252226584Sdim#define VGE_INTMASK_ALL 0x10 253226584Sdim#define VGE_INTMASK_ALL2 0x18 254226584Sdim 255226584Sdim/* Transmit host error status register */ 256226584Sdim 257226584Sdim#define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */ 258226584Sdim#define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */ 259226584Sdim#define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */ 260226584Sdim#define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */ 261226584Sdim 262226584Sdim/* Receive host error status register */ 263226584Sdim 264226584Sdim#define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */ 265226584Sdim#define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */ 266226584Sdim#define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */ 267226584Sdim#define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */ 268226584Sdim 269226584Sdim/* Interrupt status register */ 270226584Sdim 271226584Sdim#define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ 272226584Sdim#define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ 273226584Sdim#define VGE_ISR_RXOK 0x00000004 /* normal RX done */ 274226584Sdim#define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */ 275226584Sdim#define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */ 276226584Sdim#define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */ 277226584Sdim#define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */ 278226584Sdim#define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */ 279226584Sdim#define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ 280226584Sdim#define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */ 281226584Sdim#define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */ 282226584Sdim#define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */ 283226584Sdim#define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ 284226584Sdim#define VGE_ISR_LINKSTS 0x00008000 /* link status change */ 285226584Sdim#define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */ 286226584Sdim#define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */ 287226584Sdim#define VGE_ISR_PWR 0x00040000 /* wake up power event */ 288226584Sdim#define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */ 289226584Sdim#define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */ 290226584Sdim#define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ 291226584Sdim#define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */ 292226584Sdim#define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ 293226584Sdim#define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */ 294226584Sdim#define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ 295226584Sdim#define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */ 296226584Sdim#define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */ 297226584Sdim#define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */ 298226584Sdim#define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */ 299226584Sdim 300226584Sdim#define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \ 301226584Sdim VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \ 302226584Sdim VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \ 303226584Sdim VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL) 304226584Sdim 305226584Sdim/* Interrupt mask register */ 306226584Sdim 307226584Sdim#define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ 308226584Sdim#define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ 309226584Sdim#define VGE_IMR_RXOK 0x00000004 /* normal RX done */ 310226584Sdim#define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */ 311226584Sdim#define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */ 312226584Sdim#define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */ 313226584Sdim#define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */ 314226584Sdim#define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */ 315226584Sdim#define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ 316226584Sdim#define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */ 317226584Sdim#define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */ 318226584Sdim#define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */ 319226584Sdim#define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ 320226584Sdim#define VGE_IMR_LINKSTS 0x00008000 /* link status change */ 321226584Sdim#define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */ 322226584Sdim#define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */ 323226584Sdim#define VGE_IMR_PWR 0x00040000 /* wake up power event */ 324226584Sdim#define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */ 325226584Sdim#define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */ 326226584Sdim#define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ 327226584Sdim#define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */ 328226584Sdim#define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ 329226584Sdim#define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */ 330226584Sdim#define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ 331226584Sdim#define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */ 332226584Sdim#define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */ 333226584Sdim#define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */ 334226584Sdim#define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */ 335226584Sdim 336226584Sdim/* TX descriptor queue control/status register */ 337226584Sdim 338226584Sdim#define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */ 339226584Sdim#define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */ 340226584Sdim#define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */ 341226584Sdim#define VGE_TXQCSR_DEAD0 0x0008 /* queue 0 dead indicator */ 342226584Sdim#define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */ 343226584Sdim#define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */ 344226584Sdim#define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */ 345226584Sdim#define VGE_TXQCSR_DEAD1 0x0080 /* queue 1 dead indicator */ 346226584Sdim#define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */ 347226584Sdim#define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */ 348226584Sdim#define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */ 349226584Sdim#define VGE_TXQCSR_DEAD2 0x0800 /* queue 2 dead indicator */ 350226584Sdim#define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */ 351226584Sdim#define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */ 352226584Sdim#define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */ 353226584Sdim#define VGE_TXQCSR_DEAD3 0x8000 /* queue 3 dead indicator */ 354226584Sdim 355226584Sdim/* RX descriptor queue control/status register */ 356226584Sdim 357226584Sdim#define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */ 358226584Sdim#define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */ 359226584Sdim#define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */ 360226584Sdim#define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */ 361226584Sdim 362226584Sdim/* RX/TX queue empty interrupt delay timer register */ 363226584Sdim 364226584Sdim#define VGE_QTIMER_PENDCNT 0x3F 365226584Sdim#define VGE_QTIMER_RESOLUTION 0xC0 366226584Sdim 367226584Sdim#define VGE_QTIMER_RES_1US 0x00 368226584Sdim#define VGE_QTIMER_RES_4US 0x40 369226584Sdim#define VGE_QTIMER_RES_16US 0x80 370226584Sdim#define VGE_QTIMER_RES_64US 0xC0 371226584Sdim 372226584Sdim/* CAM address register */ 373226584Sdim 374226584Sdim#define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */ 375226584Sdim#define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */ 376226584Sdim#define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */ 377226584Sdim 378226584Sdim#define VGE_CAM_MAXADDRS 64 379226584Sdim 380226584Sdim/* 381226584Sdim * CAM command register 382226584Sdim * Note that the page select bits in this register affect three 383226584Sdim * different things: 384226584Sdim * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the 385226584Sdim * page select bits control whether the MAR0/MAR1 registers affect 386226584Sdim * the multicast hash filter or the CAM table) 387226584Sdim * - The behavior of the interrupt holdoff timer register at offset 388226584Sdim * 0x20 (the page select bits allow you to set the interrupt 389226584Sdim * holdoff timer, the TX interrupt supression count or the 390226584Sdim * RX interrupt supression count) 391226584Sdim * - The behavior the WOL pattern programming registers at offset 392226584Sdim * 0xC0 (controls which pattern is set) 393226584Sdim */ 394226584Sdim 395226584Sdim 396226584Sdim#define VGE_CAMCTL_WRITE 0x04 /* CAM write command */ 397226584Sdim#define VGE_CAMCTL_READ 0x08 /* CAM read command */ 398226584Sdim#define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */ 399226584Sdim#define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */ 400226584Sdim#define VGE_CAMCTL_PAGESEL 0xC0 /* page select */ 401226584Sdim 402226584Sdim#define VGE_PAGESEL_MAR 0x00 403226584Sdim#define VGE_PAGESEL_CAMMASK 0x40 404226584Sdim#define VGE_PAGESEL_CAMDATA 0x80 405226584Sdim 406226584Sdim#define VGE_PAGESEL_INTHLDOFF 0x00 407226584Sdim#define VGE_PAGESEL_TXSUPPTHR 0x40 408226584Sdim#define VGE_PAGESEL_RXSUPPTHR 0x80 409226584Sdim 410226584Sdim#define VGE_PAGESEL_WOLPAT0 0x00 411226584Sdim#define VGE_PAGESEL_WOLPAT1 0x40 412226584Sdim 413226584Sdim/* MII port config register */ 414226584Sdim 415226584Sdim#define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */ 416226584Sdim#define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */ 417226584Sdim#define VGE_MIICFG_POLLINT 0xC0 /* polling interval */ 418226584Sdim 419226584Sdim#define VGE_MIIPOLLINT_1024 0x00 420226584Sdim#define VGE_MIIPOLLINT_512 0x40 421226584Sdim#define VGE_MIIPOLLINT_128 0x80 422226584Sdim#define VGE_MIIPOLLINT_64 0xC0 423226584Sdim 424226584Sdim/* MII port status register */ 425226584Sdim 426226584Sdim#define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */ 427226584Sdim 428226584Sdim/* PHY status register */ 429226584Sdim 430226584Sdim#define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */ 431226584Sdim#define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */ 432226584Sdim#define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */ 433226584Sdim#define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */ 434226584Sdim#define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */ 435226584Sdim#define VGE_PHYSTS_LINK 0x40 /* link status */ 436226584Sdim#define VGE_PHYSTS_RESETSTS 0x80 /* reset status */ 437226584Sdim 438226584Sdim/* MII management command register */ 439226584Sdim 440226584Sdim#define VGE_MIICMD_MDC 0x01 /* clock pin */ 441226584Sdim#define VGE_MIICMD_MDI 0x02 /* data in pin */ 442226584Sdim#define VGE_MIICMD_MDO 0x04 /* data out pin */ 443226584Sdim#define VGE_MIICMD_MOUT 0x08 /* data out pin enable */ 444226584Sdim#define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */ 445226584Sdim#define VGE_MIICMD_WCMD 0x20 /* embedded mode write */ 446226584Sdim#define VGE_MIICMD_RCMD 0x40 /* embadded mode read */ 447226584Sdim#define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */ 448226584Sdim 449226584Sdim/* MII address register */ 450226584Sdim 451226584Sdim#define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */ 452226584Sdim 453226584Sdim/* Chip config register A */ 454226584Sdim 455226584Sdim#define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */ 456226584Sdim#define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */ 457226584Sdim#define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */ 458226584Sdim#define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */ 459226584Sdim#define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */ 460226584Sdim 461226584Sdim/* Chip config register B */ 462226584Sdim/* Note: some of these bits are not documented in the manual! */ 463226584Sdim 464226584Sdim#define VGE_CHIPCFG1_BAKOPT 0x01 465226584Sdim#define VGE_CHIPCFG1_MBA 0x02 466226584Sdim#define VGE_CHIPCFG1_CAP 0x04 467226584Sdim#define VGE_CHIPCFG1_CRANDOM 0x08 468226584Sdim#define VGE_CHIPCFG1_OFSET 0x10 469226584Sdim#define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */ 470226584Sdim#define VGE_CHIPCFG1_MIIOPT 0x40 471226584Sdim#define VGE_CHIPCFG1_GTCKOPT 0x80 472226584Sdim 473226584Sdim/* Chip config register C */ 474226584Sdim 475226584Sdim#define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */ 476226584Sdim 477226584Sdim/* Chip config register D */ 478226584Sdim 479226584Sdim#define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */ 480226584Sdim#define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */ 481226584Sdim 482226584Sdim/* DMA config register 0 */ 483226584Sdim 484226584Sdim#define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */ 485226584Sdim 486226584Sdim#define VGE_DMABURST_8 0x00 487226584Sdim#define VGE_DMABURST_16 0x01 488226584Sdim#define VGE_DMABURST_32 0x02 489226584Sdim#define VGE_DMABURST_64 0x03 490226584Sdim#define VGE_DMABURST_128 0x04 491226584Sdim#define VGE_DMABURST_256 0x05 492226584Sdim#define VGE_DMABURST_STRFWD 0x07 493226584Sdim 494226584Sdim/* DMA config register 1 */ 495226584Sdim 496226584Sdim#define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */ 497226584Sdim#define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */ 498226584Sdim#define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */ 499226584Sdim#define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */ 500226584Sdim#define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */ 501226584Sdim#define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */ 502226584Sdim 503226584Sdim/* RX MAC config register */ 504226584Sdim 505226584Sdim#define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */ 506226584Sdim#define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */ 507226584Sdim#define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */ 508226584Sdim#define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */ 509226584Sdim#define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */ 510226584Sdim 511226584Sdim#define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion 512226584Sdim RX: rx all, no tag extraction */ 513226584Sdim 514226584Sdim#define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion 515226584Sdim RX: rx only tagged pkts, no 516226584Sdim extraction */ 517226584Sdim 518226584Sdim#define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion, 519226584Sdim RX: rx all, extract tags */ 520226584Sdim 521226584Sdim#define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion, 522226584Sdim RX: rx only tagged pkts, 523226584Sdim with extraction */ 524226584Sdim 525226584Sdim#define VGE_RXFIFOTHR_128BYTES 0x00 526226584Sdim#define VGE_RXFIFOTHR_512BYTES 0x10 527226584Sdim#define VGE_RXFIFOTHR_1024BYTES 0x20 528226584Sdim#define VGE_RXFIFOTHR_STRNFWD 0x30 529226584Sdim 530226584Sdim/* TX MAC config register */ 531226584Sdim 532226584Sdim#define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at 533226584Sdim 13th byte 534226584Sdim 0 == insert VLANM tag after 535226584Sdim SNAP header (21st byte) */ 536226584Sdim#define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */ 537226584Sdim#define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */ 538226584Sdim#define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */ 539226584Sdim 540226584Sdim#define VGE_TXBLOCK_64PKTS 0x00 541226584Sdim#define VGE_TXBLOCK_32PKTS 0x04 542226584Sdim#define VGE_TXBLOCK_128PKTS 0x08 543226584Sdim#define VGE_TXBLOCK_8PKTS 0x0C 544226584Sdim 545226584Sdim/* MIB control/status register */ 546226584Sdim#define VGE_MIBCSR_CLR 0x01 547226584Sdim#define VGE_MIBCSR_RINI 0x02 548226584Sdim#define VGE_MIBCSR_FLUSH 0x04 549226584Sdim#define VGE_MIBCSR_FREEZE 0x08 550226584Sdim#define VGE_MIBCSR_HI_80 0x00 551226584Sdim#define VGE_MIBCSR_HI_C0 0x10 552226584Sdim#define VGE_MIBCSR_BISTGO 0x40 553226584Sdim#define VGE_MIBCSR_BISTOK 0x80 554226584Sdim 555226584Sdim/* MIB data index. */ 556226584Sdim#define VGE_MIB_RX_FRAMES 0 557226584Sdim#define VGE_MIB_RX_GOOD_FRAMES 1 558226584Sdim#define VGE_MIB_TX_GOOD_FRAMES 2 559226584Sdim#define VGE_MIB_RX_FIFO_OVERRUNS 3 560226584Sdim#define VGE_MIB_RX_RUNTS 4 561226584Sdim#define VGE_MIB_RX_RUNTS_ERRS 5 562226584Sdim#define VGE_MIB_RX_PKTS_64 6 563226584Sdim#define VGE_MIB_TX_PKTS_64 7 564226584Sdim#define VGE_MIB_RX_PKTS_65_127 8 565226584Sdim#define VGE_MIB_TX_PKTS_65_127 9 566226584Sdim#define VGE_MIB_RX_PKTS_128_255 10 567226584Sdim#define VGE_MIB_TX_PKTS_128_255 11 568226584Sdim#define VGE_MIB_RX_PKTS_256_511 12 569226584Sdim#define VGE_MIB_TX_PKTS_256_511 13 570226584Sdim#define VGE_MIB_RX_PKTS_512_1023 14 571226584Sdim#define VGE_MIB_TX_PKTS_512_1023 15 572226584Sdim#define VGE_MIB_RX_PKTS_1024_1518 16 573226584Sdim#define VGE_MIB_TX_PKTS_1024_1518 17 574226584Sdim#define VGE_MIB_TX_COLLS 18 575226584Sdim#define VGE_MIB_RX_CRCERRS 19 576226584Sdim#define VGE_MIB_RX_JUMBOS 20 577226584Sdim#define VGE_MIB_TX_JUMBOS 21 578226584Sdim#define VGE_MIB_RX_PAUSE 22 579226584Sdim#define VGE_MIB_TX_PAUSE 23 580226584Sdim#define VGE_MIB_RX_ALIGNERRS 24 581226584Sdim#define VGE_MIB_RX_PKTS_1519_MAX 25 582226584Sdim#define VGE_MIB_RX_PKTS_1519_MAX_ERRS 26 583226584Sdim#define VGE_MIB_TX_SQEERRS 27 584226584Sdim#define VGE_MIB_RX_NOBUFS 28 585226584Sdim#define VGE_MIB_RX_SYMERRS 29 586226584Sdim#define VGE_MIB_RX_LENERRS 30 587226584Sdim#define VGE_MIB_TX_LATECOLLS 31 588226584Sdim 589226584Sdim#define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1) 590226584Sdim#define VGE_MIB_DATA_MASK 0x00FFFFFF 591226584Sdim#define VGE_MIB_DATA_IDX(x) ((x) >> 24) 592226584Sdim 593226584Sdim/* Sticky bit shadow register */ 594226584Sdim 595226584Sdim#define VGE_STICKHW_DS0 0x01 596226584Sdim#define VGE_STICKHW_DS1 0x02 597226584Sdim#define VGE_STICKHW_WOL_ENB 0x04 598226584Sdim#define VGE_STICKHW_WOL_STS 0x08 599226584Sdim#define VGE_STICKHW_SWPTAG 0x10 600226584Sdim 601226584Sdim/* WOL pattern control */ 602226584Sdim#define VGE_WOLCR0_PATTERN0 0x01 603226584Sdim#define VGE_WOLCR0_PATTERN1 0x02 604226584Sdim#define VGE_WOLCR0_PATTERN2 0x04 605226584Sdim#define VGE_WOLCR0_PATTERN3 0x08 606226584Sdim#define VGE_WOLCR0_PATTERN4 0x10 607226584Sdim#define VGE_WOLCR0_PATTERN5 0x20 608226584Sdim#define VGE_WOLCR0_PATTERN6 0x40 609226584Sdim#define VGE_WOLCR0_PATTERN7 0x80 610226584Sdim#define VGE_WOLCR0_PATTERN_ALL 0xFF 611226584Sdim 612226584Sdim/* WOL event control */ 613226584Sdim#define VGE_WOLCR1_UCAST 0x01 614226584Sdim#define VGE_WOLCR1_MAGIC 0x02 615226584Sdim#define VGE_WOLCR1_LINKON 0x04 616226584Sdim#define VGE_WOLCR1_LINKOFF 0x08 617226584Sdim 618226584Sdim/* Poweer management config */ 619226584Sdim#define VGE_PWRCFG_LEGACY_WOLEN 0x01 620226584Sdim#define VGE_PWRCFG_WOL_PULSE 0x20 621226584Sdim#define VGE_PWRCFG_WOL_BUTTON 0x00 622226584Sdim 623226584Sdim/* WOL config register */ 624226584Sdim#define VGE_WOLCFG_PHYINT_ENB 0x01 625226584Sdim#define VGE_WOLCFG_SAB 0x10 626226584Sdim#define VGE_WOLCFG_SAM 0x20 627226584Sdim#define VGE_WOLCFG_PMEOVR 0x80 628226584Sdim 629226584Sdim/* EEPROM control/status register */ 630226584Sdim 631226584Sdim#define VGE_EECSR_EDO 0x01 /* data out pin */ 632226584Sdim#define VGE_EECSR_EDI 0x02 /* data in pin */ 633226584Sdim#define VGE_EECSR_ECK 0x04 /* clock pin */ 634226584Sdim#define VGE_EECSR_ECS 0x08 /* chip select pin */ 635226584Sdim#define VGE_EECSR_DPM 0x10 /* direct program mode enable */ 636226584Sdim#define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */ 637226584Sdim#define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */ 638226584Sdim 639226584Sdim/* EEPROM embedded command register */ 640226584Sdim 641226584Sdim#define VGE_EECMD_ERD 0x01 /* EEPROM read command */ 642226584Sdim#define VGE_EECMD_EWR 0x02 /* EEPROM write command */ 643226584Sdim#define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */ 644226584Sdim#define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */ 645226584Sdim#define VGE_EECMD_EDONE 0x80 /* read/write done */ 646226584Sdim 647226584Sdim/* Chip operation and diagnostic control register */ 648226584Sdim 649226584Sdim#define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */ 650226584Sdim#define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */ 651226584Sdim#define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */ 652226584Sdim#define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */ 653226584Sdim#define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */ 654226584Sdim#define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */ 655226584Sdim#define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */ 656226584Sdim#define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */ 657226584Sdim 658226584Sdim/* Location of station address in EEPROM */ 659226584Sdim#define VGE_EE_EADDR 0 660226584Sdim 661226584Sdim/* DMA descriptor structures */ 662226584Sdim 663226584Sdim/* 664226584Sdim * Each TX DMA descriptor has a control and status word, and 7 665226584Sdim * fragment address/length words. If a transmitted packet spans 666226584Sdim * more than 7 fragments, it has to be coalesced. 667226584Sdim */ 668226584Sdim 669226584Sdim#define VGE_TX_FRAGS 7 670226584Sdim 671226584Sdimstruct vge_tx_frag { 672226584Sdim uint32_t vge_addrlo; 673226584Sdim uint32_t vge_addrhi; 674226584Sdim}; 675226584Sdim 676226584Sdim/* 677226584Sdim * The high bit in the buflen field of fragment #0 has special meaning. 678226584Sdim * Normally, the chip requires the driver to issue a TX poll command 679226584Sdim * for every packet that gets put in the TX DMA queue. Sometimes though, 680226584Sdim * the driver might want to queue up several packets at once and just 681226584Sdim * issue one transmit command to have all of them processed. In order 682226584Sdim * to obtain this behavior, the special 'queue' bit must be set. 683226584Sdim */ 684226584Sdim 685226584Sdim#define VGE_TXDESC_Q 0x80000000 686226584Sdim 687226584Sdimstruct vge_tx_desc { 688226584Sdim uint32_t vge_sts; 689226584Sdim uint32_t vge_ctl; 690226584Sdim struct vge_tx_frag vge_frag[VGE_TX_FRAGS]; 691226584Sdim}; 692226584Sdim 693226584Sdim#define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */ 694226584Sdim#define VGE_TDSTS_COLL 0x00000010 /* collision seen */ 695226584Sdim#define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */ 696226584Sdim#define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */ 697226584Sdim#define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */ 698226584Sdim#define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */ 699226584Sdim#define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */ 700226584Sdim#define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */ 701226584Sdim#define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */ 702226584Sdim#define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */ 703226584Sdim#define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */ 704226584Sdim#define VGE_TDSTS_TXERR 0x00008000 /* error occurred */ 705226584Sdim#define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */ 706226584Sdim#define VGE_TDSTS_OWN 0x80000000 /* own bit */ 707226584Sdim 708226584Sdim#define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */ 709226584Sdim#define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */ 710226584Sdim#define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */ 711226584Sdim#define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */ 712226584Sdim#define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */ 713226584Sdim#define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */ 714226584Sdim#define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */ 715226584Sdim#define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */ 716226584Sdim#define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */ 717226584Sdim#define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */ 718226584Sdim#define VGE_TDCTL_TIC 0x00800000 /* transfer int request */ 719226584Sdim#define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */ 720226584Sdim#define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */ 721226584Sdim 722226584Sdim#define VGE_TD_LS_MOF 0x00000000 /* middle of large send */ 723226584Sdim#define VGE_TD_LS_SOF 0x01000000 /* start of large send */ 724226584Sdim#define VGE_TD_LS_EOF 0x02000000 /* end of large send */ 725226584Sdim#define VGE_TD_LS_NORM 0x03000000 /* normal frame */ 726226584Sdim 727226584Sdim/* Receive DMA descriptors have a single fragment pointer. */ 728226584Sdim 729226584Sdimstruct vge_rx_desc { 730226584Sdim uint32_t vge_sts; 731226584Sdim uint32_t vge_ctl; 732226584Sdim uint32_t vge_addrlo; 733226584Sdim uint32_t vge_addrhi; 734226584Sdim}; 735226584Sdim 736226584Sdim/* 737226584Sdim * Like the TX descriptor, the high bit in the buflen field in the 738226584Sdim * RX descriptor has special meaning. This bit controls whether or 739226584Sdim * not interrupts are generated for this descriptor. 740226584Sdim */ 741226584Sdim 742226584Sdim#define VGE_RXDESC_I 0x80000000 743226584Sdim 744226584Sdim#define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */ 745226584Sdim#define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */ 746226584Sdim#define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */ 747226584Sdim#define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */ 748226584Sdim#define VGE_RDSTS_RLERR 0x00000010 /* RX length error */ 749226584Sdim#define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */ 750226584Sdim#define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */ 751226584Sdim#define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */ 752226584Sdim#define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */ 753226584Sdim#define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */ 754226584Sdim#define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */ 755226584Sdim#define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */ 756226584Sdim#define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */ 757226584Sdim#define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */ 758226584Sdim#define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */ 759226584Sdim#define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */ 760226584Sdim#define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */ 761226584Sdim#define VGE_RDSTS_OWN 0x80000000 /* own bit. */ 762226584Sdim 763226584Sdim#define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */ 764226584Sdim#define VGE_RXPKT_EOF 0x00000100 /* first frag in frame */ 765226584Sdim#define VGE_RXPKT_SOF 0x00000200 /* last frag in frame */ 766226584Sdim#define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */ 767226584Sdim 768226584Sdim#define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */ 769226584Sdim#define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */ 770226584Sdim#define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */ 771226584Sdim#define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */ 772226584Sdim#define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */ 773226584Sdim#define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */ 774226584Sdim#define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */ 775226584Sdim#define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */ 776226584Sdim#define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */ 777226584Sdim 778226584Sdim#endif /* _IF_VGEREG_H_ */ 779226584Sdim