if_uralreg.h revision 188417
1184610Salfred/* $FreeBSD: head/sys/dev/usb2/wlan/if_uralreg.h 188417 2009-02-09 22:12:47Z thompsa $ */ 2184610Salfred 3184610Salfred/*- 4184610Salfred * Copyright (c) 2005, 2006 5184610Salfred * Damien Bergamini <damien.bergamini@free.fr> 6184610Salfred * 7184610Salfred * Permission to use, copy, modify, and distribute this software for any 8184610Salfred * purpose with or without fee is hereby granted, provided that the above 9184610Salfred * copyright notice and this permission notice appear in all copies. 10184610Salfred * 11184610Salfred * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12184610Salfred * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13184610Salfred * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14184610Salfred * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15184610Salfred * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16184610Salfred * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17184610Salfred * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18184610Salfred */ 19184610Salfred 20188417Sthompsa#define RAL_NOISE_FLOOR -95 21188417Sthompsa#define RAL_RSSI_CORR 120 22184610Salfred 23188417Sthompsa#define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) 24188417Sthompsa#define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) 25188417Sthompsa#define RAL_FRAME_SIZE 0x780 /* NOTE: using 0x980 does not work */ 26184610Salfred 27188417Sthompsa#define RAL_CONFIG_NO 1 28188417Sthompsa#define RAL_IFACE_INDEX 0 29184610Salfred 30188417Sthompsa#define RAL_VENDOR_REQUEST 0x01 31188417Sthompsa#define RAL_WRITE_MAC 0x02 32188417Sthompsa#define RAL_READ_MAC 0x03 33188417Sthompsa#define RAL_WRITE_MULTI_MAC 0x06 34188417Sthompsa#define RAL_READ_MULTI_MAC 0x07 35188417Sthompsa#define RAL_READ_EEPROM 0x09 36184610Salfred 37188417Sthompsa/* 38188417Sthompsa * MAC registers. 39188417Sthompsa */ 40188417Sthompsa#define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 41188417Sthompsa#define RAL_MAC_CSR1 0x0402 /* System control */ 42188417Sthompsa#define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 43188417Sthompsa#define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 44188417Sthompsa#define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 45188417Sthompsa#define RAL_MAC_CSR5 0x040a /* BSSID0 */ 46188417Sthompsa#define RAL_MAC_CSR6 0x040c /* BSSID1 */ 47188417Sthompsa#define RAL_MAC_CSR7 0x040e /* BSSID2 */ 48188417Sthompsa#define RAL_MAC_CSR8 0x0410 /* Max frame length */ 49188417Sthompsa#define RAL_MAC_CSR9 0x0412 /* Timer control */ 50188417Sthompsa#define RAL_MAC_CSR10 0x0414 /* Slot time */ 51188417Sthompsa#define RAL_MAC_CSR11 0x0416 /* IFS */ 52188417Sthompsa#define RAL_MAC_CSR12 0x0418 /* EIFS */ 53188417Sthompsa#define RAL_MAC_CSR13 0x041a /* Power mode0 */ 54188417Sthompsa#define RAL_MAC_CSR14 0x041c /* Power mode1 */ 55188417Sthompsa#define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 56188417Sthompsa#define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 57188417Sthompsa#define RAL_MAC_CSR17 0x0422 /* Power state control */ 58188417Sthompsa#define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 59188417Sthompsa#define RAL_MAC_CSR19 0x0426 /* GPIO control */ 60188417Sthompsa#define RAL_MAC_CSR20 0x0428 /* LED control0 */ 61188417Sthompsa#define RAL_MAC_CSR22 0x042c /* XXX not documented */ 62184610Salfred 63188417Sthompsa/* 64188417Sthompsa * Tx/Rx Registers. 65188417Sthompsa */ 66188417Sthompsa#define RAL_TXRX_CSR0 0x0440 /* Security control */ 67188417Sthompsa#define RAL_TXRX_CSR2 0x0444 /* Rx control */ 68188417Sthompsa#define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 69188417Sthompsa#define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 70188417Sthompsa#define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 71188417Sthompsa#define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 72188417Sthompsa#define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 73188417Sthompsa#define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 74188417Sthompsa#define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 75188417Sthompsa#define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 76188417Sthompsa#define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 77188417Sthompsa#define RAL_TXRX_CSR21 0x046a /* XXX not documented */ 78184610Salfred 79188417Sthompsa/* 80188417Sthompsa * Security registers. 81188417Sthompsa */ 82188417Sthompsa#define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 83184610Salfred 84188417Sthompsa/* 85188417Sthompsa * PHY registers. 86188417Sthompsa */ 87188417Sthompsa#define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 88188417Sthompsa#define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 89188417Sthompsa#define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 90188417Sthompsa#define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 91188417Sthompsa#define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 92188417Sthompsa#define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 93188417Sthompsa#define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 94188417Sthompsa#define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 95184610Salfred 96188417Sthompsa/* 97188417Sthompsa * Statistics registers. 98188417Sthompsa */ 99188417Sthompsa#define RAL_STA_CSR0 0x04e0 /* FCS error */ 100184610Salfred 101184610Salfred 102188417Sthompsa#define RAL_DISABLE_RX (1 << 0) 103188417Sthompsa#define RAL_DROP_CRC (1 << 1) 104188417Sthompsa#define RAL_DROP_PHY (1 << 2) 105188417Sthompsa#define RAL_DROP_CTL (1 << 3) 106188417Sthompsa#define RAL_DROP_NOT_TO_ME (1 << 4) 107188417Sthompsa#define RAL_DROP_TODS (1 << 5) 108188417Sthompsa#define RAL_DROP_BAD_VERSION (1 << 6) 109188417Sthompsa#define RAL_DROP_MULTICAST (1 << 9) 110188417Sthompsa#define RAL_DROP_BROADCAST (1 << 10) 111184610Salfred 112188417Sthompsa#define RAL_SHORT_PREAMBLE (1 << 2) 113184610Salfred 114188417Sthompsa#define RAL_RESET_ASIC (1 << 0) 115188417Sthompsa#define RAL_RESET_BBP (1 << 1) 116188417Sthompsa#define RAL_HOST_READY (1 << 2) 117184610Salfred 118188417Sthompsa#define RAL_ENABLE_TSF (1 << 0) 119188417Sthompsa#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 120188417Sthompsa#define RAL_ENABLE_TBCN (1 << 3) 121188417Sthompsa#define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 122184610Salfred 123188417Sthompsa#define RAL_RF_AWAKE (3 << 7) 124188417Sthompsa#define RAL_BBP_AWAKE (3 << 5) 125184610Salfred 126188417Sthompsa#define RAL_BBP_WRITE (1 << 15) 127188417Sthompsa#define RAL_BBP_BUSY (1 << 0) 128184610Salfred 129188417Sthompsa#define RAL_RF1_AUTOTUNE 0x08000 130188417Sthompsa#define RAL_RF3_AUTOTUNE 0x00040 131188417Sthompsa 132188417Sthompsa#define RAL_RF_2522 0x00 133188417Sthompsa#define RAL_RF_2523 0x01 134188417Sthompsa#define RAL_RF_2524 0x02 135188417Sthompsa#define RAL_RF_2525 0x03 136188417Sthompsa#define RAL_RF_2525E 0x04 137188417Sthompsa#define RAL_RF_2526 0x05 138184610Salfred/* dual-band RF */ 139188417Sthompsa#define RAL_RF_5222 0x10 140184610Salfred 141188417Sthompsa#define RAL_BBP_VERSION 0 142188417Sthompsa#define RAL_BBP_TX 2 143188417Sthompsa#define RAL_BBP_RX 14 144184610Salfred 145188417Sthompsa#define RAL_BBP_ANTA 0x00 146188417Sthompsa#define RAL_BBP_DIVERSITY 0x01 147188417Sthompsa#define RAL_BBP_ANTB 0x02 148188417Sthompsa#define RAL_BBP_ANTMASK 0x03 149188417Sthompsa#define RAL_BBP_FLIPIQ 0x04 150184610Salfred 151188417Sthompsa#define RAL_JAPAN_FILTER 0x08 152184610Salfred 153188417Sthompsastruct ural_tx_desc { 154188417Sthompsa uint32_t flags; 155188417Sthompsa#define RAL_TX_RETRY(x) ((x) << 4) 156188417Sthompsa#define RAL_TX_MORE_FRAG (1 << 8) 157188417Sthompsa#define RAL_TX_ACK (1 << 9) 158188417Sthompsa#define RAL_TX_TIMESTAMP (1 << 10) 159188417Sthompsa#define RAL_TX_OFDM (1 << 11) 160188417Sthompsa#define RAL_TX_NEWSEQ (1 << 12) 161184610Salfred 162188417Sthompsa#define RAL_TX_IFS_MASK 0x00006000 163188417Sthompsa#define RAL_TX_IFS_BACKOFF (0 << 13) 164188417Sthompsa#define RAL_TX_IFS_SIFS (1 << 13) 165188417Sthompsa#define RAL_TX_IFS_NEWBACKOFF (2 << 13) 166188417Sthompsa#define RAL_TX_IFS_NONE (3 << 13) 167184610Salfred 168188417Sthompsa uint16_t wme; 169188417Sthompsa#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 170188417Sthompsa#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 171188417Sthompsa#define RAL_AIFSN(x) (((x) & 0x3) << 6) 172188417Sthompsa#define RAL_IVOFFSET(x) (((x) & 0x3f)) 173184610Salfred 174188417Sthompsa uint16_t reserved1; 175188417Sthompsa uint8_t plcp_signal; 176188417Sthompsa uint8_t plcp_service; 177188417Sthompsa#define RAL_PLCP_LENGEXT 0x80 178188417Sthompsa 179188417Sthompsa uint8_t plcp_length_lo; 180188417Sthompsa uint8_t plcp_length_hi; 181188417Sthompsa uint32_t iv; 182188417Sthompsa uint32_t eiv; 183184610Salfred} __packed; 184184610Salfred 185184610Salfredstruct ural_rx_desc { 186188417Sthompsa uint32_t flags; 187188417Sthompsa#define RAL_RX_CRC_ERROR (1 << 5) 188188417Sthompsa#define RAL_RX_OFDM (1 << 6) 189188417Sthompsa#define RAL_RX_PHY_ERROR (1 << 7) 190188417Sthompsa 191188417Sthompsa uint8_t rssi; 192188417Sthompsa uint8_t rate; 193188417Sthompsa uint16_t reserved; 194188417Sthompsa 195188417Sthompsa uint32_t iv; 196188417Sthompsa uint32_t eiv; 197184610Salfred} __packed; 198188417Sthompsa 199188417Sthompsa#define RAL_RF_LOBUSY (1 << 15) 200188417Sthompsa#define RAL_RF_BUSY (1 << 31) 201188417Sthompsa#define RAL_RF_20BIT (20 << 24) 202188417Sthompsa 203188417Sthompsa#define RAL_RF1 0 204188417Sthompsa#define RAL_RF2 2 205188417Sthompsa#define RAL_RF3 1 206188417Sthompsa#define RAL_RF4 3 207188417Sthompsa 208188417Sthompsa#define RAL_EEPROM_ADDRESS 0x0004 209188417Sthompsa#define RAL_EEPROM_TXPOWER 0x003c 210188417Sthompsa#define RAL_EEPROM_CONFIG0 0x0016 211188417Sthompsa#define RAL_EEPROM_BBP_BASE 0x001c 212