if_uralreg.h revision 184610
1184610Salfred/* $FreeBSD: head/sys/dev/usb2/wlan/if_ural2_reg.h 184610 2008-11-04 02:31:03Z alfred $ */ 2184610Salfred 3184610Salfred/*- 4184610Salfred * Copyright (c) 2005, 2006 5184610Salfred * Damien Bergamini <damien.bergamini@free.fr> 6184610Salfred * 7184610Salfred * Permission to use, copy, modify, and distribute this software for any 8184610Salfred * purpose with or without fee is hereby granted, provided that the above 9184610Salfred * copyright notice and this permission notice appear in all copies. 10184610Salfred * 11184610Salfred * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12184610Salfred * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13184610Salfred * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14184610Salfred * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15184610Salfred * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16184610Salfred * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17184610Salfred * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18184610Salfred */ 19184610Salfred 20184610Salfred#define RAL_NOISE_FLOOR -95 21184610Salfred#define RAL_RSSI_CORR 120 22184610Salfred 23184610Salfred#define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) 24184610Salfred#define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) 25184610Salfred#define RAL_FRAME_SIZE 0x780 /* NOTE: using 0x980 does not work */ 26184610Salfred#if (RAL_FRAME_SIZE % 0x80) 27184610Salfred#error "Invalid RAL_FRAME_SIZE" 28184610Salfred#endif 29184610Salfred 30184610Salfred#define RAL_CONFIG_NO 1 31184610Salfred#define RAL_IFACE_INDEX 0 32184610Salfred 33184610Salfred#define RAL_VENDOR_REQUEST 0x01 34184610Salfred#define RAL_WRITE_MAC 0x02 35184610Salfred#define RAL_READ_MAC 0x03 36184610Salfred#define RAL_WRITE_MULTI_MAC 0x06 37184610Salfred#define RAL_READ_MULTI_MAC 0x07 38184610Salfred#define RAL_READ_EEPROM 0x09 39184610Salfred 40184610Salfred/* MAC registers. */ 41184610Salfred#define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 42184610Salfred#define RAL_MAC_CSR1 0x0402 /* System control */ 43184610Salfred#define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 44184610Salfred#define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 45184610Salfred#define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 46184610Salfred#define RAL_MAC_CSR5 0x040a /* BSSID0 */ 47184610Salfred#define RAL_MAC_CSR6 0x040c /* BSSID1 */ 48184610Salfred#define RAL_MAC_CSR7 0x040e /* BSSID2 */ 49184610Salfred#define RAL_MAC_CSR8 0x0410 /* Max frame length */ 50184610Salfred#define RAL_MAC_CSR9 0x0412 /* Timer control */ 51184610Salfred#define RAL_MAC_CSR10 0x0414 /* Slot time */ 52184610Salfred#define RAL_MAC_CSR11 0x0416 /* IFS */ 53184610Salfred#define RAL_MAC_CSR12 0x0418 /* EIFS */ 54184610Salfred#define RAL_MAC_CSR13 0x041a /* Power mode0 */ 55184610Salfred#define RAL_MAC_CSR14 0x041c /* Power mode1 */ 56184610Salfred#define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 57184610Salfred#define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 58184610Salfred#define RAL_MAC_CSR17 0x0422 /* Power state control */ 59184610Salfred#define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 60184610Salfred#define RAL_MAC_CSR19 0x0426 /* GPIO control */ 61184610Salfred#define RAL_MAC_CSR20 0x0428 /* LED control0 */ 62184610Salfred#define RAL_MAC_CSR22 0x042c /* XXX not documented */ 63184610Salfred 64184610Salfred/* Tx/Rx Registers. */ 65184610Salfred#define RAL_TXRX_CSR0 0x0440 /* Security control */ 66184610Salfred#define RAL_TXRX_CSR2 0x0444 /* Rx control */ 67184610Salfred#define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 68184610Salfred#define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 69184610Salfred#define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 70184610Salfred#define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 71184610Salfred#define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 72184610Salfred#define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 73184610Salfred#define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 74184610Salfred#define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 75184610Salfred#define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 76184610Salfred#define RAL_TXRX_CSR21 0x046a /* XXX not documented */ 77184610Salfred 78184610Salfred/* Security registers. */ 79184610Salfred#define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 80184610Salfred 81184610Salfred/* PHY registers. */ 82184610Salfred#define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 83184610Salfred#define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 84184610Salfred#define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 85184610Salfred#define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 86184610Salfred#define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 87184610Salfred#define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 88184610Salfred#define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 89184610Salfred#define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 90184610Salfred 91184610Salfred/* Statistics registers. */ 92184610Salfred#define RAL_STA_CSR0 0x04e0 /* FCS error */ 93184610Salfred 94184610Salfred#define RAL_DISABLE_RX (1 << 0) 95184610Salfred#define RAL_DROP_CRC (1 << 1) 96184610Salfred#define RAL_DROP_PHY (1 << 2) 97184610Salfred#define RAL_DROP_CTL (1 << 3) 98184610Salfred#define RAL_DROP_NOT_TO_ME (1 << 4) 99184610Salfred#define RAL_DROP_TODS (1 << 5) 100184610Salfred#define RAL_DROP_BAD_VERSION (1 << 6) 101184610Salfred#define RAL_DROP_MULTICAST (1 << 9) 102184610Salfred#define RAL_DROP_BROADCAST (1 << 10) 103184610Salfred 104184610Salfred#define RAL_SHORT_PREAMBLE (1 << 2) 105184610Salfred 106184610Salfred#define RAL_RESET_ASIC (1 << 0) 107184610Salfred#define RAL_RESET_BBP (1 << 1) 108184610Salfred#define RAL_HOST_READY (1 << 2) 109184610Salfred 110184610Salfred#define RAL_ENABLE_TSF (1 << 0) 111184610Salfred#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 112184610Salfred#define RAL_ENABLE_TBCN (1 << 3) 113184610Salfred#define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 114184610Salfred 115184610Salfred#define RAL_RF_AWAKE (3 << 7) 116184610Salfred#define RAL_BBP_AWAKE (3 << 5) 117184610Salfred 118184610Salfred#define RAL_BBP_WRITE (1 << 15) 119184610Salfred#define RAL_BBP_BUSY (1 << 0) 120184610Salfred 121184610Salfred#define RAL_RF1_AUTOTUNE 0x08000 122184610Salfred#define RAL_RF3_AUTOTUNE 0x00040 123184610Salfred 124184610Salfred#define RAL_RF_2522 0x00 125184610Salfred#define RAL_RF_2523 0x01 126184610Salfred#define RAL_RF_2524 0x02 127184610Salfred#define RAL_RF_2525 0x03 128184610Salfred#define RAL_RF_2525E 0x04 129184610Salfred#define RAL_RF_2526 0x05 130184610Salfred/* dual-band RF */ 131184610Salfred#define RAL_RF_5222 0x10 132184610Salfred 133184610Salfred#define RAL_BBP_VERSION 0 134184610Salfred#define RAL_BBP_TX 2 135184610Salfred#define RAL_BBP_RX 14 136184610Salfred 137184610Salfred#define RAL_BBP_ANTA 0x00 138184610Salfred#define RAL_BBP_DIVERSITY 0x01 139184610Salfred#define RAL_BBP_ANTB 0x02 140184610Salfred#define RAL_BBP_ANTMASK 0x03 141184610Salfred#define RAL_BBP_FLIPIQ 0x04 142184610Salfred 143184610Salfred#define RAL_JAPAN_FILTER 0x08 144184610Salfred 145184610Salfred#define RAL_RF_LOBUSY (1 << 15) 146184610Salfred#define RAL_RF_BUSY (1 << 31) 147184610Salfred#define RAL_RF_20BIT (20 << 24) 148184610Salfred 149184610Salfred#define RAL_RF1 0 150184610Salfred#define RAL_RF2 2 151184610Salfred#define RAL_RF3 1 152184610Salfred#define RAL_RF4 3 153184610Salfred 154184610Salfred#define RAL_EEPROM_ADDRESS 0x0004 155184610Salfred#define RAL_EEPROM_TXPOWER 0x003c 156184610Salfred#define RAL_EEPROM_CONFIG0 0x0016 157184610Salfred#define RAL_EEPROM_BBP_BASE 0x001c 158184610Salfred 159184610Salfredstruct ural_tx_desc { 160184610Salfred uint32_t flags; 161184610Salfred#define RAL_TX_PACKET_ID(x) ((x) & 0xf) 162184610Salfred#define RAL_TX_RETRY(x) ((x) << 4) 163184610Salfred#define RAL_TX_MORE_FRAG (1 << 8) 164184610Salfred#define RAL_TX_ACK (1 << 9) 165184610Salfred#define RAL_TX_TIMESTAMP (1 << 10) 166184610Salfred#define RAL_TX_OFDM (1 << 11) 167184610Salfred#define RAL_TX_NEWSEQ (1 << 12) 168184610Salfred#define RAL_TX_IFS_MASK 0x00006000 169184610Salfred#define RAL_TX_IFS_BACKOFF (0 << 13) 170184610Salfred#define RAL_TX_IFS_SIFS (1 << 13) 171184610Salfred#define RAL_TX_IFS_NEWBACKOFF (2 << 13) 172184610Salfred#define RAL_TX_IFS_NONE (3 << 13) 173184610Salfred uint16_t wme; 174184610Salfred#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 175184610Salfred#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 176184610Salfred#define RAL_AIFSN(x) (((x) & 0x3) << 6) 177184610Salfred#define RAL_IVOFFSET(x) (((x) & 0x3f)) 178184610Salfred uint16_t reserved1; 179184610Salfred uint8_t plcp_signal; 180184610Salfred uint8_t plcp_service; 181184610Salfred#define RAL_PLCP_LENGEXT 0x80 182184610Salfred uint8_t plcp_length_lo; 183184610Salfred uint8_t plcp_length_hi; 184184610Salfred uint32_t iv; 185184610Salfred uint32_t eiv; 186184610Salfred} __packed; 187184610Salfred 188184610Salfredstruct ural_rx_desc { 189184610Salfred uint32_t flags; 190184610Salfred#define RAL_RX_CRC_ERROR (1 << 5) 191184610Salfred#define RAL_RX_OFDM (1 << 6) 192184610Salfred#define RAL_RX_PHY_ERROR (1 << 7) 193184610Salfred uint8_t rssi; 194184610Salfred uint8_t rate; 195184610Salfred uint16_t reserved; 196184610Salfred uint32_t iv; 197184610Salfred uint32_t eiv; 198184610Salfred} __packed; 199