if_ural.c revision 212127
1/* $FreeBSD: head/sys/dev/usb/wlan/if_ural.c 212127 2010-09-02 03:28:03Z thompsa $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_ural.c 212127 2010-09-02 03:28:03Z thompsa $"); 25 26/*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/mbuf.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64#endif 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR ural_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_uralreg.h> 79#include <dev/usb/wlan/if_uralvar.h> 80 81#ifdef USB_DEBUG 82static int ural_debug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 85SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 86 "Debug level"); 87#endif 88 89#define URAL_RSSI(rssi) \ 90 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 91 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 92 93/* various supported device vendors/products */ 94static const struct usb_device_id ural_devs[] = { 95#define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96 URAL_DEV(ASUS, WL167G), 97 URAL_DEV(ASUS, RT2570), 98 URAL_DEV(BELKIN, F5D7050), 99 URAL_DEV(BELKIN, F5D7051), 100 URAL_DEV(CISCOLINKSYS, HU200TS), 101 URAL_DEV(CISCOLINKSYS, WUSB54G), 102 URAL_DEV(CISCOLINKSYS, WUSB54GP), 103 URAL_DEV(CONCEPTRONIC2, C54RU), 104 URAL_DEV(DLINK, DWLG122), 105 URAL_DEV(GIGABYTE, GN54G), 106 URAL_DEV(GIGABYTE, GNWBKG), 107 URAL_DEV(GUILLEMOT, HWGUSB254), 108 URAL_DEV(MELCO, KG54), 109 URAL_DEV(MELCO, KG54AI), 110 URAL_DEV(MELCO, KG54YB), 111 URAL_DEV(MELCO, NINWIFI), 112 URAL_DEV(MSI, RT2570), 113 URAL_DEV(MSI, RT2570_2), 114 URAL_DEV(MSI, RT2570_3), 115 URAL_DEV(NOVATECH, NV902), 116 URAL_DEV(RALINK, RT2570), 117 URAL_DEV(RALINK, RT2570_2), 118 URAL_DEV(RALINK, RT2570_3), 119 URAL_DEV(SIEMENS2, WL54G), 120 URAL_DEV(SMC, 2862WG), 121 URAL_DEV(SPHAIRON, UB801R), 122 URAL_DEV(SURECOM, RT2570), 123 URAL_DEV(VTECH, RT2570), 124 URAL_DEV(ZINWELL, RT2570), 125#undef URAL_DEV 126}; 127 128static usb_callback_t ural_bulk_read_callback; 129static usb_callback_t ural_bulk_write_callback; 130 131static usb_error_t ural_do_request(struct ural_softc *sc, 132 struct usb_device_request *req, void *data); 133static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 134 const char name[IFNAMSIZ], int unit, int opmode, 135 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 136 const uint8_t mac[IEEE80211_ADDR_LEN]); 137static void ural_vap_delete(struct ieee80211vap *); 138static void ural_tx_free(struct ural_tx_data *, int); 139static void ural_setup_tx_list(struct ural_softc *); 140static void ural_unsetup_tx_list(struct ural_softc *); 141static int ural_newstate(struct ieee80211vap *, 142 enum ieee80211_state, int); 143static void ural_setup_tx_desc(struct ural_softc *, 144 struct ural_tx_desc *, uint32_t, int, int); 145static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 146 struct ieee80211_node *); 147static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 148 struct ieee80211_node *); 149static int ural_tx_data(struct ural_softc *, struct mbuf *, 150 struct ieee80211_node *); 151static void ural_start(struct ifnet *); 152static int ural_ioctl(struct ifnet *, u_long, caddr_t); 153static void ural_set_testmode(struct ural_softc *); 154static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 155 int); 156static uint16_t ural_read(struct ural_softc *, uint16_t); 157static void ural_read_multi(struct ural_softc *, uint16_t, void *, 158 int); 159static void ural_write(struct ural_softc *, uint16_t, uint16_t); 160static void ural_write_multi(struct ural_softc *, uint16_t, void *, 161 int) __unused; 162static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 163static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 164static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 165static void ural_scan_start(struct ieee80211com *); 166static void ural_scan_end(struct ieee80211com *); 167static void ural_set_channel(struct ieee80211com *); 168static void ural_set_chan(struct ural_softc *, 169 struct ieee80211_channel *); 170static void ural_disable_rf_tune(struct ural_softc *); 171static void ural_enable_tsf_sync(struct ural_softc *); 172static void ural_enable_tsf(struct ural_softc *); 173static void ural_update_slot(struct ifnet *); 174static void ural_set_txpreamble(struct ural_softc *); 175static void ural_set_basicrates(struct ural_softc *, 176 const struct ieee80211_channel *); 177static void ural_set_bssid(struct ural_softc *, const uint8_t *); 178static void ural_set_macaddr(struct ural_softc *, uint8_t *); 179static void ural_update_promisc(struct ifnet *); 180static void ural_setpromisc(struct ural_softc *); 181static const char *ural_get_rf(int); 182static void ural_read_eeprom(struct ural_softc *); 183static int ural_bbp_init(struct ural_softc *); 184static void ural_set_txantenna(struct ural_softc *, int); 185static void ural_set_rxantenna(struct ural_softc *, int); 186static void ural_init_locked(struct ural_softc *); 187static void ural_init(void *); 188static void ural_stop(struct ural_softc *); 189static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 190 const struct ieee80211_bpf_params *); 191static void ural_ratectl_start(struct ural_softc *, 192 struct ieee80211_node *); 193static void ural_ratectl_timeout(void *); 194static void ural_ratectl_task(void *, int); 195static int ural_pause(struct ural_softc *sc, int timeout); 196 197/* 198 * Default values for MAC registers; values taken from the reference driver. 199 */ 200static const struct { 201 uint16_t reg; 202 uint16_t val; 203} ural_def_mac[] = { 204 { RAL_TXRX_CSR5, 0x8c8d }, 205 { RAL_TXRX_CSR6, 0x8b8a }, 206 { RAL_TXRX_CSR7, 0x8687 }, 207 { RAL_TXRX_CSR8, 0x0085 }, 208 { RAL_MAC_CSR13, 0x1111 }, 209 { RAL_MAC_CSR14, 0x1e11 }, 210 { RAL_TXRX_CSR21, 0xe78f }, 211 { RAL_MAC_CSR9, 0xff1d }, 212 { RAL_MAC_CSR11, 0x0002 }, 213 { RAL_MAC_CSR22, 0x0053 }, 214 { RAL_MAC_CSR15, 0x0000 }, 215 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 216 { RAL_TXRX_CSR19, 0x0000 }, 217 { RAL_TXRX_CSR18, 0x005a }, 218 { RAL_PHY_CSR2, 0x0000 }, 219 { RAL_TXRX_CSR0, 0x1ec0 }, 220 { RAL_PHY_CSR4, 0x000f } 221}; 222 223/* 224 * Default values for BBP registers; values taken from the reference driver. 225 */ 226static const struct { 227 uint8_t reg; 228 uint8_t val; 229} ural_def_bbp[] = { 230 { 3, 0x02 }, 231 { 4, 0x19 }, 232 { 14, 0x1c }, 233 { 15, 0x30 }, 234 { 16, 0xac }, 235 { 17, 0x48 }, 236 { 18, 0x18 }, 237 { 19, 0xff }, 238 { 20, 0x1e }, 239 { 21, 0x08 }, 240 { 22, 0x08 }, 241 { 23, 0x08 }, 242 { 24, 0x80 }, 243 { 25, 0x50 }, 244 { 26, 0x08 }, 245 { 27, 0x23 }, 246 { 30, 0x10 }, 247 { 31, 0x2b }, 248 { 32, 0xb9 }, 249 { 34, 0x12 }, 250 { 35, 0x50 }, 251 { 39, 0xc4 }, 252 { 40, 0x02 }, 253 { 41, 0x60 }, 254 { 53, 0x10 }, 255 { 54, 0x18 }, 256 { 56, 0x08 }, 257 { 57, 0x10 }, 258 { 58, 0x08 }, 259 { 61, 0x60 }, 260 { 62, 0x10 }, 261 { 75, 0xff } 262}; 263 264/* 265 * Default values for RF register R2 indexed by channel numbers. 266 */ 267static const uint32_t ural_rf2522_r2[] = { 268 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 269 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 270}; 271 272static const uint32_t ural_rf2523_r2[] = { 273 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 274 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 275}; 276 277static const uint32_t ural_rf2524_r2[] = { 278 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 279 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 280}; 281 282static const uint32_t ural_rf2525_r2[] = { 283 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 284 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 285}; 286 287static const uint32_t ural_rf2525_hi_r2[] = { 288 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 289 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 290}; 291 292static const uint32_t ural_rf2525e_r2[] = { 293 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 294 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 295}; 296 297static const uint32_t ural_rf2526_hi_r2[] = { 298 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 299 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 300}; 301 302static const uint32_t ural_rf2526_r2[] = { 303 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 304 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 305}; 306 307/* 308 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 309 * values taken from the reference driver. 310 */ 311static const struct { 312 uint8_t chan; 313 uint32_t r1; 314 uint32_t r2; 315 uint32_t r4; 316} ural_rf5222[] = { 317 { 1, 0x08808, 0x0044d, 0x00282 }, 318 { 2, 0x08808, 0x0044e, 0x00282 }, 319 { 3, 0x08808, 0x0044f, 0x00282 }, 320 { 4, 0x08808, 0x00460, 0x00282 }, 321 { 5, 0x08808, 0x00461, 0x00282 }, 322 { 6, 0x08808, 0x00462, 0x00282 }, 323 { 7, 0x08808, 0x00463, 0x00282 }, 324 { 8, 0x08808, 0x00464, 0x00282 }, 325 { 9, 0x08808, 0x00465, 0x00282 }, 326 { 10, 0x08808, 0x00466, 0x00282 }, 327 { 11, 0x08808, 0x00467, 0x00282 }, 328 { 12, 0x08808, 0x00468, 0x00282 }, 329 { 13, 0x08808, 0x00469, 0x00282 }, 330 { 14, 0x08808, 0x0046b, 0x00286 }, 331 332 { 36, 0x08804, 0x06225, 0x00287 }, 333 { 40, 0x08804, 0x06226, 0x00287 }, 334 { 44, 0x08804, 0x06227, 0x00287 }, 335 { 48, 0x08804, 0x06228, 0x00287 }, 336 { 52, 0x08804, 0x06229, 0x00287 }, 337 { 56, 0x08804, 0x0622a, 0x00287 }, 338 { 60, 0x08804, 0x0622b, 0x00287 }, 339 { 64, 0x08804, 0x0622c, 0x00287 }, 340 341 { 100, 0x08804, 0x02200, 0x00283 }, 342 { 104, 0x08804, 0x02201, 0x00283 }, 343 { 108, 0x08804, 0x02202, 0x00283 }, 344 { 112, 0x08804, 0x02203, 0x00283 }, 345 { 116, 0x08804, 0x02204, 0x00283 }, 346 { 120, 0x08804, 0x02205, 0x00283 }, 347 { 124, 0x08804, 0x02206, 0x00283 }, 348 { 128, 0x08804, 0x02207, 0x00283 }, 349 { 132, 0x08804, 0x02208, 0x00283 }, 350 { 136, 0x08804, 0x02209, 0x00283 }, 351 { 140, 0x08804, 0x0220a, 0x00283 }, 352 353 { 149, 0x08808, 0x02429, 0x00281 }, 354 { 153, 0x08808, 0x0242b, 0x00281 }, 355 { 157, 0x08808, 0x0242d, 0x00281 }, 356 { 161, 0x08808, 0x0242f, 0x00281 } 357}; 358 359static const struct usb_config ural_config[URAL_N_TRANSFER] = { 360 [URAL_BULK_WR] = { 361 .type = UE_BULK, 362 .endpoint = UE_ADDR_ANY, 363 .direction = UE_DIR_OUT, 364 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 365 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 366 .callback = ural_bulk_write_callback, 367 .timeout = 5000, /* ms */ 368 }, 369 [URAL_BULK_RD] = { 370 .type = UE_BULK, 371 .endpoint = UE_ADDR_ANY, 372 .direction = UE_DIR_IN, 373 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 374 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 375 .callback = ural_bulk_read_callback, 376 }, 377}; 378 379static device_probe_t ural_match; 380static device_attach_t ural_attach; 381static device_detach_t ural_detach; 382 383static device_method_t ural_methods[] = { 384 /* Device interface */ 385 DEVMETHOD(device_probe, ural_match), 386 DEVMETHOD(device_attach, ural_attach), 387 DEVMETHOD(device_detach, ural_detach), 388 389 { 0, 0 } 390}; 391 392static driver_t ural_driver = { 393 .name = "ural", 394 .methods = ural_methods, 395 .size = sizeof(struct ural_softc), 396}; 397 398static devclass_t ural_devclass; 399 400DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 401MODULE_DEPEND(ural, usb, 1, 1, 1); 402MODULE_DEPEND(ural, wlan, 1, 1, 1); 403MODULE_VERSION(ural, 1); 404 405static int 406ural_match(device_t self) 407{ 408 struct usb_attach_arg *uaa = device_get_ivars(self); 409 410 if (uaa->usb_mode != USB_MODE_HOST) 411 return (ENXIO); 412 if (uaa->info.bConfigIndex != 0) 413 return (ENXIO); 414 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 415 return (ENXIO); 416 417 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 418} 419 420static int 421ural_attach(device_t self) 422{ 423 struct usb_attach_arg *uaa = device_get_ivars(self); 424 struct ural_softc *sc = device_get_softc(self); 425 struct ifnet *ifp; 426 struct ieee80211com *ic; 427 uint8_t iface_index, bands; 428 int error; 429 430 device_set_usb_desc(self); 431 sc->sc_udev = uaa->device; 432 sc->sc_dev = self; 433 434 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 435 MTX_NETWORK_LOCK, MTX_DEF); 436 437 iface_index = RAL_IFACE_INDEX; 438 error = usbd_transfer_setup(uaa->device, 439 &iface_index, sc->sc_xfer, ural_config, 440 URAL_N_TRANSFER, sc, &sc->sc_mtx); 441 if (error) { 442 device_printf(self, "could not allocate USB transfers, " 443 "err=%s\n", usbd_errstr(error)); 444 goto detach; 445 } 446 447 RAL_LOCK(sc); 448 /* retrieve RT2570 rev. no */ 449 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 450 451 /* retrieve MAC address and various other things from EEPROM */ 452 ural_read_eeprom(sc); 453 RAL_UNLOCK(sc); 454 455 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 456 sc->asic_rev, ural_get_rf(sc->rf_rev)); 457 458 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 459 if (ifp == NULL) { 460 device_printf(sc->sc_dev, "can not if_alloc()\n"); 461 goto detach; 462 } 463 ic = ifp->if_l2com; 464 465 ifp->if_softc = sc; 466 if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 467 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 468 ifp->if_init = ural_init; 469 ifp->if_ioctl = ural_ioctl; 470 ifp->if_start = ural_start; 471 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 472 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 473 IFQ_SET_READY(&ifp->if_snd); 474 475 ic->ic_ifp = ifp; 476 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 477 478 /* set device capabilities */ 479 ic->ic_caps = 480 IEEE80211_C_STA /* station mode supported */ 481 | IEEE80211_C_IBSS /* IBSS mode supported */ 482 | IEEE80211_C_MONITOR /* monitor mode supported */ 483 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 484 | IEEE80211_C_TXPMGT /* tx power management */ 485 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 486 | IEEE80211_C_SHSLOT /* short slot time supported */ 487 | IEEE80211_C_BGSCAN /* bg scanning supported */ 488 | IEEE80211_C_WPA /* 802.11i */ 489 | IEEE80211_C_RATECTL /* use ratectl */ 490 ; 491 492 bands = 0; 493 setbit(&bands, IEEE80211_MODE_11B); 494 setbit(&bands, IEEE80211_MODE_11G); 495 if (sc->rf_rev == RAL_RF_5222) 496 setbit(&bands, IEEE80211_MODE_11A); 497 ieee80211_init_channels(ic, NULL, &bands); 498 499 ieee80211_ifattach(ic, sc->sc_bssid); 500 ic->ic_update_promisc = ural_update_promisc; 501 ic->ic_raw_xmit = ural_raw_xmit; 502 ic->ic_scan_start = ural_scan_start; 503 ic->ic_scan_end = ural_scan_end; 504 ic->ic_set_channel = ural_set_channel; 505 506 ic->ic_vap_create = ural_vap_create; 507 ic->ic_vap_delete = ural_vap_delete; 508 509 ieee80211_radiotap_attach(ic, 510 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 511 RAL_TX_RADIOTAP_PRESENT, 512 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 513 RAL_RX_RADIOTAP_PRESENT); 514 515 if (bootverbose) 516 ieee80211_announce(ic); 517 518 return (0); 519 520detach: 521 ural_detach(self); 522 return (ENXIO); /* failure */ 523} 524 525static int 526ural_detach(device_t self) 527{ 528 struct ural_softc *sc = device_get_softc(self); 529 struct ifnet *ifp = sc->sc_ifp; 530 struct ieee80211com *ic; 531 532 /* stop all USB transfers */ 533 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 534 535 /* free TX list, if any */ 536 RAL_LOCK(sc); 537 ural_unsetup_tx_list(sc); 538 RAL_UNLOCK(sc); 539 540 if (ifp) { 541 ic = ifp->if_l2com; 542 ieee80211_ifdetach(ic); 543 if_free(ifp); 544 } 545 mtx_destroy(&sc->sc_mtx); 546 547 return (0); 548} 549 550static usb_error_t 551ural_do_request(struct ural_softc *sc, 552 struct usb_device_request *req, void *data) 553{ 554 usb_error_t err; 555 int ntries = 10; 556 557 while (ntries--) { 558 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 559 req, data, 0, NULL, 250 /* ms */); 560 if (err == 0) 561 break; 562 563 DPRINTFN(1, "Control request failed, %s (retrying)\n", 564 usbd_errstr(err)); 565 if (ural_pause(sc, hz / 100)) 566 break; 567 } 568 return (err); 569} 570 571static struct ieee80211vap * 572ural_vap_create(struct ieee80211com *ic, 573 const char name[IFNAMSIZ], int unit, int opmode, int flags, 574 const uint8_t bssid[IEEE80211_ADDR_LEN], 575 const uint8_t mac[IEEE80211_ADDR_LEN]) 576{ 577 struct ural_softc *sc = ic->ic_ifp->if_softc; 578 struct ural_vap *uvp; 579 struct ieee80211vap *vap; 580 581 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 582 return NULL; 583 uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 584 M_80211_VAP, M_NOWAIT | M_ZERO); 585 if (uvp == NULL) 586 return NULL; 587 vap = &uvp->vap; 588 /* enable s/w bmiss handling for sta mode */ 589 ieee80211_vap_setup(ic, vap, name, unit, opmode, 590 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 591 592 /* override state transition machine */ 593 uvp->newstate = vap->iv_newstate; 594 vap->iv_newstate = ural_newstate; 595 596 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 597 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 598 ieee80211_ratectl_init(vap); 599 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 600 601 /* complete setup */ 602 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 603 ic->ic_opmode = opmode; 604 return vap; 605} 606 607static void 608ural_vap_delete(struct ieee80211vap *vap) 609{ 610 struct ural_vap *uvp = URAL_VAP(vap); 611 struct ieee80211com *ic = vap->iv_ic; 612 613 usb_callout_drain(&uvp->ratectl_ch); 614 ieee80211_draintask(ic, &uvp->ratectl_task); 615 ieee80211_ratectl_deinit(vap); 616 ieee80211_vap_detach(vap); 617 free(uvp, M_80211_VAP); 618} 619 620static void 621ural_tx_free(struct ural_tx_data *data, int txerr) 622{ 623 struct ural_softc *sc = data->sc; 624 625 if (data->m != NULL) { 626 if (data->m->m_flags & M_TXCB) 627 ieee80211_process_callback(data->ni, data->m, 628 txerr ? ETIMEDOUT : 0); 629 m_freem(data->m); 630 data->m = NULL; 631 632 ieee80211_free_node(data->ni); 633 data->ni = NULL; 634 } 635 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 636 sc->tx_nfree++; 637} 638 639static void 640ural_setup_tx_list(struct ural_softc *sc) 641{ 642 struct ural_tx_data *data; 643 int i; 644 645 sc->tx_nfree = 0; 646 STAILQ_INIT(&sc->tx_q); 647 STAILQ_INIT(&sc->tx_free); 648 649 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 650 data = &sc->tx_data[i]; 651 652 data->sc = sc; 653 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 654 sc->tx_nfree++; 655 } 656} 657 658static void 659ural_unsetup_tx_list(struct ural_softc *sc) 660{ 661 struct ural_tx_data *data; 662 int i; 663 664 /* make sure any subsequent use of the queues will fail */ 665 sc->tx_nfree = 0; 666 STAILQ_INIT(&sc->tx_q); 667 STAILQ_INIT(&sc->tx_free); 668 669 /* free up all node references and mbufs */ 670 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 671 data = &sc->tx_data[i]; 672 673 if (data->m != NULL) { 674 m_freem(data->m); 675 data->m = NULL; 676 } 677 if (data->ni != NULL) { 678 ieee80211_free_node(data->ni); 679 data->ni = NULL; 680 } 681 } 682} 683 684static int 685ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 686{ 687 struct ural_vap *uvp = URAL_VAP(vap); 688 struct ieee80211com *ic = vap->iv_ic; 689 struct ural_softc *sc = ic->ic_ifp->if_softc; 690 const struct ieee80211_txparam *tp; 691 struct ieee80211_node *ni; 692 struct mbuf *m; 693 694 DPRINTF("%s -> %s\n", 695 ieee80211_state_name[vap->iv_state], 696 ieee80211_state_name[nstate]); 697 698 IEEE80211_UNLOCK(ic); 699 RAL_LOCK(sc); 700 usb_callout_stop(&uvp->ratectl_ch); 701 702 switch (nstate) { 703 case IEEE80211_S_INIT: 704 if (vap->iv_state == IEEE80211_S_RUN) { 705 /* abort TSF synchronization */ 706 ural_write(sc, RAL_TXRX_CSR19, 0); 707 708 /* force tx led to stop blinking */ 709 ural_write(sc, RAL_MAC_CSR20, 0); 710 } 711 break; 712 713 case IEEE80211_S_RUN: 714 ni = ieee80211_ref_node(vap->iv_bss); 715 716 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 717 ural_update_slot(ic->ic_ifp); 718 ural_set_txpreamble(sc); 719 ural_set_basicrates(sc, ic->ic_bsschan); 720 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 721 ural_set_bssid(sc, sc->sc_bssid); 722 } 723 724 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 725 vap->iv_opmode == IEEE80211_M_IBSS) { 726 m = ieee80211_beacon_alloc(ni, &uvp->bo); 727 if (m == NULL) { 728 device_printf(sc->sc_dev, 729 "could not allocate beacon\n"); 730 RAL_UNLOCK(sc); 731 IEEE80211_LOCK(ic); 732 ieee80211_free_node(ni); 733 return (-1); 734 } 735 ieee80211_ref_node(ni); 736 if (ural_tx_bcn(sc, m, ni) != 0) { 737 device_printf(sc->sc_dev, 738 "could not send beacon\n"); 739 RAL_UNLOCK(sc); 740 IEEE80211_LOCK(ic); 741 ieee80211_free_node(ni); 742 return (-1); 743 } 744 } 745 746 /* make tx led blink on tx (controlled by ASIC) */ 747 ural_write(sc, RAL_MAC_CSR20, 1); 748 749 if (vap->iv_opmode != IEEE80211_M_MONITOR) 750 ural_enable_tsf_sync(sc); 751 else 752 ural_enable_tsf(sc); 753 754 /* enable automatic rate adaptation */ 755 /* XXX should use ic_bsschan but not valid until after newstate call below */ 756 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 757 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 758 ural_ratectl_start(sc, ni); 759 ieee80211_free_node(ni); 760 break; 761 762 default: 763 break; 764 } 765 RAL_UNLOCK(sc); 766 IEEE80211_LOCK(ic); 767 return (uvp->newstate(vap, nstate, arg)); 768} 769 770 771static void 772ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 773{ 774 struct ural_softc *sc = usbd_xfer_softc(xfer); 775 struct ifnet *ifp = sc->sc_ifp; 776 struct ieee80211vap *vap; 777 struct ural_tx_data *data; 778 struct mbuf *m; 779 struct usb_page_cache *pc; 780 int len; 781 782 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 783 784 switch (USB_GET_STATE(xfer)) { 785 case USB_ST_TRANSFERRED: 786 DPRINTFN(11, "transfer complete, %d bytes\n", len); 787 788 /* free resources */ 789 data = usbd_xfer_get_priv(xfer); 790 ural_tx_free(data, 0); 791 usbd_xfer_set_priv(xfer, NULL); 792 793 ifp->if_opackets++; 794 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 795 796 /* FALLTHROUGH */ 797 case USB_ST_SETUP: 798tr_setup: 799 data = STAILQ_FIRST(&sc->tx_q); 800 if (data) { 801 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 802 m = data->m; 803 804 if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 805 DPRINTFN(0, "data overflow, %u bytes\n", 806 m->m_pkthdr.len); 807 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 808 } 809 pc = usbd_xfer_get_frame(xfer, 0); 810 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 811 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 812 m->m_pkthdr.len); 813 814 vap = data->ni->ni_vap; 815 if (ieee80211_radiotap_active_vap(vap)) { 816 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 817 818 tap->wt_flags = 0; 819 tap->wt_rate = data->rate; 820 tap->wt_antenna = sc->tx_ant; 821 822 ieee80211_radiotap_tx(vap, m); 823 } 824 825 /* xfer length needs to be a multiple of two! */ 826 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 827 if ((len % 64) == 0) 828 len += 2; 829 830 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 831 m->m_pkthdr.len, len); 832 833 usbd_xfer_set_frame_len(xfer, 0, len); 834 usbd_xfer_set_priv(xfer, data); 835 836 usbd_transfer_submit(xfer); 837 } 838 RAL_UNLOCK(sc); 839 ural_start(ifp); 840 RAL_LOCK(sc); 841 break; 842 843 default: /* Error */ 844 DPRINTFN(11, "transfer error, %s\n", 845 usbd_errstr(error)); 846 847 ifp->if_oerrors++; 848 data = usbd_xfer_get_priv(xfer); 849 if (data != NULL) { 850 ural_tx_free(data, error); 851 usbd_xfer_set_priv(xfer, NULL); 852 } 853 854 if (error == USB_ERR_STALLED) { 855 /* try to clear stall first */ 856 usbd_xfer_set_stall(xfer); 857 goto tr_setup; 858 } 859 if (error == USB_ERR_TIMEOUT) 860 device_printf(sc->sc_dev, "device timeout\n"); 861 break; 862 } 863} 864 865static void 866ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 867{ 868 struct ural_softc *sc = usbd_xfer_softc(xfer); 869 struct ifnet *ifp = sc->sc_ifp; 870 struct ieee80211com *ic = ifp->if_l2com; 871 struct ieee80211_node *ni; 872 struct mbuf *m = NULL; 873 struct usb_page_cache *pc; 874 uint32_t flags; 875 int8_t rssi = 0, nf = 0; 876 int len; 877 878 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 879 880 switch (USB_GET_STATE(xfer)) { 881 case USB_ST_TRANSFERRED: 882 883 DPRINTFN(15, "rx done, actlen=%d\n", len); 884 885 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 886 DPRINTF("%s: xfer too short %d\n", 887 device_get_nameunit(sc->sc_dev), len); 888 ifp->if_ierrors++; 889 goto tr_setup; 890 } 891 892 len -= RAL_RX_DESC_SIZE; 893 /* rx descriptor is located at the end */ 894 pc = usbd_xfer_get_frame(xfer, 0); 895 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 896 897 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 898 nf = RAL_NOISE_FLOOR; 899 flags = le32toh(sc->sc_rx_desc.flags); 900 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 901 /* 902 * This should not happen since we did not 903 * request to receive those frames when we 904 * filled RAL_TXRX_CSR2: 905 */ 906 DPRINTFN(5, "PHY or CRC error\n"); 907 ifp->if_ierrors++; 908 goto tr_setup; 909 } 910 911 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 912 if (m == NULL) { 913 DPRINTF("could not allocate mbuf\n"); 914 ifp->if_ierrors++; 915 goto tr_setup; 916 } 917 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 918 919 /* finalize mbuf */ 920 m->m_pkthdr.rcvif = ifp; 921 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 922 923 if (ieee80211_radiotap_active(ic)) { 924 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 925 926 /* XXX set once */ 927 tap->wr_flags = 0; 928 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 929 (flags & RAL_RX_OFDM) ? 930 IEEE80211_T_OFDM : IEEE80211_T_CCK); 931 tap->wr_antenna = sc->rx_ant; 932 tap->wr_antsignal = nf + rssi; 933 tap->wr_antnoise = nf; 934 } 935 /* Strip trailing 802.11 MAC FCS. */ 936 m_adj(m, -IEEE80211_CRC_LEN); 937 938 /* FALLTHROUGH */ 939 case USB_ST_SETUP: 940tr_setup: 941 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 942 usbd_transfer_submit(xfer); 943 944 /* 945 * At the end of a USB callback it is always safe to unlock 946 * the private mutex of a device! That is why we do the 947 * "ieee80211_input" here, and not some lines up! 948 */ 949 RAL_UNLOCK(sc); 950 if (m) { 951 ni = ieee80211_find_rxnode(ic, 952 mtod(m, struct ieee80211_frame_min *)); 953 if (ni != NULL) { 954 (void) ieee80211_input(ni, m, rssi, nf); 955 ieee80211_free_node(ni); 956 } else 957 (void) ieee80211_input_all(ic, m, rssi, nf); 958 } 959 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 960 !IFQ_IS_EMPTY(&ifp->if_snd)) 961 ural_start(ifp); 962 RAL_LOCK(sc); 963 return; 964 965 default: /* Error */ 966 if (error != USB_ERR_CANCELLED) { 967 /* try to clear stall first */ 968 usbd_xfer_set_stall(xfer); 969 goto tr_setup; 970 } 971 return; 972 } 973} 974 975static uint8_t 976ural_plcp_signal(int rate) 977{ 978 switch (rate) { 979 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 980 case 12: return 0xb; 981 case 18: return 0xf; 982 case 24: return 0xa; 983 case 36: return 0xe; 984 case 48: return 0x9; 985 case 72: return 0xd; 986 case 96: return 0x8; 987 case 108: return 0xc; 988 989 /* CCK rates (NB: not IEEE std, device-specific) */ 990 case 2: return 0x0; 991 case 4: return 0x1; 992 case 11: return 0x2; 993 case 22: return 0x3; 994 } 995 return 0xff; /* XXX unsupported/unknown rate */ 996} 997 998static void 999ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 1000 uint32_t flags, int len, int rate) 1001{ 1002 struct ifnet *ifp = sc->sc_ifp; 1003 struct ieee80211com *ic = ifp->if_l2com; 1004 uint16_t plcp_length; 1005 int remainder; 1006 1007 desc->flags = htole32(flags); 1008 desc->flags |= htole32(RAL_TX_NEWSEQ); 1009 desc->flags |= htole32(len << 16); 1010 1011 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1012 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1013 1014 /* setup PLCP fields */ 1015 desc->plcp_signal = ural_plcp_signal(rate); 1016 desc->plcp_service = 4; 1017 1018 len += IEEE80211_CRC_LEN; 1019 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1020 desc->flags |= htole32(RAL_TX_OFDM); 1021 1022 plcp_length = len & 0xfff; 1023 desc->plcp_length_hi = plcp_length >> 6; 1024 desc->plcp_length_lo = plcp_length & 0x3f; 1025 } else { 1026 plcp_length = (16 * len + rate - 1) / rate; 1027 if (rate == 22) { 1028 remainder = (16 * len) % 22; 1029 if (remainder != 0 && remainder < 7) 1030 desc->plcp_service |= RAL_PLCP_LENGEXT; 1031 } 1032 desc->plcp_length_hi = plcp_length >> 8; 1033 desc->plcp_length_lo = plcp_length & 0xff; 1034 1035 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1036 desc->plcp_signal |= 0x08; 1037 } 1038 1039 desc->iv = 0; 1040 desc->eiv = 0; 1041} 1042 1043#define RAL_TX_TIMEOUT 5000 1044 1045static int 1046ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1047{ 1048 struct ieee80211vap *vap = ni->ni_vap; 1049 struct ieee80211com *ic = ni->ni_ic; 1050 struct ifnet *ifp = sc->sc_ifp; 1051 const struct ieee80211_txparam *tp; 1052 struct ural_tx_data *data; 1053 1054 if (sc->tx_nfree == 0) { 1055 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1056 m_freem(m0); 1057 ieee80211_free_node(ni); 1058 return EIO; 1059 } 1060 data = STAILQ_FIRST(&sc->tx_free); 1061 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1062 sc->tx_nfree--; 1063 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1064 1065 data->m = m0; 1066 data->ni = ni; 1067 data->rate = tp->mgmtrate; 1068 1069 ural_setup_tx_desc(sc, &data->desc, 1070 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1071 tp->mgmtrate); 1072 1073 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1074 m0->m_pkthdr.len, tp->mgmtrate); 1075 1076 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1077 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1078 1079 return (0); 1080} 1081 1082static int 1083ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1084{ 1085 struct ieee80211vap *vap = ni->ni_vap; 1086 struct ieee80211com *ic = ni->ni_ic; 1087 const struct ieee80211_txparam *tp; 1088 struct ural_tx_data *data; 1089 struct ieee80211_frame *wh; 1090 struct ieee80211_key *k; 1091 uint32_t flags; 1092 uint16_t dur; 1093 1094 RAL_LOCK_ASSERT(sc, MA_OWNED); 1095 1096 data = STAILQ_FIRST(&sc->tx_free); 1097 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1098 sc->tx_nfree--; 1099 1100 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1101 1102 wh = mtod(m0, struct ieee80211_frame *); 1103 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1104 k = ieee80211_crypto_encap(ni, m0); 1105 if (k == NULL) { 1106 m_freem(m0); 1107 return ENOBUFS; 1108 } 1109 wh = mtod(m0, struct ieee80211_frame *); 1110 } 1111 1112 data->m = m0; 1113 data->ni = ni; 1114 data->rate = tp->mgmtrate; 1115 1116 flags = 0; 1117 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1118 flags |= RAL_TX_ACK; 1119 1120 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1121 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1122 *(uint16_t *)wh->i_dur = htole16(dur); 1123 1124 /* tell hardware to add timestamp for probe responses */ 1125 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1126 IEEE80211_FC0_TYPE_MGT && 1127 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1128 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1129 flags |= RAL_TX_TIMESTAMP; 1130 } 1131 1132 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1133 1134 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1135 m0->m_pkthdr.len, tp->mgmtrate); 1136 1137 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1138 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1139 1140 return 0; 1141} 1142 1143static int 1144ural_sendprot(struct ural_softc *sc, 1145 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1146{ 1147 struct ieee80211com *ic = ni->ni_ic; 1148 const struct ieee80211_frame *wh; 1149 struct ural_tx_data *data; 1150 struct mbuf *mprot; 1151 int protrate, ackrate, pktlen, flags, isshort; 1152 uint16_t dur; 1153 1154 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1155 ("protection %d", prot)); 1156 1157 wh = mtod(m, const struct ieee80211_frame *); 1158 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1159 1160 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1161 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1162 1163 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1164 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1165 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1166 flags = RAL_TX_RETRY(7); 1167 if (prot == IEEE80211_PROT_RTSCTS) { 1168 /* NB: CTS is the same size as an ACK */ 1169 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1170 flags |= RAL_TX_ACK; 1171 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1172 } else { 1173 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1174 } 1175 if (mprot == NULL) { 1176 /* XXX stat + msg */ 1177 return ENOBUFS; 1178 } 1179 data = STAILQ_FIRST(&sc->tx_free); 1180 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1181 sc->tx_nfree--; 1182 1183 data->m = mprot; 1184 data->ni = ieee80211_ref_node(ni); 1185 data->rate = protrate; 1186 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1187 1188 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1189 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1190 1191 return 0; 1192} 1193 1194static int 1195ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1196 const struct ieee80211_bpf_params *params) 1197{ 1198 struct ieee80211com *ic = ni->ni_ic; 1199 struct ural_tx_data *data; 1200 uint32_t flags; 1201 int error; 1202 int rate; 1203 1204 RAL_LOCK_ASSERT(sc, MA_OWNED); 1205 KASSERT(params != NULL, ("no raw xmit params")); 1206 1207 rate = params->ibp_rate0; 1208 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1209 m_freem(m0); 1210 return EINVAL; 1211 } 1212 flags = 0; 1213 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1214 flags |= RAL_TX_ACK; 1215 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1216 error = ural_sendprot(sc, m0, ni, 1217 params->ibp_flags & IEEE80211_BPF_RTS ? 1218 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1219 rate); 1220 if (error || sc->tx_nfree == 0) { 1221 m_freem(m0); 1222 return ENOBUFS; 1223 } 1224 flags |= RAL_TX_IFS_SIFS; 1225 } 1226 1227 data = STAILQ_FIRST(&sc->tx_free); 1228 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1229 sc->tx_nfree--; 1230 1231 data->m = m0; 1232 data->ni = ni; 1233 data->rate = rate; 1234 1235 /* XXX need to setup descriptor ourself */ 1236 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1237 1238 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1239 m0->m_pkthdr.len, rate); 1240 1241 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1242 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1243 1244 return 0; 1245} 1246 1247static int 1248ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1249{ 1250 struct ieee80211vap *vap = ni->ni_vap; 1251 struct ieee80211com *ic = ni->ni_ic; 1252 struct ural_tx_data *data; 1253 struct ieee80211_frame *wh; 1254 const struct ieee80211_txparam *tp; 1255 struct ieee80211_key *k; 1256 uint32_t flags = 0; 1257 uint16_t dur; 1258 int error, rate; 1259 1260 RAL_LOCK_ASSERT(sc, MA_OWNED); 1261 1262 wh = mtod(m0, struct ieee80211_frame *); 1263 1264 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1265 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1266 rate = tp->mcastrate; 1267 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1268 rate = tp->ucastrate; 1269 else 1270 rate = ni->ni_txrate; 1271 1272 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1273 k = ieee80211_crypto_encap(ni, m0); 1274 if (k == NULL) { 1275 m_freem(m0); 1276 return ENOBUFS; 1277 } 1278 /* packet header may have moved, reset our local pointer */ 1279 wh = mtod(m0, struct ieee80211_frame *); 1280 } 1281 1282 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1283 int prot = IEEE80211_PROT_NONE; 1284 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1285 prot = IEEE80211_PROT_RTSCTS; 1286 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1287 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1288 prot = ic->ic_protmode; 1289 if (prot != IEEE80211_PROT_NONE) { 1290 error = ural_sendprot(sc, m0, ni, prot, rate); 1291 if (error || sc->tx_nfree == 0) { 1292 m_freem(m0); 1293 return ENOBUFS; 1294 } 1295 flags |= RAL_TX_IFS_SIFS; 1296 } 1297 } 1298 1299 data = STAILQ_FIRST(&sc->tx_free); 1300 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1301 sc->tx_nfree--; 1302 1303 data->m = m0; 1304 data->ni = ni; 1305 data->rate = rate; 1306 1307 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1308 flags |= RAL_TX_ACK; 1309 flags |= RAL_TX_RETRY(7); 1310 1311 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1312 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1313 *(uint16_t *)wh->i_dur = htole16(dur); 1314 } 1315 1316 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1317 1318 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1319 m0->m_pkthdr.len, rate); 1320 1321 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1322 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1323 1324 return 0; 1325} 1326 1327static void 1328ural_start(struct ifnet *ifp) 1329{ 1330 struct ural_softc *sc = ifp->if_softc; 1331 struct ieee80211_node *ni; 1332 struct mbuf *m; 1333 1334 RAL_LOCK(sc); 1335 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1336 RAL_UNLOCK(sc); 1337 return; 1338 } 1339 for (;;) { 1340 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1341 if (m == NULL) 1342 break; 1343 if (sc->tx_nfree < RAL_TX_MINFREE) { 1344 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1345 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1346 break; 1347 } 1348 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1349 if (ural_tx_data(sc, m, ni) != 0) { 1350 ieee80211_free_node(ni); 1351 ifp->if_oerrors++; 1352 break; 1353 } 1354 } 1355 RAL_UNLOCK(sc); 1356} 1357 1358static int 1359ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1360{ 1361 struct ural_softc *sc = ifp->if_softc; 1362 struct ieee80211com *ic = ifp->if_l2com; 1363 struct ifreq *ifr = (struct ifreq *) data; 1364 int error = 0, startall = 0; 1365 1366 switch (cmd) { 1367 case SIOCSIFFLAGS: 1368 RAL_LOCK(sc); 1369 if (ifp->if_flags & IFF_UP) { 1370 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1371 ural_init_locked(sc); 1372 startall = 1; 1373 } else 1374 ural_setpromisc(sc); 1375 } else { 1376 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1377 ural_stop(sc); 1378 } 1379 RAL_UNLOCK(sc); 1380 if (startall) 1381 ieee80211_start_all(ic); 1382 break; 1383 case SIOCGIFMEDIA: 1384 case SIOCSIFMEDIA: 1385 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1386 break; 1387 default: 1388 error = ether_ioctl(ifp, cmd, data); 1389 break; 1390 } 1391 return error; 1392} 1393 1394static void 1395ural_set_testmode(struct ural_softc *sc) 1396{ 1397 struct usb_device_request req; 1398 usb_error_t error; 1399 1400 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1401 req.bRequest = RAL_VENDOR_REQUEST; 1402 USETW(req.wValue, 4); 1403 USETW(req.wIndex, 1); 1404 USETW(req.wLength, 0); 1405 1406 error = ural_do_request(sc, &req, NULL); 1407 if (error != 0) { 1408 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1409 usbd_errstr(error)); 1410 } 1411} 1412 1413static void 1414ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1415{ 1416 struct usb_device_request req; 1417 usb_error_t error; 1418 1419 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1420 req.bRequest = RAL_READ_EEPROM; 1421 USETW(req.wValue, 0); 1422 USETW(req.wIndex, addr); 1423 USETW(req.wLength, len); 1424 1425 error = ural_do_request(sc, &req, buf); 1426 if (error != 0) { 1427 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1428 usbd_errstr(error)); 1429 } 1430} 1431 1432static uint16_t 1433ural_read(struct ural_softc *sc, uint16_t reg) 1434{ 1435 struct usb_device_request req; 1436 usb_error_t error; 1437 uint16_t val; 1438 1439 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1440 req.bRequest = RAL_READ_MAC; 1441 USETW(req.wValue, 0); 1442 USETW(req.wIndex, reg); 1443 USETW(req.wLength, sizeof (uint16_t)); 1444 1445 error = ural_do_request(sc, &req, &val); 1446 if (error != 0) { 1447 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1448 usbd_errstr(error)); 1449 return 0; 1450 } 1451 1452 return le16toh(val); 1453} 1454 1455static void 1456ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1457{ 1458 struct usb_device_request req; 1459 usb_error_t error; 1460 1461 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1462 req.bRequest = RAL_READ_MULTI_MAC; 1463 USETW(req.wValue, 0); 1464 USETW(req.wIndex, reg); 1465 USETW(req.wLength, len); 1466 1467 error = ural_do_request(sc, &req, buf); 1468 if (error != 0) { 1469 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1470 usbd_errstr(error)); 1471 } 1472} 1473 1474static void 1475ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1476{ 1477 struct usb_device_request req; 1478 usb_error_t error; 1479 1480 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1481 req.bRequest = RAL_WRITE_MAC; 1482 USETW(req.wValue, val); 1483 USETW(req.wIndex, reg); 1484 USETW(req.wLength, 0); 1485 1486 error = ural_do_request(sc, &req, NULL); 1487 if (error != 0) { 1488 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1489 usbd_errstr(error)); 1490 } 1491} 1492 1493static void 1494ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1495{ 1496 struct usb_device_request req; 1497 usb_error_t error; 1498 1499 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1500 req.bRequest = RAL_WRITE_MULTI_MAC; 1501 USETW(req.wValue, 0); 1502 USETW(req.wIndex, reg); 1503 USETW(req.wLength, len); 1504 1505 error = ural_do_request(sc, &req, buf); 1506 if (error != 0) { 1507 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1508 usbd_errstr(error)); 1509 } 1510} 1511 1512static void 1513ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1514{ 1515 uint16_t tmp; 1516 int ntries; 1517 1518 for (ntries = 0; ntries < 100; ntries++) { 1519 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1520 break; 1521 if (ural_pause(sc, hz / 100)) 1522 break; 1523 } 1524 if (ntries == 100) { 1525 device_printf(sc->sc_dev, "could not write to BBP\n"); 1526 return; 1527 } 1528 1529 tmp = reg << 8 | val; 1530 ural_write(sc, RAL_PHY_CSR7, tmp); 1531} 1532 1533static uint8_t 1534ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1535{ 1536 uint16_t val; 1537 int ntries; 1538 1539 val = RAL_BBP_WRITE | reg << 8; 1540 ural_write(sc, RAL_PHY_CSR7, val); 1541 1542 for (ntries = 0; ntries < 100; ntries++) { 1543 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1544 break; 1545 if (ural_pause(sc, hz / 100)) 1546 break; 1547 } 1548 if (ntries == 100) { 1549 device_printf(sc->sc_dev, "could not read BBP\n"); 1550 return 0; 1551 } 1552 1553 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1554} 1555 1556static void 1557ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1558{ 1559 uint32_t tmp; 1560 int ntries; 1561 1562 for (ntries = 0; ntries < 100; ntries++) { 1563 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1564 break; 1565 if (ural_pause(sc, hz / 100)) 1566 break; 1567 } 1568 if (ntries == 100) { 1569 device_printf(sc->sc_dev, "could not write to RF\n"); 1570 return; 1571 } 1572 1573 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1574 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1575 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1576 1577 /* remember last written value in sc */ 1578 sc->rf_regs[reg] = val; 1579 1580 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1581} 1582 1583static void 1584ural_scan_start(struct ieee80211com *ic) 1585{ 1586 struct ifnet *ifp = ic->ic_ifp; 1587 struct ural_softc *sc = ifp->if_softc; 1588 1589 RAL_LOCK(sc); 1590 ural_write(sc, RAL_TXRX_CSR19, 0); 1591 ural_set_bssid(sc, ifp->if_broadcastaddr); 1592 RAL_UNLOCK(sc); 1593} 1594 1595static void 1596ural_scan_end(struct ieee80211com *ic) 1597{ 1598 struct ural_softc *sc = ic->ic_ifp->if_softc; 1599 1600 RAL_LOCK(sc); 1601 ural_enable_tsf_sync(sc); 1602 ural_set_bssid(sc, sc->sc_bssid); 1603 RAL_UNLOCK(sc); 1604 1605} 1606 1607static void 1608ural_set_channel(struct ieee80211com *ic) 1609{ 1610 struct ural_softc *sc = ic->ic_ifp->if_softc; 1611 1612 RAL_LOCK(sc); 1613 ural_set_chan(sc, ic->ic_curchan); 1614 RAL_UNLOCK(sc); 1615} 1616 1617static void 1618ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1619{ 1620 struct ifnet *ifp = sc->sc_ifp; 1621 struct ieee80211com *ic = ifp->if_l2com; 1622 uint8_t power, tmp; 1623 int i, chan; 1624 1625 chan = ieee80211_chan2ieee(ic, c); 1626 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1627 return; 1628 1629 if (IEEE80211_IS_CHAN_2GHZ(c)) 1630 power = min(sc->txpow[chan - 1], 31); 1631 else 1632 power = 31; 1633 1634 /* adjust txpower using ifconfig settings */ 1635 power -= (100 - ic->ic_txpowlimit) / 8; 1636 1637 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1638 1639 switch (sc->rf_rev) { 1640 case RAL_RF_2522: 1641 ural_rf_write(sc, RAL_RF1, 0x00814); 1642 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1643 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1644 break; 1645 1646 case RAL_RF_2523: 1647 ural_rf_write(sc, RAL_RF1, 0x08804); 1648 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1649 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1650 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1651 break; 1652 1653 case RAL_RF_2524: 1654 ural_rf_write(sc, RAL_RF1, 0x0c808); 1655 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1656 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1657 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1658 break; 1659 1660 case RAL_RF_2525: 1661 ural_rf_write(sc, RAL_RF1, 0x08808); 1662 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1663 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1664 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1665 1666 ural_rf_write(sc, RAL_RF1, 0x08808); 1667 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1668 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1669 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1670 break; 1671 1672 case RAL_RF_2525E: 1673 ural_rf_write(sc, RAL_RF1, 0x08808); 1674 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1675 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1676 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1677 break; 1678 1679 case RAL_RF_2526: 1680 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1681 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1682 ural_rf_write(sc, RAL_RF1, 0x08804); 1683 1684 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1685 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1686 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1687 break; 1688 1689 /* dual-band RF */ 1690 case RAL_RF_5222: 1691 for (i = 0; ural_rf5222[i].chan != chan; i++); 1692 1693 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1694 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1695 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1696 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1697 break; 1698 } 1699 1700 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1701 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1702 /* set Japan filter bit for channel 14 */ 1703 tmp = ural_bbp_read(sc, 70); 1704 1705 tmp &= ~RAL_JAPAN_FILTER; 1706 if (chan == 14) 1707 tmp |= RAL_JAPAN_FILTER; 1708 1709 ural_bbp_write(sc, 70, tmp); 1710 1711 /* clear CRC errors */ 1712 ural_read(sc, RAL_STA_CSR0); 1713 1714 ural_pause(sc, hz / 100); 1715 ural_disable_rf_tune(sc); 1716 } 1717 1718 /* XXX doesn't belong here */ 1719 /* update basic rate set */ 1720 ural_set_basicrates(sc, c); 1721 1722 /* give the hardware some time to do the switchover */ 1723 ural_pause(sc, hz / 100); 1724} 1725 1726/* 1727 * Disable RF auto-tuning. 1728 */ 1729static void 1730ural_disable_rf_tune(struct ural_softc *sc) 1731{ 1732 uint32_t tmp; 1733 1734 if (sc->rf_rev != RAL_RF_2523) { 1735 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1736 ural_rf_write(sc, RAL_RF1, tmp); 1737 } 1738 1739 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1740 ural_rf_write(sc, RAL_RF3, tmp); 1741 1742 DPRINTFN(2, "disabling RF autotune\n"); 1743} 1744 1745/* 1746 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1747 * synchronization. 1748 */ 1749static void 1750ural_enable_tsf_sync(struct ural_softc *sc) 1751{ 1752 struct ifnet *ifp = sc->sc_ifp; 1753 struct ieee80211com *ic = ifp->if_l2com; 1754 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1755 uint16_t logcwmin, preload, tmp; 1756 1757 /* first, disable TSF synchronization */ 1758 ural_write(sc, RAL_TXRX_CSR19, 0); 1759 1760 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1761 ural_write(sc, RAL_TXRX_CSR18, tmp); 1762 1763 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1764 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1765 tmp = logcwmin << 12 | preload; 1766 ural_write(sc, RAL_TXRX_CSR20, tmp); 1767 1768 /* finally, enable TSF synchronization */ 1769 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1770 if (ic->ic_opmode == IEEE80211_M_STA) 1771 tmp |= RAL_ENABLE_TSF_SYNC(1); 1772 else 1773 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1774 ural_write(sc, RAL_TXRX_CSR19, tmp); 1775 1776 DPRINTF("enabling TSF synchronization\n"); 1777} 1778 1779static void 1780ural_enable_tsf(struct ural_softc *sc) 1781{ 1782 /* first, disable TSF synchronization */ 1783 ural_write(sc, RAL_TXRX_CSR19, 0); 1784 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1785} 1786 1787#define RAL_RXTX_TURNAROUND 5 /* us */ 1788static void 1789ural_update_slot(struct ifnet *ifp) 1790{ 1791 struct ural_softc *sc = ifp->if_softc; 1792 struct ieee80211com *ic = ifp->if_l2com; 1793 uint16_t slottime, sifs, eifs; 1794 1795 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1796 1797 /* 1798 * These settings may sound a bit inconsistent but this is what the 1799 * reference driver does. 1800 */ 1801 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1802 sifs = 16 - RAL_RXTX_TURNAROUND; 1803 eifs = 364; 1804 } else { 1805 sifs = 10 - RAL_RXTX_TURNAROUND; 1806 eifs = 64; 1807 } 1808 1809 ural_write(sc, RAL_MAC_CSR10, slottime); 1810 ural_write(sc, RAL_MAC_CSR11, sifs); 1811 ural_write(sc, RAL_MAC_CSR12, eifs); 1812} 1813 1814static void 1815ural_set_txpreamble(struct ural_softc *sc) 1816{ 1817 struct ifnet *ifp = sc->sc_ifp; 1818 struct ieee80211com *ic = ifp->if_l2com; 1819 uint16_t tmp; 1820 1821 tmp = ural_read(sc, RAL_TXRX_CSR10); 1822 1823 tmp &= ~RAL_SHORT_PREAMBLE; 1824 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1825 tmp |= RAL_SHORT_PREAMBLE; 1826 1827 ural_write(sc, RAL_TXRX_CSR10, tmp); 1828} 1829 1830static void 1831ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1832{ 1833 /* XXX wrong, take from rate set */ 1834 /* update basic rate set */ 1835 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1836 /* 11a basic rates: 6, 12, 24Mbps */ 1837 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1838 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1839 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1840 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1841 } else { 1842 /* 11b basic rates: 1, 2Mbps */ 1843 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1844 } 1845} 1846 1847static void 1848ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1849{ 1850 uint16_t tmp; 1851 1852 tmp = bssid[0] | bssid[1] << 8; 1853 ural_write(sc, RAL_MAC_CSR5, tmp); 1854 1855 tmp = bssid[2] | bssid[3] << 8; 1856 ural_write(sc, RAL_MAC_CSR6, tmp); 1857 1858 tmp = bssid[4] | bssid[5] << 8; 1859 ural_write(sc, RAL_MAC_CSR7, tmp); 1860 1861 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1862} 1863 1864static void 1865ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1866{ 1867 uint16_t tmp; 1868 1869 tmp = addr[0] | addr[1] << 8; 1870 ural_write(sc, RAL_MAC_CSR2, tmp); 1871 1872 tmp = addr[2] | addr[3] << 8; 1873 ural_write(sc, RAL_MAC_CSR3, tmp); 1874 1875 tmp = addr[4] | addr[5] << 8; 1876 ural_write(sc, RAL_MAC_CSR4, tmp); 1877 1878 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1879} 1880 1881static void 1882ural_setpromisc(struct ural_softc *sc) 1883{ 1884 struct ifnet *ifp = sc->sc_ifp; 1885 uint32_t tmp; 1886 1887 tmp = ural_read(sc, RAL_TXRX_CSR2); 1888 1889 tmp &= ~RAL_DROP_NOT_TO_ME; 1890 if (!(ifp->if_flags & IFF_PROMISC)) 1891 tmp |= RAL_DROP_NOT_TO_ME; 1892 1893 ural_write(sc, RAL_TXRX_CSR2, tmp); 1894 1895 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 1896 "entering" : "leaving"); 1897} 1898 1899static void 1900ural_update_promisc(struct ifnet *ifp) 1901{ 1902 struct ural_softc *sc = ifp->if_softc; 1903 1904 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1905 return; 1906 1907 RAL_LOCK(sc); 1908 ural_setpromisc(sc); 1909 RAL_UNLOCK(sc); 1910} 1911 1912static const char * 1913ural_get_rf(int rev) 1914{ 1915 switch (rev) { 1916 case RAL_RF_2522: return "RT2522"; 1917 case RAL_RF_2523: return "RT2523"; 1918 case RAL_RF_2524: return "RT2524"; 1919 case RAL_RF_2525: return "RT2525"; 1920 case RAL_RF_2525E: return "RT2525e"; 1921 case RAL_RF_2526: return "RT2526"; 1922 case RAL_RF_5222: return "RT5222"; 1923 default: return "unknown"; 1924 } 1925} 1926 1927static void 1928ural_read_eeprom(struct ural_softc *sc) 1929{ 1930 uint16_t val; 1931 1932 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1933 val = le16toh(val); 1934 sc->rf_rev = (val >> 11) & 0x7; 1935 sc->hw_radio = (val >> 10) & 0x1; 1936 sc->led_mode = (val >> 6) & 0x7; 1937 sc->rx_ant = (val >> 4) & 0x3; 1938 sc->tx_ant = (val >> 2) & 0x3; 1939 sc->nb_ant = val & 0x3; 1940 1941 /* read MAC address */ 1942 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 1943 1944 /* read default values for BBP registers */ 1945 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1946 1947 /* read Tx power for all b/g channels */ 1948 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1949} 1950 1951static int 1952ural_bbp_init(struct ural_softc *sc) 1953{ 1954#define N(a) (sizeof (a) / sizeof ((a)[0])) 1955 int i, ntries; 1956 1957 /* wait for BBP to be ready */ 1958 for (ntries = 0; ntries < 100; ntries++) { 1959 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1960 break; 1961 if (ural_pause(sc, hz / 100)) 1962 break; 1963 } 1964 if (ntries == 100) { 1965 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1966 return EIO; 1967 } 1968 1969 /* initialize BBP registers to default values */ 1970 for (i = 0; i < N(ural_def_bbp); i++) 1971 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1972 1973#if 0 1974 /* initialize BBP registers to values stored in EEPROM */ 1975 for (i = 0; i < 16; i++) { 1976 if (sc->bbp_prom[i].reg == 0xff) 1977 continue; 1978 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1979 } 1980#endif 1981 1982 return 0; 1983#undef N 1984} 1985 1986static void 1987ural_set_txantenna(struct ural_softc *sc, int antenna) 1988{ 1989 uint16_t tmp; 1990 uint8_t tx; 1991 1992 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1993 if (antenna == 1) 1994 tx |= RAL_BBP_ANTA; 1995 else if (antenna == 2) 1996 tx |= RAL_BBP_ANTB; 1997 else 1998 tx |= RAL_BBP_DIVERSITY; 1999 2000 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2001 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2002 sc->rf_rev == RAL_RF_5222) 2003 tx |= RAL_BBP_FLIPIQ; 2004 2005 ural_bbp_write(sc, RAL_BBP_TX, tx); 2006 2007 /* update values in PHY_CSR5 and PHY_CSR6 */ 2008 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2009 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2010 2011 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2012 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2013} 2014 2015static void 2016ural_set_rxantenna(struct ural_softc *sc, int antenna) 2017{ 2018 uint8_t rx; 2019 2020 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2021 if (antenna == 1) 2022 rx |= RAL_BBP_ANTA; 2023 else if (antenna == 2) 2024 rx |= RAL_BBP_ANTB; 2025 else 2026 rx |= RAL_BBP_DIVERSITY; 2027 2028 /* need to force no I/Q flip for RF 2525e and 2526 */ 2029 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2030 rx &= ~RAL_BBP_FLIPIQ; 2031 2032 ural_bbp_write(sc, RAL_BBP_RX, rx); 2033} 2034 2035static void 2036ural_init_locked(struct ural_softc *sc) 2037{ 2038#define N(a) (sizeof (a) / sizeof ((a)[0])) 2039 struct ifnet *ifp = sc->sc_ifp; 2040 struct ieee80211com *ic = ifp->if_l2com; 2041 uint16_t tmp; 2042 int i, ntries; 2043 2044 RAL_LOCK_ASSERT(sc, MA_OWNED); 2045 2046 ural_set_testmode(sc); 2047 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2048 2049 ural_stop(sc); 2050 2051 /* initialize MAC registers to default values */ 2052 for (i = 0; i < N(ural_def_mac); i++) 2053 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2054 2055 /* wait for BBP and RF to wake up (this can take a long time!) */ 2056 for (ntries = 0; ntries < 100; ntries++) { 2057 tmp = ural_read(sc, RAL_MAC_CSR17); 2058 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2059 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2060 break; 2061 if (ural_pause(sc, hz / 100)) 2062 break; 2063 } 2064 if (ntries == 100) { 2065 device_printf(sc->sc_dev, 2066 "timeout waiting for BBP/RF to wakeup\n"); 2067 goto fail; 2068 } 2069 2070 /* we're ready! */ 2071 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2072 2073 /* set basic rate set (will be updated later) */ 2074 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2075 2076 if (ural_bbp_init(sc) != 0) 2077 goto fail; 2078 2079 ural_set_chan(sc, ic->ic_curchan); 2080 2081 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2082 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2083 2084 ural_set_txantenna(sc, sc->tx_ant); 2085 ural_set_rxantenna(sc, sc->rx_ant); 2086 2087 ural_set_macaddr(sc, IF_LLADDR(ifp)); 2088 2089 /* 2090 * Allocate Tx and Rx xfer queues. 2091 */ 2092 ural_setup_tx_list(sc); 2093 2094 /* kick Rx */ 2095 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2096 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2097 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2098 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2099 tmp |= RAL_DROP_TODS; 2100 if (!(ifp->if_flags & IFF_PROMISC)) 2101 tmp |= RAL_DROP_NOT_TO_ME; 2102 } 2103 ural_write(sc, RAL_TXRX_CSR2, tmp); 2104 2105 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2106 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2107 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2108 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2109 return; 2110 2111fail: ural_stop(sc); 2112#undef N 2113} 2114 2115static void 2116ural_init(void *priv) 2117{ 2118 struct ural_softc *sc = priv; 2119 struct ifnet *ifp = sc->sc_ifp; 2120 struct ieee80211com *ic = ifp->if_l2com; 2121 2122 RAL_LOCK(sc); 2123 ural_init_locked(sc); 2124 RAL_UNLOCK(sc); 2125 2126 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2127 ieee80211_start_all(ic); /* start all vap's */ 2128} 2129 2130static void 2131ural_stop(struct ural_softc *sc) 2132{ 2133 struct ifnet *ifp = sc->sc_ifp; 2134 2135 RAL_LOCK_ASSERT(sc, MA_OWNED); 2136 2137 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2138 2139 /* 2140 * Drain all the transfers, if not already drained: 2141 */ 2142 RAL_UNLOCK(sc); 2143 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2144 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2145 RAL_LOCK(sc); 2146 2147 ural_unsetup_tx_list(sc); 2148 2149 /* disable Rx */ 2150 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2151 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2152 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2153 /* wait a little */ 2154 ural_pause(sc, hz / 10); 2155 ural_write(sc, RAL_MAC_CSR1, 0); 2156 /* wait a little */ 2157 ural_pause(sc, hz / 10); 2158} 2159 2160static int 2161ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2162 const struct ieee80211_bpf_params *params) 2163{ 2164 struct ieee80211com *ic = ni->ni_ic; 2165 struct ifnet *ifp = ic->ic_ifp; 2166 struct ural_softc *sc = ifp->if_softc; 2167 2168 RAL_LOCK(sc); 2169 /* prevent management frames from being sent if we're not ready */ 2170 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2171 RAL_UNLOCK(sc); 2172 m_freem(m); 2173 ieee80211_free_node(ni); 2174 return ENETDOWN; 2175 } 2176 if (sc->tx_nfree < RAL_TX_MINFREE) { 2177 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2178 RAL_UNLOCK(sc); 2179 m_freem(m); 2180 ieee80211_free_node(ni); 2181 return EIO; 2182 } 2183 2184 ifp->if_opackets++; 2185 2186 if (params == NULL) { 2187 /* 2188 * Legacy path; interpret frame contents to decide 2189 * precisely how to send the frame. 2190 */ 2191 if (ural_tx_mgt(sc, m, ni) != 0) 2192 goto bad; 2193 } else { 2194 /* 2195 * Caller supplied explicit parameters to use in 2196 * sending the frame. 2197 */ 2198 if (ural_tx_raw(sc, m, ni, params) != 0) 2199 goto bad; 2200 } 2201 RAL_UNLOCK(sc); 2202 return 0; 2203bad: 2204 ifp->if_oerrors++; 2205 RAL_UNLOCK(sc); 2206 ieee80211_free_node(ni); 2207 return EIO; /* XXX */ 2208} 2209 2210static void 2211ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2212{ 2213 struct ieee80211vap *vap = ni->ni_vap; 2214 struct ural_vap *uvp = URAL_VAP(vap); 2215 2216 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2217 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2218 2219 ieee80211_ratectl_node_init(ni); 2220 2221 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2222} 2223 2224static void 2225ural_ratectl_timeout(void *arg) 2226{ 2227 struct ural_vap *uvp = arg; 2228 struct ieee80211vap *vap = &uvp->vap; 2229 struct ieee80211com *ic = vap->iv_ic; 2230 2231 ieee80211_runtask(ic, &uvp->ratectl_task); 2232} 2233 2234static void 2235ural_ratectl_task(void *arg, int pending) 2236{ 2237 struct ural_vap *uvp = arg; 2238 struct ieee80211vap *vap = &uvp->vap; 2239 struct ieee80211com *ic = vap->iv_ic; 2240 struct ifnet *ifp = ic->ic_ifp; 2241 struct ural_softc *sc = ifp->if_softc; 2242 struct ieee80211_node *ni; 2243 int ok, fail; 2244 int sum, retrycnt; 2245 2246 ni = ieee80211_ref_node(vap->iv_bss); 2247 RAL_LOCK(sc); 2248 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2249 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2250 2251 ok = sc->sta[7] + /* TX ok w/o retry */ 2252 sc->sta[8]; /* TX ok w/ retry */ 2253 fail = sc->sta[9]; /* TX retry-fail count */ 2254 sum = ok+fail; 2255 retrycnt = sc->sta[8] + fail; 2256 2257 ieee80211_ratectl_tx_update(vap, ni, &sum, &ok, &retrycnt); 2258 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2259 2260 ifp->if_oerrors += fail; /* count TX retry-fail as Tx errors */ 2261 2262 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2263 RAL_UNLOCK(sc); 2264 ieee80211_free_node(ni); 2265} 2266 2267static int 2268ural_pause(struct ural_softc *sc, int timeout) 2269{ 2270 2271 usb_pause_mtx(&sc->sc_mtx, timeout); 2272 return (0); 2273} 2274