if_ural.c revision 190526
1195609Smp/* $FreeBSD: head/sys/dev/usb/wlan/if_ural.c 190526 2009-03-29 17:59:14Z sam $ */ 259243Sobrien 359243Sobrien/*- 459243Sobrien * Copyright (c) 2005, 2006 559243Sobrien * Damien Bergamini <damien.bergamini@free.fr> 659243Sobrien * 759243Sobrien * Copyright (c) 2006, 2008 859243Sobrien * Hans Petter Selasky <hselasky@FreeBSD.org> 959243Sobrien * 1059243Sobrien * Permission to use, copy, modify, and distribute this software for any 1159243Sobrien * purpose with or without fee is hereby granted, provided that the above 1259243Sobrien * copyright notice and this permission notice appear in all copies. 1359243Sobrien * 1459243Sobrien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1559243Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1659243Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1759243Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1859243Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1959243Sobrien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 2059243Sobrien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 2159243Sobrien */ 2259243Sobrien 2359243Sobrien#include <sys/cdefs.h> 2459243Sobrien__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_ural.c 190526 2009-03-29 17:59:14Z sam $"); 2559243Sobrien 2659243Sobrien/*- 2759243Sobrien * Ralink Technology RT2500USB chipset driver 2859243Sobrien * http://www.ralinktech.com/ 2959243Sobrien */ 3059243Sobrien 3159243Sobrien#include "usbdevs.h" 3259243Sobrien#include <dev/usb/usb.h> 3359243Sobrien#include <dev/usb/usb_mfunc.h> 3459243Sobrien#include <dev/usb/usb_error.h> 3559243Sobrien 3659243Sobrien#define USB_DEBUG_VAR ural_debug 3759243Sobrien 3859243Sobrien#include <dev/usb/usb_core.h> 3959243Sobrien#include <dev/usb/usb_lookup.h> 4059243Sobrien#include <dev/usb/usb_process.h> 4159243Sobrien#include <dev/usb/usb_debug.h> 4259243Sobrien#include <dev/usb/usb_request.h> 4359243Sobrien#include <dev/usb/usb_busdma.h> 4459243Sobrien#include <dev/usb/usb_util.h> 4559243Sobrien 4659243Sobrien#include <dev/usb/wlan/usb_wlan.h> 4759243Sobrien#include <dev/usb/wlan/if_uralreg.h> 4859243Sobrien#include <dev/usb/wlan/if_uralvar.h> 4959243Sobrien 5059243Sobrien#if USB_DEBUG 5159243Sobrienstatic int ural_debug = 0; 5259243Sobrien 5359243SobrienSYSCTL_NODE(_hw_usb2, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 5459243SobrienSYSCTL_INT(_hw_usb2_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 5559243Sobrien "Debug level"); 5659243Sobrien#endif 5759243Sobrien 5859243Sobrien#define URAL_RSSI(rssi) \ 5959243Sobrien ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 6059243Sobrien ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 6159243Sobrien 6259243Sobrien/* various supported device vendors/products */ 6359243Sobrienstatic const struct usb2_device_id ural_devs[] = { 6459243Sobrien { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_ASUS_WL167G) }, 6559243Sobrien { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_RALINK_RT2570) }, 6659243Sobrien { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7050) }, 6759243Sobrien { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7051) }, 6859243Sobrien { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_HU200TS) }, 6959243Sobrien { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54G) }, 7059243Sobrien { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54GP) }, 7159243Sobrien { USB_VP(USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_C54RU) }, 7259243Sobrien { USB_VP(USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWLG122) }, 73100616Smp { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GN54G) }, 7459243Sobrien { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GNWBKG) }, 7559243Sobrien { USB_VP(USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUSB254) }, 7659243Sobrien { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54) }, 7759243Sobrien { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54AI) }, 7859243Sobrien { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54YB) }, 7959243Sobrien { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_NINWIFI) }, 8059243Sobrien { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570) }, 8159243Sobrien { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_2) }, 8259243Sobrien { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_3) }, 8359243Sobrien { USB_VP(USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_NV902) }, 8459243Sobrien { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570) }, 8559243Sobrien { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_2) }, 8659243Sobrien { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_3) }, 8759243Sobrien { USB_VP(USB_VENDOR_SIEMENS2, USB_PRODUCT_SIEMENS2_WL54G) }, 8859243Sobrien { USB_VP(USB_VENDOR_SMC, USB_PRODUCT_SMC_2862WG) }, 8959243Sobrien { USB_VP(USB_VENDOR_SPHAIRON, USB_PRODUCT_SPHAIRON_UB801R) }, 9059243Sobrien { USB_VP(USB_VENDOR_SURECOM, USB_PRODUCT_SURECOM_RT2570) }, 91195609Smp { USB_VP(USB_VENDOR_VTECH, USB_PRODUCT_VTECH_RT2570) }, 9259243Sobrien { USB_VP(USB_VENDOR_ZINWELL, USB_PRODUCT_ZINWELL_RT2570) }, 9359243Sobrien}; 9459243Sobrien 9559243Sobrienstatic usb2_callback_t ural_bulk_read_callback; 9659243Sobrienstatic usb2_callback_t ural_bulk_write_callback; 9759243Sobrien 9859243Sobrienstatic usb2_proc_callback_t ural_command_wrapper; 9959243Sobrienstatic usb2_proc_callback_t ural_attach_post; 10059243Sobrienstatic usb2_proc_callback_t ural_task; 10159243Sobrienstatic usb2_proc_callback_t ural_scantask; 10259243Sobrienstatic usb2_proc_callback_t ural_promisctask; 10359243Sobrienstatic usb2_proc_callback_t ural_amrr_task; 10459243Sobrienstatic usb2_proc_callback_t ural_init_task; 10559243Sobrienstatic usb2_proc_callback_t ural_stop_task; 10659243Sobrienstatic usb2_proc_callback_t ural_flush_task; 10759243Sobrien 10859243Sobrienstatic usb2_error_t ural_do_request(struct ural_softc *sc, 10959243Sobrien struct usb2_device_request *req, void *data); 11059243Sobrienstatic struct ieee80211vap *ural_vap_create(struct ieee80211com *, 11159243Sobrien const char name[IFNAMSIZ], int unit, int opmode, 11259243Sobrien int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 11359243Sobrien const uint8_t mac[IEEE80211_ADDR_LEN]); 11459243Sobrienstatic void ural_vap_delete(struct ieee80211vap *); 11559243Sobrienstatic void ural_tx_free(struct ural_tx_data *, int); 11659243Sobrienstatic void ural_setup_tx_list(struct ural_softc *); 11759243Sobrienstatic void ural_unsetup_tx_list(struct ural_softc *); 118167465Smpstatic int ural_newstate(struct ieee80211vap *, 119167465Smp enum ieee80211_state, int); 120167465Smpstatic void ural_setup_tx_desc(struct ural_softc *, 121167465Smp struct ural_tx_desc *, uint32_t, int, int); 122167465Smpstatic int ural_tx_bcn(struct ural_softc *, struct mbuf *, 123167465Smp struct ieee80211_node *); 124167465Smpstatic int ural_tx_mgt(struct ural_softc *, struct mbuf *, 125167465Smp struct ieee80211_node *); 126167465Smpstatic int ural_tx_data(struct ural_softc *, struct mbuf *, 12759243Sobrien struct ieee80211_node *); 12859243Sobrienstatic void ural_start(struct ifnet *); 12959243Sobrienstatic int ural_ioctl(struct ifnet *, u_long, caddr_t); 130167465Smpstatic void ural_set_testmode(struct ural_softc *); 13159243Sobrienstatic void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 13259243Sobrien int); 13359243Sobrienstatic uint16_t ural_read(struct ural_softc *, uint16_t); 13459243Sobrienstatic void ural_read_multi(struct ural_softc *, uint16_t, void *, 13559243Sobrien int); 13659243Sobrienstatic void ural_write(struct ural_softc *, uint16_t, uint16_t); 13759243Sobrienstatic void ural_write_multi(struct ural_softc *, uint16_t, void *, 138167465Smp int) __unused; 13959243Sobrienstatic void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 14059243Sobrienstatic uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 14159243Sobrienstatic void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 14259243Sobrienstatic struct ieee80211_node *ural_node_alloc(struct ieee80211vap *, 14359243Sobrien const uint8_t mac[IEEE80211_ADDR_LEN]); 14459243Sobrienstatic void ural_newassoc(struct ieee80211_node *, int); 14559243Sobrienstatic void ural_scan_start(struct ieee80211com *); 14659243Sobrienstatic void ural_scan_end(struct ieee80211com *); 14759243Sobrienstatic void ural_set_channel(struct ieee80211com *); 14859243Sobrienstatic void ural_set_chan(struct ural_softc *, 14959243Sobrien struct ieee80211_channel *); 15059243Sobrienstatic void ural_disable_rf_tune(struct ural_softc *); 151167465Smpstatic void ural_enable_tsf_sync(struct ural_softc *); 15259243Sobrienstatic void ural_update_slot(struct ifnet *); 15359243Sobrienstatic void ural_set_txpreamble(struct ural_softc *); 15459243Sobrienstatic void ural_set_basicrates(struct ural_softc *, 15559243Sobrien const struct ieee80211_channel *); 15659243Sobrienstatic void ural_set_bssid(struct ural_softc *, const uint8_t *); 15759243Sobrienstatic void ural_set_macaddr(struct ural_softc *, uint8_t *); 15859243Sobrienstatic void ural_update_promisc(struct ifnet *); 15959243Sobrienstatic const char *ural_get_rf(int); 16059243Sobrienstatic void ural_read_eeprom(struct ural_softc *); 16159243Sobrienstatic int ural_bbp_init(struct ural_softc *); 16259243Sobrienstatic void ural_set_txantenna(struct ural_softc *, int); 16359243Sobrienstatic void ural_set_rxantenna(struct ural_softc *, int); 16459243Sobrienstatic void ural_init(void *); 165167465Smpstatic int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 16659243Sobrien const struct ieee80211_bpf_params *); 16759243Sobrienstatic void ural_amrr_start(struct ural_softc *, 16859243Sobrien struct ieee80211_node *); 16959243Sobrienstatic void ural_amrr_timeout(void *); 17059243Sobrienstatic int ural_pause(struct ural_softc *sc, int timeout); 17159243Sobrienstatic void ural_queue_command(struct ural_softc *, 17259243Sobrien usb2_proc_callback_t *, struct usb2_proc_msg *, 17359243Sobrien struct usb2_proc_msg *); 17459243Sobrien 175167465Smp/* 17659243Sobrien * Default values for MAC registers; values taken from the reference driver. 17759243Sobrien */ 17859243Sobrienstatic const struct { 17959243Sobrien uint16_t reg; 18059243Sobrien uint16_t val; 18159243Sobrien} ural_def_mac[] = { 18259243Sobrien { RAL_TXRX_CSR5, 0x8c8d }, 18359243Sobrien { RAL_TXRX_CSR6, 0x8b8a }, 18459243Sobrien { RAL_TXRX_CSR7, 0x8687 }, 18559243Sobrien { RAL_TXRX_CSR8, 0x0085 }, 18659243Sobrien { RAL_MAC_CSR13, 0x1111 }, 18759243Sobrien { RAL_MAC_CSR14, 0x1e11 }, 18859243Sobrien { RAL_TXRX_CSR21, 0xe78f }, 18959243Sobrien { RAL_MAC_CSR9, 0xff1d }, 19059243Sobrien { RAL_MAC_CSR11, 0x0002 }, 19159243Sobrien { RAL_MAC_CSR22, 0x0053 }, 19259243Sobrien { RAL_MAC_CSR15, 0x0000 }, 19359243Sobrien { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 19459243Sobrien { RAL_TXRX_CSR19, 0x0000 }, 19559243Sobrien { RAL_TXRX_CSR18, 0x005a }, 19659243Sobrien { RAL_PHY_CSR2, 0x0000 }, 19759243Sobrien { RAL_TXRX_CSR0, 0x1ec0 }, 19859243Sobrien { RAL_PHY_CSR4, 0x000f } 19959243Sobrien}; 20059243Sobrien 20159243Sobrien/* 20259243Sobrien * Default values for BBP registers; values taken from the reference driver. 20359243Sobrien */ 20459243Sobrienstatic const struct { 20559243Sobrien uint8_t reg; 20659243Sobrien uint8_t val; 20759243Sobrien} ural_def_bbp[] = { 20859243Sobrien { 3, 0x02 }, 20959243Sobrien { 4, 0x19 }, 21059243Sobrien { 14, 0x1c }, 21159243Sobrien { 15, 0x30 }, 21259243Sobrien { 16, 0xac }, 213167465Smp { 17, 0x48 }, 21459243Sobrien { 18, 0x18 }, 21559243Sobrien { 19, 0xff }, 21659243Sobrien { 20, 0x1e }, 21759243Sobrien { 21, 0x08 }, 21859243Sobrien { 22, 0x08 }, 219195609Smp { 23, 0x08 }, 22059243Sobrien { 24, 0x80 }, 22159243Sobrien { 25, 0x50 }, 22259243Sobrien { 26, 0x08 }, 22359243Sobrien { 27, 0x23 }, 224195609Smp { 30, 0x10 }, 225195609Smp { 31, 0x2b }, 22659243Sobrien { 32, 0xb9 }, 22759243Sobrien { 34, 0x12 }, 22859243Sobrien { 35, 0x50 }, 22959243Sobrien { 39, 0xc4 }, 23059243Sobrien { 40, 0x02 }, 23159243Sobrien { 41, 0x60 }, 23259243Sobrien { 53, 0x10 }, 23359243Sobrien { 54, 0x18 }, 23459243Sobrien { 56, 0x08 }, 23559243Sobrien { 57, 0x10 }, 23659243Sobrien { 58, 0x08 }, 23759243Sobrien { 61, 0x60 }, 23859243Sobrien { 62, 0x10 }, 239167465Smp { 75, 0xff } 24059243Sobrien}; 24159243Sobrien 24259243Sobrien/* 24359243Sobrien * Default values for RF register R2 indexed by channel numbers. 24459243Sobrien */ 24559243Sobrienstatic const uint32_t ural_rf2522_r2[] = { 24659243Sobrien 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 24759243Sobrien 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 24859243Sobrien}; 24959243Sobrien 25059243Sobrienstatic const uint32_t ural_rf2523_r2[] = { 25159243Sobrien 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 25259243Sobrien 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 25359243Sobrien}; 25459243Sobrien 25559243Sobrienstatic const uint32_t ural_rf2524_r2[] = { 25659243Sobrien 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 25759243Sobrien 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 258167465Smp}; 259167465Smp 26059243Sobrienstatic const uint32_t ural_rf2525_r2[] = { 26159243Sobrien 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 26259243Sobrien 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 26359243Sobrien}; 26459243Sobrien 26559243Sobrienstatic const uint32_t ural_rf2525_hi_r2[] = { 26659243Sobrien 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 26759243Sobrien 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 26859243Sobrien}; 269167465Smp 27059243Sobrienstatic const uint32_t ural_rf2525e_r2[] = { 27159243Sobrien 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 27259243Sobrien 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 27359243Sobrien}; 27459243Sobrien 27559243Sobrienstatic const uint32_t ural_rf2526_hi_r2[] = { 27659243Sobrien 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 27759243Sobrien 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 27859243Sobrien}; 27959243Sobrien 28059243Sobrienstatic const uint32_t ural_rf2526_r2[] = { 28159243Sobrien 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 28259243Sobrien 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 28359243Sobrien}; 28459243Sobrien 28559243Sobrien/* 28659243Sobrien * For dual-band RF, RF registers R1 and R4 also depend on channel number; 287167465Smp * values taken from the reference driver. 288167465Smp */ 289167465Smpstatic const struct { 29059243Sobrien uint8_t chan; 29159243Sobrien uint32_t r1; 29259243Sobrien uint32_t r2; 29359243Sobrien uint32_t r4; 29459243Sobrien} ural_rf5222[] = { 29559243Sobrien { 1, 0x08808, 0x0044d, 0x00282 }, 29659243Sobrien { 2, 0x08808, 0x0044e, 0x00282 }, 29759243Sobrien { 3, 0x08808, 0x0044f, 0x00282 }, 29859243Sobrien { 4, 0x08808, 0x00460, 0x00282 }, 29959243Sobrien { 5, 0x08808, 0x00461, 0x00282 }, 30059243Sobrien { 6, 0x08808, 0x00462, 0x00282 }, 30159243Sobrien { 7, 0x08808, 0x00463, 0x00282 }, 30259243Sobrien { 8, 0x08808, 0x00464, 0x00282 }, 30359243Sobrien { 9, 0x08808, 0x00465, 0x00282 }, 30459243Sobrien { 10, 0x08808, 0x00466, 0x00282 }, 30559243Sobrien { 11, 0x08808, 0x00467, 0x00282 }, 306167465Smp { 12, 0x08808, 0x00468, 0x00282 }, 30759243Sobrien { 13, 0x08808, 0x00469, 0x00282 }, 30859243Sobrien { 14, 0x08808, 0x0046b, 0x00286 }, 30959243Sobrien 31059243Sobrien { 36, 0x08804, 0x06225, 0x00287 }, 31159243Sobrien { 40, 0x08804, 0x06226, 0x00287 }, 31259243Sobrien { 44, 0x08804, 0x06227, 0x00287 }, 31359243Sobrien { 48, 0x08804, 0x06228, 0x00287 }, 31459243Sobrien { 52, 0x08804, 0x06229, 0x00287 }, 31559243Sobrien { 56, 0x08804, 0x0622a, 0x00287 }, 316167465Smp { 60, 0x08804, 0x0622b, 0x00287 }, 31759243Sobrien { 64, 0x08804, 0x0622c, 0x00287 }, 318167465Smp 319167465Smp { 100, 0x08804, 0x02200, 0x00283 }, 320167465Smp { 104, 0x08804, 0x02201, 0x00283 }, 321167465Smp { 108, 0x08804, 0x02202, 0x00283 }, 322195609Smp { 112, 0x08804, 0x02203, 0x00283 }, 323195609Smp { 116, 0x08804, 0x02204, 0x00283 }, 32459243Sobrien { 120, 0x08804, 0x02205, 0x00283 }, 32559243Sobrien { 124, 0x08804, 0x02206, 0x00283 }, 32659243Sobrien { 128, 0x08804, 0x02207, 0x00283 }, 32759243Sobrien { 132, 0x08804, 0x02208, 0x00283 }, 32859243Sobrien { 136, 0x08804, 0x02209, 0x00283 }, 32959243Sobrien { 140, 0x08804, 0x0220a, 0x00283 }, 330167465Smp 33159243Sobrien { 149, 0x08808, 0x02429, 0x00281 }, 33259243Sobrien { 153, 0x08808, 0x0242b, 0x00281 }, 33359243Sobrien { 157, 0x08808, 0x0242d, 0x00281 }, 334167465Smp { 161, 0x08808, 0x0242f, 0x00281 } 33559243Sobrien}; 336167465Smp 33759243Sobrienstatic const struct usb2_config ural_config[URAL_N_TRANSFER] = { 33859243Sobrien [URAL_BULK_WR] = { 33959243Sobrien .type = UE_BULK, 34059243Sobrien .endpoint = UE_ADDR_ANY, 34159243Sobrien .direction = UE_DIR_OUT, 34259243Sobrien .mh.bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 34359243Sobrien .mh.flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 34459243Sobrien .mh.callback = ural_bulk_write_callback, 34559243Sobrien .mh.timeout = 5000, /* ms */ 34659243Sobrien }, 34759243Sobrien [URAL_BULK_RD] = { 34859243Sobrien .type = UE_BULK, 34959243Sobrien .endpoint = UE_ADDR_ANY, 35059243Sobrien .direction = UE_DIR_IN, 35159243Sobrien .mh.bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 352167465Smp .mh.flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 35359243Sobrien .mh.callback = ural_bulk_read_callback, 35459243Sobrien }, 35559243Sobrien}; 35659243Sobrien 35759243Sobrienstatic device_probe_t ural_match; 35859243Sobrienstatic device_attach_t ural_attach; 35959243Sobrienstatic device_detach_t ural_detach; 36059243Sobrien 361167465Smpstatic device_method_t ural_methods[] = { 36259243Sobrien /* Device interface */ 36359243Sobrien DEVMETHOD(device_probe, ural_match), 36459243Sobrien DEVMETHOD(device_attach, ural_attach), 36559243Sobrien DEVMETHOD(device_detach, ural_detach), 36659243Sobrien 36759243Sobrien { 0, 0 } 36859243Sobrien}; 369167465Smp 37059243Sobrienstatic driver_t ural_driver = { 37159243Sobrien .name = "ural", 37259243Sobrien .methods = ural_methods, 37359243Sobrien .size = sizeof(struct ural_softc), 37459243Sobrien}; 37559243Sobrien 37659243Sobrienstatic devclass_t ural_devclass; 37759243Sobrien 37859243SobrienDRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 37959243SobrienMODULE_DEPEND(ural, usb, 1, 1, 1); 38059243SobrienMODULE_DEPEND(ural, wlan, 1, 1, 1); 38159243SobrienMODULE_DEPEND(ural, wlan_amrr, 1, 1, 1); 38259243Sobrien 383167465Smpstatic int 38459243Sobrienural_match(device_t self) 38559243Sobrien{ 38659243Sobrien struct usb2_attach_arg *uaa = device_get_ivars(self); 38759243Sobrien 38859243Sobrien if (uaa->usb2_mode != USB_MODE_HOST) 38959243Sobrien return (ENXIO); 39059243Sobrien if (uaa->info.bConfigIndex != 0) 39159243Sobrien return (ENXIO); 39259243Sobrien if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 39359243Sobrien return (ENXIO); 39459243Sobrien 39559243Sobrien return (usb2_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 39659243Sobrien} 39759243Sobrien 39859243Sobrienstatic int 39959243Sobrienural_attach(device_t self) 40059243Sobrien{ 401167465Smp struct usb2_attach_arg *uaa = device_get_ivars(self); 40259243Sobrien struct ural_softc *sc = device_get_softc(self); 40359243Sobrien int error; 40459243Sobrien uint8_t iface_index; 40559243Sobrien 40659243Sobrien device_set_usb2_desc(self); 407167465Smp sc->sc_udev = uaa->device; 40859243Sobrien sc->sc_dev = self; 40959243Sobrien 41059243Sobrien mtx_init(&sc->sc_mtx, device_get_nameunit(self), 41159243Sobrien MTX_NETWORK_LOCK, MTX_DEF); 41259243Sobrien 41359243Sobrien cv_init(&sc->sc_cmd_cv, "wtxdone"); 41459243Sobrien 415167465Smp iface_index = RAL_IFACE_INDEX; 41659243Sobrien error = usb2_transfer_setup(uaa->device, 41759243Sobrien &iface_index, sc->sc_xfer, ural_config, 41859243Sobrien URAL_N_TRANSFER, sc, &sc->sc_mtx); 419167465Smp if (error) { 42059243Sobrien device_printf(self, "could not allocate USB transfers, " 42159243Sobrien "err=%s\n", usb2_errstr(error)); 42259243Sobrien goto detach; 42359243Sobrien } 42459243Sobrien error = usb2_proc_create(&sc->sc_tq, &sc->sc_mtx, 42559243Sobrien device_get_nameunit(self), USB_PRI_MED); 42659243Sobrien if (error) { 42759243Sobrien device_printf(self, "could not setup config thread!\n"); 42859243Sobrien goto detach; 42959243Sobrien } 43059243Sobrien 43159243Sobrien /* fork rest of the attach code */ 43259243Sobrien RAL_LOCK(sc); 43359243Sobrien ural_queue_command(sc, ural_attach_post, 43459243Sobrien &sc->sc_synctask[0].hdr, 435167465Smp &sc->sc_synctask[1].hdr); 43659243Sobrien RAL_UNLOCK(sc); 437167465Smp return (0); 43859243Sobrien 43959243Sobriendetach: 44059243Sobrien ural_detach(self); 44159243Sobrien return (ENXIO); /* failure */ 44259243Sobrien} 44359243Sobrien 44459243Sobrienstatic void 44559243Sobrienural_attach_post(struct usb2_proc_msg *pm) 44659243Sobrien{ 44759243Sobrien struct ural_task *task = (struct ural_task *)pm; 44859243Sobrien struct ural_softc *sc = task->sc; 44959243Sobrien struct ifnet *ifp; 45059243Sobrien struct ieee80211com *ic; 45159243Sobrien uint8_t bands; 452167465Smp 453167465Smp /* retrieve RT2570 rev. no */ 454167465Smp sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 45559243Sobrien 45659243Sobrien /* retrieve MAC address and various other things from EEPROM */ 457167465Smp ural_read_eeprom(sc); 45859243Sobrien 45959243Sobrien /* XXX Async attach race */ 46059243Sobrien if (usb2_proc_is_gone(&sc->sc_tq)) 46159243Sobrien return; 46259243Sobrien 46359243Sobrien RAL_UNLOCK(sc); 46459243Sobrien 465167465Smp device_printf(sc->sc_dev, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 46659243Sobrien sc->asic_rev, ural_get_rf(sc->rf_rev)); 46759243Sobrien 46859243Sobrien ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 46959243Sobrien if (ifp == NULL) { 47059243Sobrien device_printf(sc->sc_dev, "can not if_alloc()\n"); 47159243Sobrien RAL_LOCK(sc); 472167465Smp return; 47359243Sobrien } 47459243Sobrien ic = ifp->if_l2com; 47559243Sobrien 476167465Smp ifp->if_softc = sc; 47759243Sobrien if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 47859243Sobrien ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 479167465Smp ifp->if_init = ural_init; 48059243Sobrien ifp->if_ioctl = ural_ioctl; 48159243Sobrien ifp->if_start = ural_start; 48259243Sobrien IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 48359243Sobrien ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 48459243Sobrien IFQ_SET_READY(&ifp->if_snd); 485167465Smp 48659243Sobrien ic->ic_ifp = ifp; 48759243Sobrien ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 48859243Sobrien 48959243Sobrien /* set device capabilities */ 490167465Smp ic->ic_caps = 491167465Smp IEEE80211_C_STA /* station mode supported */ 492167465Smp | IEEE80211_C_IBSS /* IBSS mode supported */ 49359243Sobrien | IEEE80211_C_MONITOR /* monitor mode supported */ 49459243Sobrien | IEEE80211_C_HOSTAP /* HostAp mode supported */ 49559243Sobrien | IEEE80211_C_TXPMGT /* tx power management */ 49659243Sobrien | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 49759243Sobrien | IEEE80211_C_SHSLOT /* short slot time supported */ 49859243Sobrien | IEEE80211_C_BGSCAN /* bg scanning supported */ 49959243Sobrien | IEEE80211_C_WPA /* 802.11i */ 50059243Sobrien ; 50159243Sobrien 502167465Smp bands = 0; 50359243Sobrien setbit(&bands, IEEE80211_MODE_11B); 50459243Sobrien setbit(&bands, IEEE80211_MODE_11G); 50559243Sobrien if (sc->rf_rev == RAL_RF_5222) 50659243Sobrien setbit(&bands, IEEE80211_MODE_11A); 50759243Sobrien ieee80211_init_channels(ic, NULL, &bands); 50859243Sobrien 509167465Smp ieee80211_ifattach(ic, sc->sc_bssid); 510167465Smp ic->ic_update_promisc = ural_update_promisc; 51159243Sobrien ic->ic_newassoc = ural_newassoc; 512167465Smp ic->ic_raw_xmit = ural_raw_xmit; 51359243Sobrien ic->ic_node_alloc = ural_node_alloc; 51459243Sobrien ic->ic_scan_start = ural_scan_start; 51559243Sobrien ic->ic_scan_end = ural_scan_end; 51659243Sobrien ic->ic_set_channel = ural_set_channel; 51759243Sobrien 518167465Smp ic->ic_vap_create = ural_vap_create; 51959243Sobrien ic->ic_vap_delete = ural_vap_delete; 52059243Sobrien 521167465Smp sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 522167465Smp 52359243Sobrien bpfattach(ifp, DLT_IEEE802_11_RADIO, 52459243Sobrien sizeof (struct ieee80211_frame) + sizeof(sc->sc_txtap)); 525167465Smp 526167465Smp sc->sc_rxtap_len = sizeof sc->sc_rxtap; 527167465Smp sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 52859243Sobrien sc->sc_rxtap.wr_ihdr.it_present = htole32(RAL_RX_RADIOTAP_PRESENT); 52959243Sobrien 530167465Smp sc->sc_txtap_len = sizeof sc->sc_txtap; 53159243Sobrien sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 53259243Sobrien sc->sc_txtap.wt_ihdr.it_present = htole32(RAL_TX_RADIOTAP_PRESENT); 533167465Smp 534167465Smp if (bootverbose) 535167465Smp ieee80211_announce(ic); 536167465Smp 53759243Sobrien RAL_LOCK(sc); 53859243Sobrien} 53959243Sobrien 54059243Sobrienstatic int 54159243Sobrienural_detach(device_t self) 54259243Sobrien{ 54359243Sobrien struct ural_softc *sc = device_get_softc(self); 544167465Smp struct ifnet *ifp = sc->sc_ifp; 545167465Smp struct ieee80211com *ic; 54659243Sobrien 54759243Sobrien /* wait for any post attach or other command to complete */ 548145479Smp usb2_proc_drain(&sc->sc_tq); 54959243Sobrien 550167465Smp /* stop all USB transfers */ 55159243Sobrien usb2_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 55259243Sobrien usb2_proc_free(&sc->sc_tq); 55359243Sobrien 554167465Smp /* free TX list, if any */ 555167465Smp RAL_LOCK(sc); 556167465Smp ural_unsetup_tx_list(sc); 557167465Smp RAL_UNLOCK(sc); 558167465Smp 559167465Smp if (ifp) { 560167465Smp ic = ifp->if_l2com; 56159243Sobrien bpfdetach(ifp); 562167465Smp ieee80211_ifdetach(ic); 56359243Sobrien if_free(ifp); 56459243Sobrien } 56559243Sobrien cv_destroy(&sc->sc_cmd_cv); 56659243Sobrien mtx_destroy(&sc->sc_mtx); 56759243Sobrien 56859243Sobrien return (0); 56959243Sobrien} 57059243Sobrien 57159243Sobrienstatic usb2_error_t 57259243Sobrienural_do_request(struct ural_softc *sc, 573167465Smp struct usb2_device_request *req, void *data) 57459243Sobrien{ 57559243Sobrien usb2_error_t err; 576167465Smp int ntries = 10; 577167465Smp 57859243Sobrien while (ntries--) { 57959243Sobrien err = usb2_do_request_proc(sc->sc_udev, &sc->sc_tq, 580167465Smp req, data, 0, NULL, 250 /* ms */); 581167465Smp if (err == 0) 58259243Sobrien break; 583167465Smp 584167465Smp DPRINTFN(1, "Control request failed, %s (retrying)\n", 585167465Smp usb2_errstr(err)); 586167465Smp if (ural_pause(sc, hz / 100)) 587167465Smp break; 58869408Sache } 589167465Smp return (err); 59069408Sache} 591167465Smp 59269408Sachestatic struct ieee80211vap * 59359243Sobrienural_vap_create(struct ieee80211com *ic, 594167465Smp const char name[IFNAMSIZ], int unit, int opmode, int flags, 595167465Smp const uint8_t bssid[IEEE80211_ADDR_LEN], 596167465Smp const uint8_t mac[IEEE80211_ADDR_LEN]) 597167465Smp{ 598167465Smp struct ural_softc *sc = ic->ic_ifp->if_softc; 599167465Smp struct ural_vap *uvp; 600167465Smp struct ieee80211vap *vap; 601167465Smp 60259243Sobrien if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 60359243Sobrien return NULL; 604167465Smp uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 605167465Smp M_80211_VAP, M_NOWAIT | M_ZERO); 606167465Smp if (uvp == NULL) 607167465Smp return NULL; 60859243Sobrien vap = &uvp->vap; 60959243Sobrien /* enable s/w bmiss handling for sta mode */ 61059243Sobrien ieee80211_vap_setup(ic, vap, name, unit, opmode, 611145479Smp flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 612167465Smp 61359243Sobrien /* override state transition machine */ 61459243Sobrien uvp->newstate = vap->iv_newstate; 61559243Sobrien vap->iv_newstate = ural_newstate; 61659243Sobrien 61759243Sobrien uvp->sc = sc; 61859243Sobrien usb2_callout_init_mtx(&uvp->amrr_ch, &sc->sc_mtx, 0); 61959243Sobrien ieee80211_amrr_init(&uvp->amrr, vap, 620167465Smp IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 621145479Smp IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 62259243Sobrien 1000 /* 1 sec */); 62359243Sobrien 62459243Sobrien /* complete setup */ 62559243Sobrien ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 62659243Sobrien ic->ic_opmode = opmode; 62759243Sobrien return vap; 62859243Sobrien} 62959243Sobrien 63059243Sobrienstatic void 63159243Sobrienural_flush_task(struct usb2_proc_msg *pm) 63259243Sobrien{ 63359243Sobrien /* nothing to do */ 63459243Sobrien} 63559243Sobrien 63659243Sobrienstatic void 63759243Sobrienural_vap_delete(struct ieee80211vap *vap) 63859243Sobrien{ 63959243Sobrien struct ural_vap *uvp = URAL_VAP(vap); 64059243Sobrien struct ural_softc *sc = uvp->sc; 64159243Sobrien 64259243Sobrien RAL_LOCK(sc); 64359243Sobrien /* wait for any pending tasks to complete */ 64459243Sobrien ural_queue_command(sc, ural_flush_task, 64559243Sobrien &sc->sc_synctask[0].hdr, 64659243Sobrien &sc->sc_synctask[1].hdr); 64759243Sobrien RAL_UNLOCK(sc); 64859243Sobrien 64959243Sobrien usb2_callout_drain(&uvp->amrr_ch); 65083098Smp ieee80211_amrr_cleanup(&uvp->amrr); 65183098Smp ieee80211_vap_detach(vap); 65283098Smp free(uvp, M_80211_VAP); 65359243Sobrien} 65459243Sobrien 65559243Sobrienstatic void 65659243Sobrienural_tx_free(struct ural_tx_data *data, int txerr) 65759243Sobrien{ 65859243Sobrien struct ural_softc *sc = data->sc; 65959243Sobrien 66059243Sobrien if (data->m != NULL) { 66159243Sobrien if (data->m->m_flags & M_TXCB) 662145479Smp ieee80211_process_callback(data->ni, data->m, 663145479Smp txerr ? ETIMEDOUT : 0); 66459243Sobrien m_freem(data->m); 66559243Sobrien data->m = NULL; 66659243Sobrien 66759243Sobrien ieee80211_free_node(data->ni); 66859243Sobrien data->ni = NULL; 66959243Sobrien } 67059243Sobrien STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 67159243Sobrien sc->tx_nfree++; 67259243Sobrien} 673167465Smp 674195609Smpstatic void 67559243Sobrienural_setup_tx_list(struct ural_softc *sc) 67659243Sobrien{ 67759243Sobrien struct ural_tx_data *data; 67869408Sache int i; 67959243Sobrien 68059243Sobrien sc->tx_nfree = 0; 68159243Sobrien STAILQ_INIT(&sc->tx_q); 68259243Sobrien STAILQ_INIT(&sc->tx_free); 68359243Sobrien 68459243Sobrien for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 68559243Sobrien data = &sc->tx_data[i]; 68659243Sobrien 68759243Sobrien data->sc = sc; 68859243Sobrien STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 68959243Sobrien sc->tx_nfree++; 69059243Sobrien } 69159243Sobrien} 69259243Sobrien 69359243Sobrienstatic void 69459243Sobrienural_unsetup_tx_list(struct ural_softc *sc) 69569408Sache{ 69659243Sobrien struct ural_tx_data *data; 69769408Sache int i; 69859243Sobrien 69959243Sobrien /* make sure any subsequent use of the queues will fail */ 70059243Sobrien sc->tx_nfree = 0; 70159243Sobrien STAILQ_INIT(&sc->tx_q); 70269408Sache STAILQ_INIT(&sc->tx_free); 70359243Sobrien 70459243Sobrien /* free up all node references and mbufs */ 70559243Sobrien for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 70659243Sobrien data = &sc->tx_data[i]; 70759243Sobrien 70859243Sobrien if (data->m != NULL) { 70959243Sobrien m_freem(data->m); 71059243Sobrien data->m = NULL; 71159243Sobrien } 712167465Smp if (data->ni != NULL) { 71359243Sobrien ieee80211_free_node(data->ni); 714167465Smp data->ni = NULL; 71559243Sobrien } 71659243Sobrien } 71759243Sobrien} 718167465Smp 719167465Smpstatic void 72059243Sobrienural_task(struct usb2_proc_msg *pm) 72159243Sobrien{ 72269408Sache struct ural_task *task = (struct ural_task *)pm; 72359243Sobrien struct ural_softc *sc = task->sc; 72469408Sache struct ifnet *ifp = sc->sc_ifp; 72559243Sobrien struct ieee80211com *ic = ifp->if_l2com; 72669408Sache struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 72759243Sobrien struct ural_vap *uvp = URAL_VAP(vap); 72859243Sobrien const struct ieee80211_txparam *tp; 72959243Sobrien enum ieee80211_state ostate; 73059243Sobrien struct ieee80211_node *ni; 73159243Sobrien struct mbuf *m; 73259243Sobrien 73359243Sobrien ostate = vap->iv_state; 73459243Sobrien 735167465Smp switch (sc->sc_state) { 73659243Sobrien case IEEE80211_S_INIT: 73769408Sache if (ostate == IEEE80211_S_RUN) { 738167465Smp /* abort TSF synchronization */ 73969408Sache ural_write(sc, RAL_TXRX_CSR19, 0); 74059243Sobrien 74159243Sobrien /* force tx led to stop blinking */ 74259243Sobrien ural_write(sc, RAL_MAC_CSR20, 0); 74359243Sobrien } 74459243Sobrien break; 745145479Smp 746145479Smp case IEEE80211_S_RUN: 74759243Sobrien ni = vap->iv_bss; 74859243Sobrien 74959243Sobrien if (vap->iv_opmode != IEEE80211_M_MONITOR) { 75059243Sobrien ural_update_slot(ic->ic_ifp); 75159243Sobrien ural_set_txpreamble(sc); 75259243Sobrien ural_set_basicrates(sc, ic->ic_bsschan); 75359243Sobrien IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 75459243Sobrien ural_set_bssid(sc, sc->sc_bssid); 75569408Sache } 75659243Sobrien 75769408Sache if (vap->iv_opmode == IEEE80211_M_HOSTAP || 75859243Sobrien vap->iv_opmode == IEEE80211_M_IBSS) { 75969408Sache m = ieee80211_beacon_alloc(ni, &uvp->bo); 76059243Sobrien if (m == NULL) { 76159243Sobrien device_printf(sc->sc_dev, 76259243Sobrien "could not allocate beacon\n"); 763 return; 764 } 765 766 if (ural_tx_bcn(sc, m, ni) != 0) { 767 device_printf(sc->sc_dev, 768 "could not send beacon\n"); 769 return; 770 } 771 } 772 773 /* make tx led blink on tx (controlled by ASIC) */ 774 ural_write(sc, RAL_MAC_CSR20, 1); 775 776 if (vap->iv_opmode != IEEE80211_M_MONITOR) 777 ural_enable_tsf_sync(sc); 778 779 /* enable automatic rate adaptation */ 780 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 781 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 782 ural_amrr_start(sc, ni); 783 784 break; 785 786 default: 787 break; 788 } 789 790 RAL_UNLOCK(sc); 791 IEEE80211_LOCK(ic); 792 uvp->newstate(vap, sc->sc_state, sc->sc_arg); 793 if (vap->iv_newstate_cb != NULL) 794 vap->iv_newstate_cb(vap, sc->sc_state, sc->sc_arg); 795 IEEE80211_UNLOCK(ic); 796 RAL_LOCK(sc); 797} 798 799static void 800ural_scantask(struct usb2_proc_msg *pm) 801{ 802 struct ural_task *task = (struct ural_task *)pm; 803 struct ural_softc *sc = task->sc; 804 struct ifnet *ifp = sc->sc_ifp; 805 struct ieee80211com *ic = ifp->if_l2com; 806 807 RAL_LOCK_ASSERT(sc, MA_OWNED); 808 809 switch (sc->sc_scan_action) { 810 case URAL_SCAN_START: 811 /* abort TSF synchronization */ 812 DPRINTF("starting scan\n"); 813 ural_write(sc, RAL_TXRX_CSR19, 0); 814 ural_set_bssid(sc, ifp->if_broadcastaddr); 815 break; 816 817 case URAL_SET_CHANNEL: 818 ural_set_chan(sc, ic->ic_curchan); 819 break; 820 821 default: /* URAL_SCAN_END */ 822 DPRINTF("stopping scan\n"); 823 ural_enable_tsf_sync(sc); 824 ural_set_bssid(sc, sc->sc_bssid); 825 break; 826 } 827} 828 829static int 830ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 831{ 832 struct ural_vap *uvp = URAL_VAP(vap); 833 struct ieee80211com *ic = vap->iv_ic; 834 struct ural_softc *sc = ic->ic_ifp->if_softc; 835 836 DPRINTF("%s -> %s\n", 837 ieee80211_state_name[vap->iv_state], 838 ieee80211_state_name[nstate]); 839 840 RAL_LOCK(sc); 841 usb2_callout_stop(&uvp->amrr_ch); 842 843 /* do it in a process context */ 844 sc->sc_state = nstate; 845 sc->sc_arg = arg; 846 RAL_UNLOCK(sc); 847 848 if (nstate == IEEE80211_S_INIT) { 849 uvp->newstate(vap, nstate, arg); 850 return 0; 851 } else { 852 RAL_LOCK(sc); 853 ural_queue_command(sc, ural_task, &sc->sc_task[0].hdr, 854 &sc->sc_task[1].hdr); 855 RAL_UNLOCK(sc); 856 return EINPROGRESS; 857 } 858} 859 860 861static void 862ural_bulk_write_callback(struct usb2_xfer *xfer) 863{ 864 struct ural_softc *sc = xfer->priv_sc; 865 struct ifnet *ifp = sc->sc_ifp; 866 struct ieee80211com *ic = ifp->if_l2com; 867 struct ieee80211_channel *c = ic->ic_curchan; 868 struct ural_tx_data *data; 869 struct mbuf *m; 870 unsigned int len; 871 872 /* wakeup waiting command, if any */ 873 if (sc->sc_last_task != NULL) 874 cv_signal(&sc->sc_cmd_cv); 875 876 switch (USB_GET_STATE(xfer)) { 877 case USB_ST_TRANSFERRED: 878 DPRINTFN(11, "transfer complete, %d bytes\n", xfer->actlen); 879 880 /* free resources */ 881 data = xfer->priv_fifo; 882 ural_tx_free(data, 0); 883 xfer->priv_fifo = NULL; 884 885 ifp->if_opackets++; 886 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 887 888 /* FALLTHROUGH */ 889 case USB_ST_SETUP: 890tr_setup: 891 /* wait for command to complete, if any */ 892 if (sc->sc_last_task != NULL) 893 break; 894 895 data = STAILQ_FIRST(&sc->tx_q); 896 if (data) { 897 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 898 m = data->m; 899 900 if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 901 DPRINTFN(0, "data overflow, %u bytes\n", 902 m->m_pkthdr.len); 903 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 904 } 905 usb2_copy_in(xfer->frbuffers, 0, &data->desc, 906 RAL_TX_DESC_SIZE); 907 usb2_m_copy_in(xfer->frbuffers, RAL_TX_DESC_SIZE, m, 0, 908 m->m_pkthdr.len); 909 910 if (bpf_peers_present(ifp->if_bpf)) { 911 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 912 913 tap->wt_flags = 0; 914 tap->wt_rate = data->rate; 915 tap->wt_chan_freq = htole16(c->ic_freq); 916 tap->wt_chan_flags = htole16(c->ic_flags); 917 tap->wt_antenna = sc->tx_ant; 918 919 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m); 920 } 921 922 /* xfer length needs to be a multiple of two! */ 923 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 924 if ((len % 64) == 0) 925 len += 2; 926 927 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 928 m->m_pkthdr.len, len); 929 930 xfer->frlengths[0] = len; 931 xfer->priv_fifo = data; 932 933 usb2_start_hardware(xfer); 934 } 935 break; 936 937 default: /* Error */ 938 DPRINTFN(11, "transfer error, %s\n", 939 usb2_errstr(xfer->error)); 940 941 ifp->if_oerrors++; 942 data = xfer->priv_fifo; 943 if (data != NULL) { 944 ural_tx_free(data, xfer->error); 945 xfer->priv_fifo = NULL; 946 } 947 948 if (xfer->error == USB_ERR_STALLED) { 949 /* try to clear stall first */ 950 xfer->flags.stall_pipe = 1; 951 goto tr_setup; 952 } 953 if (xfer->error == USB_ERR_TIMEOUT) 954 device_printf(sc->sc_dev, "device timeout\n"); 955 break; 956 } 957} 958 959static void 960ural_bulk_read_callback(struct usb2_xfer *xfer) 961{ 962 struct ural_softc *sc = xfer->priv_sc; 963 struct ifnet *ifp = sc->sc_ifp; 964 struct ieee80211com *ic = ifp->if_l2com; 965 struct ieee80211_node *ni; 966 struct mbuf *m = NULL; 967 uint32_t flags; 968 uint8_t rssi = 0; 969 unsigned int len; 970 971 switch (USB_GET_STATE(xfer)) { 972 case USB_ST_TRANSFERRED: 973 974 DPRINTFN(15, "rx done, actlen=%d\n", xfer->actlen); 975 976 len = xfer->actlen; 977 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 978 DPRINTF("%s: xfer too short %d\n", 979 device_get_nameunit(sc->sc_dev), len); 980 ifp->if_ierrors++; 981 goto tr_setup; 982 } 983 984 len -= RAL_RX_DESC_SIZE; 985 /* rx descriptor is located at the end */ 986 usb2_copy_out(xfer->frbuffers, len, &sc->sc_rx_desc, 987 RAL_RX_DESC_SIZE); 988 989 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 990 flags = le32toh(sc->sc_rx_desc.flags); 991 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 992 /* 993 * This should not happen since we did not 994 * request to receive those frames when we 995 * filled RAL_TXRX_CSR2: 996 */ 997 DPRINTFN(5, "PHY or CRC error\n"); 998 ifp->if_ierrors++; 999 goto tr_setup; 1000 } 1001 1002 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1003 if (m == NULL) { 1004 DPRINTF("could not allocate mbuf\n"); 1005 ifp->if_ierrors++; 1006 goto tr_setup; 1007 } 1008 usb2_copy_out(xfer->frbuffers, 0, mtod(m, uint8_t *), len); 1009 1010 /* finalize mbuf */ 1011 m->m_pkthdr.rcvif = ifp; 1012 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 1013 1014 if (bpf_peers_present(ifp->if_bpf)) { 1015 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 1016 1017 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1018 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 1019 (flags & RAL_RX_OFDM) ? 1020 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1021 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1022 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1023 tap->wr_antenna = sc->rx_ant; 1024 tap->wr_antsignal = rssi; 1025 1026 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1027 } 1028 /* Strip trailing 802.11 MAC FCS. */ 1029 m_adj(m, -IEEE80211_CRC_LEN); 1030 1031 /* FALLTHROUGH */ 1032 case USB_ST_SETUP: 1033tr_setup: 1034 xfer->frlengths[0] = xfer->max_data_length; 1035 usb2_start_hardware(xfer); 1036 1037 /* 1038 * At the end of a USB callback it is always safe to unlock 1039 * the private mutex of a device! That is why we do the 1040 * "ieee80211_input" here, and not some lines up! 1041 */ 1042 if (m) { 1043 RAL_UNLOCK(sc); 1044 ni = ieee80211_find_rxnode(ic, 1045 mtod(m, struct ieee80211_frame_min *)); 1046 if (ni != NULL) { 1047 (void) ieee80211_input(ni, m, rssi, 1048 RAL_NOISE_FLOOR, 0); 1049 ieee80211_free_node(ni); 1050 } else 1051 (void) ieee80211_input_all(ic, m, rssi, 1052 RAL_NOISE_FLOOR, 0); 1053 RAL_LOCK(sc); 1054 } 1055 return; 1056 1057 default: /* Error */ 1058 if (xfer->error != USB_ERR_CANCELLED) { 1059 /* try to clear stall first */ 1060 xfer->flags.stall_pipe = 1; 1061 goto tr_setup; 1062 } 1063 return; 1064 } 1065} 1066 1067static uint8_t 1068ural_plcp_signal(int rate) 1069{ 1070 switch (rate) { 1071 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1072 case 12: return 0xb; 1073 case 18: return 0xf; 1074 case 24: return 0xa; 1075 case 36: return 0xe; 1076 case 48: return 0x9; 1077 case 72: return 0xd; 1078 case 96: return 0x8; 1079 case 108: return 0xc; 1080 1081 /* CCK rates (NB: not IEEE std, device-specific) */ 1082 case 2: return 0x0; 1083 case 4: return 0x1; 1084 case 11: return 0x2; 1085 case 22: return 0x3; 1086 } 1087 return 0xff; /* XXX unsupported/unknown rate */ 1088} 1089 1090static void 1091ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 1092 uint32_t flags, int len, int rate) 1093{ 1094 struct ifnet *ifp = sc->sc_ifp; 1095 struct ieee80211com *ic = ifp->if_l2com; 1096 uint16_t plcp_length; 1097 int remainder; 1098 1099 desc->flags = htole32(flags); 1100 desc->flags |= htole32(RAL_TX_NEWSEQ); 1101 desc->flags |= htole32(len << 16); 1102 1103 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1104 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1105 1106 /* setup PLCP fields */ 1107 desc->plcp_signal = ural_plcp_signal(rate); 1108 desc->plcp_service = 4; 1109 1110 len += IEEE80211_CRC_LEN; 1111 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 1112 desc->flags |= htole32(RAL_TX_OFDM); 1113 1114 plcp_length = len & 0xfff; 1115 desc->plcp_length_hi = plcp_length >> 6; 1116 desc->plcp_length_lo = plcp_length & 0x3f; 1117 } else { 1118 plcp_length = (16 * len + rate - 1) / rate; 1119 if (rate == 22) { 1120 remainder = (16 * len) % 22; 1121 if (remainder != 0 && remainder < 7) 1122 desc->plcp_service |= RAL_PLCP_LENGEXT; 1123 } 1124 desc->plcp_length_hi = plcp_length >> 8; 1125 desc->plcp_length_lo = plcp_length & 0xff; 1126 1127 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1128 desc->plcp_signal |= 0x08; 1129 } 1130 1131 desc->iv = 0; 1132 desc->eiv = 0; 1133} 1134 1135#define RAL_TX_TIMEOUT 5000 1136 1137static int 1138ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1139{ 1140 struct ieee80211vap *vap = ni->ni_vap; 1141 struct ieee80211com *ic = ni->ni_ic; 1142 struct ifnet *ifp = sc->sc_ifp; 1143 const struct ieee80211_txparam *tp; 1144 struct ural_tx_data *data; 1145 1146 if (sc->tx_nfree == 0) { 1147 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1148 m_freem(m0); 1149 ieee80211_free_node(ni); 1150 return EIO; 1151 } 1152 data = STAILQ_FIRST(&sc->tx_free); 1153 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1154 sc->tx_nfree--; 1155 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1156 1157 data->m = m0; 1158 data->ni = ni; 1159 data->rate = tp->mgmtrate; 1160 1161 ural_setup_tx_desc(sc, &data->desc, 1162 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1163 tp->mgmtrate); 1164 1165 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1166 m0->m_pkthdr.len, tp->mgmtrate); 1167 1168 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1169 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1170 1171 return (0); 1172} 1173 1174static int 1175ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1176{ 1177 struct ieee80211vap *vap = ni->ni_vap; 1178 struct ieee80211com *ic = ni->ni_ic; 1179 const struct ieee80211_txparam *tp; 1180 struct ural_tx_data *data; 1181 struct ieee80211_frame *wh; 1182 struct ieee80211_key *k; 1183 uint32_t flags; 1184 uint16_t dur; 1185 1186 RAL_LOCK_ASSERT(sc, MA_OWNED); 1187 1188 data = STAILQ_FIRST(&sc->tx_free); 1189 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1190 sc->tx_nfree--; 1191 1192 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1193 1194 wh = mtod(m0, struct ieee80211_frame *); 1195 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1196 k = ieee80211_crypto_encap(ni, m0); 1197 if (k == NULL) { 1198 m_freem(m0); 1199 return ENOBUFS; 1200 } 1201 wh = mtod(m0, struct ieee80211_frame *); 1202 } 1203 1204 data->m = m0; 1205 data->ni = ni; 1206 data->rate = tp->mgmtrate; 1207 1208 flags = 0; 1209 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1210 flags |= RAL_TX_ACK; 1211 1212 dur = ieee80211_ack_duration(sc->sc_rates, tp->mgmtrate, 1213 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1214 *(uint16_t *)wh->i_dur = htole16(dur); 1215 1216 /* tell hardware to add timestamp for probe responses */ 1217 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1218 IEEE80211_FC0_TYPE_MGT && 1219 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1220 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1221 flags |= RAL_TX_TIMESTAMP; 1222 } 1223 1224 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1225 1226 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1227 m0->m_pkthdr.len, tp->mgmtrate); 1228 1229 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1230 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1231 1232 return 0; 1233} 1234 1235static int 1236ural_sendprot(struct ural_softc *sc, 1237 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1238{ 1239 struct ieee80211com *ic = ni->ni_ic; 1240 const struct ieee80211_frame *wh; 1241 struct ural_tx_data *data; 1242 struct mbuf *mprot; 1243 int protrate, ackrate, pktlen, flags, isshort; 1244 uint16_t dur; 1245 1246 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1247 ("protection %d", prot)); 1248 1249 wh = mtod(m, const struct ieee80211_frame *); 1250 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1251 1252 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 1253 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 1254 1255 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1256 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort); 1257 + ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1258 flags = RAL_TX_RETRY(7); 1259 if (prot == IEEE80211_PROT_RTSCTS) { 1260 /* NB: CTS is the same size as an ACK */ 1261 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1262 flags |= RAL_TX_ACK; 1263 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1264 } else { 1265 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1266 } 1267 if (mprot == NULL) { 1268 /* XXX stat + msg */ 1269 return ENOBUFS; 1270 } 1271 data = STAILQ_FIRST(&sc->tx_free); 1272 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1273 sc->tx_nfree--; 1274 1275 data->m = mprot; 1276 data->ni = ieee80211_ref_node(ni); 1277 data->rate = protrate; 1278 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1279 1280 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1281 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1282 1283 return 0; 1284} 1285 1286static int 1287ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1288 const struct ieee80211_bpf_params *params) 1289{ 1290 struct ural_tx_data *data; 1291 uint32_t flags; 1292 int error; 1293 int rate; 1294 1295 RAL_LOCK_ASSERT(sc, MA_OWNED); 1296 KASSERT(params != NULL, ("no raw xmit params")); 1297 1298 rate = params->ibp_rate0 & IEEE80211_RATE_VAL; 1299 /* XXX validate */ 1300 if (rate == 0) { 1301 m_freem(m0); 1302 return EINVAL; 1303 } 1304 flags = 0; 1305 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1306 flags |= RAL_TX_ACK; 1307 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1308 error = ural_sendprot(sc, m0, ni, 1309 params->ibp_flags & IEEE80211_BPF_RTS ? 1310 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1311 rate); 1312 if (error || sc->tx_nfree == 0) { 1313 m_freem(m0); 1314 return ENOBUFS; 1315 } 1316 flags |= RAL_TX_IFS_SIFS; 1317 } 1318 1319 data = STAILQ_FIRST(&sc->tx_free); 1320 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1321 sc->tx_nfree--; 1322 1323 data->m = m0; 1324 data->ni = ni; 1325 data->rate = rate; 1326 1327 /* XXX need to setup descriptor ourself */ 1328 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1329 1330 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1331 m0->m_pkthdr.len, rate); 1332 1333 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1334 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1335 1336 return 0; 1337} 1338 1339static int 1340ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1341{ 1342 struct ieee80211vap *vap = ni->ni_vap; 1343 struct ieee80211com *ic = ni->ni_ic; 1344 struct ural_tx_data *data; 1345 struct ieee80211_frame *wh; 1346 const struct ieee80211_txparam *tp; 1347 struct ieee80211_key *k; 1348 uint32_t flags = 0; 1349 uint16_t dur; 1350 int error, rate; 1351 1352 RAL_LOCK_ASSERT(sc, MA_OWNED); 1353 1354 wh = mtod(m0, struct ieee80211_frame *); 1355 1356 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1357 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1358 rate = tp->mcastrate; 1359 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1360 rate = tp->ucastrate; 1361 else 1362 rate = ni->ni_txrate; 1363 1364 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1365 k = ieee80211_crypto_encap(ni, m0); 1366 if (k == NULL) { 1367 m_freem(m0); 1368 return ENOBUFS; 1369 } 1370 /* packet header may have moved, reset our local pointer */ 1371 wh = mtod(m0, struct ieee80211_frame *); 1372 } 1373 1374 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1375 int prot = IEEE80211_PROT_NONE; 1376 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1377 prot = IEEE80211_PROT_RTSCTS; 1378 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1379 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 1380 prot = ic->ic_protmode; 1381 if (prot != IEEE80211_PROT_NONE) { 1382 error = ural_sendprot(sc, m0, ni, prot, rate); 1383 if (error || sc->tx_nfree == 0) { 1384 m_freem(m0); 1385 return ENOBUFS; 1386 } 1387 flags |= RAL_TX_IFS_SIFS; 1388 } 1389 } 1390 1391 data = STAILQ_FIRST(&sc->tx_free); 1392 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1393 sc->tx_nfree--; 1394 1395 data->m = m0; 1396 data->ni = ni; 1397 data->rate = rate; 1398 1399 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1400 flags |= RAL_TX_ACK; 1401 flags |= RAL_TX_RETRY(7); 1402 1403 dur = ieee80211_ack_duration(sc->sc_rates, rate, 1404 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1405 *(uint16_t *)wh->i_dur = htole16(dur); 1406 } 1407 1408 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1409 1410 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1411 m0->m_pkthdr.len, rate); 1412 1413 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1414 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1415 1416 return 0; 1417} 1418 1419static void 1420ural_start(struct ifnet *ifp) 1421{ 1422 struct ural_softc *sc = ifp->if_softc; 1423 struct ieee80211_node *ni; 1424 struct mbuf *m; 1425 1426 RAL_LOCK(sc); 1427 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1428 RAL_UNLOCK(sc); 1429 return; 1430 } 1431 for (;;) { 1432 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1433 if (m == NULL) 1434 break; 1435 if (sc->tx_nfree < RAL_TX_MINFREE) { 1436 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1437 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1438 break; 1439 } 1440 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1441 m = ieee80211_encap(ni, m); 1442 if (m == NULL) { 1443 ieee80211_free_node(ni); 1444 ifp->if_oerrors++; 1445 continue; 1446 } 1447 if (ural_tx_data(sc, m, ni) != 0) { 1448 ieee80211_free_node(ni); 1449 ifp->if_oerrors++; 1450 break; 1451 } 1452 } 1453 RAL_UNLOCK(sc); 1454} 1455 1456static int 1457ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1458{ 1459 struct ural_softc *sc = ifp->if_softc; 1460 struct ieee80211com *ic = ifp->if_l2com; 1461 struct ifreq *ifr = (struct ifreq *) data; 1462 int error = 0, startall = 0; 1463 1464 switch (cmd) { 1465 case SIOCSIFFLAGS: 1466 RAL_LOCK(sc); 1467 if (ifp->if_flags & IFF_UP) { 1468 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1469 ural_queue_command(sc, ural_init_task, 1470 &sc->sc_synctask[0].hdr, 1471 &sc->sc_synctask[1].hdr); 1472 startall = 1; 1473 } else 1474 ural_queue_command(sc, ural_promisctask, 1475 &sc->sc_promisctask[0].hdr, 1476 &sc->sc_promisctask[1].hdr); 1477 } else { 1478 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1479 ural_queue_command(sc, ural_stop_task, 1480 &sc->sc_synctask[0].hdr, 1481 &sc->sc_synctask[1].hdr); 1482 } 1483 } 1484 RAL_UNLOCK(sc); 1485 if (startall) 1486 ieee80211_start_all(ic); 1487 break; 1488 case SIOCGIFMEDIA: 1489 case SIOCSIFMEDIA: 1490 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1491 break; 1492 default: 1493 error = ether_ioctl(ifp, cmd, data); 1494 break; 1495 } 1496 return error; 1497} 1498 1499static void 1500ural_set_testmode(struct ural_softc *sc) 1501{ 1502 struct usb2_device_request req; 1503 usb2_error_t error; 1504 1505 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1506 req.bRequest = RAL_VENDOR_REQUEST; 1507 USETW(req.wValue, 4); 1508 USETW(req.wIndex, 1); 1509 USETW(req.wLength, 0); 1510 1511 error = ural_do_request(sc, &req, NULL); 1512 if (error != 0) { 1513 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1514 usb2_errstr(error)); 1515 } 1516} 1517 1518static void 1519ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1520{ 1521 struct usb2_device_request req; 1522 usb2_error_t error; 1523 1524 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1525 req.bRequest = RAL_READ_EEPROM; 1526 USETW(req.wValue, 0); 1527 USETW(req.wIndex, addr); 1528 USETW(req.wLength, len); 1529 1530 error = ural_do_request(sc, &req, buf); 1531 if (error != 0) { 1532 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1533 usb2_errstr(error)); 1534 } 1535} 1536 1537static uint16_t 1538ural_read(struct ural_softc *sc, uint16_t reg) 1539{ 1540 struct usb2_device_request req; 1541 usb2_error_t error; 1542 uint16_t val; 1543 1544 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1545 req.bRequest = RAL_READ_MAC; 1546 USETW(req.wValue, 0); 1547 USETW(req.wIndex, reg); 1548 USETW(req.wLength, sizeof (uint16_t)); 1549 1550 error = ural_do_request(sc, &req, &val); 1551 if (error != 0) { 1552 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1553 usb2_errstr(error)); 1554 return 0; 1555 } 1556 1557 return le16toh(val); 1558} 1559 1560static void 1561ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1562{ 1563 struct usb2_device_request req; 1564 usb2_error_t error; 1565 1566 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1567 req.bRequest = RAL_READ_MULTI_MAC; 1568 USETW(req.wValue, 0); 1569 USETW(req.wIndex, reg); 1570 USETW(req.wLength, len); 1571 1572 error = ural_do_request(sc, &req, buf); 1573 if (error != 0) { 1574 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1575 usb2_errstr(error)); 1576 } 1577} 1578 1579static void 1580ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1581{ 1582 struct usb2_device_request req; 1583 usb2_error_t error; 1584 1585 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1586 req.bRequest = RAL_WRITE_MAC; 1587 USETW(req.wValue, val); 1588 USETW(req.wIndex, reg); 1589 USETW(req.wLength, 0); 1590 1591 error = ural_do_request(sc, &req, NULL); 1592 if (error != 0) { 1593 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1594 usb2_errstr(error)); 1595 } 1596} 1597 1598static void 1599ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1600{ 1601 struct usb2_device_request req; 1602 usb2_error_t error; 1603 1604 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1605 req.bRequest = RAL_WRITE_MULTI_MAC; 1606 USETW(req.wValue, 0); 1607 USETW(req.wIndex, reg); 1608 USETW(req.wLength, len); 1609 1610 error = ural_do_request(sc, &req, buf); 1611 if (error != 0) { 1612 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1613 usb2_errstr(error)); 1614 } 1615} 1616 1617static void 1618ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1619{ 1620 uint16_t tmp; 1621 int ntries; 1622 1623 for (ntries = 0; ntries < 100; ntries++) { 1624 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1625 break; 1626 if (ural_pause(sc, hz / 100)) 1627 break; 1628 } 1629 if (ntries == 100) { 1630 device_printf(sc->sc_dev, "could not write to BBP\n"); 1631 return; 1632 } 1633 1634 tmp = reg << 8 | val; 1635 ural_write(sc, RAL_PHY_CSR7, tmp); 1636} 1637 1638static uint8_t 1639ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1640{ 1641 uint16_t val; 1642 int ntries; 1643 1644 val = RAL_BBP_WRITE | reg << 8; 1645 ural_write(sc, RAL_PHY_CSR7, val); 1646 1647 for (ntries = 0; ntries < 100; ntries++) { 1648 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1649 break; 1650 if (ural_pause(sc, hz / 100)) 1651 break; 1652 } 1653 if (ntries == 100) { 1654 device_printf(sc->sc_dev, "could not read BBP\n"); 1655 return 0; 1656 } 1657 1658 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1659} 1660 1661static void 1662ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1663{ 1664 uint32_t tmp; 1665 int ntries; 1666 1667 for (ntries = 0; ntries < 100; ntries++) { 1668 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1669 break; 1670 if (ural_pause(sc, hz / 100)) 1671 break; 1672 } 1673 if (ntries == 100) { 1674 device_printf(sc->sc_dev, "could not write to RF\n"); 1675 return; 1676 } 1677 1678 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1679 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1680 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1681 1682 /* remember last written value in sc */ 1683 sc->rf_regs[reg] = val; 1684 1685 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1686} 1687 1688/* ARGUSED */ 1689static struct ieee80211_node * 1690ural_node_alloc(struct ieee80211vap *vap __unused, 1691 const uint8_t mac[IEEE80211_ADDR_LEN] __unused) 1692{ 1693 struct ural_node *un; 1694 1695 un = malloc(sizeof(struct ural_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1696 return un != NULL ? &un->ni : NULL; 1697} 1698 1699static void 1700ural_newassoc(struct ieee80211_node *ni, int isnew) 1701{ 1702 struct ieee80211vap *vap = ni->ni_vap; 1703 1704 ieee80211_amrr_node_init(&URAL_VAP(vap)->amrr, &URAL_NODE(ni)->amn, ni); 1705} 1706 1707static void 1708ural_scan_start(struct ieee80211com *ic) 1709{ 1710 struct ural_softc *sc = ic->ic_ifp->if_softc; 1711 1712 RAL_LOCK(sc); 1713 /* do it in a process context */ 1714 sc->sc_scan_action = URAL_SCAN_START; 1715 ural_queue_command(sc, ural_scantask, 1716 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1717 RAL_UNLOCK(sc); 1718 1719} 1720 1721static void 1722ural_scan_end(struct ieee80211com *ic) 1723{ 1724 struct ural_softc *sc = ic->ic_ifp->if_softc; 1725 1726 RAL_LOCK(sc); 1727 /* do it in a process context */ 1728 sc->sc_scan_action = URAL_SCAN_END; 1729 ural_queue_command(sc, ural_scantask, 1730 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1731 RAL_UNLOCK(sc); 1732 1733} 1734 1735static void 1736ural_set_channel(struct ieee80211com *ic) 1737{ 1738 struct ural_softc *sc = ic->ic_ifp->if_softc; 1739 1740 RAL_LOCK(sc); 1741 /* do it in a process context */ 1742 sc->sc_scan_action = URAL_SET_CHANNEL; 1743 ural_queue_command(sc, ural_scantask, 1744 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1745 1746 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 1747 RAL_UNLOCK(sc); 1748} 1749 1750static void 1751ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1752{ 1753 struct ifnet *ifp = sc->sc_ifp; 1754 struct ieee80211com *ic = ifp->if_l2com; 1755 uint8_t power, tmp; 1756 int i, chan; 1757 1758 chan = ieee80211_chan2ieee(ic, c); 1759 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1760 return; 1761 1762 if (IEEE80211_IS_CHAN_2GHZ(c)) 1763 power = min(sc->txpow[chan - 1], 31); 1764 else 1765 power = 31; 1766 1767 /* adjust txpower using ifconfig settings */ 1768 power -= (100 - ic->ic_txpowlimit) / 8; 1769 1770 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1771 1772 switch (sc->rf_rev) { 1773 case RAL_RF_2522: 1774 ural_rf_write(sc, RAL_RF1, 0x00814); 1775 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1776 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1777 break; 1778 1779 case RAL_RF_2523: 1780 ural_rf_write(sc, RAL_RF1, 0x08804); 1781 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1782 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1783 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1784 break; 1785 1786 case RAL_RF_2524: 1787 ural_rf_write(sc, RAL_RF1, 0x0c808); 1788 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1789 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1790 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1791 break; 1792 1793 case RAL_RF_2525: 1794 ural_rf_write(sc, RAL_RF1, 0x08808); 1795 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1796 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1797 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1798 1799 ural_rf_write(sc, RAL_RF1, 0x08808); 1800 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1801 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1802 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1803 break; 1804 1805 case RAL_RF_2525E: 1806 ural_rf_write(sc, RAL_RF1, 0x08808); 1807 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1808 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1809 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1810 break; 1811 1812 case RAL_RF_2526: 1813 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1814 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1815 ural_rf_write(sc, RAL_RF1, 0x08804); 1816 1817 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1818 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1819 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1820 break; 1821 1822 /* dual-band RF */ 1823 case RAL_RF_5222: 1824 for (i = 0; ural_rf5222[i].chan != chan; i++); 1825 1826 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1827 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1828 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1829 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1830 break; 1831 } 1832 1833 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1834 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1835 /* set Japan filter bit for channel 14 */ 1836 tmp = ural_bbp_read(sc, 70); 1837 1838 tmp &= ~RAL_JAPAN_FILTER; 1839 if (chan == 14) 1840 tmp |= RAL_JAPAN_FILTER; 1841 1842 ural_bbp_write(sc, 70, tmp); 1843 1844 /* clear CRC errors */ 1845 ural_read(sc, RAL_STA_CSR0); 1846 1847 ural_pause(sc, hz / 100); 1848 ural_disable_rf_tune(sc); 1849 } 1850 1851 /* XXX doesn't belong here */ 1852 /* update basic rate set */ 1853 ural_set_basicrates(sc, c); 1854 1855 /* give the hardware some time to do the switchover */ 1856 ural_pause(sc, hz / 100); 1857} 1858 1859/* 1860 * Disable RF auto-tuning. 1861 */ 1862static void 1863ural_disable_rf_tune(struct ural_softc *sc) 1864{ 1865 uint32_t tmp; 1866 1867 if (sc->rf_rev != RAL_RF_2523) { 1868 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1869 ural_rf_write(sc, RAL_RF1, tmp); 1870 } 1871 1872 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1873 ural_rf_write(sc, RAL_RF3, tmp); 1874 1875 DPRINTFN(2, "disabling RF autotune\n"); 1876} 1877 1878/* 1879 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1880 * synchronization. 1881 */ 1882static void 1883ural_enable_tsf_sync(struct ural_softc *sc) 1884{ 1885 struct ifnet *ifp = sc->sc_ifp; 1886 struct ieee80211com *ic = ifp->if_l2com; 1887 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1888 uint16_t logcwmin, preload, tmp; 1889 1890 /* first, disable TSF synchronization */ 1891 ural_write(sc, RAL_TXRX_CSR19, 0); 1892 1893 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1894 ural_write(sc, RAL_TXRX_CSR18, tmp); 1895 1896 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1897 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1898 tmp = logcwmin << 12 | preload; 1899 ural_write(sc, RAL_TXRX_CSR20, tmp); 1900 1901 /* finally, enable TSF synchronization */ 1902 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1903 if (ic->ic_opmode == IEEE80211_M_STA) 1904 tmp |= RAL_ENABLE_TSF_SYNC(1); 1905 else 1906 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1907 ural_write(sc, RAL_TXRX_CSR19, tmp); 1908 1909 DPRINTF("enabling TSF synchronization\n"); 1910} 1911 1912#define RAL_RXTX_TURNAROUND 5 /* us */ 1913static void 1914ural_update_slot(struct ifnet *ifp) 1915{ 1916 struct ural_softc *sc = ifp->if_softc; 1917 struct ieee80211com *ic = ifp->if_l2com; 1918 uint16_t slottime, sifs, eifs; 1919 1920 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1921 1922 /* 1923 * These settings may sound a bit inconsistent but this is what the 1924 * reference driver does. 1925 */ 1926 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1927 sifs = 16 - RAL_RXTX_TURNAROUND; 1928 eifs = 364; 1929 } else { 1930 sifs = 10 - RAL_RXTX_TURNAROUND; 1931 eifs = 64; 1932 } 1933 1934 ural_write(sc, RAL_MAC_CSR10, slottime); 1935 ural_write(sc, RAL_MAC_CSR11, sifs); 1936 ural_write(sc, RAL_MAC_CSR12, eifs); 1937} 1938 1939static void 1940ural_set_txpreamble(struct ural_softc *sc) 1941{ 1942 struct ifnet *ifp = sc->sc_ifp; 1943 struct ieee80211com *ic = ifp->if_l2com; 1944 uint16_t tmp; 1945 1946 tmp = ural_read(sc, RAL_TXRX_CSR10); 1947 1948 tmp &= ~RAL_SHORT_PREAMBLE; 1949 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1950 tmp |= RAL_SHORT_PREAMBLE; 1951 1952 ural_write(sc, RAL_TXRX_CSR10, tmp); 1953} 1954 1955static void 1956ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1957{ 1958 /* XXX wrong, take from rate set */ 1959 /* update basic rate set */ 1960 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1961 /* 11a basic rates: 6, 12, 24Mbps */ 1962 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1963 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1964 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1965 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1966 } else { 1967 /* 11b basic rates: 1, 2Mbps */ 1968 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1969 } 1970} 1971 1972static void 1973ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1974{ 1975 uint16_t tmp; 1976 1977 tmp = bssid[0] | bssid[1] << 8; 1978 ural_write(sc, RAL_MAC_CSR5, tmp); 1979 1980 tmp = bssid[2] | bssid[3] << 8; 1981 ural_write(sc, RAL_MAC_CSR6, tmp); 1982 1983 tmp = bssid[4] | bssid[5] << 8; 1984 ural_write(sc, RAL_MAC_CSR7, tmp); 1985 1986 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1987} 1988 1989static void 1990ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1991{ 1992 uint16_t tmp; 1993 1994 tmp = addr[0] | addr[1] << 8; 1995 ural_write(sc, RAL_MAC_CSR2, tmp); 1996 1997 tmp = addr[2] | addr[3] << 8; 1998 ural_write(sc, RAL_MAC_CSR3, tmp); 1999 2000 tmp = addr[4] | addr[5] << 8; 2001 ural_write(sc, RAL_MAC_CSR4, tmp); 2002 2003 DPRINTF("setting MAC address to %6D\n", addr, ":"); 2004} 2005 2006static void 2007ural_promisctask(struct usb2_proc_msg *pm) 2008{ 2009 struct ural_task *task = (struct ural_task *)pm; 2010 struct ural_softc *sc = task->sc; 2011 struct ifnet *ifp = sc->sc_ifp; 2012 uint32_t tmp; 2013 2014 tmp = ural_read(sc, RAL_TXRX_CSR2); 2015 2016 tmp &= ~RAL_DROP_NOT_TO_ME; 2017 if (!(ifp->if_flags & IFF_PROMISC)) 2018 tmp |= RAL_DROP_NOT_TO_ME; 2019 2020 ural_write(sc, RAL_TXRX_CSR2, tmp); 2021 2022 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2023 "entering" : "leaving"); 2024} 2025 2026static void 2027ural_update_promisc(struct ifnet *ifp) 2028{ 2029 struct ural_softc *sc = ifp->if_softc; 2030 2031 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2032 return; 2033 2034 RAL_LOCK(sc); 2035 ural_queue_command(sc, ural_promisctask, 2036 &sc->sc_promisctask[0].hdr, 2037 &sc->sc_promisctask[1].hdr); 2038 RAL_UNLOCK(sc); 2039} 2040 2041static const char * 2042ural_get_rf(int rev) 2043{ 2044 switch (rev) { 2045 case RAL_RF_2522: return "RT2522"; 2046 case RAL_RF_2523: return "RT2523"; 2047 case RAL_RF_2524: return "RT2524"; 2048 case RAL_RF_2525: return "RT2525"; 2049 case RAL_RF_2525E: return "RT2525e"; 2050 case RAL_RF_2526: return "RT2526"; 2051 case RAL_RF_5222: return "RT5222"; 2052 default: return "unknown"; 2053 } 2054} 2055 2056static void 2057ural_read_eeprom(struct ural_softc *sc) 2058{ 2059 uint16_t val; 2060 2061 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 2062 val = le16toh(val); 2063 sc->rf_rev = (val >> 11) & 0x7; 2064 sc->hw_radio = (val >> 10) & 0x1; 2065 sc->led_mode = (val >> 6) & 0x7; 2066 sc->rx_ant = (val >> 4) & 0x3; 2067 sc->tx_ant = (val >> 2) & 0x3; 2068 sc->nb_ant = val & 0x3; 2069 2070 /* read MAC address */ 2071 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 2072 2073 /* read default values for BBP registers */ 2074 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 2075 2076 /* read Tx power for all b/g channels */ 2077 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 2078} 2079 2080static int 2081ural_bbp_init(struct ural_softc *sc) 2082{ 2083#define N(a) (sizeof (a) / sizeof ((a)[0])) 2084 int i, ntries; 2085 2086 /* wait for BBP to be ready */ 2087 for (ntries = 0; ntries < 100; ntries++) { 2088 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 2089 break; 2090 if (ural_pause(sc, hz / 100)) 2091 break; 2092 } 2093 if (ntries == 100) { 2094 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2095 return EIO; 2096 } 2097 2098 /* initialize BBP registers to default values */ 2099 for (i = 0; i < N(ural_def_bbp); i++) 2100 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 2101 2102#if 0 2103 /* initialize BBP registers to values stored in EEPROM */ 2104 for (i = 0; i < 16; i++) { 2105 if (sc->bbp_prom[i].reg == 0xff) 2106 continue; 2107 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2108 } 2109#endif 2110 2111 return 0; 2112#undef N 2113} 2114 2115static void 2116ural_set_txantenna(struct ural_softc *sc, int antenna) 2117{ 2118 uint16_t tmp; 2119 uint8_t tx; 2120 2121 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 2122 if (antenna == 1) 2123 tx |= RAL_BBP_ANTA; 2124 else if (antenna == 2) 2125 tx |= RAL_BBP_ANTB; 2126 else 2127 tx |= RAL_BBP_DIVERSITY; 2128 2129 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2130 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2131 sc->rf_rev == RAL_RF_5222) 2132 tx |= RAL_BBP_FLIPIQ; 2133 2134 ural_bbp_write(sc, RAL_BBP_TX, tx); 2135 2136 /* update values in PHY_CSR5 and PHY_CSR6 */ 2137 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2138 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2139 2140 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2141 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2142} 2143 2144static void 2145ural_set_rxantenna(struct ural_softc *sc, int antenna) 2146{ 2147 uint8_t rx; 2148 2149 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2150 if (antenna == 1) 2151 rx |= RAL_BBP_ANTA; 2152 else if (antenna == 2) 2153 rx |= RAL_BBP_ANTB; 2154 else 2155 rx |= RAL_BBP_DIVERSITY; 2156 2157 /* need to force no I/Q flip for RF 2525e and 2526 */ 2158 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2159 rx &= ~RAL_BBP_FLIPIQ; 2160 2161 ural_bbp_write(sc, RAL_BBP_RX, rx); 2162} 2163 2164static void 2165ural_init_task(struct usb2_proc_msg *pm) 2166{ 2167#define N(a) (sizeof (a) / sizeof ((a)[0])) 2168 struct ural_task *task = (struct ural_task *)pm; 2169 struct ural_softc *sc = task->sc; 2170 struct ifnet *ifp = sc->sc_ifp; 2171 struct ieee80211com *ic = ifp->if_l2com; 2172 uint16_t tmp; 2173 int i, ntries; 2174 2175 RAL_LOCK_ASSERT(sc, MA_OWNED); 2176 2177 ural_set_testmode(sc); 2178 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2179 2180 ural_stop_task(pm); 2181 2182 /* initialize MAC registers to default values */ 2183 for (i = 0; i < N(ural_def_mac); i++) 2184 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2185 2186 /* wait for BBP and RF to wake up (this can take a long time!) */ 2187 for (ntries = 0; ntries < 100; ntries++) { 2188 tmp = ural_read(sc, RAL_MAC_CSR17); 2189 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2190 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2191 break; 2192 if (ural_pause(sc, hz / 100)) 2193 break; 2194 } 2195 if (ntries == 100) { 2196 device_printf(sc->sc_dev, 2197 "timeout waiting for BBP/RF to wakeup\n"); 2198 goto fail; 2199 } 2200 2201 /* we're ready! */ 2202 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2203 2204 /* set basic rate set (will be updated later) */ 2205 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2206 2207 if (ural_bbp_init(sc) != 0) 2208 goto fail; 2209 2210 ural_set_chan(sc, ic->ic_curchan); 2211 2212 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2213 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2214 2215 ural_set_txantenna(sc, sc->tx_ant); 2216 ural_set_rxantenna(sc, sc->rx_ant); 2217 2218 ural_set_macaddr(sc, IF_LLADDR(ifp)); 2219 2220 /* 2221 * Allocate Tx and Rx xfer queues. 2222 */ 2223 ural_setup_tx_list(sc); 2224 2225 /* kick Rx */ 2226 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2227 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2228 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2229 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2230 tmp |= RAL_DROP_TODS; 2231 if (!(ifp->if_flags & IFF_PROMISC)) 2232 tmp |= RAL_DROP_NOT_TO_ME; 2233 } 2234 ural_write(sc, RAL_TXRX_CSR2, tmp); 2235 2236 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2237 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2238 usb2_transfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2239 usb2_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2240 return; 2241 2242fail: ural_stop_task(pm); 2243#undef N 2244} 2245 2246static void 2247ural_init(void *priv) 2248{ 2249 struct ural_softc *sc = priv; 2250 struct ifnet *ifp = sc->sc_ifp; 2251 struct ieee80211com *ic = ifp->if_l2com; 2252 2253 RAL_LOCK(sc); 2254 ural_queue_command(sc, ural_init_task, 2255 &sc->sc_synctask[0].hdr, 2256 &sc->sc_synctask[1].hdr); 2257 RAL_UNLOCK(sc); 2258 2259 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2260 ieee80211_start_all(ic); /* start all vap's */ 2261} 2262 2263static void 2264ural_stop_task(struct usb2_proc_msg *pm) 2265{ 2266 struct ural_task *task = (struct ural_task *)pm; 2267 struct ural_softc *sc = task->sc; 2268 struct ifnet *ifp = sc->sc_ifp; 2269 2270 RAL_LOCK_ASSERT(sc, MA_OWNED); 2271 2272 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2273 2274 /* 2275 * Drain all the transfers, if not already drained: 2276 */ 2277 RAL_UNLOCK(sc); 2278 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2279 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2280 RAL_LOCK(sc); 2281 2282 ural_unsetup_tx_list(sc); 2283 2284 /* disable Rx */ 2285 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2286 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2287 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2288 /* wait a little */ 2289 ural_pause(sc, hz / 10); 2290 ural_write(sc, RAL_MAC_CSR1, 0); 2291 /* wait a little */ 2292 ural_pause(sc, hz / 10); 2293} 2294 2295static int 2296ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2297 const struct ieee80211_bpf_params *params) 2298{ 2299 struct ieee80211com *ic = ni->ni_ic; 2300 struct ifnet *ifp = ic->ic_ifp; 2301 struct ural_softc *sc = ifp->if_softc; 2302 2303 RAL_LOCK(sc); 2304 /* prevent management frames from being sent if we're not ready */ 2305 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2306 RAL_UNLOCK(sc); 2307 m_freem(m); 2308 ieee80211_free_node(ni); 2309 return ENETDOWN; 2310 } 2311 if (sc->tx_nfree < RAL_TX_MINFREE) { 2312 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2313 RAL_UNLOCK(sc); 2314 m_freem(m); 2315 ieee80211_free_node(ni); 2316 return EIO; 2317 } 2318 2319 ifp->if_opackets++; 2320 2321 if (params == NULL) { 2322 /* 2323 * Legacy path; interpret frame contents to decide 2324 * precisely how to send the frame. 2325 */ 2326 if (ural_tx_mgt(sc, m, ni) != 0) 2327 goto bad; 2328 } else { 2329 /* 2330 * Caller supplied explicit parameters to use in 2331 * sending the frame. 2332 */ 2333 if (ural_tx_raw(sc, m, ni, params) != 0) 2334 goto bad; 2335 } 2336 RAL_UNLOCK(sc); 2337 return 0; 2338bad: 2339 ifp->if_oerrors++; 2340 RAL_UNLOCK(sc); 2341 ieee80211_free_node(ni); 2342 return EIO; /* XXX */ 2343} 2344 2345static void 2346ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni) 2347{ 2348 struct ieee80211vap *vap = ni->ni_vap; 2349 struct ural_vap *uvp = URAL_VAP(vap); 2350 2351 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2352 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2353 2354 ieee80211_amrr_node_init(&uvp->amrr, &URAL_NODE(ni)->amn, ni); 2355 2356 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2357} 2358 2359static void 2360ural_amrr_timeout(void *arg) 2361{ 2362 struct ural_vap *uvp = arg; 2363 struct ural_softc *sc = uvp->sc; 2364 2365 ural_queue_command(sc, ural_amrr_task, 2366 &uvp->amrr_task[0].hdr, &uvp->amrr_task[1].hdr); 2367} 2368 2369static void 2370ural_amrr_task(struct usb2_proc_msg *pm) 2371{ 2372 struct ural_task *task = (struct ural_task *)pm; 2373 struct ural_softc *sc = task->sc; 2374 struct ifnet *ifp = sc->sc_ifp; 2375 struct ieee80211com *ic = ifp->if_l2com; 2376 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2377 struct ural_vap *uvp = URAL_VAP(vap); 2378 struct ieee80211_node *ni = vap->iv_bss; 2379 int ok, fail; 2380 2381 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2382 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2383 2384 ok = sc->sta[7] + /* TX ok w/o retry */ 2385 sc->sta[8]; /* TX ok w/ retry */ 2386 fail = sc->sta[9]; /* TX retry-fail count */ 2387 2388 ieee80211_amrr_tx_update(&URAL_NODE(ni)->amn, 2389 ok+fail, ok, sc->sta[8] + fail); 2390 (void) ieee80211_amrr_choose(ni, &URAL_NODE(ni)->amn); 2391 2392 ifp->if_oerrors += fail; /* count TX retry-fail as Tx errors */ 2393 2394 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2395} 2396 2397static int 2398ural_pause(struct ural_softc *sc, int timeout) 2399{ 2400 if (usb2_proc_is_gone(&sc->sc_tq)) 2401 return (1); 2402 2403 usb2_pause_mtx(&sc->sc_mtx, timeout); 2404 return (0); 2405} 2406 2407static void 2408ural_command_wrapper(struct usb2_proc_msg *pm) 2409{ 2410 struct ural_task *task = (struct ural_task *)pm; 2411 struct ural_softc *sc = task->sc; 2412 struct ifnet *ifp; 2413 2414 /* wait for pending transfer, if any */ 2415 while (usb2_transfer_pending(sc->sc_xfer[URAL_BULK_WR])) 2416 cv_wait(&sc->sc_cmd_cv, &sc->sc_mtx); 2417 2418 /* make sure any hardware FIFOs are emptied */ 2419 ural_pause(sc, hz / 1000); 2420 2421 /* execute task */ 2422 task->func(pm); 2423 2424 /* check if this is the last task executed */ 2425 if (sc->sc_last_task == task) { 2426 sc->sc_last_task = NULL; 2427 ifp = sc->sc_ifp; 2428 /* re-start TX, if any */ 2429 if ((ifp != NULL) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 2430 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 2431 } 2432} 2433 2434static void 2435ural_queue_command(struct ural_softc *sc, usb2_proc_callback_t *fn, 2436 struct usb2_proc_msg *t0, struct usb2_proc_msg *t1) 2437{ 2438 struct ural_task *task; 2439 2440 RAL_LOCK_ASSERT(sc, MA_OWNED); 2441 2442 /* 2443 * NOTE: The task cannot get executed before we drop the 2444 * "sc_mtx" mutex. It is safe to update fields in the message 2445 * structure after that the message got queued. 2446 */ 2447 task = (struct ural_task *) 2448 usb2_proc_msignal(&sc->sc_tq, t0, t1); 2449 2450 /* Setup callback and softc pointers */ 2451 task->hdr.pm_callback = ural_command_wrapper; 2452 task->func = fn; 2453 task->sc = sc; 2454 2455 /* Make sure that any TX operation will stop */ 2456 sc->sc_last_task = task; 2457 2458 /* 2459 * Init, stop and flush must be synchronous! 2460 */ 2461 if ((fn == ural_init_task) || (fn == ural_stop_task) || 2462 (fn == ural_stop_task)) 2463 usb2_proc_mwait(&sc->sc_tq, t0, t1); 2464} 2465