if_ural.c revision 189123
1/* $FreeBSD: head/sys/dev/usb/wlan/if_ural.c 189123 2009-02-27 21:14:29Z thompsa $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_ural.c 189123 2009-02-27 21:14:29Z thompsa $"); 25 26/*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31#include "usbdevs.h" 32#include <dev/usb/usb.h> 33#include <dev/usb/usb_mfunc.h> 34#include <dev/usb/usb_error.h> 35 36#define USB_DEBUG_VAR ural_debug 37 38#include <dev/usb/usb_core.h> 39#include <dev/usb/usb_lookup.h> 40#include <dev/usb/usb_process.h> 41#include <dev/usb/usb_debug.h> 42#include <dev/usb/usb_request.h> 43#include <dev/usb/usb_busdma.h> 44#include <dev/usb/usb_util.h> 45 46#include <dev/usb/wlan/usb_wlan.h> 47#include <dev/usb/wlan/if_uralreg.h> 48#include <dev/usb/wlan/if_uralvar.h> 49 50#if USB_DEBUG 51static int ural_debug = 0; 52 53SYSCTL_NODE(_hw_usb2, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 54SYSCTL_INT(_hw_usb2_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 55 "Debug level"); 56#endif 57 58#define URAL_RSSI(rssi) \ 59 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 60 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 61 62/* various supported device vendors/products */ 63static const struct usb2_device_id ural_devs[] = { 64 { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_ASUS_WL167G) }, 65 { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_RALINK_RT2570) }, 66 { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7050) }, 67 { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7051) }, 68 { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_HU200TS) }, 69 { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54G) }, 70 { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54GP) }, 71 { USB_VP(USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_C54RU) }, 72 { USB_VP(USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWLG122) }, 73 { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GN54G) }, 74 { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GNWBKG) }, 75 { USB_VP(USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUSB254) }, 76 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54) }, 77 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54AI) }, 78 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54YB) }, 79 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_NINWIFI) }, 80 { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570) }, 81 { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_2) }, 82 { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_3) }, 83 { USB_VP(USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_NV902) }, 84 { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570) }, 85 { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_2) }, 86 { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_3) }, 87 { USB_VP(USB_VENDOR_SIEMENS2, USB_PRODUCT_SIEMENS2_WL54G) }, 88 { USB_VP(USB_VENDOR_SMC, USB_PRODUCT_SMC_2862WG) }, 89 { USB_VP(USB_VENDOR_SPHAIRON, USB_PRODUCT_SPHAIRON_UB801R) }, 90 { USB_VP(USB_VENDOR_SURECOM, USB_PRODUCT_SURECOM_RT2570) }, 91 { USB_VP(USB_VENDOR_VTECH, USB_PRODUCT_VTECH_RT2570) }, 92 { USB_VP(USB_VENDOR_ZINWELL, USB_PRODUCT_ZINWELL_RT2570) }, 93}; 94 95static usb2_callback_t ural_bulk_read_callback; 96static usb2_callback_t ural_bulk_write_callback; 97 98static usb2_proc_callback_t ural_command_wrapper; 99static usb2_proc_callback_t ural_attach_post; 100static usb2_proc_callback_t ural_task; 101static usb2_proc_callback_t ural_scantask; 102static usb2_proc_callback_t ural_promisctask; 103static usb2_proc_callback_t ural_amrr_task; 104static usb2_proc_callback_t ural_init_task; 105static usb2_proc_callback_t ural_stop_task; 106static usb2_proc_callback_t ural_flush_task; 107 108static usb2_error_t ural_do_request(struct ural_softc *sc, 109 struct usb2_device_request *req, void *data); 110static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 111 const char name[IFNAMSIZ], int unit, int opmode, 112 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 113 const uint8_t mac[IEEE80211_ADDR_LEN]); 114static void ural_vap_delete(struct ieee80211vap *); 115static void ural_tx_free(struct ural_tx_data *, int); 116static void ural_setup_tx_list(struct ural_softc *); 117static void ural_unsetup_tx_list(struct ural_softc *); 118static int ural_newstate(struct ieee80211vap *, 119 enum ieee80211_state, int); 120static void ural_setup_tx_desc(struct ural_softc *, 121 struct ural_tx_desc *, uint32_t, int, int); 122static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 123 struct ieee80211_node *); 124static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 125 struct ieee80211_node *); 126static int ural_tx_data(struct ural_softc *, struct mbuf *, 127 struct ieee80211_node *); 128static void ural_start(struct ifnet *); 129static int ural_ioctl(struct ifnet *, u_long, caddr_t); 130static void ural_set_testmode(struct ural_softc *); 131static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 132 int); 133static uint16_t ural_read(struct ural_softc *, uint16_t); 134static void ural_read_multi(struct ural_softc *, uint16_t, void *, 135 int); 136static void ural_write(struct ural_softc *, uint16_t, uint16_t); 137static void ural_write_multi(struct ural_softc *, uint16_t, void *, 138 int) __unused; 139static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 140static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 141static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 142static struct ieee80211_node *ural_node_alloc(struct ieee80211vap *, 143 const uint8_t mac[IEEE80211_ADDR_LEN]); 144static void ural_newassoc(struct ieee80211_node *, int); 145static void ural_scan_start(struct ieee80211com *); 146static void ural_scan_end(struct ieee80211com *); 147static void ural_set_channel(struct ieee80211com *); 148static void ural_set_chan(struct ural_softc *, 149 struct ieee80211_channel *); 150static void ural_disable_rf_tune(struct ural_softc *); 151static void ural_enable_tsf_sync(struct ural_softc *); 152static void ural_update_slot(struct ifnet *); 153static void ural_set_txpreamble(struct ural_softc *); 154static void ural_set_basicrates(struct ural_softc *, 155 const struct ieee80211_channel *); 156static void ural_set_bssid(struct ural_softc *, const uint8_t *); 157static void ural_set_macaddr(struct ural_softc *, uint8_t *); 158static void ural_update_mcast(struct ifnet *); 159static void ural_update_promisc(struct ifnet *); 160static const char *ural_get_rf(int); 161static void ural_read_eeprom(struct ural_softc *); 162static int ural_bbp_init(struct ural_softc *); 163static void ural_set_txantenna(struct ural_softc *, int); 164static void ural_set_rxantenna(struct ural_softc *, int); 165static void ural_init(void *); 166static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 167 const struct ieee80211_bpf_params *); 168static void ural_amrr_start(struct ural_softc *, 169 struct ieee80211_node *); 170static void ural_amrr_timeout(void *); 171static int ural_pause(struct ural_softc *sc, int timeout); 172static void ural_queue_command(struct ural_softc *, 173 usb2_proc_callback_t *, struct usb2_proc_msg *, 174 struct usb2_proc_msg *); 175 176/* 177 * Default values for MAC registers; values taken from the reference driver. 178 */ 179static const struct { 180 uint16_t reg; 181 uint16_t val; 182} ural_def_mac[] = { 183 { RAL_TXRX_CSR5, 0x8c8d }, 184 { RAL_TXRX_CSR6, 0x8b8a }, 185 { RAL_TXRX_CSR7, 0x8687 }, 186 { RAL_TXRX_CSR8, 0x0085 }, 187 { RAL_MAC_CSR13, 0x1111 }, 188 { RAL_MAC_CSR14, 0x1e11 }, 189 { RAL_TXRX_CSR21, 0xe78f }, 190 { RAL_MAC_CSR9, 0xff1d }, 191 { RAL_MAC_CSR11, 0x0002 }, 192 { RAL_MAC_CSR22, 0x0053 }, 193 { RAL_MAC_CSR15, 0x0000 }, 194 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 195 { RAL_TXRX_CSR19, 0x0000 }, 196 { RAL_TXRX_CSR18, 0x005a }, 197 { RAL_PHY_CSR2, 0x0000 }, 198 { RAL_TXRX_CSR0, 0x1ec0 }, 199 { RAL_PHY_CSR4, 0x000f } 200}; 201 202/* 203 * Default values for BBP registers; values taken from the reference driver. 204 */ 205static const struct { 206 uint8_t reg; 207 uint8_t val; 208} ural_def_bbp[] = { 209 { 3, 0x02 }, 210 { 4, 0x19 }, 211 { 14, 0x1c }, 212 { 15, 0x30 }, 213 { 16, 0xac }, 214 { 17, 0x48 }, 215 { 18, 0x18 }, 216 { 19, 0xff }, 217 { 20, 0x1e }, 218 { 21, 0x08 }, 219 { 22, 0x08 }, 220 { 23, 0x08 }, 221 { 24, 0x80 }, 222 { 25, 0x50 }, 223 { 26, 0x08 }, 224 { 27, 0x23 }, 225 { 30, 0x10 }, 226 { 31, 0x2b }, 227 { 32, 0xb9 }, 228 { 34, 0x12 }, 229 { 35, 0x50 }, 230 { 39, 0xc4 }, 231 { 40, 0x02 }, 232 { 41, 0x60 }, 233 { 53, 0x10 }, 234 { 54, 0x18 }, 235 { 56, 0x08 }, 236 { 57, 0x10 }, 237 { 58, 0x08 }, 238 { 61, 0x60 }, 239 { 62, 0x10 }, 240 { 75, 0xff } 241}; 242 243/* 244 * Default values for RF register R2 indexed by channel numbers. 245 */ 246static const uint32_t ural_rf2522_r2[] = { 247 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 248 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 249}; 250 251static const uint32_t ural_rf2523_r2[] = { 252 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 253 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 254}; 255 256static const uint32_t ural_rf2524_r2[] = { 257 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 258 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 259}; 260 261static const uint32_t ural_rf2525_r2[] = { 262 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 263 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 264}; 265 266static const uint32_t ural_rf2525_hi_r2[] = { 267 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 268 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 269}; 270 271static const uint32_t ural_rf2525e_r2[] = { 272 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 273 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 274}; 275 276static const uint32_t ural_rf2526_hi_r2[] = { 277 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 278 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 279}; 280 281static const uint32_t ural_rf2526_r2[] = { 282 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 283 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 284}; 285 286/* 287 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 288 * values taken from the reference driver. 289 */ 290static const struct { 291 uint8_t chan; 292 uint32_t r1; 293 uint32_t r2; 294 uint32_t r4; 295} ural_rf5222[] = { 296 { 1, 0x08808, 0x0044d, 0x00282 }, 297 { 2, 0x08808, 0x0044e, 0x00282 }, 298 { 3, 0x08808, 0x0044f, 0x00282 }, 299 { 4, 0x08808, 0x00460, 0x00282 }, 300 { 5, 0x08808, 0x00461, 0x00282 }, 301 { 6, 0x08808, 0x00462, 0x00282 }, 302 { 7, 0x08808, 0x00463, 0x00282 }, 303 { 8, 0x08808, 0x00464, 0x00282 }, 304 { 9, 0x08808, 0x00465, 0x00282 }, 305 { 10, 0x08808, 0x00466, 0x00282 }, 306 { 11, 0x08808, 0x00467, 0x00282 }, 307 { 12, 0x08808, 0x00468, 0x00282 }, 308 { 13, 0x08808, 0x00469, 0x00282 }, 309 { 14, 0x08808, 0x0046b, 0x00286 }, 310 311 { 36, 0x08804, 0x06225, 0x00287 }, 312 { 40, 0x08804, 0x06226, 0x00287 }, 313 { 44, 0x08804, 0x06227, 0x00287 }, 314 { 48, 0x08804, 0x06228, 0x00287 }, 315 { 52, 0x08804, 0x06229, 0x00287 }, 316 { 56, 0x08804, 0x0622a, 0x00287 }, 317 { 60, 0x08804, 0x0622b, 0x00287 }, 318 { 64, 0x08804, 0x0622c, 0x00287 }, 319 320 { 100, 0x08804, 0x02200, 0x00283 }, 321 { 104, 0x08804, 0x02201, 0x00283 }, 322 { 108, 0x08804, 0x02202, 0x00283 }, 323 { 112, 0x08804, 0x02203, 0x00283 }, 324 { 116, 0x08804, 0x02204, 0x00283 }, 325 { 120, 0x08804, 0x02205, 0x00283 }, 326 { 124, 0x08804, 0x02206, 0x00283 }, 327 { 128, 0x08804, 0x02207, 0x00283 }, 328 { 132, 0x08804, 0x02208, 0x00283 }, 329 { 136, 0x08804, 0x02209, 0x00283 }, 330 { 140, 0x08804, 0x0220a, 0x00283 }, 331 332 { 149, 0x08808, 0x02429, 0x00281 }, 333 { 153, 0x08808, 0x0242b, 0x00281 }, 334 { 157, 0x08808, 0x0242d, 0x00281 }, 335 { 161, 0x08808, 0x0242f, 0x00281 } 336}; 337 338static const struct usb2_config ural_config[URAL_N_TRANSFER] = { 339 [URAL_BULK_WR] = { 340 .type = UE_BULK, 341 .endpoint = UE_ADDR_ANY, 342 .direction = UE_DIR_OUT, 343 .mh.bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 344 .mh.flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 345 .mh.callback = ural_bulk_write_callback, 346 .mh.timeout = 5000, /* ms */ 347 }, 348 [URAL_BULK_RD] = { 349 .type = UE_BULK, 350 .endpoint = UE_ADDR_ANY, 351 .direction = UE_DIR_IN, 352 .mh.bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 353 .mh.flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 354 .mh.callback = ural_bulk_read_callback, 355 }, 356}; 357 358static device_probe_t ural_match; 359static device_attach_t ural_attach; 360static device_detach_t ural_detach; 361 362static device_method_t ural_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, ural_match), 365 DEVMETHOD(device_attach, ural_attach), 366 DEVMETHOD(device_detach, ural_detach), 367 368 { 0, 0 } 369}; 370 371static driver_t ural_driver = { 372 .name = "ural", 373 .methods = ural_methods, 374 .size = sizeof(struct ural_softc), 375}; 376 377static devclass_t ural_devclass; 378 379DRIVER_MODULE(ural, ushub, ural_driver, ural_devclass, NULL, 0); 380MODULE_DEPEND(ural, usb, 1, 1, 1); 381MODULE_DEPEND(ural, wlan, 1, 1, 1); 382MODULE_DEPEND(ural, wlan_amrr, 1, 1, 1); 383 384static int 385ural_match(device_t self) 386{ 387 struct usb2_attach_arg *uaa = device_get_ivars(self); 388 389 if (uaa->usb2_mode != USB_MODE_HOST) 390 return (ENXIO); 391 if (uaa->info.bConfigIndex != 0) 392 return (ENXIO); 393 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 394 return (ENXIO); 395 396 return (usb2_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 397} 398 399static int 400ural_attach(device_t self) 401{ 402 struct usb2_attach_arg *uaa = device_get_ivars(self); 403 struct ural_softc *sc = device_get_softc(self); 404 int error; 405 uint8_t iface_index; 406 407 device_set_usb2_desc(self); 408 sc->sc_udev = uaa->device; 409 sc->sc_dev = self; 410 411 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 412 MTX_NETWORK_LOCK, MTX_DEF); 413 414 cv_init(&sc->sc_cmd_cv, "wtxdone"); 415 416 iface_index = RAL_IFACE_INDEX; 417 error = usb2_transfer_setup(uaa->device, 418 &iface_index, sc->sc_xfer, ural_config, 419 URAL_N_TRANSFER, sc, &sc->sc_mtx); 420 if (error) { 421 device_printf(self, "could not allocate USB transfers, " 422 "err=%s\n", usb2_errstr(error)); 423 goto detach; 424 } 425 error = usb2_proc_create(&sc->sc_tq, &sc->sc_mtx, 426 device_get_nameunit(self), USB_PRI_MED); 427 if (error) { 428 device_printf(self, "could not setup config thread!\n"); 429 goto detach; 430 } 431 432 /* fork rest of the attach code */ 433 RAL_LOCK(sc); 434 ural_queue_command(sc, ural_attach_post, 435 &sc->sc_synctask[0].hdr, 436 &sc->sc_synctask[1].hdr); 437 RAL_UNLOCK(sc); 438 return (0); 439 440detach: 441 ural_detach(self); 442 return (ENXIO); /* failure */ 443} 444 445static void 446ural_attach_post(struct usb2_proc_msg *pm) 447{ 448 struct ural_task *task = (struct ural_task *)pm; 449 struct ural_softc *sc = task->sc; 450 struct ifnet *ifp; 451 struct ieee80211com *ic; 452 uint8_t bands; 453 454 /* retrieve RT2570 rev. no */ 455 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 456 457 /* retrieve MAC address and various other things from EEPROM */ 458 ural_read_eeprom(sc); 459 460 /* XXX Async attach race */ 461 if (usb2_proc_is_gone(&sc->sc_tq)) 462 return; 463 464 RAL_UNLOCK(sc); 465 466 device_printf(sc->sc_dev, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 467 sc->asic_rev, ural_get_rf(sc->rf_rev)); 468 469 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 470 if (ifp == NULL) { 471 device_printf(sc->sc_dev, "can not if_alloc()\n"); 472 RAL_LOCK(sc); 473 return; 474 } 475 ic = ifp->if_l2com; 476 477 ifp->if_softc = sc; 478 if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 479 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 480 ifp->if_init = ural_init; 481 ifp->if_ioctl = ural_ioctl; 482 ifp->if_start = ural_start; 483 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 484 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 485 IFQ_SET_READY(&ifp->if_snd); 486 487 ic->ic_ifp = ifp; 488 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 489 IEEE80211_ADDR_COPY(ic->ic_myaddr, sc->sc_bssid); 490 491 /* set device capabilities */ 492 ic->ic_caps = 493 IEEE80211_C_STA /* station mode supported */ 494 | IEEE80211_C_IBSS /* IBSS mode supported */ 495 | IEEE80211_C_MONITOR /* monitor mode supported */ 496 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 497 | IEEE80211_C_TXPMGT /* tx power management */ 498 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 499 | IEEE80211_C_SHSLOT /* short slot time supported */ 500 | IEEE80211_C_BGSCAN /* bg scanning supported */ 501 | IEEE80211_C_WPA /* 802.11i */ 502 ; 503 504 bands = 0; 505 setbit(&bands, IEEE80211_MODE_11B); 506 setbit(&bands, IEEE80211_MODE_11G); 507 if (sc->rf_rev == RAL_RF_5222) 508 setbit(&bands, IEEE80211_MODE_11A); 509 ieee80211_init_channels(ic, NULL, &bands); 510 511 ieee80211_ifattach(ic); 512 ic->ic_update_mcast = ural_update_mcast; 513 ic->ic_update_promisc = ural_update_promisc; 514 ic->ic_newassoc = ural_newassoc; 515 ic->ic_raw_xmit = ural_raw_xmit; 516 ic->ic_node_alloc = ural_node_alloc; 517 ic->ic_scan_start = ural_scan_start; 518 ic->ic_scan_end = ural_scan_end; 519 ic->ic_set_channel = ural_set_channel; 520 521 ic->ic_vap_create = ural_vap_create; 522 ic->ic_vap_delete = ural_vap_delete; 523 524 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 525 526 bpfattach(ifp, DLT_IEEE802_11_RADIO, 527 sizeof (struct ieee80211_frame) + sizeof(sc->sc_txtap)); 528 529 sc->sc_rxtap_len = sizeof sc->sc_rxtap; 530 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 531 sc->sc_rxtap.wr_ihdr.it_present = htole32(RAL_RX_RADIOTAP_PRESENT); 532 533 sc->sc_txtap_len = sizeof sc->sc_txtap; 534 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 535 sc->sc_txtap.wt_ihdr.it_present = htole32(RAL_TX_RADIOTAP_PRESENT); 536 537 if (bootverbose) 538 ieee80211_announce(ic); 539 540 RAL_LOCK(sc); 541} 542 543static int 544ural_detach(device_t self) 545{ 546 struct ural_softc *sc = device_get_softc(self); 547 struct ifnet *ifp = sc->sc_ifp; 548 struct ieee80211com *ic; 549 550 /* wait for any post attach or other command to complete */ 551 usb2_proc_drain(&sc->sc_tq); 552 553 /* stop all USB transfers */ 554 usb2_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 555 usb2_proc_free(&sc->sc_tq); 556 557 /* free TX list, if any */ 558 RAL_LOCK(sc); 559 ural_unsetup_tx_list(sc); 560 RAL_UNLOCK(sc); 561 562 if (ifp) { 563 ic = ifp->if_l2com; 564 bpfdetach(ifp); 565 ieee80211_ifdetach(ic); 566 if_free(ifp); 567 } 568 cv_destroy(&sc->sc_cmd_cv); 569 mtx_destroy(&sc->sc_mtx); 570 571 return (0); 572} 573 574static usb2_error_t 575ural_do_request(struct ural_softc *sc, 576 struct usb2_device_request *req, void *data) 577{ 578 usb2_error_t err; 579 int ntries = 10; 580 581 while (ntries--) { 582 err = usb2_do_request_proc(sc->sc_udev, &sc->sc_tq, 583 req, data, 0, NULL, 250 /* ms */); 584 if (err == 0) 585 break; 586 587 DPRINTFN(1, "Control request failed, %s (retrying)\n", 588 usb2_errstr(err)); 589 if (ural_pause(sc, hz / 100)) 590 break; 591 } 592 return (err); 593} 594 595static struct ieee80211vap * 596ural_vap_create(struct ieee80211com *ic, 597 const char name[IFNAMSIZ], int unit, int opmode, int flags, 598 const uint8_t bssid[IEEE80211_ADDR_LEN], 599 const uint8_t mac[IEEE80211_ADDR_LEN]) 600{ 601 struct ural_softc *sc = ic->ic_ifp->if_softc; 602 struct ural_vap *uvp; 603 struct ieee80211vap *vap; 604 605 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 606 return NULL; 607 uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 608 M_80211_VAP, M_NOWAIT | M_ZERO); 609 if (uvp == NULL) 610 return NULL; 611 vap = &uvp->vap; 612 /* enable s/w bmiss handling for sta mode */ 613 ieee80211_vap_setup(ic, vap, name, unit, opmode, 614 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 615 616 /* override state transition machine */ 617 uvp->newstate = vap->iv_newstate; 618 vap->iv_newstate = ural_newstate; 619 620 uvp->sc = sc; 621 usb2_callout_init_mtx(&uvp->amrr_ch, &sc->sc_mtx, 0); 622 ieee80211_amrr_init(&uvp->amrr, vap, 623 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 624 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 625 1000 /* 1 sec */); 626 627 /* complete setup */ 628 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 629 ic->ic_opmode = opmode; 630 return vap; 631} 632 633static void 634ural_flush_task(struct usb2_proc_msg *pm) 635{ 636 /* nothing to do */ 637} 638 639static void 640ural_vap_delete(struct ieee80211vap *vap) 641{ 642 struct ural_vap *uvp = URAL_VAP(vap); 643 struct ural_softc *sc = uvp->sc; 644 645 RAL_LOCK(sc); 646 /* wait for any pending tasks to complete */ 647 ural_queue_command(sc, ural_flush_task, 648 &sc->sc_synctask[0].hdr, 649 &sc->sc_synctask[1].hdr); 650 RAL_UNLOCK(sc); 651 652 usb2_callout_drain(&uvp->amrr_ch); 653 ieee80211_amrr_cleanup(&uvp->amrr); 654 ieee80211_vap_detach(vap); 655 free(uvp, M_80211_VAP); 656} 657 658static void 659ural_tx_free(struct ural_tx_data *data, int txerr) 660{ 661 struct ural_softc *sc = data->sc; 662 663 if (data->m != NULL) { 664 if (data->m->m_flags & M_TXCB) 665 ieee80211_process_callback(data->ni, data->m, 666 txerr ? ETIMEDOUT : 0); 667 m_freem(data->m); 668 data->m = NULL; 669 670 ieee80211_free_node(data->ni); 671 data->ni = NULL; 672 } 673 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 674 sc->tx_nfree++; 675} 676 677static void 678ural_setup_tx_list(struct ural_softc *sc) 679{ 680 struct ural_tx_data *data; 681 int i; 682 683 sc->tx_nfree = 0; 684 STAILQ_INIT(&sc->tx_q); 685 STAILQ_INIT(&sc->tx_free); 686 687 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 688 data = &sc->tx_data[i]; 689 690 data->sc = sc; 691 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 692 sc->tx_nfree++; 693 } 694} 695 696static void 697ural_unsetup_tx_list(struct ural_softc *sc) 698{ 699 struct ural_tx_data *data; 700 int i; 701 702 /* make sure any subsequent use of the queues will fail */ 703 sc->tx_nfree = 0; 704 STAILQ_INIT(&sc->tx_q); 705 STAILQ_INIT(&sc->tx_free); 706 707 /* free up all node references and mbufs */ 708 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 709 data = &sc->tx_data[i]; 710 711 if (data->m != NULL) { 712 m_freem(data->m); 713 data->m = NULL; 714 } 715 if (data->ni != NULL) { 716 ieee80211_free_node(data->ni); 717 data->ni = NULL; 718 } 719 } 720} 721 722static void 723ural_task(struct usb2_proc_msg *pm) 724{ 725 struct ural_task *task = (struct ural_task *)pm; 726 struct ural_softc *sc = task->sc; 727 struct ifnet *ifp = sc->sc_ifp; 728 struct ieee80211com *ic = ifp->if_l2com; 729 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 730 struct ural_vap *uvp = URAL_VAP(vap); 731 const struct ieee80211_txparam *tp; 732 enum ieee80211_state ostate; 733 struct ieee80211_node *ni; 734 struct mbuf *m; 735 736 ostate = vap->iv_state; 737 738 switch (sc->sc_state) { 739 case IEEE80211_S_INIT: 740 if (ostate == IEEE80211_S_RUN) { 741 /* abort TSF synchronization */ 742 ural_write(sc, RAL_TXRX_CSR19, 0); 743 744 /* force tx led to stop blinking */ 745 ural_write(sc, RAL_MAC_CSR20, 0); 746 } 747 break; 748 749 case IEEE80211_S_RUN: 750 ni = vap->iv_bss; 751 752 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 753 ural_update_slot(ic->ic_ifp); 754 ural_set_txpreamble(sc); 755 ural_set_basicrates(sc, ic->ic_bsschan); 756 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 757 ural_set_bssid(sc, sc->sc_bssid); 758 } 759 760 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 761 vap->iv_opmode == IEEE80211_M_IBSS) { 762 m = ieee80211_beacon_alloc(ni, &uvp->bo); 763 if (m == NULL) { 764 device_printf(sc->sc_dev, 765 "could not allocate beacon\n"); 766 return; 767 } 768 769 if (ural_tx_bcn(sc, m, ni) != 0) { 770 device_printf(sc->sc_dev, 771 "could not send beacon\n"); 772 return; 773 } 774 } 775 776 /* make tx led blink on tx (controlled by ASIC) */ 777 ural_write(sc, RAL_MAC_CSR20, 1); 778 779 if (vap->iv_opmode != IEEE80211_M_MONITOR) 780 ural_enable_tsf_sync(sc); 781 782 /* enable automatic rate adaptation */ 783 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 784 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 785 ural_amrr_start(sc, ni); 786 787 break; 788 789 default: 790 break; 791 } 792 793 RAL_UNLOCK(sc); 794 IEEE80211_LOCK(ic); 795 uvp->newstate(vap, sc->sc_state, sc->sc_arg); 796 if (vap->iv_newstate_cb != NULL) 797 vap->iv_newstate_cb(vap, sc->sc_state, sc->sc_arg); 798 IEEE80211_UNLOCK(ic); 799 RAL_LOCK(sc); 800} 801 802static void 803ural_scantask(struct usb2_proc_msg *pm) 804{ 805 struct ural_task *task = (struct ural_task *)pm; 806 struct ural_softc *sc = task->sc; 807 struct ifnet *ifp = sc->sc_ifp; 808 struct ieee80211com *ic = ifp->if_l2com; 809 810 RAL_LOCK_ASSERT(sc, MA_OWNED); 811 812 switch (sc->sc_scan_action) { 813 case URAL_SCAN_START: 814 /* abort TSF synchronization */ 815 DPRINTF("starting scan\n"); 816 ural_write(sc, RAL_TXRX_CSR19, 0); 817 ural_set_bssid(sc, ifp->if_broadcastaddr); 818 break; 819 820 case URAL_SET_CHANNEL: 821 ural_set_chan(sc, ic->ic_curchan); 822 break; 823 824 default: /* URAL_SCAN_END */ 825 DPRINTF("stopping scan\n"); 826 ural_enable_tsf_sync(sc); 827 ural_set_bssid(sc, sc->sc_bssid); 828 break; 829 } 830} 831 832static int 833ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 834{ 835 struct ural_vap *uvp = URAL_VAP(vap); 836 struct ieee80211com *ic = vap->iv_ic; 837 struct ural_softc *sc = ic->ic_ifp->if_softc; 838 839 DPRINTF("%s -> %s\n", 840 ieee80211_state_name[vap->iv_state], 841 ieee80211_state_name[nstate]); 842 843 RAL_LOCK(sc); 844 usb2_callout_stop(&uvp->amrr_ch); 845 846 /* do it in a process context */ 847 sc->sc_state = nstate; 848 sc->sc_arg = arg; 849 RAL_UNLOCK(sc); 850 851 if (nstate == IEEE80211_S_INIT) { 852 uvp->newstate(vap, nstate, arg); 853 return 0; 854 } else { 855 RAL_LOCK(sc); 856 ural_queue_command(sc, ural_task, &sc->sc_task[0].hdr, 857 &sc->sc_task[1].hdr); 858 RAL_UNLOCK(sc); 859 return EINPROGRESS; 860 } 861} 862 863 864static void 865ural_bulk_write_callback(struct usb2_xfer *xfer) 866{ 867 struct ural_softc *sc = xfer->priv_sc; 868 struct ifnet *ifp = sc->sc_ifp; 869 struct ieee80211com *ic = ifp->if_l2com; 870 struct ieee80211_channel *c = ic->ic_curchan; 871 struct ural_tx_data *data; 872 struct mbuf *m; 873 unsigned int len; 874 875 /* wakeup waiting command, if any */ 876 if (sc->sc_last_task != NULL) 877 cv_signal(&sc->sc_cmd_cv); 878 879 switch (USB_GET_STATE(xfer)) { 880 case USB_ST_TRANSFERRED: 881 DPRINTFN(11, "transfer complete, %d bytes\n", xfer->actlen); 882 883 /* free resources */ 884 data = xfer->priv_fifo; 885 ural_tx_free(data, 0); 886 xfer->priv_fifo = NULL; 887 888 ifp->if_opackets++; 889 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 890 891 /* FALLTHROUGH */ 892 case USB_ST_SETUP: 893tr_setup: 894 /* wait for command to complete, if any */ 895 if (sc->sc_last_task != NULL) 896 break; 897 898 data = STAILQ_FIRST(&sc->tx_q); 899 if (data) { 900 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 901 m = data->m; 902 903 if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 904 DPRINTFN(0, "data overflow, %u bytes\n", 905 m->m_pkthdr.len); 906 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 907 } 908 usb2_copy_in(xfer->frbuffers, 0, &data->desc, 909 RAL_TX_DESC_SIZE); 910 usb2_m_copy_in(xfer->frbuffers, RAL_TX_DESC_SIZE, m, 0, 911 m->m_pkthdr.len); 912 913 if (bpf_peers_present(ifp->if_bpf)) { 914 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 915 916 tap->wt_flags = 0; 917 tap->wt_rate = data->rate; 918 tap->wt_chan_freq = htole16(c->ic_freq); 919 tap->wt_chan_flags = htole16(c->ic_flags); 920 tap->wt_antenna = sc->tx_ant; 921 922 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m); 923 } 924 925 /* xfer length needs to be a multiple of two! */ 926 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 927 if ((len % 64) == 0) 928 len += 2; 929 930 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 931 m->m_pkthdr.len, len); 932 933 xfer->frlengths[0] = len; 934 xfer->priv_fifo = data; 935 936 usb2_start_hardware(xfer); 937 } 938 break; 939 940 default: /* Error */ 941 DPRINTFN(11, "transfer error, %s\n", 942 usb2_errstr(xfer->error)); 943 944 ifp->if_oerrors++; 945 data = xfer->priv_fifo; 946 if (data != NULL) { 947 ural_tx_free(data, xfer->error); 948 xfer->priv_fifo = NULL; 949 } 950 951 if (xfer->error == USB_ERR_STALLED) { 952 /* try to clear stall first */ 953 xfer->flags.stall_pipe = 1; 954 goto tr_setup; 955 } 956 if (xfer->error == USB_ERR_TIMEOUT) 957 device_printf(sc->sc_dev, "device timeout\n"); 958 break; 959 } 960} 961 962static void 963ural_bulk_read_callback(struct usb2_xfer *xfer) 964{ 965 struct ural_softc *sc = xfer->priv_sc; 966 struct ifnet *ifp = sc->sc_ifp; 967 struct ieee80211com *ic = ifp->if_l2com; 968 struct ieee80211_node *ni; 969 struct mbuf *m = NULL; 970 uint32_t flags; 971 uint8_t rssi = 0; 972 unsigned int len; 973 974 switch (USB_GET_STATE(xfer)) { 975 case USB_ST_TRANSFERRED: 976 977 DPRINTFN(15, "rx done, actlen=%d\n", xfer->actlen); 978 979 len = xfer->actlen; 980 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 981 DPRINTF("%s: xfer too short %d\n", 982 device_get_nameunit(sc->sc_dev), len); 983 ifp->if_ierrors++; 984 goto tr_setup; 985 } 986 987 len -= RAL_RX_DESC_SIZE; 988 /* rx descriptor is located at the end */ 989 usb2_copy_out(xfer->frbuffers, len, &sc->sc_rx_desc, 990 RAL_RX_DESC_SIZE); 991 992 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 993 flags = le32toh(sc->sc_rx_desc.flags); 994 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 995 /* 996 * This should not happen since we did not 997 * request to receive those frames when we 998 * filled RAL_TXRX_CSR2: 999 */ 1000 DPRINTFN(5, "PHY or CRC error\n"); 1001 ifp->if_ierrors++; 1002 goto tr_setup; 1003 } 1004 1005 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1006 if (m == NULL) { 1007 DPRINTF("could not allocate mbuf\n"); 1008 ifp->if_ierrors++; 1009 goto tr_setup; 1010 } 1011 usb2_copy_out(xfer->frbuffers, 0, mtod(m, uint8_t *), len); 1012 1013 /* finalize mbuf */ 1014 m->m_pkthdr.rcvif = ifp; 1015 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 1016 1017 if (bpf_peers_present(ifp->if_bpf)) { 1018 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 1019 1020 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1021 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 1022 (flags & RAL_RX_OFDM) ? 1023 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1024 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1025 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1026 tap->wr_antenna = sc->rx_ant; 1027 tap->wr_antsignal = rssi; 1028 1029 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1030 } 1031 /* Strip trailing 802.11 MAC FCS. */ 1032 m_adj(m, -IEEE80211_CRC_LEN); 1033 1034 /* FALLTHROUGH */ 1035 case USB_ST_SETUP: 1036tr_setup: 1037 xfer->frlengths[0] = xfer->max_data_length; 1038 usb2_start_hardware(xfer); 1039 1040 /* 1041 * At the end of a USB callback it is always safe to unlock 1042 * the private mutex of a device! That is why we do the 1043 * "ieee80211_input" here, and not some lines up! 1044 */ 1045 if (m) { 1046 RAL_UNLOCK(sc); 1047 ni = ieee80211_find_rxnode(ic, 1048 mtod(m, struct ieee80211_frame_min *)); 1049 if (ni != NULL) { 1050 (void) ieee80211_input(ni, m, rssi, 1051 RAL_NOISE_FLOOR, 0); 1052 ieee80211_free_node(ni); 1053 } else 1054 (void) ieee80211_input_all(ic, m, rssi, 1055 RAL_NOISE_FLOOR, 0); 1056 RAL_LOCK(sc); 1057 } 1058 return; 1059 1060 default: /* Error */ 1061 if (xfer->error != USB_ERR_CANCELLED) { 1062 /* try to clear stall first */ 1063 xfer->flags.stall_pipe = 1; 1064 goto tr_setup; 1065 } 1066 return; 1067 } 1068} 1069 1070static uint8_t 1071ural_plcp_signal(int rate) 1072{ 1073 switch (rate) { 1074 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1075 case 12: return 0xb; 1076 case 18: return 0xf; 1077 case 24: return 0xa; 1078 case 36: return 0xe; 1079 case 48: return 0x9; 1080 case 72: return 0xd; 1081 case 96: return 0x8; 1082 case 108: return 0xc; 1083 1084 /* CCK rates (NB: not IEEE std, device-specific) */ 1085 case 2: return 0x0; 1086 case 4: return 0x1; 1087 case 11: return 0x2; 1088 case 22: return 0x3; 1089 } 1090 return 0xff; /* XXX unsupported/unknown rate */ 1091} 1092 1093static void 1094ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 1095 uint32_t flags, int len, int rate) 1096{ 1097 struct ifnet *ifp = sc->sc_ifp; 1098 struct ieee80211com *ic = ifp->if_l2com; 1099 uint16_t plcp_length; 1100 int remainder; 1101 1102 desc->flags = htole32(flags); 1103 desc->flags |= htole32(RAL_TX_NEWSEQ); 1104 desc->flags |= htole32(len << 16); 1105 1106 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1107 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1108 1109 /* setup PLCP fields */ 1110 desc->plcp_signal = ural_plcp_signal(rate); 1111 desc->plcp_service = 4; 1112 1113 len += IEEE80211_CRC_LEN; 1114 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 1115 desc->flags |= htole32(RAL_TX_OFDM); 1116 1117 plcp_length = len & 0xfff; 1118 desc->plcp_length_hi = plcp_length >> 6; 1119 desc->plcp_length_lo = plcp_length & 0x3f; 1120 } else { 1121 plcp_length = (16 * len + rate - 1) / rate; 1122 if (rate == 22) { 1123 remainder = (16 * len) % 22; 1124 if (remainder != 0 && remainder < 7) 1125 desc->plcp_service |= RAL_PLCP_LENGEXT; 1126 } 1127 desc->plcp_length_hi = plcp_length >> 8; 1128 desc->plcp_length_lo = plcp_length & 0xff; 1129 1130 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1131 desc->plcp_signal |= 0x08; 1132 } 1133 1134 desc->iv = 0; 1135 desc->eiv = 0; 1136} 1137 1138#define RAL_TX_TIMEOUT 5000 1139 1140static int 1141ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1142{ 1143 struct ieee80211vap *vap = ni->ni_vap; 1144 struct ieee80211com *ic = ni->ni_ic; 1145 struct ifnet *ifp = sc->sc_ifp; 1146 const struct ieee80211_txparam *tp; 1147 struct ural_tx_data *data; 1148 1149 if (sc->tx_nfree == 0) { 1150 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1151 m_freem(m0); 1152 ieee80211_free_node(ni); 1153 return EIO; 1154 } 1155 data = STAILQ_FIRST(&sc->tx_free); 1156 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1157 sc->tx_nfree--; 1158 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1159 1160 data->m = m0; 1161 data->ni = ni; 1162 data->rate = tp->mgmtrate; 1163 1164 ural_setup_tx_desc(sc, &data->desc, 1165 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1166 tp->mgmtrate); 1167 1168 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1169 m0->m_pkthdr.len, tp->mgmtrate); 1170 1171 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1172 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1173 1174 return (0); 1175} 1176 1177static int 1178ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1179{ 1180 struct ieee80211vap *vap = ni->ni_vap; 1181 struct ieee80211com *ic = ni->ni_ic; 1182 const struct ieee80211_txparam *tp; 1183 struct ural_tx_data *data; 1184 struct ieee80211_frame *wh; 1185 struct ieee80211_key *k; 1186 uint32_t flags; 1187 uint16_t dur; 1188 1189 RAL_LOCK_ASSERT(sc, MA_OWNED); 1190 1191 data = STAILQ_FIRST(&sc->tx_free); 1192 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1193 sc->tx_nfree--; 1194 1195 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1196 1197 wh = mtod(m0, struct ieee80211_frame *); 1198 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1199 k = ieee80211_crypto_encap(ni, m0); 1200 if (k == NULL) { 1201 m_freem(m0); 1202 return ENOBUFS; 1203 } 1204 wh = mtod(m0, struct ieee80211_frame *); 1205 } 1206 1207 data->m = m0; 1208 data->ni = ni; 1209 data->rate = tp->mgmtrate; 1210 1211 flags = 0; 1212 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1213 flags |= RAL_TX_ACK; 1214 1215 dur = ieee80211_ack_duration(sc->sc_rates, tp->mgmtrate, 1216 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1217 *(uint16_t *)wh->i_dur = htole16(dur); 1218 1219 /* tell hardware to add timestamp for probe responses */ 1220 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1221 IEEE80211_FC0_TYPE_MGT && 1222 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1223 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1224 flags |= RAL_TX_TIMESTAMP; 1225 } 1226 1227 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1228 1229 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1230 m0->m_pkthdr.len, tp->mgmtrate); 1231 1232 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1233 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1234 1235 return 0; 1236} 1237 1238static int 1239ural_sendprot(struct ural_softc *sc, 1240 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1241{ 1242 struct ieee80211com *ic = ni->ni_ic; 1243 const struct ieee80211_frame *wh; 1244 struct ural_tx_data *data; 1245 struct mbuf *mprot; 1246 int protrate, ackrate, pktlen, flags, isshort; 1247 uint16_t dur; 1248 1249 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1250 ("protection %d", prot)); 1251 1252 wh = mtod(m, const struct ieee80211_frame *); 1253 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1254 1255 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 1256 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 1257 1258 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1259 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort); 1260 + ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1261 flags = RAL_TX_RETRY(7); 1262 if (prot == IEEE80211_PROT_RTSCTS) { 1263 /* NB: CTS is the same size as an ACK */ 1264 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1265 flags |= RAL_TX_ACK; 1266 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1267 } else { 1268 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1269 } 1270 if (mprot == NULL) { 1271 /* XXX stat + msg */ 1272 return ENOBUFS; 1273 } 1274 data = STAILQ_FIRST(&sc->tx_free); 1275 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1276 sc->tx_nfree--; 1277 1278 data->m = mprot; 1279 data->ni = ieee80211_ref_node(ni); 1280 data->rate = protrate; 1281 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1282 1283 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1284 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1285 1286 return 0; 1287} 1288 1289static int 1290ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1291 const struct ieee80211_bpf_params *params) 1292{ 1293 struct ural_tx_data *data; 1294 uint32_t flags; 1295 int error; 1296 int rate; 1297 1298 RAL_LOCK_ASSERT(sc, MA_OWNED); 1299 KASSERT(params != NULL, ("no raw xmit params")); 1300 1301 rate = params->ibp_rate0 & IEEE80211_RATE_VAL; 1302 /* XXX validate */ 1303 if (rate == 0) { 1304 m_freem(m0); 1305 return EINVAL; 1306 } 1307 flags = 0; 1308 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1309 flags |= RAL_TX_ACK; 1310 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1311 error = ural_sendprot(sc, m0, ni, 1312 params->ibp_flags & IEEE80211_BPF_RTS ? 1313 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1314 rate); 1315 if (error || sc->tx_nfree == 0) { 1316 m_freem(m0); 1317 return ENOBUFS; 1318 } 1319 flags |= RAL_TX_IFS_SIFS; 1320 } 1321 1322 data = STAILQ_FIRST(&sc->tx_free); 1323 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1324 sc->tx_nfree--; 1325 1326 data->m = m0; 1327 data->ni = ni; 1328 data->rate = rate; 1329 1330 /* XXX need to setup descriptor ourself */ 1331 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1332 1333 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1334 m0->m_pkthdr.len, rate); 1335 1336 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1337 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1338 1339 return 0; 1340} 1341 1342static int 1343ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1344{ 1345 struct ieee80211vap *vap = ni->ni_vap; 1346 struct ieee80211com *ic = ni->ni_ic; 1347 struct ural_tx_data *data; 1348 struct ieee80211_frame *wh; 1349 const struct ieee80211_txparam *tp; 1350 struct ieee80211_key *k; 1351 uint32_t flags = 0; 1352 uint16_t dur; 1353 int error, rate; 1354 1355 RAL_LOCK_ASSERT(sc, MA_OWNED); 1356 1357 wh = mtod(m0, struct ieee80211_frame *); 1358 1359 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1360 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1361 rate = tp->mcastrate; 1362 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1363 rate = tp->ucastrate; 1364 else 1365 rate = ni->ni_txrate; 1366 1367 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1368 k = ieee80211_crypto_encap(ni, m0); 1369 if (k == NULL) { 1370 m_freem(m0); 1371 return ENOBUFS; 1372 } 1373 /* packet header may have moved, reset our local pointer */ 1374 wh = mtod(m0, struct ieee80211_frame *); 1375 } 1376 1377 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1378 int prot = IEEE80211_PROT_NONE; 1379 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1380 prot = IEEE80211_PROT_RTSCTS; 1381 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1382 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 1383 prot = ic->ic_protmode; 1384 if (prot != IEEE80211_PROT_NONE) { 1385 error = ural_sendprot(sc, m0, ni, prot, rate); 1386 if (error || sc->tx_nfree == 0) { 1387 m_freem(m0); 1388 return ENOBUFS; 1389 } 1390 flags |= RAL_TX_IFS_SIFS; 1391 } 1392 } 1393 1394 data = STAILQ_FIRST(&sc->tx_free); 1395 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1396 sc->tx_nfree--; 1397 1398 data->m = m0; 1399 data->ni = ni; 1400 data->rate = rate; 1401 1402 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1403 flags |= RAL_TX_ACK; 1404 flags |= RAL_TX_RETRY(7); 1405 1406 dur = ieee80211_ack_duration(sc->sc_rates, rate, 1407 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1408 *(uint16_t *)wh->i_dur = htole16(dur); 1409 } 1410 1411 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1412 1413 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1414 m0->m_pkthdr.len, rate); 1415 1416 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1417 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1418 1419 return 0; 1420} 1421 1422static void 1423ural_start(struct ifnet *ifp) 1424{ 1425 struct ural_softc *sc = ifp->if_softc; 1426 struct ieee80211_node *ni; 1427 struct mbuf *m; 1428 1429 RAL_LOCK(sc); 1430 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1431 RAL_UNLOCK(sc); 1432 return; 1433 } 1434 for (;;) { 1435 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1436 if (m == NULL) 1437 break; 1438 if (sc->tx_nfree < RAL_TX_MINFREE) { 1439 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1440 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1441 break; 1442 } 1443 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1444 m = ieee80211_encap(ni, m); 1445 if (m == NULL) { 1446 ieee80211_free_node(ni); 1447 ifp->if_oerrors++; 1448 continue; 1449 } 1450 if (ural_tx_data(sc, m, ni) != 0) { 1451 ieee80211_free_node(ni); 1452 ifp->if_oerrors++; 1453 break; 1454 } 1455 } 1456 RAL_UNLOCK(sc); 1457} 1458 1459static int 1460ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1461{ 1462 struct ural_softc *sc = ifp->if_softc; 1463 struct ieee80211com *ic = ifp->if_l2com; 1464 struct ifreq *ifr = (struct ifreq *) data; 1465 int error = 0, startall = 0; 1466 1467 switch (cmd) { 1468 case SIOCSIFFLAGS: 1469 RAL_LOCK(sc); 1470 if (ifp->if_flags & IFF_UP) { 1471 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1472 ural_queue_command(sc, ural_init_task, 1473 &sc->sc_synctask[0].hdr, 1474 &sc->sc_synctask[1].hdr); 1475 startall = 1; 1476 } else 1477 ural_queue_command(sc, ural_promisctask, 1478 &sc->sc_promisctask[0].hdr, 1479 &sc->sc_promisctask[1].hdr); 1480 } else { 1481 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1482 ural_queue_command(sc, ural_stop_task, 1483 &sc->sc_synctask[0].hdr, 1484 &sc->sc_synctask[1].hdr); 1485 } 1486 } 1487 RAL_UNLOCK(sc); 1488 if (startall) 1489 ieee80211_start_all(ic); 1490 break; 1491 case SIOCGIFMEDIA: 1492 case SIOCSIFMEDIA: 1493 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1494 break; 1495 default: 1496 error = ether_ioctl(ifp, cmd, data); 1497 break; 1498 } 1499 return error; 1500} 1501 1502static void 1503ural_set_testmode(struct ural_softc *sc) 1504{ 1505 struct usb2_device_request req; 1506 usb2_error_t error; 1507 1508 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1509 req.bRequest = RAL_VENDOR_REQUEST; 1510 USETW(req.wValue, 4); 1511 USETW(req.wIndex, 1); 1512 USETW(req.wLength, 0); 1513 1514 error = ural_do_request(sc, &req, NULL); 1515 if (error != 0) { 1516 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1517 usb2_errstr(error)); 1518 } 1519} 1520 1521static void 1522ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1523{ 1524 struct usb2_device_request req; 1525 usb2_error_t error; 1526 1527 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1528 req.bRequest = RAL_READ_EEPROM; 1529 USETW(req.wValue, 0); 1530 USETW(req.wIndex, addr); 1531 USETW(req.wLength, len); 1532 1533 error = ural_do_request(sc, &req, buf); 1534 if (error != 0) { 1535 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1536 usb2_errstr(error)); 1537 } 1538} 1539 1540static uint16_t 1541ural_read(struct ural_softc *sc, uint16_t reg) 1542{ 1543 struct usb2_device_request req; 1544 usb2_error_t error; 1545 uint16_t val; 1546 1547 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1548 req.bRequest = RAL_READ_MAC; 1549 USETW(req.wValue, 0); 1550 USETW(req.wIndex, reg); 1551 USETW(req.wLength, sizeof (uint16_t)); 1552 1553 error = ural_do_request(sc, &req, &val); 1554 if (error != 0) { 1555 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1556 usb2_errstr(error)); 1557 return 0; 1558 } 1559 1560 return le16toh(val); 1561} 1562 1563static void 1564ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1565{ 1566 struct usb2_device_request req; 1567 usb2_error_t error; 1568 1569 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1570 req.bRequest = RAL_READ_MULTI_MAC; 1571 USETW(req.wValue, 0); 1572 USETW(req.wIndex, reg); 1573 USETW(req.wLength, len); 1574 1575 error = ural_do_request(sc, &req, buf); 1576 if (error != 0) { 1577 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1578 usb2_errstr(error)); 1579 } 1580} 1581 1582static void 1583ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1584{ 1585 struct usb2_device_request req; 1586 usb2_error_t error; 1587 1588 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1589 req.bRequest = RAL_WRITE_MAC; 1590 USETW(req.wValue, val); 1591 USETW(req.wIndex, reg); 1592 USETW(req.wLength, 0); 1593 1594 error = ural_do_request(sc, &req, NULL); 1595 if (error != 0) { 1596 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1597 usb2_errstr(error)); 1598 } 1599} 1600 1601static void 1602ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1603{ 1604 struct usb2_device_request req; 1605 usb2_error_t error; 1606 1607 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1608 req.bRequest = RAL_WRITE_MULTI_MAC; 1609 USETW(req.wValue, 0); 1610 USETW(req.wIndex, reg); 1611 USETW(req.wLength, len); 1612 1613 error = ural_do_request(sc, &req, buf); 1614 if (error != 0) { 1615 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1616 usb2_errstr(error)); 1617 } 1618} 1619 1620static void 1621ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1622{ 1623 uint16_t tmp; 1624 int ntries; 1625 1626 for (ntries = 0; ntries < 100; ntries++) { 1627 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1628 break; 1629 if (ural_pause(sc, hz / 100)) 1630 break; 1631 } 1632 if (ntries == 100) { 1633 device_printf(sc->sc_dev, "could not write to BBP\n"); 1634 return; 1635 } 1636 1637 tmp = reg << 8 | val; 1638 ural_write(sc, RAL_PHY_CSR7, tmp); 1639} 1640 1641static uint8_t 1642ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1643{ 1644 uint16_t val; 1645 int ntries; 1646 1647 val = RAL_BBP_WRITE | reg << 8; 1648 ural_write(sc, RAL_PHY_CSR7, val); 1649 1650 for (ntries = 0; ntries < 100; ntries++) { 1651 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1652 break; 1653 if (ural_pause(sc, hz / 100)) 1654 break; 1655 } 1656 if (ntries == 100) { 1657 device_printf(sc->sc_dev, "could not read BBP\n"); 1658 return 0; 1659 } 1660 1661 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1662} 1663 1664static void 1665ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1666{ 1667 uint32_t tmp; 1668 int ntries; 1669 1670 for (ntries = 0; ntries < 100; ntries++) { 1671 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1672 break; 1673 if (ural_pause(sc, hz / 100)) 1674 break; 1675 } 1676 if (ntries == 100) { 1677 device_printf(sc->sc_dev, "could not write to RF\n"); 1678 return; 1679 } 1680 1681 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1682 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1683 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1684 1685 /* remember last written value in sc */ 1686 sc->rf_regs[reg] = val; 1687 1688 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1689} 1690 1691/* ARGUSED */ 1692static struct ieee80211_node * 1693ural_node_alloc(struct ieee80211vap *vap __unused, 1694 const uint8_t mac[IEEE80211_ADDR_LEN] __unused) 1695{ 1696 struct ural_node *un; 1697 1698 un = malloc(sizeof(struct ural_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1699 return un != NULL ? &un->ni : NULL; 1700} 1701 1702static void 1703ural_newassoc(struct ieee80211_node *ni, int isnew) 1704{ 1705 struct ieee80211vap *vap = ni->ni_vap; 1706 1707 ieee80211_amrr_node_init(&URAL_VAP(vap)->amrr, &URAL_NODE(ni)->amn, ni); 1708} 1709 1710static void 1711ural_scan_start(struct ieee80211com *ic) 1712{ 1713 struct ural_softc *sc = ic->ic_ifp->if_softc; 1714 1715 RAL_LOCK(sc); 1716 /* do it in a process context */ 1717 sc->sc_scan_action = URAL_SCAN_START; 1718 ural_queue_command(sc, ural_scantask, 1719 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1720 RAL_UNLOCK(sc); 1721 1722} 1723 1724static void 1725ural_scan_end(struct ieee80211com *ic) 1726{ 1727 struct ural_softc *sc = ic->ic_ifp->if_softc; 1728 1729 RAL_LOCK(sc); 1730 /* do it in a process context */ 1731 sc->sc_scan_action = URAL_SCAN_END; 1732 ural_queue_command(sc, ural_scantask, 1733 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1734 RAL_UNLOCK(sc); 1735 1736} 1737 1738static void 1739ural_set_channel(struct ieee80211com *ic) 1740{ 1741 struct ural_softc *sc = ic->ic_ifp->if_softc; 1742 1743 RAL_LOCK(sc); 1744 /* do it in a process context */ 1745 sc->sc_scan_action = URAL_SET_CHANNEL; 1746 ural_queue_command(sc, ural_scantask, 1747 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1748 1749 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 1750 RAL_UNLOCK(sc); 1751} 1752 1753static void 1754ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1755{ 1756 struct ifnet *ifp = sc->sc_ifp; 1757 struct ieee80211com *ic = ifp->if_l2com; 1758 uint8_t power, tmp; 1759 int i, chan; 1760 1761 chan = ieee80211_chan2ieee(ic, c); 1762 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1763 return; 1764 1765 if (IEEE80211_IS_CHAN_2GHZ(c)) 1766 power = min(sc->txpow[chan - 1], 31); 1767 else 1768 power = 31; 1769 1770 /* adjust txpower using ifconfig settings */ 1771 power -= (100 - ic->ic_txpowlimit) / 8; 1772 1773 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1774 1775 switch (sc->rf_rev) { 1776 case RAL_RF_2522: 1777 ural_rf_write(sc, RAL_RF1, 0x00814); 1778 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1779 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1780 break; 1781 1782 case RAL_RF_2523: 1783 ural_rf_write(sc, RAL_RF1, 0x08804); 1784 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1785 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1786 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1787 break; 1788 1789 case RAL_RF_2524: 1790 ural_rf_write(sc, RAL_RF1, 0x0c808); 1791 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1792 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1793 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1794 break; 1795 1796 case RAL_RF_2525: 1797 ural_rf_write(sc, RAL_RF1, 0x08808); 1798 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1799 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1800 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1801 1802 ural_rf_write(sc, RAL_RF1, 0x08808); 1803 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1804 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1805 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1806 break; 1807 1808 case RAL_RF_2525E: 1809 ural_rf_write(sc, RAL_RF1, 0x08808); 1810 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1811 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1812 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1813 break; 1814 1815 case RAL_RF_2526: 1816 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1817 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1818 ural_rf_write(sc, RAL_RF1, 0x08804); 1819 1820 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1821 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1822 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1823 break; 1824 1825 /* dual-band RF */ 1826 case RAL_RF_5222: 1827 for (i = 0; ural_rf5222[i].chan != chan; i++); 1828 1829 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1830 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1831 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1832 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1833 break; 1834 } 1835 1836 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1837 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1838 /* set Japan filter bit for channel 14 */ 1839 tmp = ural_bbp_read(sc, 70); 1840 1841 tmp &= ~RAL_JAPAN_FILTER; 1842 if (chan == 14) 1843 tmp |= RAL_JAPAN_FILTER; 1844 1845 ural_bbp_write(sc, 70, tmp); 1846 1847 /* clear CRC errors */ 1848 ural_read(sc, RAL_STA_CSR0); 1849 1850 ural_pause(sc, hz / 100); 1851 ural_disable_rf_tune(sc); 1852 } 1853 1854 /* XXX doesn't belong here */ 1855 /* update basic rate set */ 1856 ural_set_basicrates(sc, c); 1857 1858 /* give the hardware some time to do the switchover */ 1859 ural_pause(sc, hz / 100); 1860} 1861 1862/* 1863 * Disable RF auto-tuning. 1864 */ 1865static void 1866ural_disable_rf_tune(struct ural_softc *sc) 1867{ 1868 uint32_t tmp; 1869 1870 if (sc->rf_rev != RAL_RF_2523) { 1871 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1872 ural_rf_write(sc, RAL_RF1, tmp); 1873 } 1874 1875 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1876 ural_rf_write(sc, RAL_RF3, tmp); 1877 1878 DPRINTFN(2, "disabling RF autotune\n"); 1879} 1880 1881/* 1882 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1883 * synchronization. 1884 */ 1885static void 1886ural_enable_tsf_sync(struct ural_softc *sc) 1887{ 1888 struct ifnet *ifp = sc->sc_ifp; 1889 struct ieee80211com *ic = ifp->if_l2com; 1890 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1891 uint16_t logcwmin, preload, tmp; 1892 1893 /* first, disable TSF synchronization */ 1894 ural_write(sc, RAL_TXRX_CSR19, 0); 1895 1896 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1897 ural_write(sc, RAL_TXRX_CSR18, tmp); 1898 1899 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1900 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1901 tmp = logcwmin << 12 | preload; 1902 ural_write(sc, RAL_TXRX_CSR20, tmp); 1903 1904 /* finally, enable TSF synchronization */ 1905 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1906 if (ic->ic_opmode == IEEE80211_M_STA) 1907 tmp |= RAL_ENABLE_TSF_SYNC(1); 1908 else 1909 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1910 ural_write(sc, RAL_TXRX_CSR19, tmp); 1911 1912 DPRINTF("enabling TSF synchronization\n"); 1913} 1914 1915#define RAL_RXTX_TURNAROUND 5 /* us */ 1916static void 1917ural_update_slot(struct ifnet *ifp) 1918{ 1919 struct ural_softc *sc = ifp->if_softc; 1920 struct ieee80211com *ic = ifp->if_l2com; 1921 uint16_t slottime, sifs, eifs; 1922 1923 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1924 1925 /* 1926 * These settings may sound a bit inconsistent but this is what the 1927 * reference driver does. 1928 */ 1929 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1930 sifs = 16 - RAL_RXTX_TURNAROUND; 1931 eifs = 364; 1932 } else { 1933 sifs = 10 - RAL_RXTX_TURNAROUND; 1934 eifs = 64; 1935 } 1936 1937 ural_write(sc, RAL_MAC_CSR10, slottime); 1938 ural_write(sc, RAL_MAC_CSR11, sifs); 1939 ural_write(sc, RAL_MAC_CSR12, eifs); 1940} 1941 1942static void 1943ural_set_txpreamble(struct ural_softc *sc) 1944{ 1945 struct ifnet *ifp = sc->sc_ifp; 1946 struct ieee80211com *ic = ifp->if_l2com; 1947 uint16_t tmp; 1948 1949 tmp = ural_read(sc, RAL_TXRX_CSR10); 1950 1951 tmp &= ~RAL_SHORT_PREAMBLE; 1952 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1953 tmp |= RAL_SHORT_PREAMBLE; 1954 1955 ural_write(sc, RAL_TXRX_CSR10, tmp); 1956} 1957 1958static void 1959ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1960{ 1961 /* XXX wrong, take from rate set */ 1962 /* update basic rate set */ 1963 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1964 /* 11a basic rates: 6, 12, 24Mbps */ 1965 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1966 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1967 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1968 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1969 } else { 1970 /* 11b basic rates: 1, 2Mbps */ 1971 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1972 } 1973} 1974 1975static void 1976ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1977{ 1978 uint16_t tmp; 1979 1980 tmp = bssid[0] | bssid[1] << 8; 1981 ural_write(sc, RAL_MAC_CSR5, tmp); 1982 1983 tmp = bssid[2] | bssid[3] << 8; 1984 ural_write(sc, RAL_MAC_CSR6, tmp); 1985 1986 tmp = bssid[4] | bssid[5] << 8; 1987 ural_write(sc, RAL_MAC_CSR7, tmp); 1988 1989 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1990} 1991 1992static void 1993ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1994{ 1995 uint16_t tmp; 1996 1997 tmp = addr[0] | addr[1] << 8; 1998 ural_write(sc, RAL_MAC_CSR2, tmp); 1999 2000 tmp = addr[2] | addr[3] << 8; 2001 ural_write(sc, RAL_MAC_CSR3, tmp); 2002 2003 tmp = addr[4] | addr[5] << 8; 2004 ural_write(sc, RAL_MAC_CSR4, tmp); 2005 2006 DPRINTF("setting MAC address to %6D\n", addr, ":"); 2007} 2008 2009static void 2010ural_promisctask(struct usb2_proc_msg *pm) 2011{ 2012 struct ural_task *task = (struct ural_task *)pm; 2013 struct ural_softc *sc = task->sc; 2014 struct ifnet *ifp = sc->sc_ifp; 2015 uint32_t tmp; 2016 2017 tmp = ural_read(sc, RAL_TXRX_CSR2); 2018 2019 tmp &= ~RAL_DROP_NOT_TO_ME; 2020 if (!(ifp->if_flags & IFF_PROMISC)) 2021 tmp |= RAL_DROP_NOT_TO_ME; 2022 2023 ural_write(sc, RAL_TXRX_CSR2, tmp); 2024 2025 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2026 "entering" : "leaving"); 2027} 2028 2029static void 2030ural_update_mcast(struct ifnet *ifp) 2031{ 2032 /* not supported */ 2033} 2034 2035static void 2036ural_update_promisc(struct ifnet *ifp) 2037{ 2038 struct ural_softc *sc = ifp->if_softc; 2039 2040 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2041 return; 2042 2043 RAL_LOCK(sc); 2044 ural_queue_command(sc, ural_promisctask, 2045 &sc->sc_promisctask[0].hdr, 2046 &sc->sc_promisctask[1].hdr); 2047 RAL_UNLOCK(sc); 2048} 2049 2050static const char * 2051ural_get_rf(int rev) 2052{ 2053 switch (rev) { 2054 case RAL_RF_2522: return "RT2522"; 2055 case RAL_RF_2523: return "RT2523"; 2056 case RAL_RF_2524: return "RT2524"; 2057 case RAL_RF_2525: return "RT2525"; 2058 case RAL_RF_2525E: return "RT2525e"; 2059 case RAL_RF_2526: return "RT2526"; 2060 case RAL_RF_5222: return "RT5222"; 2061 default: return "unknown"; 2062 } 2063} 2064 2065static void 2066ural_read_eeprom(struct ural_softc *sc) 2067{ 2068 uint16_t val; 2069 2070 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 2071 val = le16toh(val); 2072 sc->rf_rev = (val >> 11) & 0x7; 2073 sc->hw_radio = (val >> 10) & 0x1; 2074 sc->led_mode = (val >> 6) & 0x7; 2075 sc->rx_ant = (val >> 4) & 0x3; 2076 sc->tx_ant = (val >> 2) & 0x3; 2077 sc->nb_ant = val & 0x3; 2078 2079 /* read MAC address */ 2080 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 2081 2082 /* read default values for BBP registers */ 2083 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 2084 2085 /* read Tx power for all b/g channels */ 2086 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 2087} 2088 2089static int 2090ural_bbp_init(struct ural_softc *sc) 2091{ 2092#define N(a) (sizeof (a) / sizeof ((a)[0])) 2093 int i, ntries; 2094 2095 /* wait for BBP to be ready */ 2096 for (ntries = 0; ntries < 100; ntries++) { 2097 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 2098 break; 2099 if (ural_pause(sc, hz / 100)) 2100 break; 2101 } 2102 if (ntries == 100) { 2103 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2104 return EIO; 2105 } 2106 2107 /* initialize BBP registers to default values */ 2108 for (i = 0; i < N(ural_def_bbp); i++) 2109 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 2110 2111#if 0 2112 /* initialize BBP registers to values stored in EEPROM */ 2113 for (i = 0; i < 16; i++) { 2114 if (sc->bbp_prom[i].reg == 0xff) 2115 continue; 2116 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2117 } 2118#endif 2119 2120 return 0; 2121#undef N 2122} 2123 2124static void 2125ural_set_txantenna(struct ural_softc *sc, int antenna) 2126{ 2127 uint16_t tmp; 2128 uint8_t tx; 2129 2130 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 2131 if (antenna == 1) 2132 tx |= RAL_BBP_ANTA; 2133 else if (antenna == 2) 2134 tx |= RAL_BBP_ANTB; 2135 else 2136 tx |= RAL_BBP_DIVERSITY; 2137 2138 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2139 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2140 sc->rf_rev == RAL_RF_5222) 2141 tx |= RAL_BBP_FLIPIQ; 2142 2143 ural_bbp_write(sc, RAL_BBP_TX, tx); 2144 2145 /* update values in PHY_CSR5 and PHY_CSR6 */ 2146 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2147 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2148 2149 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2150 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2151} 2152 2153static void 2154ural_set_rxantenna(struct ural_softc *sc, int antenna) 2155{ 2156 uint8_t rx; 2157 2158 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2159 if (antenna == 1) 2160 rx |= RAL_BBP_ANTA; 2161 else if (antenna == 2) 2162 rx |= RAL_BBP_ANTB; 2163 else 2164 rx |= RAL_BBP_DIVERSITY; 2165 2166 /* need to force no I/Q flip for RF 2525e and 2526 */ 2167 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2168 rx &= ~RAL_BBP_FLIPIQ; 2169 2170 ural_bbp_write(sc, RAL_BBP_RX, rx); 2171} 2172 2173static void 2174ural_init_task(struct usb2_proc_msg *pm) 2175{ 2176#define N(a) (sizeof (a) / sizeof ((a)[0])) 2177 struct ural_task *task = (struct ural_task *)pm; 2178 struct ural_softc *sc = task->sc; 2179 struct ifnet *ifp = sc->sc_ifp; 2180 struct ieee80211com *ic = ifp->if_l2com; 2181 uint16_t tmp; 2182 int i, ntries; 2183 2184 RAL_LOCK_ASSERT(sc, MA_OWNED); 2185 2186 ural_set_testmode(sc); 2187 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2188 2189 ural_stop_task(pm); 2190 2191 /* initialize MAC registers to default values */ 2192 for (i = 0; i < N(ural_def_mac); i++) 2193 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2194 2195 /* wait for BBP and RF to wake up (this can take a long time!) */ 2196 for (ntries = 0; ntries < 100; ntries++) { 2197 tmp = ural_read(sc, RAL_MAC_CSR17); 2198 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2199 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2200 break; 2201 if (ural_pause(sc, hz / 100)) 2202 break; 2203 } 2204 if (ntries == 100) { 2205 device_printf(sc->sc_dev, 2206 "timeout waiting for BBP/RF to wakeup\n"); 2207 goto fail; 2208 } 2209 2210 /* we're ready! */ 2211 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2212 2213 /* set basic rate set (will be updated later) */ 2214 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2215 2216 if (ural_bbp_init(sc) != 0) 2217 goto fail; 2218 2219 ural_set_chan(sc, ic->ic_curchan); 2220 2221 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2222 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2223 2224 ural_set_txantenna(sc, sc->tx_ant); 2225 ural_set_rxantenna(sc, sc->rx_ant); 2226 2227 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2228 ural_set_macaddr(sc, ic->ic_myaddr); 2229 2230 /* 2231 * Allocate Tx and Rx xfer queues. 2232 */ 2233 ural_setup_tx_list(sc); 2234 2235 /* kick Rx */ 2236 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2237 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2238 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2239 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2240 tmp |= RAL_DROP_TODS; 2241 if (!(ifp->if_flags & IFF_PROMISC)) 2242 tmp |= RAL_DROP_NOT_TO_ME; 2243 } 2244 ural_write(sc, RAL_TXRX_CSR2, tmp); 2245 2246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2247 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2248 usb2_transfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2249 usb2_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2250 return; 2251 2252fail: ural_stop_task(pm); 2253#undef N 2254} 2255 2256static void 2257ural_init(void *priv) 2258{ 2259 struct ural_softc *sc = priv; 2260 struct ifnet *ifp = sc->sc_ifp; 2261 struct ieee80211com *ic = ifp->if_l2com; 2262 2263 RAL_LOCK(sc); 2264 ural_queue_command(sc, ural_init_task, 2265 &sc->sc_synctask[0].hdr, 2266 &sc->sc_synctask[1].hdr); 2267 RAL_UNLOCK(sc); 2268 2269 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2270 ieee80211_start_all(ic); /* start all vap's */ 2271} 2272 2273static void 2274ural_stop_task(struct usb2_proc_msg *pm) 2275{ 2276 struct ural_task *task = (struct ural_task *)pm; 2277 struct ural_softc *sc = task->sc; 2278 struct ifnet *ifp = sc->sc_ifp; 2279 2280 RAL_LOCK_ASSERT(sc, MA_OWNED); 2281 2282 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2283 2284 /* 2285 * Drain all the transfers, if not already drained: 2286 */ 2287 RAL_UNLOCK(sc); 2288 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2289 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2290 RAL_LOCK(sc); 2291 2292 ural_unsetup_tx_list(sc); 2293 2294 /* disable Rx */ 2295 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2296 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2297 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2298 /* wait a little */ 2299 ural_pause(sc, hz / 10); 2300 ural_write(sc, RAL_MAC_CSR1, 0); 2301 /* wait a little */ 2302 ural_pause(sc, hz / 10); 2303} 2304 2305static int 2306ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2307 const struct ieee80211_bpf_params *params) 2308{ 2309 struct ieee80211com *ic = ni->ni_ic; 2310 struct ifnet *ifp = ic->ic_ifp; 2311 struct ural_softc *sc = ifp->if_softc; 2312 2313 RAL_LOCK(sc); 2314 /* prevent management frames from being sent if we're not ready */ 2315 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2316 RAL_UNLOCK(sc); 2317 m_freem(m); 2318 ieee80211_free_node(ni); 2319 return ENETDOWN; 2320 } 2321 if (sc->tx_nfree < RAL_TX_MINFREE) { 2322 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2323 RAL_UNLOCK(sc); 2324 m_freem(m); 2325 ieee80211_free_node(ni); 2326 return EIO; 2327 } 2328 2329 ifp->if_opackets++; 2330 2331 if (params == NULL) { 2332 /* 2333 * Legacy path; interpret frame contents to decide 2334 * precisely how to send the frame. 2335 */ 2336 if (ural_tx_mgt(sc, m, ni) != 0) 2337 goto bad; 2338 } else { 2339 /* 2340 * Caller supplied explicit parameters to use in 2341 * sending the frame. 2342 */ 2343 if (ural_tx_raw(sc, m, ni, params) != 0) 2344 goto bad; 2345 } 2346 RAL_UNLOCK(sc); 2347 return 0; 2348bad: 2349 ifp->if_oerrors++; 2350 RAL_UNLOCK(sc); 2351 ieee80211_free_node(ni); 2352 return EIO; /* XXX */ 2353} 2354 2355static void 2356ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni) 2357{ 2358 struct ieee80211vap *vap = ni->ni_vap; 2359 struct ural_vap *uvp = URAL_VAP(vap); 2360 2361 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2362 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2363 2364 ieee80211_amrr_node_init(&uvp->amrr, &URAL_NODE(ni)->amn, ni); 2365 2366 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2367} 2368 2369static void 2370ural_amrr_timeout(void *arg) 2371{ 2372 struct ural_vap *uvp = arg; 2373 struct ural_softc *sc = uvp->sc; 2374 2375 ural_queue_command(sc, ural_amrr_task, 2376 &uvp->amrr_task[0].hdr, &uvp->amrr_task[1].hdr); 2377} 2378 2379static void 2380ural_amrr_task(struct usb2_proc_msg *pm) 2381{ 2382 struct ural_task *task = (struct ural_task *)pm; 2383 struct ural_softc *sc = task->sc; 2384 struct ifnet *ifp = sc->sc_ifp; 2385 struct ieee80211com *ic = ifp->if_l2com; 2386 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2387 struct ural_vap *uvp = URAL_VAP(vap); 2388 struct ieee80211_node *ni = vap->iv_bss; 2389 int ok, fail; 2390 2391 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2392 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2393 2394 ok = sc->sta[7] + /* TX ok w/o retry */ 2395 sc->sta[8]; /* TX ok w/ retry */ 2396 fail = sc->sta[9]; /* TX retry-fail count */ 2397 2398 ieee80211_amrr_tx_update(&URAL_NODE(ni)->amn, 2399 ok+fail, ok, sc->sta[8] + fail); 2400 (void) ieee80211_amrr_choose(ni, &URAL_NODE(ni)->amn); 2401 2402 ifp->if_oerrors += fail; /* count TX retry-fail as Tx errors */ 2403 2404 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2405} 2406 2407static int 2408ural_pause(struct ural_softc *sc, int timeout) 2409{ 2410 if (usb2_proc_is_gone(&sc->sc_tq)) 2411 return (1); 2412 2413 usb2_pause_mtx(&sc->sc_mtx, timeout); 2414 return (0); 2415} 2416 2417static void 2418ural_command_wrapper(struct usb2_proc_msg *pm) 2419{ 2420 struct ural_task *task = (struct ural_task *)pm; 2421 struct ural_softc *sc = task->sc; 2422 struct ifnet *ifp; 2423 2424 /* wait for pending transfer, if any */ 2425 while (usb2_transfer_pending(sc->sc_xfer[URAL_BULK_WR])) 2426 cv_wait(&sc->sc_cmd_cv, &sc->sc_mtx); 2427 2428 /* make sure any hardware FIFOs are emptied */ 2429 ural_pause(sc, hz / 1000); 2430 2431 /* execute task */ 2432 task->func(pm); 2433 2434 /* check if this is the last task executed */ 2435 if (sc->sc_last_task == task) { 2436 sc->sc_last_task = NULL; 2437 ifp = sc->sc_ifp; 2438 /* re-start TX, if any */ 2439 if ((ifp != NULL) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 2440 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 2441 } 2442} 2443 2444static void 2445ural_queue_command(struct ural_softc *sc, usb2_proc_callback_t *fn, 2446 struct usb2_proc_msg *t0, struct usb2_proc_msg *t1) 2447{ 2448 struct ural_task *task; 2449 2450 RAL_LOCK_ASSERT(sc, MA_OWNED); 2451 2452 /* 2453 * NOTE: The task cannot get executed before we drop the 2454 * "sc_mtx" mutex. It is safe to update fields in the message 2455 * structure after that the message got queued. 2456 */ 2457 task = (struct ural_task *) 2458 usb2_proc_msignal(&sc->sc_tq, t0, t1); 2459 2460 /* Setup callback and softc pointers */ 2461 task->hdr.pm_callback = ural_command_wrapper; 2462 task->func = fn; 2463 task->sc = sc; 2464 2465 /* Make sure that any TX operation will stop */ 2466 sc->sc_last_task = task; 2467 2468 /* 2469 * Init, stop and flush must be synchronous! 2470 */ 2471 if ((fn == ural_init_task) || (fn == ural_stop_task) || 2472 (fn == ural_stop_task)) 2473 usb2_proc_mwait(&sc->sc_tq, t0, t1); 2474} 2475