if_ural.c revision 185950
1/* $FreeBSD: head/sys/dev/usb2/wlan/if_ural2.c 185950 2008-12-11 23:17:48Z thompsa $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@freebsd.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 * 22 */ 23 24/* 25 * 26 * NOTE: all function names beginning like "ural_cfg_" can only 27 * be called from within the config thread function ! 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/usb2/wlan/if_ural2.c 185950 2008-12-11 23:17:48Z thompsa $"); 32 33/*- 34 * Ralink Technology RT2500USB chipset driver 35 * http://www.ralinktech.com/ 36 */ 37 38#include <dev/usb2/include/usb2_devid.h> 39#include <dev/usb2/include/usb2_standard.h> 40#include <dev/usb2/include/usb2_mfunc.h> 41#include <dev/usb2/include/usb2_error.h> 42 43#define usb2_config_td_cc ural_config_copy 44#define usb2_config_td_softc ural_softc 45 46#define USB_DEBUG_VAR ural_debug 47 48#include <dev/usb2/core/usb2_core.h> 49#include <dev/usb2/core/usb2_lookup.h> 50#include <dev/usb2/core/usb2_process.h> 51#include <dev/usb2/core/usb2_config_td.h> 52#include <dev/usb2/core/usb2_debug.h> 53#include <dev/usb2/core/usb2_request.h> 54#include <dev/usb2/core/usb2_busdma.h> 55#include <dev/usb2/core/usb2_util.h> 56 57#include <dev/usb2/wlan/usb2_wlan.h> 58#include <dev/usb2/wlan/if_ural2_reg.h> 59#include <dev/usb2/wlan/if_ural2_var.h> 60 61#if USB_DEBUG 62static int ural_debug = 0; 63 64SYSCTL_NODE(_hw_usb2, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 65SYSCTL_INT(_hw_usb2_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 66 "Debug level"); 67#endif 68 69#define URAL_RSSI(rssi) \ 70 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 71 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 72 73/* prototypes */ 74 75static device_probe_t ural_probe; 76static device_attach_t ural_attach; 77static device_detach_t ural_detach; 78 79static usb2_callback_t ural_bulk_read_callback; 80static usb2_callback_t ural_bulk_read_clear_stall_callback; 81static usb2_callback_t ural_bulk_write_callback; 82static usb2_callback_t ural_bulk_write_clear_stall_callback; 83 84static usb2_config_td_command_t ural_cfg_first_time_setup; 85static usb2_config_td_command_t ural_config_copy; 86static usb2_config_td_command_t ural_cfg_scan_start; 87static usb2_config_td_command_t ural_cfg_scan_end; 88static usb2_config_td_command_t ural_cfg_set_chan; 89static usb2_config_td_command_t ural_cfg_enable_tsf_sync; 90static usb2_config_td_command_t ural_cfg_update_slot; 91static usb2_config_td_command_t ural_cfg_set_txpreamble; 92static usb2_config_td_command_t ural_cfg_update_promisc; 93static usb2_config_td_command_t ural_cfg_pre_init; 94static usb2_config_td_command_t ural_cfg_init; 95static usb2_config_td_command_t ural_cfg_pre_stop; 96static usb2_config_td_command_t ural_cfg_stop; 97static usb2_config_td_command_t ural_cfg_amrr_timeout; 98static usb2_config_td_command_t ural_cfg_newstate; 99 100static void ural_cfg_do_request(struct ural_softc *, 101 struct usb2_device_request *, void *); 102static void ural_cfg_set_testmode(struct ural_softc *); 103static void ural_cfg_eeprom_read(struct ural_softc *, uint16_t, void *, 104 uint16_t); 105static uint16_t ural_cfg_read(struct ural_softc *, uint16_t); 106static void ural_cfg_read_multi(struct ural_softc *, uint16_t, void *, 107 uint16_t); 108static void ural_cfg_write(struct ural_softc *, uint16_t, uint16_t); 109static void ural_cfg_write_multi(struct ural_softc *, uint16_t, void *, 110 uint16_t); 111static void ural_cfg_bbp_write(struct ural_softc *, uint8_t, uint8_t); 112static uint8_t ural_cfg_bbp_read(struct ural_softc *, uint8_t); 113static void ural_cfg_rf_write(struct ural_softc *, uint8_t, uint32_t); 114static void ural_end_of_commands(struct ural_softc *); 115static const char *ural_get_rf(int rev); 116static void ural_watchdog(void *); 117static void ural_init_cb(void *); 118static int ural_ioctl_cb(struct ifnet *, u_long cmd, caddr_t data); 119static void ural_start_cb(struct ifnet *); 120static int ural_newstate_cb(struct ieee80211vap *, 121 enum ieee80211_state, int); 122static void ural_std_command(struct ieee80211com *, 123 usb2_config_td_command_t *); 124static void ural_scan_start_cb(struct ieee80211com *); 125static void ural_scan_end_cb(struct ieee80211com *); 126static void ural_set_channel_cb(struct ieee80211com *); 127static void ural_cfg_disable_rf_tune(struct ural_softc *); 128static void ural_cfg_set_bssid(struct ural_softc *, uint8_t *); 129static void ural_cfg_set_macaddr(struct ural_softc *, uint8_t *); 130static void ural_cfg_set_txantenna(struct ural_softc *, uint8_t); 131static void ural_cfg_set_rxantenna(struct ural_softc *, uint8_t); 132static void ural_cfg_read_eeprom(struct ural_softc *); 133static uint8_t ural_cfg_bbp_init(struct ural_softc *); 134static void ural_cfg_amrr_start(struct ural_softc *); 135static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 136 const char name[IFNAMSIZ], int unit, int opmode, int flags, 137 const uint8_t bssid[IEEE80211_ADDR_LEN], const uint8_t 138 mac[IEEE80211_ADDR_LEN]); 139static void ural_vap_delete(struct ieee80211vap *); 140static struct ieee80211_node *ural_node_alloc(struct ieee80211vap *, 141 const uint8_t mac[IEEE80211_ADDR_LEN]); 142static void ural_newassoc(struct ieee80211_node *, int); 143static void ural_cfg_disable_tsf_sync(struct ural_softc *); 144static void ural_cfg_set_run(struct ural_softc *, 145 struct usb2_config_td_cc *); 146static void ural_fill_write_queue(struct ural_softc *); 147static void ural_tx_clean_queue(struct ural_softc *); 148static void ural_tx_freem(struct mbuf *); 149static void ural_tx_mgt(struct ural_softc *, struct mbuf *, 150 struct ieee80211_node *); 151static struct ieee80211vap *ural_get_vap(struct ural_softc *); 152static void ural_tx_bcn(struct ural_softc *); 153static void ural_tx_data(struct ural_softc *, struct mbuf *, 154 struct ieee80211_node *); 155static void ural_tx_prot(struct ural_softc *, const struct mbuf *, 156 struct ieee80211_node *, uint8_t, uint16_t); 157static void ural_tx_raw(struct ural_softc *, struct mbuf *, 158 struct ieee80211_node *, 159 const struct ieee80211_bpf_params *); 160static int ural_raw_xmit_cb(struct ieee80211_node *, struct mbuf *, 161 const struct ieee80211_bpf_params *); 162static void ural_setup_desc_and_tx(struct ural_softc *, struct mbuf *, 163 uint32_t, uint16_t); 164static void ural_update_mcast_cb(struct ifnet *); 165static void ural_update_promisc_cb(struct ifnet *); 166 167/* various supported device vendors/products */ 168static const struct usb2_device_id ural_devs[] = { 169 {USB_VPI(USB_VENDOR_ASUS, USB_PRODUCT_ASUS_WL167G, 0)}, 170 {USB_VPI(USB_VENDOR_ASUS, USB_PRODUCT_RALINK_RT2570, 0)}, 171 {USB_VPI(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7050, 0)}, 172 {USB_VPI(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7051, 0)}, 173 {USB_VPI(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_HU200TS, 0)}, 174 {USB_VPI(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54G, 0)}, 175 {USB_VPI(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54GP, 0)}, 176 {USB_VPI(USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_C54RU, 0)}, 177 {USB_VPI(USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWLG122, 0)}, 178 {USB_VPI(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GN54G, 0)}, 179 {USB_VPI(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GNWBKG, 0)}, 180 {USB_VPI(USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUSB254, 0)}, 181 {USB_VPI(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54, 0)}, 182 {USB_VPI(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54AI, 0)}, 183 {USB_VPI(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54YB, 0)}, 184 {USB_VPI(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_NINWIFI, 0)}, 185 {USB_VPI(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570, 0)}, 186 {USB_VPI(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_2, 0)}, 187 {USB_VPI(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_3, 0)}, 188 {USB_VPI(USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_NV902, 0)}, 189 {USB_VPI(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570, 0)}, 190 {USB_VPI(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_2, 0)}, 191 {USB_VPI(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_3, 0)}, 192 {USB_VPI(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2573, 0)}, 193 {USB_VPI(USB_VENDOR_SIEMENS2, USB_PRODUCT_SIEMENS2_WL54G, 0)}, 194 {USB_VPI(USB_VENDOR_SMC, USB_PRODUCT_SMC_2862WG, 0)}, 195 {USB_VPI(USB_VENDOR_SPHAIRON, USB_PRODUCT_SPHAIRON_UB801R, 0)}, 196 {USB_VPI(USB_VENDOR_SURECOM, USB_PRODUCT_SURECOM_RT2570, 0)}, 197 {USB_VPI(USB_VENDOR_VTECH, USB_PRODUCT_VTECH_RT2570, 0)}, 198 {USB_VPI(USB_VENDOR_ZINWELL, USB_PRODUCT_ZINWELL_RT2570, 0)}, 199}; 200 201/* 202 * Default values for MAC registers; values taken from 203 * the reference driver: 204 */ 205struct ural_def_mac { 206 uint16_t reg; 207 uint16_t val; 208}; 209 210static const struct ural_def_mac ural_def_mac[] = { 211 {RAL_TXRX_CSR5, 0x8c8d}, 212 {RAL_TXRX_CSR6, 0x8b8a}, 213 {RAL_TXRX_CSR7, 0x8687}, 214 {RAL_TXRX_CSR8, 0x0085}, 215 {RAL_MAC_CSR13, 0x1111}, 216 {RAL_MAC_CSR14, 0x1e11}, 217 {RAL_TXRX_CSR21, 0xe78f}, 218 {RAL_MAC_CSR9, 0xff1d}, 219 {RAL_MAC_CSR11, 0x0002}, 220 {RAL_MAC_CSR22, 0x0053}, 221 {RAL_MAC_CSR15, 0x0000}, 222 {RAL_MAC_CSR8, RAL_FRAME_SIZE}, 223 {RAL_TXRX_CSR19, 0x0000}, 224 {RAL_TXRX_CSR18, 0x005a}, 225 {RAL_PHY_CSR2, 0x0000}, 226 {RAL_TXRX_CSR0, 0x1ec0}, 227 {RAL_PHY_CSR4, 0x000f} 228}; 229 230/* 231 * Default values for BBP registers; values taken from the reference driver. 232 */ 233struct ural_def_bbp { 234 uint8_t reg; 235 uint8_t val; 236}; 237 238static const struct ural_def_bbp ural_def_bbp[] = { 239 {3, 0x02}, 240 {4, 0x19}, 241 {14, 0x1c}, 242 {15, 0x30}, 243 {16, 0xac}, 244 {17, 0x48}, 245 {18, 0x18}, 246 {19, 0xff}, 247 {20, 0x1e}, 248 {21, 0x08}, 249 {22, 0x08}, 250 {23, 0x08}, 251 {24, 0x80}, 252 {25, 0x50}, 253 {26, 0x08}, 254 {27, 0x23}, 255 {30, 0x10}, 256 {31, 0x2b}, 257 {32, 0xb9}, 258 {34, 0x12}, 259 {35, 0x50}, 260 {39, 0xc4}, 261 {40, 0x02}, 262 {41, 0x60}, 263 {53, 0x10}, 264 {54, 0x18}, 265 {56, 0x08}, 266 {57, 0x10}, 267 {58, 0x08}, 268 {61, 0x60}, 269 {62, 0x10}, 270 {75, 0xff} 271}; 272 273/* 274 * Default values for RF register R2 indexed by channel numbers. 275 */ 276static const uint32_t ural_rf2522_r2[] = { 277 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 278 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 279}; 280 281static const uint32_t ural_rf2523_r2[] = { 282 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 283 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 284}; 285 286static const uint32_t ural_rf2524_r2[] = { 287 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 288 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 289}; 290 291static const uint32_t ural_rf2525_r2[] = { 292 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 293 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 294}; 295 296static const uint32_t ural_rf2525_hi_r2[] = { 297 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 298 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 299}; 300 301static const uint32_t ural_rf2525e_r2[] = { 302 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 303 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 304}; 305 306static const uint32_t ural_rf2526_hi_r2[] = { 307 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 308 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 309}; 310 311static const uint32_t ural_rf2526_r2[] = { 312 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 313 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 314}; 315 316/* 317 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 318 * values taken from the reference driver. 319 */ 320struct ural_rf5222 { 321 uint8_t chan; 322 uint32_t r1; 323 uint32_t r2; 324 uint32_t r4; 325}; 326 327static const struct ural_rf5222 ural_rf5222[] = { 328 {1, 0x08808, 0x0044d, 0x00282}, 329 {2, 0x08808, 0x0044e, 0x00282}, 330 {3, 0x08808, 0x0044f, 0x00282}, 331 {4, 0x08808, 0x00460, 0x00282}, 332 {5, 0x08808, 0x00461, 0x00282}, 333 {6, 0x08808, 0x00462, 0x00282}, 334 {7, 0x08808, 0x00463, 0x00282}, 335 {8, 0x08808, 0x00464, 0x00282}, 336 {9, 0x08808, 0x00465, 0x00282}, 337 {10, 0x08808, 0x00466, 0x00282}, 338 {11, 0x08808, 0x00467, 0x00282}, 339 {12, 0x08808, 0x00468, 0x00282}, 340 {13, 0x08808, 0x00469, 0x00282}, 341 {14, 0x08808, 0x0046b, 0x00286}, 342 343 {36, 0x08804, 0x06225, 0x00287}, 344 {40, 0x08804, 0x06226, 0x00287}, 345 {44, 0x08804, 0x06227, 0x00287}, 346 {48, 0x08804, 0x06228, 0x00287}, 347 {52, 0x08804, 0x06229, 0x00287}, 348 {56, 0x08804, 0x0622a, 0x00287}, 349 {60, 0x08804, 0x0622b, 0x00287}, 350 {64, 0x08804, 0x0622c, 0x00287}, 351 352 {100, 0x08804, 0x02200, 0x00283}, 353 {104, 0x08804, 0x02201, 0x00283}, 354 {108, 0x08804, 0x02202, 0x00283}, 355 {112, 0x08804, 0x02203, 0x00283}, 356 {116, 0x08804, 0x02204, 0x00283}, 357 {120, 0x08804, 0x02205, 0x00283}, 358 {124, 0x08804, 0x02206, 0x00283}, 359 {128, 0x08804, 0x02207, 0x00283}, 360 {132, 0x08804, 0x02208, 0x00283}, 361 {136, 0x08804, 0x02209, 0x00283}, 362 {140, 0x08804, 0x0220a, 0x00283}, 363 364 {149, 0x08808, 0x02429, 0x00281}, 365 {153, 0x08808, 0x0242b, 0x00281}, 366 {157, 0x08808, 0x0242d, 0x00281}, 367 {161, 0x08808, 0x0242f, 0x00281} 368}; 369 370static const struct usb2_config ural_config[URAL_N_TRANSFER] = { 371 [0] = { 372 .type = UE_BULK, 373 .endpoint = UE_ADDR_ANY, 374 .direction = UE_DIR_OUT, 375 .mh.bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 376 .mh.flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 377 .mh.callback = &ural_bulk_write_callback, 378 .mh.timeout = 5000, /* ms */ 379 }, 380 381 [1] = { 382 .type = UE_BULK, 383 .endpoint = UE_ADDR_ANY, 384 .direction = UE_DIR_IN, 385 .mh.bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 386 .mh.flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 387 .mh.callback = &ural_bulk_read_callback, 388 }, 389 390 [2] = { 391 .type = UE_CONTROL, 392 .endpoint = 0x00, /* Control pipe */ 393 .direction = UE_DIR_ANY, 394 .mh.bufsize = sizeof(struct usb2_device_request), 395 .mh.callback = &ural_bulk_write_clear_stall_callback, 396 .mh.timeout = 1000, /* 1 second */ 397 .mh.interval = 50, /* 50ms */ 398 }, 399 400 [3] = { 401 .type = UE_CONTROL, 402 .endpoint = 0x00, /* Control pipe */ 403 .direction = UE_DIR_ANY, 404 .mh.bufsize = sizeof(struct usb2_device_request), 405 .mh.callback = &ural_bulk_read_clear_stall_callback, 406 .mh.timeout = 1000, /* 1 second */ 407 .mh.interval = 50, /* 50ms */ 408 }, 409}; 410 411static devclass_t ural_devclass; 412 413static device_method_t ural_methods[] = { 414 DEVMETHOD(device_probe, ural_probe), 415 DEVMETHOD(device_attach, ural_attach), 416 DEVMETHOD(device_detach, ural_detach), 417 {0, 0} 418}; 419 420static driver_t ural_driver = { 421 .name = "ural", 422 .methods = ural_methods, 423 .size = sizeof(struct ural_softc), 424}; 425 426DRIVER_MODULE(ural, ushub, ural_driver, ural_devclass, NULL, 0); 427MODULE_DEPEND(ural, usb2_wlan, 1, 1, 1); 428MODULE_DEPEND(ural, usb2_core, 1, 1, 1); 429MODULE_DEPEND(ural, wlan, 1, 1, 1); 430MODULE_DEPEND(ural, wlan_amrr, 1, 1, 1); 431 432static int 433ural_probe(device_t dev) 434{ 435 struct usb2_attach_arg *uaa = device_get_ivars(dev); 436 437 if (uaa->usb2_mode != USB_MODE_HOST) { 438 return (ENXIO); 439 } 440 if (uaa->info.bConfigIndex != 0) { 441 return (ENXIO); 442 } 443 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) { 444 return (ENXIO); 445 } 446 return (usb2_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 447} 448 449static int 450ural_attach(device_t dev) 451{ 452 struct usb2_attach_arg *uaa = device_get_ivars(dev); 453 struct ural_softc *sc = device_get_softc(dev); 454 int error; 455 uint8_t iface_index; 456 457 if (sc == NULL) { 458 return (ENOMEM); 459 } 460 device_set_usb2_desc(dev); 461 462 mtx_init(&sc->sc_mtx, "ural lock", MTX_NETWORK_LOCK, 463 MTX_DEF | MTX_RECURSE); 464 465 snprintf(sc->sc_name, sizeof(sc->sc_name), "%s", 466 device_get_nameunit(dev)); 467 468 sc->sc_udev = uaa->device; 469 sc->sc_unit = device_get_unit(dev); 470 471 usb2_callout_init_mtx(&sc->sc_watchdog, 472 &sc->sc_mtx, CALLOUT_RETURNUNLOCKED); 473 474 iface_index = RAL_IFACE_INDEX; 475 error = usb2_transfer_setup(uaa->device, 476 &iface_index, sc->sc_xfer, ural_config, 477 URAL_N_TRANSFER, sc, &sc->sc_mtx); 478 479 if (error) { 480 device_printf(dev, "could not allocate USB transfers, " 481 "err=%s\n", usb2_errstr(error)); 482 goto detach; 483 } 484 error = usb2_config_td_setup(&sc->sc_config_td, sc, &sc->sc_mtx, 485 &ural_end_of_commands, 486 sizeof(struct usb2_config_td_cc), 24); 487 if (error) { 488 device_printf(dev, "could not setup config " 489 "thread!\n"); 490 goto detach; 491 } 492 mtx_lock(&sc->sc_mtx); 493 494 /* start setup */ 495 496 usb2_config_td_queue_command 497 (&sc->sc_config_td, NULL, &ural_cfg_first_time_setup, 0, 0); 498 499 /* start watchdog (will exit mutex) */ 500 501 ural_watchdog(sc); 502 503 return (0); /* success */ 504 505detach: 506 ural_detach(dev); 507 return (ENXIO); /* failure */ 508} 509 510static int 511ural_detach(device_t dev) 512{ 513 struct ural_softc *sc = device_get_softc(dev); 514 struct ieee80211com *ic; 515 struct ifnet *ifp; 516 517 usb2_config_td_drain(&sc->sc_config_td); 518 519 mtx_lock(&sc->sc_mtx); 520 521 usb2_callout_stop(&sc->sc_watchdog); 522 523 ural_cfg_pre_stop(sc, NULL, 0); 524 525 ifp = sc->sc_ifp; 526 ic = ifp->if_l2com; 527 528 mtx_unlock(&sc->sc_mtx); 529 530 /* stop all USB transfers first */ 531 usb2_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 532 533 /* get rid of any late children */ 534 bus_generic_detach(dev); 535 536 if (ifp) { 537 bpfdetach(ifp); 538 ieee80211_ifdetach(ic); 539 if_free(ifp); 540 } 541 usb2_config_td_unsetup(&sc->sc_config_td); 542 543 usb2_callout_drain(&sc->sc_watchdog); 544 545 mtx_destroy(&sc->sc_mtx); 546 547 return (0); 548} 549 550/*========================================================================* 551 * REGISTER READ / WRITE WRAPPER ROUTINES 552 *========================================================================*/ 553 554static void 555ural_cfg_do_request(struct ural_softc *sc, struct usb2_device_request *req, 556 void *data) 557{ 558 uint16_t length; 559 usb2_error_t err; 560 561repeat: 562 563 if (usb2_config_td_is_gone(&sc->sc_config_td)) { 564 goto error; 565 } 566 err = usb2_do_request_flags 567 (sc->sc_udev, &sc->sc_mtx, req, data, 0, NULL, 1000); 568 569 if (err) { 570 571 DPRINTF("device request failed, err=%s " 572 "(ignored)\n", usb2_errstr(err)); 573 574 /* wait a little before next try */ 575 if (usb2_config_td_sleep(&sc->sc_config_td, hz / 4)) { 576 goto error; 577 } 578 /* try until we are detached */ 579 goto repeat; 580 581error: 582 /* the device has been detached */ 583 length = UGETW(req->wLength); 584 585 if ((req->bmRequestType & UT_READ) && length) { 586 bzero(data, length); 587 } 588 } 589} 590 591static void 592ural_cfg_set_testmode(struct ural_softc *sc) 593{ 594 struct usb2_device_request req; 595 596 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 597 req.bRequest = RAL_VENDOR_REQUEST; 598 USETW(req.wValue, 4); 599 USETW(req.wIndex, 1); 600 USETW(req.wLength, 0); 601 602 ural_cfg_do_request(sc, &req, NULL); 603} 604 605static void 606ural_cfg_eeprom_read(struct ural_softc *sc, uint16_t addr, 607 void *buf, uint16_t len) 608{ 609 struct usb2_device_request req; 610 611 req.bmRequestType = UT_READ_VENDOR_DEVICE; 612 req.bRequest = RAL_READ_EEPROM; 613 USETW(req.wValue, 0); 614 USETW(req.wIndex, addr); 615 USETW(req.wLength, len); 616 617 ural_cfg_do_request(sc, &req, buf); 618} 619 620static uint16_t 621ural_cfg_read(struct ural_softc *sc, uint16_t reg) 622{ 623 struct usb2_device_request req; 624 uint16_t val; 625 626 req.bmRequestType = UT_READ_VENDOR_DEVICE; 627 req.bRequest = RAL_READ_MAC; 628 USETW(req.wValue, 0); 629 USETW(req.wIndex, reg); 630 USETW(req.wLength, sizeof(val)); 631 632 ural_cfg_do_request(sc, &req, &val); 633 634 return (le16toh(val)); 635} 636 637static void 638ural_cfg_read_multi(struct ural_softc *sc, uint16_t reg, 639 void *buf, uint16_t len) 640{ 641 struct usb2_device_request req; 642 643 req.bmRequestType = UT_READ_VENDOR_DEVICE; 644 req.bRequest = RAL_READ_MULTI_MAC; 645 USETW(req.wValue, 0); 646 USETW(req.wIndex, reg); 647 USETW(req.wLength, len); 648 649 ural_cfg_do_request(sc, &req, buf); 650} 651 652static void 653ural_cfg_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 654{ 655 struct usb2_device_request req; 656 657 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 658 req.bRequest = RAL_WRITE_MAC; 659 USETW(req.wValue, val); 660 USETW(req.wIndex, reg); 661 USETW(req.wLength, 0); 662 663 ural_cfg_do_request(sc, &req, NULL); 664} 665 666static void 667ural_cfg_write_multi(struct ural_softc *sc, uint16_t reg, 668 void *buf, uint16_t len) 669{ 670 struct usb2_device_request req; 671 672 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 673 req.bRequest = RAL_WRITE_MULTI_MAC; 674 USETW(req.wValue, 0); 675 USETW(req.wIndex, reg); 676 USETW(req.wLength, len); 677 678 ural_cfg_do_request(sc, &req, buf); 679} 680 681static uint8_t 682ural_cfg_bbp_disbusy(struct ural_softc *sc) 683{ 684 uint16_t tmp; 685 uint8_t to; 686 687 for (to = 0;; to++) { 688 if (to < 100) { 689 tmp = ural_cfg_read(sc, RAL_PHY_CSR8); 690 tmp &= RAL_BBP_BUSY; 691 692 if (tmp == 0) { 693 return (0); 694 } 695 if (usb2_config_td_sleep(&sc->sc_config_td, hz / 100)) { 696 break; 697 } 698 } else { 699 break; 700 } 701 } 702 DPRINTF("could not disbusy BBP\n"); 703 return (1); /* failure */ 704} 705 706static void 707ural_cfg_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 708{ 709 uint16_t tmp; 710 711 if (ural_cfg_bbp_disbusy(sc)) { 712 return; 713 } 714 tmp = (reg << 8) | val; 715 ural_cfg_write(sc, RAL_PHY_CSR7, tmp); 716} 717 718static uint8_t 719ural_cfg_bbp_read(struct ural_softc *sc, uint8_t reg) 720{ 721 uint16_t val; 722 723 if (ural_cfg_bbp_disbusy(sc)) { 724 return (0); 725 } 726 val = RAL_BBP_WRITE | (reg << 8); 727 ural_cfg_write(sc, RAL_PHY_CSR7, val); 728 729 if (ural_cfg_bbp_disbusy(sc)) { 730 return (0); 731 } 732 return (ural_cfg_read(sc, RAL_PHY_CSR7) & 0xff); 733} 734 735static void 736ural_cfg_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 737{ 738 uint32_t tmp; 739 uint8_t to; 740 741 reg &= 3; 742 743 /* remember last written value */ 744 sc->sc_rf_regs[reg] = val; 745 746 for (to = 0;; to++) { 747 if (to < 100) { 748 tmp = ural_cfg_read(sc, RAL_PHY_CSR10); 749 750 if (!(tmp & RAL_RF_LOBUSY)) { 751 break; 752 } 753 if (usb2_config_td_sleep(&sc->sc_config_td, hz / 100)) { 754 return; 755 } 756 } else { 757 DPRINTF("could not write to RF\n"); 758 return; 759 } 760 } 761 762 tmp = RAL_RF_BUSY | RAL_RF_20BIT | ((val & 0xfffff) << 2) | reg; 763 ural_cfg_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 764 ural_cfg_write(sc, RAL_PHY_CSR10, tmp >> 16); 765 766 DPRINTFN(16, "RF R[%u] <- 0x%05x\n", reg, val & 0xfffff); 767} 768 769static void 770ural_cfg_first_time_setup(struct ural_softc *sc, 771 struct usb2_config_td_cc *cc, uint16_t refcount) 772{ 773 struct ieee80211com *ic; 774 struct ifnet *ifp; 775 uint8_t bands; 776 777 /* setup RX tap header */ 778 sc->sc_rxtap_len = sizeof(sc->sc_rxtap); 779 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 780 sc->sc_rxtap.wr_ihdr.it_present = htole32(RAL_RX_RADIOTAP_PRESENT); 781 782 /* setup TX tap header */ 783 sc->sc_txtap_len = sizeof(sc->sc_txtap); 784 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 785 sc->sc_txtap.wt_ihdr.it_present = htole32(RAL_TX_RADIOTAP_PRESENT); 786 787 /* retrieve RT2570 rev. no */ 788 sc->sc_asic_rev = ural_cfg_read(sc, RAL_MAC_CSR0); 789 790 /* retrieve MAC address and various other things from EEPROM */ 791 ural_cfg_read_eeprom(sc); 792 793 printf("%s: MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 794 sc->sc_name, sc->sc_asic_rev, ural_get_rf(sc->sc_rf_rev)); 795 796 mtx_unlock(&sc->sc_mtx); 797 798 ifp = if_alloc(IFT_IEEE80211); 799 800 mtx_lock(&sc->sc_mtx); 801 802 if (ifp == NULL) { 803 DPRINTFN(0, "could not if_alloc()!\n"); 804 goto done; 805 } 806 sc->sc_evilhack = ifp; 807 sc->sc_ifp = ifp; 808 ic = ifp->if_l2com; 809 810 ifp->if_softc = sc; 811 if_initname(ifp, "ural", sc->sc_unit); 812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 813 ifp->if_init = &ural_init_cb; 814 ifp->if_ioctl = &ural_ioctl_cb; 815 ifp->if_start = &ural_start_cb; 816 ifp->if_watchdog = NULL; 817 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 818 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 819 IFQ_SET_READY(&ifp->if_snd); 820 821 bcopy(sc->sc_myaddr, ic->ic_myaddr, sizeof(ic->ic_myaddr)); 822 823 ic->ic_ifp = ifp; 824 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 825 ic->ic_opmode = IEEE80211_M_STA; 826 827 /* set device capabilities */ 828 ic->ic_caps = 829 IEEE80211_C_STA /* station mode supported */ 830 | IEEE80211_C_IBSS /* IBSS mode supported */ 831 | IEEE80211_C_MONITOR /* monitor mode supported */ 832 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 833 | IEEE80211_C_TXPMGT /* tx power management */ 834 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 835 | IEEE80211_C_SHSLOT /* short slot time supported */ 836 | IEEE80211_C_BGSCAN /* bg scanning supported */ 837 | IEEE80211_C_WPA /* 802.11i */ 838 ; 839 840 bands = 0; 841 setbit(&bands, IEEE80211_MODE_11B); 842 setbit(&bands, IEEE80211_MODE_11G); 843 844 if (sc->sc_rf_rev == RAL_RF_5222) { 845 setbit(&bands, IEEE80211_MODE_11A); 846 } 847 ieee80211_init_channels(ic, NULL, &bands); 848 849 mtx_unlock(&sc->sc_mtx); 850 851 ieee80211_ifattach(ic); 852 853 mtx_lock(&sc->sc_mtx); 854 855 ic->ic_newassoc = &ural_newassoc; 856 ic->ic_raw_xmit = &ural_raw_xmit_cb; 857 ic->ic_node_alloc = &ural_node_alloc; 858 ic->ic_update_mcast = &ural_update_mcast_cb; 859 ic->ic_update_promisc = &ural_update_promisc_cb; 860 ic->ic_scan_start = &ural_scan_start_cb; 861 ic->ic_scan_end = &ural_scan_end_cb; 862 ic->ic_set_channel = &ural_set_channel_cb; 863 ic->ic_vap_create = &ural_vap_create; 864 ic->ic_vap_delete = &ural_vap_delete; 865 866 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 867 868 mtx_unlock(&sc->sc_mtx); 869 870 bpfattach(ifp, DLT_IEEE802_11_RADIO, 871 sizeof(struct ieee80211_frame) + sizeof(sc->sc_txtap)); 872 873 if (bootverbose) { 874 ieee80211_announce(ic); 875 } 876 mtx_lock(&sc->sc_mtx); 877done: 878 return; 879} 880 881static void 882ural_end_of_commands(struct ural_softc *sc) 883{ 884 sc->sc_flags &= ~URAL_FLAG_WAIT_COMMAND; 885 886 /* start write transfer, if not started */ 887 usb2_transfer_start(sc->sc_xfer[0]); 888} 889 890static void 891ural_config_copy_chan(struct ural_config_copy_chan *cc, 892 struct ieee80211com *ic, struct ieee80211_channel *c) 893{ 894 if (!c) 895 return; 896 cc->chan_to_ieee = 897 ieee80211_chan2ieee(ic, c); 898 if (c != IEEE80211_CHAN_ANYC) { 899 cc->chan_to_mode = 900 ieee80211_chan2mode(c); 901 if (IEEE80211_IS_CHAN_B(c)) 902 cc->chan_is_b = 1; 903 if (IEEE80211_IS_CHAN_A(c)) 904 cc->chan_is_a = 1; 905 if (IEEE80211_IS_CHAN_2GHZ(c)) 906 cc->chan_is_2ghz = 1; 907 if (IEEE80211_IS_CHAN_5GHZ(c)) 908 cc->chan_is_5ghz = 1; 909 if (IEEE80211_IS_CHAN_ANYG(c)) 910 cc->chan_is_g = 1; 911 } 912} 913 914static void 915ural_config_copy(struct ural_softc *sc, 916 struct usb2_config_td_cc *cc, uint16_t refcount) 917{ 918 struct ifnet *ifp; 919 struct ieee80211com *ic; 920 struct ieee80211_node *ni; 921 struct ieee80211vap *vap; 922 const struct ieee80211_txparam *tp; 923 924 bzero(cc, sizeof(*cc)); 925 926 ifp = sc->sc_ifp; 927 if (ifp) { 928 cc->if_flags = ifp->if_flags; 929 bcopy(ifp->if_broadcastaddr, cc->if_broadcastaddr, 930 sizeof(cc->if_broadcastaddr)); 931 932 ic = ifp->if_l2com; 933 if (ic) { 934 ural_config_copy_chan(&cc->ic_curchan, ic, ic->ic_curchan); 935 ural_config_copy_chan(&cc->ic_bsschan, ic, ic->ic_bsschan); 936 vap = TAILQ_FIRST(&ic->ic_vaps); 937 if (vap) { 938 ni = vap->iv_bss; 939 if (ni) { 940 cc->iv_bss.ni_intval = ni->ni_intval; 941 bcopy(ni->ni_bssid, cc->iv_bss.ni_bssid, 942 sizeof(cc->iv_bss.ni_bssid)); 943 } 944 tp = vap->iv_txparms + cc->ic_bsschan.chan_to_mode; 945 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 946 cc->iv_bss.fixed_rate_none = 1; 947 } 948 } 949 cc->ic_opmode = ic->ic_opmode; 950 cc->ic_flags = ic->ic_flags; 951 cc->ic_txpowlimit = ic->ic_txpowlimit; 952 cc->ic_curmode = ic->ic_curmode; 953 954 bcopy(ic->ic_myaddr, cc->ic_myaddr, 955 sizeof(cc->ic_myaddr)); 956 } 957 } 958 sc->sc_flags |= URAL_FLAG_WAIT_COMMAND; 959} 960 961static const char * 962ural_get_rf(int rev) 963{ 964 switch (rev) { 965 case RAL_RF_2522:return "RT2522"; 966 case RAL_RF_2523: 967 return "RT2523"; 968 case RAL_RF_2524: 969 return "RT2524"; 970 case RAL_RF_2525: 971 return "RT2525"; 972 case RAL_RF_2525E: 973 return "RT2525e"; 974 case RAL_RF_2526: 975 return "RT2526"; 976 case RAL_RF_5222: 977 return "RT5222"; 978 default: 979 return "unknown"; 980 } 981} 982 983/*------------------------------------------------------------------------* 984 * ural_bulk_read_callback - data read "thread" 985 *------------------------------------------------------------------------*/ 986static void 987ural_bulk_read_callback(struct usb2_xfer *xfer) 988{ 989 struct ural_softc *sc = xfer->priv_sc; 990 struct ifnet *ifp = sc->sc_ifp; 991 struct ieee80211com *ic = ifp->if_l2com; 992 struct ieee80211_node *ni; 993 struct mbuf *m = NULL; 994 uint32_t flags; 995 uint32_t max_len; 996 uint32_t real_len; 997 uint8_t rssi = 0; 998 999 switch (USB_GET_STATE(xfer)) { 1000 case USB_ST_TRANSFERRED: 1001 1002 DPRINTFN(15, "rx done, actlen=%d\n", xfer->actlen); 1003 1004 if (xfer->actlen < RAL_RX_DESC_SIZE) { 1005 DPRINTF("too short transfer, " 1006 "%d bytes\n", xfer->actlen); 1007 ifp->if_ierrors++; 1008 goto tr_setup; 1009 } 1010 max_len = (xfer->actlen - RAL_RX_DESC_SIZE); 1011 1012 usb2_copy_out(xfer->frbuffers, max_len, 1013 &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 1014 1015 flags = le32toh(sc->sc_rx_desc.flags); 1016 1017 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 1018 /* 1019 * This should not happen since we did not 1020 * request to receive those frames when we 1021 * filled RAL_TXRX_CSR2: 1022 */ 1023 DPRINTFN(6, "PHY or CRC error\n"); 1024 ifp->if_ierrors++; 1025 goto tr_setup; 1026 } 1027 if (max_len > MCLBYTES) { 1028 max_len = MCLBYTES; 1029 } 1030 real_len = (flags >> 16) & 0xfff; 1031 1032 if (real_len > max_len) { 1033 DPRINTF("invalid length in RX " 1034 "descriptor, %u bytes, received %u bytes\n", 1035 real_len, max_len); 1036 ifp->if_ierrors++; 1037 goto tr_setup; 1038 } 1039 /* ieee80211_input() will check if the mbuf is too short */ 1040 1041 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1042 1043 if (m == NULL) { 1044 DPRINTF("could not allocate mbuf\n"); 1045 ifp->if_ierrors++; 1046 goto tr_setup; 1047 } 1048 usb2_copy_out(xfer->frbuffers, 0, m->m_data, max_len); 1049 1050 /* finalize mbuf */ 1051 m->m_pkthdr.rcvif = ifp; 1052 m->m_pkthdr.len = m->m_len = real_len; 1053 1054 DPRINTF("real length=%d bytes\n", real_len); 1055 1056 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 1057 1058 if (bpf_peers_present(ifp->if_bpf)) { 1059 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 1060 1061 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1062 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 1063 (sc->sc_rx_desc.flags & htole32(RAL_RX_OFDM)) ? 1064 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1065 1066 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1067 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1068 tap->wr_antenna = sc->sc_rx_ant; 1069 tap->wr_antsignal = rssi; 1070 1071 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1072 } 1073 /* Strip trailing 802.11 MAC FCS. */ 1074 m_adj(m, -IEEE80211_CRC_LEN); 1075 1076 case USB_ST_SETUP: 1077tr_setup: 1078 1079 if (sc->sc_flags & URAL_FLAG_READ_STALL) { 1080 usb2_transfer_start(sc->sc_xfer[3]); 1081 } else { 1082 xfer->frlengths[0] = xfer->max_data_length; 1083 usb2_start_hardware(xfer); 1084 } 1085 1086 /* 1087 * At the end of a USB callback it is always safe to unlock 1088 * the private mutex of a device! That is why we do the 1089 * "ieee80211_input" here, and not some lines up! 1090 */ 1091 if (m) { 1092 mtx_unlock(&sc->sc_mtx); 1093 1094 ni = ieee80211_find_rxnode(ic, (void *)(m->m_data)); 1095 1096 if (ni) { 1097 /* send the frame to the 802.11 layer */ 1098 if (ieee80211_input(ni, m, rssi, RAL_NOISE_FLOOR, 0)) { 1099 /* ignore */ 1100 } 1101 /* node is no longer needed */ 1102 ieee80211_free_node(ni); 1103 } else { 1104 /* broadcast */ 1105 if (ieee80211_input_all(ic, m, rssi, RAL_NOISE_FLOOR, 0)) { 1106 /* ignore */ 1107 } 1108 } 1109 1110 mtx_lock(&sc->sc_mtx); 1111 } 1112 return; 1113 1114 default: /* Error */ 1115 if (xfer->error != USB_ERR_CANCELLED) { 1116 /* try to clear stall first */ 1117 sc->sc_flags |= URAL_FLAG_READ_STALL; 1118 usb2_transfer_start(sc->sc_xfer[3]); 1119 } 1120 return; 1121 1122 } 1123} 1124 1125static void 1126ural_bulk_read_clear_stall_callback(struct usb2_xfer *xfer) 1127{ 1128 struct ural_softc *sc = xfer->priv_sc; 1129 struct usb2_xfer *xfer_other = sc->sc_xfer[1]; 1130 1131 if (usb2_clear_stall_callback(xfer, xfer_other)) { 1132 DPRINTF("stall cleared\n"); 1133 sc->sc_flags &= ~URAL_FLAG_READ_STALL; 1134 usb2_transfer_start(xfer_other); 1135 } 1136} 1137 1138static uint8_t 1139ural_plcp_signal(uint16_t rate) 1140{ 1141 ; /* indent fix */ 1142 switch (rate) { 1143 /* CCK rates (NB: not IEEE std, device-specific) */ 1144 case 2: 1145 return (0x0); 1146 case 4: 1147 return (0x1); 1148 case 11: 1149 return (0x2); 1150 case 22: 1151 return (0x3); 1152 1153 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1154 case 12: 1155 return (0xb); 1156 case 18: 1157 return (0xf); 1158 case 24: 1159 return (0xa); 1160 case 36: 1161 return (0xe); 1162 case 48: 1163 return (0x9); 1164 case 72: 1165 return (0xd); 1166 case 96: 1167 return (0x8); 1168 case 108: 1169 return (0xc); 1170 1171 /* XXX unsupported/unknown rate */ 1172 default: 1173 return (0xff); 1174 } 1175} 1176 1177/* 1178 * We assume that "m->m_pkthdr.rcvif" is pointing to the "ni" that 1179 * should be freed, when "ural_setup_desc_and_tx" is called. 1180 */ 1181static void 1182ural_setup_desc_and_tx(struct ural_softc *sc, struct mbuf *m, 1183 uint32_t flags, uint16_t rate) 1184{ 1185 struct ifnet *ifp = sc->sc_ifp; 1186 struct ieee80211com *ic = ifp->if_l2com; 1187 struct mbuf *mm; 1188 enum ieee80211_phytype phytype; 1189 uint16_t plcp_length; 1190 uint16_t len; 1191 uint8_t remainder; 1192 1193 DPRINTF("in\n"); 1194 1195 if (sc->sc_tx_queue.ifq_len >= IFQ_MAXLEN) { 1196 /* free packet */ 1197 ural_tx_freem(m); 1198 ifp->if_oerrors++; 1199 return; 1200 } 1201 if (!((sc->sc_flags & URAL_FLAG_LL_READY) && 1202 (sc->sc_flags & URAL_FLAG_HL_READY))) { 1203 /* free packet */ 1204 ural_tx_freem(m); 1205 ifp->if_oerrors++; 1206 return; 1207 } 1208 if (rate < 2) { 1209 DPRINTF("rate < 2!\n"); 1210 1211 /* avoid division by zero */ 1212 rate = 2; 1213 } 1214 ic->ic_lastdata = ticks; 1215 1216 if (bpf_peers_present(ifp->if_bpf)) { 1217 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 1218 1219 tap->wt_flags = 0; 1220 tap->wt_rate = rate; 1221 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1222 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1223 tap->wt_antenna = sc->sc_tx_ant; 1224 1225 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m); 1226 } 1227 len = m->m_pkthdr.len; 1228 1229 sc->sc_tx_desc.flags = htole32(flags); 1230 sc->sc_tx_desc.flags |= htole32(RAL_TX_NEWSEQ); 1231 sc->sc_tx_desc.flags |= htole32(len << 16); 1232 1233 sc->sc_tx_desc.wme = htole16(RAL_AIFSN(2) | 1234 RAL_LOGCWMIN(3) | 1235 RAL_LOGCWMAX(5) | 1236 RAL_IVOFFSET(sizeof(struct ieee80211_frame))); 1237 1238 /* setup PLCP fields */ 1239 sc->sc_tx_desc.plcp_signal = ural_plcp_signal(rate); 1240 sc->sc_tx_desc.plcp_service = 4; 1241 1242 len += IEEE80211_CRC_LEN; 1243 1244 phytype = ieee80211_rate2phytype(sc->sc_rates, rate); 1245 1246 if (phytype == IEEE80211_T_OFDM) { 1247 sc->sc_tx_desc.flags |= htole32(RAL_TX_OFDM); 1248 1249 plcp_length = len & 0xfff; 1250 sc->sc_tx_desc.plcp_length_hi = plcp_length >> 6; 1251 sc->sc_tx_desc.plcp_length_lo = plcp_length & 0x3f; 1252 1253 } else { 1254 plcp_length = ((16 * len) + rate - 1) / rate; 1255 if (rate == 22) { 1256 remainder = (16 * len) % 22; 1257 if ((remainder != 0) && (remainder < 7)) { 1258 sc->sc_tx_desc.plcp_service |= 1259 RAL_PLCP_LENGEXT; 1260 } 1261 } 1262 sc->sc_tx_desc.plcp_length_hi = plcp_length >> 8; 1263 sc->sc_tx_desc.plcp_length_lo = plcp_length & 0xff; 1264 1265 if ((rate != 2) && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { 1266 sc->sc_tx_desc.plcp_signal |= 0x08; 1267 } 1268 } 1269 1270 sc->sc_tx_desc.iv = 0; 1271 sc->sc_tx_desc.eiv = 0; 1272 1273 if (sizeof(sc->sc_tx_desc) > MHLEN) { 1274 DPRINTF("No room for header structure!\n"); 1275 ural_tx_freem(m); 1276 return; 1277 } 1278 mm = m_gethdr(M_NOWAIT, MT_DATA); 1279 if (mm == NULL) { 1280 DPRINTF("Could not allocate header mbuf!\n"); 1281 ural_tx_freem(m); 1282 return; 1283 } 1284 DPRINTF(" %zu %u (out)\n", sizeof(sc->sc_tx_desc), m->m_pkthdr.len); 1285 1286 bcopy(&sc->sc_tx_desc, mm->m_data, sizeof(sc->sc_tx_desc)); 1287 mm->m_len = sizeof(sc->sc_tx_desc); 1288 1289 mm->m_next = m; 1290 mm->m_pkthdr.len = mm->m_len + m->m_pkthdr.len; 1291 mm->m_pkthdr.rcvif = NULL; 1292 1293 /* start write transfer, if not started */ 1294 _IF_ENQUEUE(&sc->sc_tx_queue, mm); 1295 1296 usb2_transfer_start(sc->sc_xfer[0]); 1297} 1298 1299static void 1300ural_bulk_write_callback(struct usb2_xfer *xfer) 1301{ 1302 struct ural_softc *sc = xfer->priv_sc; 1303 struct ifnet *ifp = sc->sc_ifp; 1304 struct mbuf *m; 1305 uint16_t temp_len; 1306 uint8_t align; 1307 1308 switch (USB_GET_STATE(xfer)) { 1309 case USB_ST_TRANSFERRED: 1310 DPRINTFN(11, "transfer complete, %d bytes\n", xfer->actlen); 1311 1312 ifp->if_opackets++; 1313 1314 case USB_ST_SETUP: 1315 if (sc->sc_flags & URAL_FLAG_WRITE_STALL) { 1316 usb2_transfer_start(sc->sc_xfer[2]); 1317 break; 1318 } 1319 if (sc->sc_flags & URAL_FLAG_WAIT_COMMAND) { 1320 /* 1321 * don't send anything while a command is pending ! 1322 */ 1323 break; 1324 } 1325 ural_fill_write_queue(sc); 1326 1327 _IF_DEQUEUE(&sc->sc_tx_queue, m); 1328 1329 if (m) { 1330 1331 if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 1332 DPRINTFN(0, "data overflow, %u bytes\n", 1333 m->m_pkthdr.len); 1334 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 1335 } 1336 usb2_m_copy_in(xfer->frbuffers, 0, 1337 m, 0, m->m_pkthdr.len); 1338 1339 /* compute transfer length */ 1340 temp_len = m->m_pkthdr.len; 1341 1342 /* make transfer length 16-bit aligned */ 1343 align = (temp_len & 1); 1344 1345 /* check if we need to add two extra bytes */ 1346 if (((temp_len + align) % 64) == 0) { 1347 align += 2; 1348 } 1349 /* check if we need to align length */ 1350 if (align != 0) { 1351 /* zero the extra bytes */ 1352 usb2_bzero(xfer->frbuffers, temp_len, align); 1353 temp_len += align; 1354 } 1355 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 1356 m->m_pkthdr.len, temp_len); 1357 1358 xfer->frlengths[0] = temp_len; 1359 1360 usb2_start_hardware(xfer); 1361 1362 /* free mbuf and node */ 1363 ural_tx_freem(m); 1364 } 1365 break; 1366 1367 default: /* Error */ 1368 DPRINTFN(11, "transfer error, %s\n", 1369 usb2_errstr(xfer->error)); 1370 1371 if (xfer->error != USB_ERR_CANCELLED) { 1372 /* try to clear stall first */ 1373 sc->sc_flags |= URAL_FLAG_WRITE_STALL; 1374 usb2_transfer_start(sc->sc_xfer[2]); 1375 } 1376 ifp->if_oerrors++; 1377 break; 1378 } 1379} 1380 1381static void 1382ural_bulk_write_clear_stall_callback(struct usb2_xfer *xfer) 1383{ 1384 struct ural_softc *sc = xfer->priv_sc; 1385 struct usb2_xfer *xfer_other = sc->sc_xfer[0]; 1386 1387 if (usb2_clear_stall_callback(xfer, xfer_other)) { 1388 DPRINTF("stall cleared\n"); 1389 sc->sc_flags &= ~URAL_FLAG_WRITE_STALL; 1390 usb2_transfer_start(xfer_other); 1391 } 1392} 1393 1394static void 1395ural_watchdog(void *arg) 1396{ 1397 struct ural_softc *sc = arg; 1398 1399 mtx_assert(&sc->sc_mtx, MA_OWNED); 1400 1401 if (sc->sc_amrr_timer) { 1402 usb2_config_td_queue_command 1403 (&sc->sc_config_td, NULL, 1404 &ural_cfg_amrr_timeout, 0, 0); 1405 } 1406 usb2_callout_reset(&sc->sc_watchdog, 1407 hz, &ural_watchdog, sc); 1408 1409 mtx_unlock(&sc->sc_mtx); 1410} 1411 1412/*========================================================================* 1413 * IF-net callbacks 1414 *========================================================================*/ 1415 1416static void 1417ural_init_cb(void *arg) 1418{ 1419 struct ural_softc *sc = arg; 1420 1421 mtx_lock(&sc->sc_mtx); 1422 usb2_config_td_queue_command 1423 (&sc->sc_config_td, &ural_cfg_pre_init, 1424 &ural_cfg_init, 0, 0); 1425 mtx_unlock(&sc->sc_mtx); 1426} 1427 1428static int 1429ural_ioctl_cb(struct ifnet *ifp, u_long cmd, caddr_t data) 1430{ 1431 struct ural_softc *sc = ifp->if_softc; 1432 struct ieee80211com *ic = ifp->if_l2com; 1433 int error; 1434 1435 switch (cmd) { 1436 case SIOCSIFFLAGS: 1437 mtx_lock(&sc->sc_mtx); 1438 if (ifp->if_flags & IFF_UP) { 1439 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1440 usb2_config_td_queue_command 1441 (&sc->sc_config_td, &ural_cfg_pre_init, 1442 &ural_cfg_init, 0, 0); 1443 } 1444 } else { 1445 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1446 usb2_config_td_queue_command 1447 (&sc->sc_config_td, &ural_cfg_pre_stop, 1448 &ural_cfg_stop, 0, 0); 1449 } 1450 } 1451 mtx_unlock(&sc->sc_mtx); 1452 error = 0; 1453 break; 1454 1455 case SIOCGIFMEDIA: 1456 case SIOCSIFMEDIA: 1457 error = ifmedia_ioctl(ifp, (void *)data, &ic->ic_media, cmd); 1458 break; 1459 1460 default: 1461 error = ether_ioctl(ifp, cmd, data); 1462 } 1463 return (error); 1464} 1465 1466static void 1467ural_start_cb(struct ifnet *ifp) 1468{ 1469 struct ural_softc *sc = ifp->if_softc; 1470 1471 mtx_lock(&sc->sc_mtx); 1472 /* start write transfer, if not started */ 1473 usb2_transfer_start(sc->sc_xfer[0]); 1474 mtx_unlock(&sc->sc_mtx); 1475} 1476 1477static void 1478ural_cfg_newstate(struct ural_softc *sc, 1479 struct usb2_config_td_cc *cc, uint16_t refcount) 1480{ 1481 struct ifnet *ifp = sc->sc_ifp; 1482 struct ieee80211com *ic = ifp->if_l2com; 1483 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1484 struct ural_vap *uvp = URAL_VAP(vap); 1485 enum ieee80211_state ostate; 1486 enum ieee80211_state nstate; 1487 int arg; 1488 1489 ostate = vap->iv_state; 1490 nstate = sc->sc_ns_state; 1491 arg = sc->sc_ns_arg; 1492 1493 if (ostate == IEEE80211_S_INIT) { 1494 /* We are leaving INIT. TSF sync should be off. */ 1495 ural_cfg_disable_tsf_sync(sc); 1496 } 1497 switch (nstate) { 1498 case IEEE80211_S_INIT: 1499 break; 1500 1501 case IEEE80211_S_RUN: 1502 ural_cfg_set_run(sc, cc); 1503 break; 1504 1505 default: 1506 break; 1507 } 1508 1509 mtx_unlock(&sc->sc_mtx); 1510 IEEE80211_LOCK(ic); 1511 uvp->newstate(vap, nstate, arg); 1512 if (vap->iv_newstate_cb != NULL) 1513 vap->iv_newstate_cb(vap, nstate, arg); 1514 IEEE80211_UNLOCK(ic); 1515 mtx_lock(&sc->sc_mtx); 1516} 1517 1518static int 1519ural_newstate_cb(struct ieee80211vap *vap, 1520 enum ieee80211_state nstate, int arg) 1521{ 1522 struct ural_vap *uvp = URAL_VAP(vap); 1523 struct ieee80211com *ic = vap->iv_ic; 1524 struct ural_softc *sc = ic->ic_ifp->if_softc; 1525 1526 DPRINTF("setting new state: %d\n", nstate); 1527 1528 /* Special case - cannot defer this call and cannot block ! */ 1529 if (nstate == IEEE80211_S_INIT) { 1530 /* stop timers */ 1531 mtx_lock(&sc->sc_mtx); 1532 sc->sc_amrr_timer = 0; 1533 mtx_unlock(&sc->sc_mtx); 1534 return (uvp->newstate(vap, nstate, arg)); 1535 } 1536 mtx_lock(&sc->sc_mtx); 1537 if (usb2_config_td_is_gone(&sc->sc_config_td)) { 1538 mtx_unlock(&sc->sc_mtx); 1539 return (0); /* nothing to do */ 1540 } 1541 /* store next state */ 1542 sc->sc_ns_state = nstate; 1543 sc->sc_ns_arg = arg; 1544 1545 /* stop timers */ 1546 sc->sc_amrr_timer = 0; 1547 1548 /* 1549 * USB configuration can only be done from the USB configuration 1550 * thread: 1551 */ 1552 usb2_config_td_queue_command 1553 (&sc->sc_config_td, &ural_config_copy, 1554 &ural_cfg_newstate, 0, 0); 1555 1556 mtx_unlock(&sc->sc_mtx); 1557 1558 return (EINPROGRESS); 1559} 1560 1561static void 1562ural_std_command(struct ieee80211com *ic, usb2_config_td_command_t *func) 1563{ 1564 struct ural_softc *sc = ic->ic_ifp->if_softc; 1565 1566 mtx_lock(&sc->sc_mtx); 1567 1568 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 1569 1570 usb2_config_td_queue_command 1571 (&sc->sc_config_td, &ural_config_copy, func, 0, 0); 1572 1573 mtx_unlock(&sc->sc_mtx); 1574} 1575 1576static void 1577ural_scan_start_cb(struct ieee80211com *ic) 1578{ 1579 ural_std_command(ic, &ural_cfg_scan_start); 1580} 1581 1582static void 1583ural_scan_end_cb(struct ieee80211com *ic) 1584{ 1585 ural_std_command(ic, &ural_cfg_scan_end); 1586} 1587 1588static void 1589ural_set_channel_cb(struct ieee80211com *ic) 1590{ 1591 ural_std_command(ic, &ural_cfg_set_chan); 1592} 1593 1594/*========================================================================* 1595 * configure sub-routines, ural_cfg_xxx 1596 *========================================================================*/ 1597 1598static void 1599ural_cfg_scan_start(struct ural_softc *sc, 1600 struct usb2_config_td_cc *cc, uint16_t refcount) 1601{ 1602 /* abort TSF synchronization */ 1603 ural_cfg_disable_tsf_sync(sc); 1604 ural_cfg_set_bssid(sc, cc->if_broadcastaddr); 1605} 1606 1607static void 1608ural_cfg_scan_end(struct ural_softc *sc, 1609 struct usb2_config_td_cc *cc, uint16_t refcount) 1610{ 1611 /* enable TSF synchronization */ 1612 ural_cfg_enable_tsf_sync(sc, cc, 0); 1613 ural_cfg_set_bssid(sc, cc->iv_bss.ni_bssid); 1614} 1615 1616static void 1617ural_cfg_set_chan(struct ural_softc *sc, 1618 struct usb2_config_td_cc *cc, uint16_t refcount) 1619{ 1620 enum { 1621 N_RF5222 = (sizeof(ural_rf5222) / sizeof(ural_rf5222[0])), 1622 }; 1623 uint32_t i; 1624 uint32_t chan; 1625 uint8_t power; 1626 uint8_t tmp; 1627 1628 chan = cc->ic_curchan.chan_to_ieee; 1629 1630 if ((chan == 0) || 1631 (chan == IEEE80211_CHAN_ANY)) { 1632 /* nothing to do */ 1633 return; 1634 } 1635 if (cc->ic_curchan.chan_is_2ghz) 1636 power = min(sc->sc_txpow[chan - 1], 31); 1637 else 1638 power = 31; 1639 1640 /* adjust txpower using ifconfig settings */ 1641 power -= (100 - cc->ic_txpowlimit) / 8; 1642 1643 DPRINTFN(3, "setting channel to %u, " 1644 "tx-power to %u\n", chan, power); 1645 1646 switch (sc->sc_rf_rev) { 1647 case RAL_RF_2522: 1648 ural_cfg_rf_write(sc, RAL_RF1, 0x00814); 1649 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1650 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x00040); 1651 break; 1652 1653 case RAL_RF_2523: 1654 ural_cfg_rf_write(sc, RAL_RF1, 0x08804); 1655 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1656 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x38044); 1657 ural_cfg_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1658 break; 1659 1660 case RAL_RF_2524: 1661 ural_cfg_rf_write(sc, RAL_RF1, 0x0c808); 1662 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1663 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x00040); 1664 ural_cfg_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1665 break; 1666 1667 case RAL_RF_2525: 1668 ural_cfg_rf_write(sc, RAL_RF1, 0x08808); 1669 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1670 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x18044); 1671 ural_cfg_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1672 1673 ural_cfg_rf_write(sc, RAL_RF1, 0x08808); 1674 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1675 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x18044); 1676 ural_cfg_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1677 break; 1678 1679 case RAL_RF_2525E: 1680 ural_cfg_rf_write(sc, RAL_RF1, 0x08808); 1681 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1682 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x18044); 1683 ural_cfg_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1684 break; 1685 1686 case RAL_RF_2526: 1687 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1688 ural_cfg_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1689 ural_cfg_rf_write(sc, RAL_RF1, 0x08804); 1690 1691 ural_cfg_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1692 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x18044); 1693 ural_cfg_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1694 break; 1695 1696 /* dual-band RF */ 1697 case RAL_RF_5222: 1698 for (i = 0; i < N_RF5222; i++) { 1699 if (ural_rf5222[i].chan == chan) { 1700 ural_cfg_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1701 ural_cfg_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1702 ural_cfg_rf_write(sc, RAL_RF3, (power << 7) | 0x00040); 1703 ural_cfg_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1704 break; 1705 } 1706 } 1707 break; 1708 } 1709 1710 if ((cc->ic_opmode != IEEE80211_M_MONITOR) && 1711 (!(cc->ic_flags & IEEE80211_F_SCAN))) { 1712 1713 /* set Japan filter bit for channel 14 */ 1714 tmp = ural_cfg_bbp_read(sc, 70); 1715 1716 if (chan == 14) { 1717 tmp |= RAL_JAPAN_FILTER; 1718 } else { 1719 tmp &= ~RAL_JAPAN_FILTER; 1720 } 1721 1722 ural_cfg_bbp_write(sc, 70, tmp); 1723 1724 /* clear CRC errors */ 1725 ural_cfg_read(sc, RAL_STA_CSR0); 1726 1727 ural_cfg_disable_rf_tune(sc); 1728 } 1729 /* update basic rate set */ 1730 if (cc->ic_curchan.chan_is_b) { 1731 /* 11b basic rates: 1, 2Mbps */ 1732 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x3); 1733 } else if (cc->ic_curchan.chan_is_a) { 1734 /* 11a basic rates: 6, 12, 24Mbps */ 1735 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x150); 1736 } else { 1737 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1738 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x15f); 1739 } 1740 1741 /* wait a little */ 1742 if (usb2_config_td_sleep(&sc->sc_config_td, hz / 100)) { 1743 return; 1744 } 1745} 1746 1747static void 1748ural_cfg_set_run(struct ural_softc *sc, 1749 struct usb2_config_td_cc *cc) 1750{ 1751 if (cc->ic_opmode != IEEE80211_M_MONITOR) { 1752 ural_cfg_update_slot(sc, cc, 0); 1753 ural_cfg_set_txpreamble(sc, cc, 0); 1754 1755 /* update basic rate set */ 1756 1757 if (cc->ic_bsschan.chan_is_5ghz) { 1758 /* 11a basic rates: 6, 12, 24Mbps */ 1759 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x150); 1760 } else if (cc->ic_bsschan.chan_is_g) { 1761 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1762 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x15f); 1763 } else { 1764 /* 11b basic rates: 1, 2Mbps */ 1765 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x3); 1766 } 1767 ural_cfg_set_bssid(sc, cc->iv_bss.ni_bssid); 1768 } 1769 if ((cc->ic_opmode == IEEE80211_M_HOSTAP) || 1770 (cc->ic_opmode == IEEE80211_M_IBSS)) { 1771 ural_tx_bcn(sc); 1772 } 1773 /* make tx led blink on tx (controlled by ASIC) */ 1774 ural_cfg_write(sc, RAL_MAC_CSR20, 1); 1775 1776 if (cc->ic_opmode != IEEE80211_M_MONITOR) { 1777 ural_cfg_enable_tsf_sync(sc, cc, 0); 1778 } 1779 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 1780 ural_cfg_read_multi(sc, RAL_STA_CSR0, sc->sc_sta, sizeof(sc->sc_sta)); 1781 1782 if (cc->iv_bss.fixed_rate_none) { 1783 /* enable automatic rate adaptation */ 1784 ural_cfg_amrr_start(sc); 1785 } 1786} 1787 1788/*------------------------------------------------------------------------* 1789 * ural_cfg_disable_rf_tune - disable RF auto-tuning 1790 *------------------------------------------------------------------------*/ 1791static void 1792ural_cfg_disable_rf_tune(struct ural_softc *sc) 1793{ 1794 uint32_t tmp; 1795 1796 if (sc->sc_rf_rev != RAL_RF_2523) { 1797 tmp = sc->sc_rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1798 ural_cfg_rf_write(sc, RAL_RF1, tmp); 1799 } 1800 tmp = sc->sc_rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1801 ural_cfg_rf_write(sc, RAL_RF3, tmp); 1802 1803 DPRINTFN(3, "disabling RF autotune\n"); 1804} 1805 1806/*------------------------------------------------------------------------* 1807 * ural_cfg_enable_tsf_sync - refer to IEEE Std 802.11-1999 pp. 123 1808 * for more information on TSF synchronization 1809 *------------------------------------------------------------------------*/ 1810static void 1811ural_cfg_enable_tsf_sync(struct ural_softc *sc, 1812 struct usb2_config_td_cc *cc, uint16_t refcount) 1813{ 1814 uint16_t logcwmin; 1815 uint16_t preload; 1816 uint16_t tmp; 1817 1818 /* first, disable TSF synchronization */ 1819 ural_cfg_write(sc, RAL_TXRX_CSR19, 0); 1820 1821 tmp = (16 * cc->iv_bss.ni_intval) << 4; 1822 ural_cfg_write(sc, RAL_TXRX_CSR18, tmp); 1823 1824 logcwmin = (cc->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1825 preload = (cc->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1826 tmp = (logcwmin << 12) | preload; 1827 ural_cfg_write(sc, RAL_TXRX_CSR20, tmp); 1828 1829 /* finally, enable TSF synchronization */ 1830 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1831 if (cc->ic_opmode == IEEE80211_M_STA) 1832 tmp |= RAL_ENABLE_TSF_SYNC(1); 1833 else 1834 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1835 1836 ural_cfg_write(sc, RAL_TXRX_CSR19, tmp); 1837 1838 DPRINTF("enabling TSF synchronization\n"); 1839} 1840 1841static void 1842ural_cfg_disable_tsf_sync(struct ural_softc *sc) 1843{ 1844 /* abort TSF synchronization */ 1845 ural_cfg_write(sc, RAL_TXRX_CSR19, 0); 1846 1847 /* force tx led to stop blinking */ 1848 ural_cfg_write(sc, RAL_MAC_CSR20, 0); 1849} 1850 1851#define RAL_RXTX_TURNAROUND 5 /* us */ 1852 1853static void 1854ural_cfg_update_slot(struct ural_softc *sc, 1855 struct usb2_config_td_cc *cc, uint16_t refcount) 1856{ 1857 uint16_t slottime; 1858 uint16_t sifs; 1859 uint16_t eifs; 1860 1861 slottime = (cc->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1862 1863 /* 1864 * These settings may sound a bit inconsistent but this is what the 1865 * reference driver does. 1866 */ 1867 if (cc->ic_curmode == IEEE80211_MODE_11B) { 1868 sifs = 16 - RAL_RXTX_TURNAROUND; 1869 eifs = 364; 1870 } else { 1871 sifs = 10 - RAL_RXTX_TURNAROUND; 1872 eifs = 64; 1873 } 1874 1875 ural_cfg_write(sc, RAL_MAC_CSR10, slottime); 1876 ural_cfg_write(sc, RAL_MAC_CSR11, sifs); 1877 ural_cfg_write(sc, RAL_MAC_CSR12, eifs); 1878} 1879 1880static void 1881ural_cfg_set_txpreamble(struct ural_softc *sc, 1882 struct usb2_config_td_cc *cc, uint16_t refcount) 1883{ 1884 uint16_t tmp; 1885 1886 tmp = ural_cfg_read(sc, RAL_TXRX_CSR10); 1887 1888 if (cc->ic_flags & IEEE80211_F_SHPREAMBLE) { 1889 tmp |= RAL_SHORT_PREAMBLE; 1890 } else { 1891 tmp &= ~RAL_SHORT_PREAMBLE; 1892 } 1893 1894 ural_cfg_write(sc, RAL_TXRX_CSR10, tmp); 1895} 1896 1897static void 1898ural_cfg_set_bssid(struct ural_softc *sc, uint8_t *bssid) 1899{ 1900 ural_cfg_write_multi(sc, RAL_MAC_CSR5, bssid, IEEE80211_ADDR_LEN); 1901 1902 DPRINTF("setting BSSID to 0x%02x%02x%02x%02x%02x%02x\n", 1903 bssid[5], bssid[4], bssid[3], 1904 bssid[2], bssid[1], bssid[0]); 1905} 1906 1907static void 1908ural_cfg_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1909{ 1910 ural_cfg_write_multi(sc, RAL_MAC_CSR2, addr, IEEE80211_ADDR_LEN); 1911 1912 DPRINTF("setting MAC to 0x%02x%02x%02x%02x%02x%02x\n", 1913 addr[5], addr[4], addr[3], 1914 addr[2], addr[1], addr[0]); 1915} 1916 1917static void 1918ural_cfg_update_promisc(struct ural_softc *sc, 1919 struct usb2_config_td_cc *cc, uint16_t refcount) 1920{ 1921 uint16_t tmp; 1922 1923 tmp = ural_cfg_read(sc, RAL_TXRX_CSR2); 1924 1925 if (cc->if_flags & IFF_PROMISC) { 1926 tmp &= ~RAL_DROP_NOT_TO_ME; 1927 } else { 1928 tmp |= RAL_DROP_NOT_TO_ME; 1929 } 1930 1931 ural_cfg_write(sc, RAL_TXRX_CSR2, tmp); 1932 1933 DPRINTF("%s promiscuous mode\n", 1934 (cc->if_flags & IFF_PROMISC) ? 1935 "entering" : "leaving"); 1936} 1937 1938static void 1939ural_cfg_set_txantenna(struct ural_softc *sc, uint8_t antenna) 1940{ 1941 uint16_t tmp; 1942 uint8_t tx; 1943 1944 tx = ural_cfg_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1945 if (antenna == 1) 1946 tx |= RAL_BBP_ANTA; 1947 else if (antenna == 2) 1948 tx |= RAL_BBP_ANTB; 1949 else 1950 tx |= RAL_BBP_DIVERSITY; 1951 1952 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1953 if ((sc->sc_rf_rev == RAL_RF_2525E) || 1954 (sc->sc_rf_rev == RAL_RF_2526) || 1955 (sc->sc_rf_rev == RAL_RF_5222)) { 1956 tx |= RAL_BBP_FLIPIQ; 1957 } 1958 ural_cfg_bbp_write(sc, RAL_BBP_TX, tx); 1959 1960 /* update values in PHY_CSR5 and PHY_CSR6 */ 1961 tmp = ural_cfg_read(sc, RAL_PHY_CSR5) & ~0x7; 1962 ural_cfg_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1963 1964 tmp = ural_cfg_read(sc, RAL_PHY_CSR6) & ~0x7; 1965 ural_cfg_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1966} 1967 1968static void 1969ural_cfg_set_rxantenna(struct ural_softc *sc, uint8_t antenna) 1970{ 1971 uint8_t rx; 1972 1973 rx = ural_cfg_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 1974 if (antenna == 1) 1975 rx |= RAL_BBP_ANTA; 1976 else if (antenna == 2) 1977 rx |= RAL_BBP_ANTB; 1978 else 1979 rx |= RAL_BBP_DIVERSITY; 1980 1981 /* need to force no I/Q flip for RF 2525e and 2526 */ 1982 1983 if ((sc->sc_rf_rev == RAL_RF_2525E) || 1984 (sc->sc_rf_rev == RAL_RF_2526)) { 1985 rx &= ~RAL_BBP_FLIPIQ; 1986 } 1987 ural_cfg_bbp_write(sc, RAL_BBP_RX, rx); 1988} 1989 1990static void 1991ural_cfg_read_eeprom(struct ural_softc *sc) 1992{ 1993 uint16_t val; 1994 1995 ural_cfg_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1996 1997 val = le16toh(val); 1998 1999 sc->sc_rf_rev = (val >> 11) & 0x7; 2000 sc->sc_hw_radio = (val >> 10) & 0x1; 2001 sc->sc_led_mode = (val >> 6) & 0x7; 2002 sc->sc_rx_ant = (val >> 4) & 0x3; 2003 sc->sc_tx_ant = (val >> 2) & 0x3; 2004 sc->sc_nb_ant = (val & 0x3); 2005 2006 DPRINTF("val = 0x%04x\n", val); 2007 2008 /* read MAC address */ 2009 ural_cfg_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_myaddr, 2010 sizeof(sc->sc_myaddr)); 2011 2012 /* read default values for BBP registers */ 2013 ural_cfg_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->sc_bbp_prom, 2014 sizeof(sc->sc_bbp_prom)); 2015 2016 /* read Tx power for all b/g channels */ 2017 ural_cfg_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->sc_txpow, 2018 sizeof(sc->sc_txpow)); 2019} 2020 2021static uint8_t 2022ural_cfg_bbp_init(struct ural_softc *sc) 2023{ 2024 enum { 2025 N_DEF_BBP = (sizeof(ural_def_bbp) / sizeof(ural_def_bbp[0])), 2026 }; 2027 uint16_t i; 2028 uint8_t to; 2029 2030 /* wait for BBP to become ready */ 2031 for (to = 0;; to++) { 2032 if (to < 100) { 2033 if (ural_cfg_bbp_read(sc, RAL_BBP_VERSION) != 0) { 2034 break; 2035 } 2036 if (usb2_config_td_sleep(&sc->sc_config_td, hz / 100)) { 2037 return (1); /* failure */ 2038 } 2039 } else { 2040 DPRINTF("timeout waiting for BBP\n"); 2041 return (1); /* failure */ 2042 } 2043 } 2044 2045 /* initialize BBP registers to default values */ 2046 for (i = 0; i < N_DEF_BBP; i++) { 2047 ural_cfg_bbp_write(sc, ural_def_bbp[i].reg, 2048 ural_def_bbp[i].val); 2049 } 2050 2051#if 0 2052 /* initialize BBP registers to values stored in EEPROM */ 2053 for (i = 0; i < 16; i++) { 2054 if (sc->sc_bbp_prom[i].reg == 0xff) { 2055 continue; 2056 } 2057 ural_cfg_bbp_write(sc, sc->sc_bbp_prom[i].reg, 2058 sc->sc_bbp_prom[i].val); 2059 } 2060#endif 2061 return (0); /* success */ 2062} 2063 2064static void 2065ural_cfg_pre_init(struct ural_softc *sc, 2066 struct usb2_config_td_cc *cc, uint16_t refcount) 2067{ 2068 struct ifnet *ifp = sc->sc_ifp; 2069 struct ieee80211com *ic = ifp->if_l2com; 2070 2071 /* immediate configuration */ 2072 2073 ural_cfg_pre_stop(sc, cc, 0); 2074 2075 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2076 2077 sc->sc_flags |= URAL_FLAG_HL_READY; 2078 2079 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2080} 2081 2082static void 2083ural_cfg_init(struct ural_softc *sc, 2084 struct usb2_config_td_cc *cc, uint16_t refcount) 2085{ 2086 enum { 2087 N_DEF_MAC = (sizeof(ural_def_mac) / sizeof(ural_def_mac[0])), 2088 }; 2089 uint16_t tmp; 2090 uint16_t i; 2091 uint8_t to; 2092 2093 /* delayed configuration */ 2094 2095 ural_cfg_set_testmode(sc); 2096 2097 ural_cfg_write(sc, 0x308, 0x00f0); /* XXX magic */ 2098 2099 ural_cfg_stop(sc, cc, 0); 2100 2101 /* initialize MAC registers to default values */ 2102 for (i = 0; i < N_DEF_MAC; i++) { 2103 ural_cfg_write(sc, ural_def_mac[i].reg, 2104 ural_def_mac[i].val); 2105 } 2106 2107 /* wait for BBP and RF to wake up (this can take a long time!) */ 2108 for (to = 0;; to++) { 2109 if (to < 100) { 2110 tmp = ural_cfg_read(sc, RAL_MAC_CSR17); 2111 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2112 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) { 2113 break; 2114 } 2115 if (usb2_config_td_sleep(&sc->sc_config_td, hz / 100)) { 2116 goto fail; 2117 } 2118 } else { 2119 DPRINTF("timeout waiting for " 2120 "BBP/RF to wakeup\n"); 2121 goto fail; 2122 } 2123 } 2124 2125 /* we're ready! */ 2126 ural_cfg_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2127 2128 /* set basic rate set (will be updated later) */ 2129 ural_cfg_write(sc, RAL_TXRX_CSR11, 0x15f); 2130 2131 if (ural_cfg_bbp_init(sc)) { 2132 goto fail; 2133 } 2134 /* set default BSS channel */ 2135 ural_cfg_set_chan(sc, cc, 0); 2136 2137 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2138 ural_cfg_read_multi(sc, RAL_STA_CSR0, sc->sc_sta, 2139 sizeof(sc->sc_sta)); 2140 2141 DPRINTF("rx_ant=%d, tx_ant=%d\n", 2142 sc->sc_rx_ant, sc->sc_tx_ant); 2143 2144 ural_cfg_set_txantenna(sc, sc->sc_tx_ant); 2145 ural_cfg_set_rxantenna(sc, sc->sc_rx_ant); 2146 2147 ural_cfg_set_macaddr(sc, cc->ic_myaddr); 2148 2149 /* 2150 * make sure that the first transaction 2151 * clears the stall: 2152 */ 2153 sc->sc_flags |= (URAL_FLAG_READ_STALL | 2154 URAL_FLAG_WRITE_STALL | 2155 URAL_FLAG_LL_READY); 2156 2157 if ((sc->sc_flags & URAL_FLAG_LL_READY) && 2158 (sc->sc_flags & URAL_FLAG_HL_READY)) { 2159 struct ifnet *ifp = sc->sc_ifp; 2160 struct ieee80211com *ic = ifp->if_l2com; 2161 2162 /* 2163 * start the USB transfers, if not already started: 2164 */ 2165 usb2_transfer_start(sc->sc_xfer[1]); 2166 usb2_transfer_start(sc->sc_xfer[0]); 2167 2168 /* 2169 * start IEEE802.11 layer 2170 */ 2171 mtx_unlock(&sc->sc_mtx); 2172 ieee80211_start_all(ic); 2173 mtx_lock(&sc->sc_mtx); 2174 } 2175 /* 2176 * start Rx 2177 */ 2178 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2179 if (cc->ic_opmode != IEEE80211_M_MONITOR) { 2180 2181 tmp |= (RAL_DROP_CTL | RAL_DROP_BAD_VERSION); 2182 2183 if (cc->ic_opmode != IEEE80211_M_HOSTAP) { 2184 tmp |= RAL_DROP_TODS; 2185 } 2186 if (!(cc->if_flags & IFF_PROMISC)) { 2187 tmp |= RAL_DROP_NOT_TO_ME; 2188 } 2189 } 2190 ural_cfg_write(sc, RAL_TXRX_CSR2, tmp); 2191 2192 return; 2193 2194fail: 2195 ural_cfg_pre_stop(sc, NULL, 0); 2196 2197 if (cc) { 2198 ural_cfg_stop(sc, cc, 0); 2199 } 2200} 2201 2202static void 2203ural_cfg_pre_stop(struct ural_softc *sc, 2204 struct usb2_config_td_cc *cc, uint16_t refcount) 2205{ 2206 struct ifnet *ifp = sc->sc_ifp; 2207 2208 if (cc) { 2209 /* copy the needed configuration */ 2210 ural_config_copy(sc, cc, refcount); 2211 } 2212 /* immediate configuration */ 2213 2214 if (ifp) { 2215 /* clear flags */ 2216 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2217 } 2218 sc->sc_flags &= ~(URAL_FLAG_HL_READY | 2219 URAL_FLAG_LL_READY); 2220 2221 /* 2222 * stop all the transfers, if not already stopped: 2223 */ 2224 usb2_transfer_stop(sc->sc_xfer[0]); 2225 usb2_transfer_stop(sc->sc_xfer[1]); 2226 usb2_transfer_stop(sc->sc_xfer[2]); 2227 usb2_transfer_stop(sc->sc_xfer[3]); 2228 2229 /* clean up transmission */ 2230 ural_tx_clean_queue(sc); 2231} 2232 2233static void 2234ural_cfg_stop(struct ural_softc *sc, 2235 struct usb2_config_td_cc *cc, uint16_t refcount) 2236{ 2237 /* disable Rx */ 2238 ural_cfg_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2239 2240 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2241 ural_cfg_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2242 2243 /* wait a little */ 2244 usb2_config_td_sleep(&sc->sc_config_td, hz / 10); 2245 2246 /* clear reset */ 2247 ural_cfg_write(sc, RAL_MAC_CSR1, 0); 2248 2249 /* wait a little */ 2250 usb2_config_td_sleep(&sc->sc_config_td, hz / 10); 2251} 2252 2253static void 2254ural_cfg_amrr_start(struct ural_softc *sc) 2255{ 2256 struct ieee80211vap *vap; 2257 struct ieee80211_node *ni; 2258 2259 vap = ural_get_vap(sc); 2260 2261 if (vap == NULL) { 2262 return; 2263 } 2264 ni = vap->iv_bss; 2265 if (ni == NULL) { 2266 return; 2267 } 2268 /* init AMRR */ 2269 2270 ieee80211_amrr_node_init(&URAL_VAP(vap)->amrr, &URAL_NODE(ni)->amn, ni); 2271 /* enable AMRR timer */ 2272 2273 sc->sc_amrr_timer = 1; 2274} 2275 2276static void 2277ural_cfg_amrr_timeout(struct ural_softc *sc, 2278 struct usb2_config_td_cc *cc, uint16_t refcount) 2279{ 2280 struct ifnet *ifp = sc->sc_ifp; 2281 struct ieee80211vap *vap; 2282 struct ieee80211_node *ni; 2283 uint32_t ok; 2284 uint32_t fail; 2285 2286 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2287 ural_cfg_read_multi(sc, RAL_STA_CSR0, sc->sc_sta, sizeof(sc->sc_sta)); 2288 2289 vap = ural_get_vap(sc); 2290 if (vap == NULL) { 2291 return; 2292 } 2293 ni = vap->iv_bss; 2294 if (ni == NULL) { 2295 return; 2296 } 2297 if ((sc->sc_flags & URAL_FLAG_LL_READY) && 2298 (sc->sc_flags & URAL_FLAG_HL_READY)) { 2299 2300 ok = sc->sc_sta[7] + /* TX ok w/o retry */ 2301 sc->sc_sta[8]; /* TX ok w/ retry */ 2302 fail = sc->sc_sta[9]; /* TX retry-fail count */ 2303 2304 if (sc->sc_amrr_timer) { 2305 2306 ieee80211_amrr_tx_update(&URAL_NODE(ni)->amn, 2307 ok + fail, ok, sc->sc_sta[8] + fail); 2308 2309 if (ieee80211_amrr_choose(ni, &URAL_NODE(ni)->amn)) { 2310 /* ignore */ 2311 } 2312 } 2313 ifp->if_oerrors += fail; 2314 } 2315} 2316 2317static struct ieee80211vap * 2318ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 2319 int opmode, int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 2320 const uint8_t mac[IEEE80211_ADDR_LEN]) 2321{ 2322 struct ural_vap *uvp; 2323 struct ieee80211vap *vap; 2324 struct ural_softc *sc = ic->ic_ifp->if_softc; 2325 2326 /* Need to sync with config thread: */ 2327 mtx_lock(&sc->sc_mtx); 2328 if (usb2_config_td_sync(&sc->sc_config_td)) { 2329 mtx_unlock(&sc->sc_mtx); 2330 /* config thread is gone */ 2331 return (NULL); 2332 } 2333 mtx_unlock(&sc->sc_mtx); 2334 2335 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 2336 return NULL; 2337 uvp = (struct ural_vap *)malloc(sizeof(struct ural_vap), 2338 M_80211_VAP, M_NOWAIT | M_ZERO); 2339 if (uvp == NULL) 2340 return NULL; 2341 2342 vap = &uvp->vap; 2343 /* enable s/w bmiss handling for sta mode */ 2344 ieee80211_vap_setup(ic, vap, name, unit, opmode, 2345 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 2346 2347 /* override state transition machine */ 2348 uvp->newstate = vap->iv_newstate; 2349 vap->iv_newstate = &ural_newstate_cb; 2350 2351 ieee80211_amrr_init(&uvp->amrr, vap, 2352 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 2353 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 2354 1000 /* 1 sec */ ); 2355 2356 /* complete setup */ 2357 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 2358 2359 /* store current operation mode */ 2360 ic->ic_opmode = opmode; 2361 2362 return (vap); 2363} 2364 2365static void 2366ural_vap_delete(struct ieee80211vap *vap) 2367{ 2368 struct ural_vap *uvp = URAL_VAP(vap); 2369 struct ural_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2370 2371 /* Need to sync with config thread: */ 2372 mtx_lock(&sc->sc_mtx); 2373 if (usb2_config_td_sync(&sc->sc_config_td)) { 2374 /* ignore */ 2375 } 2376 mtx_unlock(&sc->sc_mtx); 2377 2378 ieee80211_amrr_cleanup(&uvp->amrr); 2379 ieee80211_vap_detach(vap); 2380 free(uvp, M_80211_VAP); 2381} 2382 2383/* ARGUSED */ 2384static struct ieee80211_node * 2385ural_node_alloc(struct ieee80211vap *vap __unused, 2386 const uint8_t mac[IEEE80211_ADDR_LEN] __unused) 2387{ 2388 struct ural_node *un; 2389 2390 un = malloc(sizeof(struct ural_node), M_80211_NODE, M_NOWAIT | M_ZERO); 2391 return ((un != NULL) ? &un->ni : NULL); 2392} 2393 2394static void 2395ural_newassoc(struct ieee80211_node *ni, int isnew) 2396{ 2397 struct ieee80211vap *vap = ni->ni_vap; 2398 2399 ieee80211_amrr_node_init(&URAL_VAP(vap)->amrr, &URAL_NODE(ni)->amn, ni); 2400} 2401 2402static void 2403ural_fill_write_queue(struct ural_softc *sc) 2404{ 2405 struct ifnet *ifp = sc->sc_ifp; 2406 struct ieee80211_node *ni; 2407 struct mbuf *m; 2408 2409 /* 2410 * We only fill up half of the queue with data frames. The rest is 2411 * reserved for other kinds of frames. 2412 */ 2413 2414 while (sc->sc_tx_queue.ifq_len < (IFQ_MAXLEN / 2)) { 2415 2416 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2417 if (m == NULL) 2418 break; 2419 2420 ni = (void *)(m->m_pkthdr.rcvif); 2421 m = ieee80211_encap(ni, m); 2422 if (m == NULL) { 2423 ieee80211_free_node(ni); 2424 continue; 2425 } 2426 ural_tx_data(sc, m, ni); 2427 } 2428} 2429 2430static void 2431ural_tx_clean_queue(struct ural_softc *sc) 2432{ 2433 struct mbuf *m; 2434 2435 for (;;) { 2436 _IF_DEQUEUE(&sc->sc_tx_queue, m); 2437 2438 if (!m) { 2439 break; 2440 } 2441 ural_tx_freem(m); 2442 } 2443} 2444 2445static void 2446ural_tx_freem(struct mbuf *m) 2447{ 2448 struct ieee80211_node *ni; 2449 2450 while (m) { 2451 ni = (void *)(m->m_pkthdr.rcvif); 2452 if (!ni) { 2453 m = m_free(m); 2454 continue; 2455 } 2456 if (m->m_flags & M_TXCB) { 2457 ieee80211_process_callback(ni, m, 0); 2458 } 2459 m_freem(m); 2460 ieee80211_free_node(ni); 2461 2462 break; 2463 } 2464} 2465 2466static void 2467ural_tx_mgt(struct ural_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2468{ 2469 struct ieee80211vap *vap = ni->ni_vap; 2470 struct ieee80211com *ic = ni->ni_ic; 2471 const struct ieee80211_txparam *tp; 2472 struct ieee80211_frame *wh; 2473 struct ieee80211_key *k; 2474 uint32_t flags; 2475 uint16_t dur; 2476 2477 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2478 2479 wh = mtod(m, struct ieee80211_frame *); 2480 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2481 k = ieee80211_crypto_encap(ni, m); 2482 if (k == NULL) { 2483 m_freem(m); 2484 ieee80211_free_node(ni); 2485 return; 2486 } 2487 wh = mtod(m, struct ieee80211_frame *); 2488 } 2489 flags = 0; 2490 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2491 flags |= RAL_TX_ACK; 2492 2493 dur = ieee80211_ack_duration(sc->sc_rates, tp->mgmtrate, 2494 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 2495 USETW(wh->i_dur, dur); 2496 2497 /* tell hardware to add timestamp for probe responses */ 2498 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 2499 IEEE80211_FC0_TYPE_MGT && 2500 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 2501 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2502 flags |= RAL_TX_TIMESTAMP; 2503 } 2504 m->m_pkthdr.rcvif = (void *)ni; 2505 ural_setup_desc_and_tx(sc, m, flags, tp->mgmtrate); 2506} 2507 2508static struct ieee80211vap * 2509ural_get_vap(struct ural_softc *sc) 2510{ 2511 struct ifnet *ifp; 2512 struct ieee80211com *ic; 2513 2514 if (sc == NULL) { 2515 return NULL; 2516 } 2517 ifp = sc->sc_ifp; 2518 if (ifp == NULL) { 2519 return NULL; 2520 } 2521 ic = ifp->if_l2com; 2522 if (ic == NULL) { 2523 return NULL; 2524 } 2525 return TAILQ_FIRST(&ic->ic_vaps); 2526} 2527 2528static void 2529ural_tx_bcn(struct ural_softc *sc) 2530{ 2531 struct ieee80211_node *ni; 2532 struct ieee80211vap *vap; 2533 struct ieee80211com *ic; 2534 const struct ieee80211_txparam *tp; 2535 struct mbuf *m; 2536 2537 vap = ural_get_vap(sc); 2538 if (vap == NULL) { 2539 return; 2540 } 2541 ni = vap->iv_bss; 2542 if (ni == NULL) { 2543 return; 2544 } 2545 ic = vap->iv_ic; 2546 if (ic == NULL) { 2547 return; 2548 } 2549 DPRINTFN(11, "Sending beacon frame.\n"); 2550 2551 m = ieee80211_beacon_alloc(ni, &URAL_VAP(vap)->bo); 2552 if (m == NULL) { 2553 DPRINTFN(0, "could not allocate beacon\n"); 2554 return; 2555 } 2556 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 2557 2558 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ni); 2559 ural_setup_desc_and_tx(sc, m, RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, 2560 tp->mgmtrate); 2561} 2562 2563static void 2564ural_tx_data(struct ural_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2565{ 2566 struct ieee80211vap *vap = ni->ni_vap; 2567 struct ieee80211com *ic = ni->ni_ic; 2568 const struct ieee80211_txparam *tp; 2569 struct ieee80211_frame *wh; 2570 struct ieee80211_key *k; 2571 uint32_t flags = 0; 2572 uint16_t dur; 2573 uint16_t rate; 2574 2575 DPRINTFN(11, "Sending data.\n"); 2576 2577 wh = mtod(m, struct ieee80211_frame *); 2578 2579 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 2580 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2581 rate = tp->mcastrate; 2582 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2583 rate = tp->ucastrate; 2584 else 2585 rate = ni->ni_txrate; 2586 2587 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2588 k = ieee80211_crypto_encap(ni, m); 2589 if (k == NULL) { 2590 m_freem(m); 2591 ieee80211_free_node(ni); 2592 return; 2593 } 2594 /* packet header may have moved, reset our local pointer */ 2595 wh = mtod(m, struct ieee80211_frame *); 2596 } 2597 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2598 uint8_t prot = IEEE80211_PROT_NONE; 2599 2600 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 2601 prot = IEEE80211_PROT_RTSCTS; 2602 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2603 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 2604 prot = ic->ic_protmode; 2605 if (prot != IEEE80211_PROT_NONE) { 2606 ural_tx_prot(sc, m, ni, prot, rate); 2607 flags |= RAL_TX_IFS_SIFS; 2608 } 2609 flags |= RAL_TX_ACK; 2610 flags |= RAL_TX_RETRY(7); 2611 2612 dur = ieee80211_ack_duration(sc->sc_rates, rate, 2613 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 2614 USETW(wh->i_dur, dur); 2615 } 2616 m->m_pkthdr.rcvif = (void *)ni; 2617 ural_setup_desc_and_tx(sc, m, flags, rate); 2618} 2619 2620static void 2621ural_tx_prot(struct ural_softc *sc, 2622 const struct mbuf *m, struct ieee80211_node *ni, 2623 uint8_t prot, uint16_t rate) 2624{ 2625 struct ieee80211com *ic = ni->ni_ic; 2626 const struct ieee80211_frame *wh; 2627 struct mbuf *mprot; 2628 uint32_t flags; 2629 uint16_t protrate; 2630 uint16_t ackrate; 2631 uint16_t pktlen; 2632 uint16_t dur; 2633 uint8_t isshort; 2634 2635 KASSERT((prot == IEEE80211_PROT_RTSCTS) || 2636 (prot == IEEE80211_PROT_CTSONLY), 2637 ("protection %u", prot)); 2638 2639 DPRINTFN(16, "Sending protection frame.\n"); 2640 2641 wh = mtod(m, const struct ieee80211_frame *); 2642 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2643 2644 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 2645 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 2646 2647 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 2648 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort); 2649 +ieee80211_ack_duration(sc->sc_rates, rate, isshort); 2650 flags = RAL_TX_RETRY(7); 2651 if (prot == IEEE80211_PROT_RTSCTS) { 2652 /* NB: CTS is the same size as an ACK */ 2653 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 2654 flags |= RAL_TX_ACK; 2655 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 2656 } else { 2657 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 2658 } 2659 if (mprot == NULL) { 2660 return; 2661 } 2662 mprot->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ni); 2663 ural_setup_desc_and_tx(sc, mprot, flags, protrate); 2664} 2665 2666static void 2667ural_tx_raw(struct ural_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2668 const struct ieee80211_bpf_params *params) 2669{ 2670 uint32_t flags; 2671 uint16_t rate; 2672 2673 DPRINTFN(11, "Sending raw frame.\n"); 2674 2675 rate = params->ibp_rate0 & IEEE80211_RATE_VAL; 2676 2677 /* XXX validate */ 2678 if (rate == 0) { 2679 m_freem(m); 2680 ieee80211_free_node(ni); 2681 return; 2682 } 2683 flags = 0; 2684 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 2685 flags |= RAL_TX_ACK; 2686 if (params->ibp_flags & (IEEE80211_BPF_RTS | IEEE80211_BPF_CTS)) { 2687 ural_tx_prot(sc, m, ni, 2688 (params->ibp_flags & IEEE80211_BPF_RTS) ? 2689 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 2690 rate); 2691 flags |= RAL_TX_IFS_SIFS; 2692 } 2693 m->m_pkthdr.rcvif = (void *)ni; 2694 ural_setup_desc_and_tx(sc, m, flags, rate); 2695} 2696 2697static int 2698ural_raw_xmit_cb(struct ieee80211_node *ni, struct mbuf *m, 2699 const struct ieee80211_bpf_params *params) 2700{ 2701 struct ieee80211com *ic = ni->ni_ic; 2702 struct ifnet *ifp = ic->ic_ifp; 2703 struct ural_softc *sc = ifp->if_softc; 2704 2705 mtx_lock(&sc->sc_mtx); 2706 if (params == NULL) { 2707 /* 2708 * Legacy path; interpret frame contents to decide 2709 * precisely how to send the frame. 2710 */ 2711 ural_tx_mgt(sc, m, ni); 2712 } else { 2713 /* 2714 * Caller supplied explicit parameters to use in 2715 * sending the frame. 2716 */ 2717 ural_tx_raw(sc, m, ni, params); 2718 } 2719 mtx_unlock(&sc->sc_mtx); 2720 return (0); 2721} 2722 2723static void 2724ural_update_mcast_cb(struct ifnet *ifp) 2725{ 2726 /* not supported */ 2727} 2728 2729static void 2730ural_update_promisc_cb(struct ifnet *ifp) 2731{ 2732 struct ural_softc *sc = ifp->if_softc; 2733 2734 mtx_lock(&sc->sc_mtx); 2735 usb2_config_td_queue_command 2736 (&sc->sc_config_td, &ural_config_copy, 2737 &ural_cfg_update_promisc, 0, 0); 2738 mtx_unlock(&sc->sc_mtx); 2739} 2740