ubsecreg.h revision 110522
1104478Ssam/* $FreeBSD: head/sys/dev/ubsec/ubsecreg.h 110522 2003-02-07 23:02:02Z sam $ */ 2104630Ssam/* $OpenBSD: ubsecreg.h,v 1.27 2002/09/11 22:40:31 jason Exp $ */ 3104478Ssam 4104478Ssam/* 5104478Ssam * Copyright (c) 2000 Theo de Raadt 6104478Ssam * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7104478Ssam * 8104478Ssam * Redistribution and use in source and binary forms, with or without 9104478Ssam * modification, are permitted provided that the following conditions 10104478Ssam * are met: 11104478Ssam * 12104478Ssam * 1. Redistributions of source code must retain the above copyright 13104478Ssam * notice, this list of conditions and the following disclaimer. 14104478Ssam * 2. Redistributions in binary form must reproduce the above copyright 15104478Ssam * notice, this list of conditions and the following disclaimer in the 16104478Ssam * documentation and/or other materials provided with the distribution. 17104478Ssam * 3. The name of the author may not be used to endorse or promote products 18104478Ssam * derived from this software without specific prior written permission. 19104478Ssam * 20104478Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21104478Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22104478Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23104478Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24104478Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25104478Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26104478Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27104478Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28104478Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29104478Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30104478Ssam * 31104478Ssam * Effort sponsored in part by the Defense Advanced Research Projects 32104478Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 33104478Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34104478Ssam * 35104478Ssam */ 36104478Ssam 37104478Ssam/* 38104478Ssam * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband 39104478Ssam * Security "uBSec" chip. Definitions from revision 2.8 of the product 40104478Ssam * datasheet. 41104478Ssam */ 42104478Ssam 43104478Ssam#define BS_BAR 0x10 /* DMA base address register */ 44104478Ssam#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ 45104478Ssam#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ 46104478Ssam 47104478Ssam#define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */ 48104478Ssam#define PCI_VENDOR_BLUESTEEL 0x15ab /* Bluesteel Networks */ 49114105Ssam 50104478Ssam/* Bluesteel Networks */ 51104478Ssam#define PCI_PRODUCT_BLUESTEEL_5501 0x0000 /* 5501 */ 52104478Ssam#define PCI_PRODUCT_BLUESTEEL_5601 0x5601 /* 5601 */ 53104478Ssam 54104478Ssam/* Broadcom */ 55104478Ssam#define PCI_PRODUCT_BROADCOM_BCM5700 0x1644 /* BCM5700 */ 56104478Ssam#define PCI_PRODUCT_BROADCOM_BCM5701 0x1645 /* BCM5701 */ 57104478Ssam#define PCI_PRODUCT_BROADCOM_5805 0x5805 /* 5805 */ 58111646Ssam#define PCI_PRODUCT_BROADCOM_5820 0x5820 /* 5820 */ 59111646Ssam#define PCI_PRODUCT_BROADCOM_5821 0x5821 /* 5821 */ 60104478Ssam#define PCI_PRODUCT_BROADCOM_5822 0x5822 /* 5822 */ 61104478Ssam#define PCI_PRODUCT_BROADCOM_5823 0x5823 /* 5823 */ 62104478Ssam 63104478Ssam#define UBS_PCI_RTY_SHIFT 8 64110522Ssam#define UBS_PCI_RTY_MASK 0xff 65104478Ssam#define UBS_PCI_RTY(misc) \ 66114105Ssam (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) 67114105Ssam 68114105Ssam#define UBS_PCI_TOUT_SHIFT 0 69114105Ssam#define UBS_PCI_TOUT_MASK 0xff 70104478Ssam#define UBS_PCI_TOUT(misc) \ 71104478Ssam (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) 72104478Ssam 73104478Ssam/* 74104478Ssam * DMA Control & Status Registers (offset from BS_BAR) 75104478Ssam */ 76104478Ssam#define BS_MCR1 0x00 /* DMA Master Command Record 1 */ 77104478Ssam#define BS_CTRL 0x04 /* DMA Control */ 78104478Ssam#define BS_STAT 0x08 /* DMA Status */ 79104478Ssam#define BS_ERR 0x0c /* DMA Error Address */ 80104478Ssam#define BS_MCR2 0x10 /* DMA Master Command Record 2 */ 81104478Ssam 82104478Ssam/* BS_CTRL - DMA Control */ 83104478Ssam#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ 84104478Ssam#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ 85104478Ssam#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ 86104478Ssam#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ 87104478Ssam#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ 88104478Ssam#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ 89104478Ssam#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ 90104478Ssam#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ 91104478Ssam#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ 92104478Ssam#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ 93104478Ssam#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ 94104478Ssam#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ 95104478Ssam#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ 96104478Ssam#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ 97104630Ssam#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) 98104478Ssam 99104478Ssam/* BS_STAT - DMA Status */ 100104478Ssam#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ 101104478Ssam#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ 102104630Ssam#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ 103104478Ssam#define BS_STAT_DMAERR 0x10000000 /* DMA error */ 104104630Ssam#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ 105104478Ssam#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ 106104478Ssam#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ 107104478Ssam#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ 108104478Ssam 109104478Ssam/* BS_ERR - DMA Error Address */ 110104478Ssam#define BS_ERR_ADDR 0xfffffffc /* error address mask */ 111104478Ssam#define BS_ERR_READ 0x00000002 /* fault was on read */ 112104478Ssam 113104630Ssamstruct ubsec_pktctx { 114104630Ssam u_int32_t pc_deskey[6]; /* 3DES key */ 115104478Ssam u_int32_t pc_hminner[5]; /* hmac inner state */ 116104478Ssam u_int32_t pc_hmouter[5]; /* hmac outer state */ 117104478Ssam u_int32_t pc_iv[2]; /* [3]DES iv */ 118104478Ssam u_int16_t pc_flags; /* flags, below */ 119104478Ssam u_int16_t pc_offset; /* crypto offset */ 120104478Ssam}; 121104478Ssam#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ 122104478Ssam#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ 123104478Ssam#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ 124104478Ssam#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ 125104478Ssam#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ 126104478Ssam#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ 127104478Ssam#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ 128104478Ssam 129104478Ssamstruct ubsec_pktctx_long { 130104478Ssam volatile u_int16_t pc_len; /* length of ctx struct */ 131104478Ssam volatile u_int16_t pc_type; /* context type, 0 */ 132104478Ssam volatile u_int16_t pc_flags; /* flags, same as above */ 133104478Ssam volatile u_int16_t pc_offset; /* crypto/auth offset */ 134104478Ssam volatile u_int32_t pc_deskey[6]; /* 3DES key */ 135104478Ssam volatile u_int32_t pc_iv[2]; /* [3]DES iv */ 136104478Ssam volatile u_int32_t pc_hminner[5]; /* hmac inner state */ 137104478Ssam volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ 138104478Ssam}; 139104478Ssam#define UBS_PKTCTX_TYPE_IPSEC 0x0000 140104478Ssam 141104478Ssamstruct ubsec_pktbuf { 142104478Ssam volatile u_int32_t pb_addr; /* address of buffer start */ 143104478Ssam volatile u_int32_t pb_next; /* pointer to next pktbuf */ 144104478Ssam volatile u_int32_t pb_len; /* packet length */ 145104478Ssam}; 146104478Ssam#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ 147104478Ssam 148104478Ssamstruct ubsec_mcr { 149104478Ssam volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ 150104478Ssam volatile u_int16_t mcr_flags; /* mcr flags (below) */ 151104478Ssam volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ 152104478Ssam struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ 153104478Ssam volatile u_int16_t mcr_reserved; 154104478Ssam volatile u_int16_t mcr_pktlen; 155104478Ssam struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ 156104478Ssam}; 157104478Ssam 158104478Ssamstruct ubsec_mcr_add { 159104478Ssam volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ 160104478Ssam struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ 161104478Ssam volatile u_int16_t mcr_reserved; 162104478Ssam volatile u_int16_t mcr_pktlen; 163104478Ssam struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ 164104478Ssam}; 165104478Ssam 166104478Ssam#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ 167104478Ssam#define UBS_MCR_ERROR 0x0002 /* error in processing */ 168104478Ssam#define UBS_MCR_ERRORCODE 0xff00 /* error type */ 169104478Ssam 170104478Ssamstruct ubsec_ctx_keyop { 171104478Ssam volatile u_int16_t ctx_len; /* command length */ 172104478Ssam volatile u_int16_t ctx_op; /* operation code */ 173104478Ssam volatile u_int8_t ctx_pad[60]; /* padding */ 174104478Ssam}; 175104478Ssam#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ 176104478Ssam#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ 177104478Ssam#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ 178104478Ssam#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ 179104478Ssam#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ 180104478Ssam#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ 181104478Ssam#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ 182104478Ssam#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ 183104478Ssam#define UBS_CTXOP_MODADD 0x43 /* modular addition */ 184104478Ssam#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ 185104478Ssam#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ 186104478Ssam#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ 187104478Ssam#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ 188104478Ssam#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ 189104478Ssam 190104478Ssamstruct ubsec_ctx_rngbypass { 191104478Ssam volatile u_int16_t rbp_len; /* command length, 64 */ 192104478Ssam volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ 193104478Ssam volatile u_int8_t rbp_pad[60]; /* padding */ 194104478Ssam}; 195104478Ssam 196104478Ssam/* modexp: C = (M ^ E) mod N */ 197104478Ssamstruct ubsec_ctx_modexp { 198104478Ssam volatile u_int16_t me_len; /* command length */ 199104478Ssam volatile u_int16_t me_op; /* modexp, 0x47 */ 200104478Ssam volatile u_int16_t me_E_len; /* E (bits) */ 201104478Ssam volatile u_int16_t me_N_len; /* N (bits) */ 202104478Ssam u_int8_t me_N[2048/8]; /* N */ 203104478Ssam}; 204104478Ssam 205104478Ssamstruct ubsec_ctx_rsapriv { 206104478Ssam volatile u_int16_t rpr_len; /* command length */ 207104478Ssam volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ 208104478Ssam volatile u_int16_t rpr_q_len; /* q (bits) */ 209104630Ssam volatile u_int16_t rpr_p_len; /* p (bits) */ 210104478Ssam u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ 211104478Ssam /* p, q, dp, dq, pinv */ 212104478Ssam}; 213104478Ssam