uart_bus.h revision 296373
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.3/sys/dev/uart/uart_bus.h 294229 2016-01-17 18:18:01Z ian $ 27 */ 28 29#ifndef _DEV_UART_BUS_H_ 30#define _DEV_UART_BUS_H_ 31 32#ifndef KLD_MODULE 33#include "opt_uart.h" 34#endif 35 36#include <sys/serial.h> 37#include <sys/timepps.h> 38 39/* Drain and flush targets. */ 40#define UART_DRAIN_RECEIVER 0x0001 41#define UART_DRAIN_TRANSMITTER 0x0002 42#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER 43#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER 44 45/* Received character status bits. */ 46#define UART_STAT_BREAK 0x0100 47#define UART_STAT_FRAMERR 0x0200 48#define UART_STAT_OVERRUN 0x0400 49#define UART_STAT_PARERR 0x0800 50 51/* UART_IOCTL() requests */ 52#define UART_IOCTL_BREAK 1 53#define UART_IOCTL_IFLOW 2 54#define UART_IOCTL_OFLOW 3 55#define UART_IOCTL_BAUD 4 56 57/* 58 * UART class & instance (=softc) 59 */ 60struct uart_class { 61 KOBJ_CLASS_FIELDS; 62 struct uart_ops *uc_ops; /* Low-level console operations. */ 63 u_int uc_range; /* Bus space address range. */ 64 u_int uc_rclk; /* Default rclk for this device. */ 65}; 66 67struct uart_softc { 68 KOBJ_FIELDS; 69 struct uart_class *sc_class; 70 struct uart_bas sc_bas; 71 device_t sc_dev; 72 73 struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */ 74 struct mtx *sc_hwmtx; 75 76 struct resource *sc_rres; /* Register resource. */ 77 int sc_rrid; 78 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */ 79 struct resource *sc_ires; /* Interrupt resource. */ 80 void *sc_icookie; 81 int sc_irid; 82 struct callout sc_timer; 83 84 int sc_callout:1; /* This UART is opened for callout. */ 85 int sc_fastintr:1; /* This UART uses fast interrupts. */ 86 int sc_hwiflow:1; /* This UART has HW input flow ctl. */ 87 int sc_hwoflow:1; /* This UART has HW output flow ctl. */ 88 int sc_leaving:1; /* This UART is going away. */ 89 int sc_opened:1; /* This UART is open for business. */ 90 int sc_polled:1; /* This UART has no interrupts. */ 91 int sc_txbusy:1; /* This UART is transmitting. */ 92 int sc_isquelch:1; /* This UART has input squelched. */ 93 int sc_testintr:1; /* This UART is under int. testing. */ 94 95 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */ 96 97 int sc_altbrk; /* State for alt break sequence. */ 98 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */ 99 100 /* Receiver data. */ 101 uint16_t *sc_rxbuf; 102 int sc_rxbufsz; 103 int sc_rxput; 104 int sc_rxget; 105 int sc_rxfifosz; /* Size of RX FIFO. */ 106 107 /* Transmitter data. */ 108 uint8_t *sc_txbuf; 109 int sc_txdatasz; 110 int sc_txfifosz; /* Size of TX FIFO and buffer. */ 111 112 /* Pulse capturing support (PPS). */ 113 struct pps_state sc_pps; 114 int sc_pps_mode; 115 sbintime_t sc_pps_captime; 116 117 /* Upper layer data. */ 118 void *sc_softih; 119 uint32_t sc_ttypend; 120 union { 121 /* TTY specific data. */ 122 struct { 123 struct tty *tp; 124 } u_tty; 125 /* Keyboard specific data. */ 126 struct { 127 } u_kbd; 128 } sc_u; 129}; 130 131extern devclass_t uart_devclass; 132extern const char uart_driver_name[]; 133 134int uart_bus_attach(device_t dev); 135int uart_bus_detach(device_t dev); 136int uart_bus_resume(device_t dev); 137serdev_intr_t *uart_bus_ihand(device_t dev, int ipend); 138int uart_bus_ipend(device_t dev); 139int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan); 140int uart_bus_sysdev(device_t dev); 141 142void uart_sched_softih(struct uart_softc *, uint32_t); 143 144int uart_tty_attach(struct uart_softc *); 145int uart_tty_detach(struct uart_softc *); 146struct mtx *uart_tty_getlock(struct uart_softc *); 147void uart_tty_intr(void *arg); 148 149/* 150 * Receive buffer operations. 151 */ 152static __inline int 153uart_rx_empty(struct uart_softc *sc) 154{ 155 156 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0); 157} 158 159static __inline int 160uart_rx_full(struct uart_softc *sc) 161{ 162 163 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz) ? 164 (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0)); 165} 166 167static __inline int 168uart_rx_get(struct uart_softc *sc) 169{ 170 int ptr, xc; 171 172 ptr = sc->sc_rxget; 173 if (ptr == sc->sc_rxput) 174 return (-1); 175 xc = sc->sc_rxbuf[ptr++]; 176 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0; 177 return (xc); 178} 179 180static __inline int 181uart_rx_next(struct uart_softc *sc) 182{ 183 int ptr; 184 185 ptr = sc->sc_rxget; 186 if (ptr == sc->sc_rxput) 187 return (-1); 188 ptr += 1; 189 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0; 190 return (0); 191} 192 193static __inline int 194uart_rx_peek(struct uart_softc *sc) 195{ 196 int ptr; 197 198 ptr = sc->sc_rxget; 199 return ((ptr == sc->sc_rxput) ? -1 : sc->sc_rxbuf[ptr]); 200} 201 202static __inline int 203uart_rx_put(struct uart_softc *sc, int xc) 204{ 205 int ptr; 206 207 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0; 208 if (ptr == sc->sc_rxget) 209 return (ENOSPC); 210 sc->sc_rxbuf[sc->sc_rxput] = xc; 211 sc->sc_rxput = ptr; 212 return (0); 213} 214 215#endif /* _DEV_UART_BUS_H_ */ 216