tw_cl_share.h revision 197409
117680Spst/* 239300Sfenner * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 317680Spst * Copyright (c) 2004-05 Vinod Kashyap 417680Spst * All rights reserved. 517680Spst * 617680Spst * Redistribution and use in source and binary forms, with or without 717680Spst * modification, are permitted provided that the following conditions 817680Spst * are met: 917680Spst * 1. Redistributions of source code must retain the above copyright 1017680Spst * notice, this list of conditions and the following disclaimer. 1117680Spst * 2. Redistributions in binary form must reproduce the above copyright 1217680Spst * notice, this list of conditions and the following disclaimer in the 1317680Spst * documentation and/or other materials provided with the distribution. 1417680Spst * 1517680Spst * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1617680Spst * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1717680Spst * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1817680Spst * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1917680Spst * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2056896Sfenner * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2156896Sfenner * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2217680Spst * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2317680Spst * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24127675Sbms * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25162021Ssam * SUCH DAMAGE. 2617680Spst * 2717680Spst * $FreeBSD: head/sys/dev/twa/tw_cl_share.h 197409 2009-09-22 16:28:07Z rdivacky $ 2856896Sfenner */ 2956896Sfenner 3056896Sfenner/* 3156896Sfenner * AMCC'S 3ware driver for 9000 series storage controllers. 32127675Sbms * 3317680Spst * Author: Vinod Kashyap 3417680Spst * Modifications by: Adam Radford 3517680Spst * Modifications by: Manjunath Ranganathaiah 36127675Sbms */ 3717680Spst 3839300Sfenner 39127675Sbms 4017680Spst#ifndef TW_CL_SHARE_H 4117680Spst 42127675Sbms#define TW_CL_SHARE_H 43127675Sbms 44127675Sbms 4517680Spst/* 46127675Sbms * Macros, structures and functions shared between OSL and CL, 47127675Sbms * and defined by CL. 48146778Ssam */ 49146778Ssam 50146778Ssam#define TW_CL_NULL ((TW_VOID *)0) 51146778Ssam#define TW_CL_TRUE 1 52146778Ssam#define TW_CL_FALSE 0 53146778Ssam 54146778Ssam#define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */ 55146778Ssam#define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */ 56146778Ssam#define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */ 57146778Ssam#define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */ 58146778Ssam#define TW_CL_DEVICE_ID_9K_SA 0x1005 /* 9000 PCIe SAS series device id */ 59146778Ssam 60146778Ssam#define TW_CL_BAR_TYPE_IO 1 /* I/O base address */ 61146778Ssam#define TW_CL_BAR_TYPE_MEM 2 /* memory base address */ 62146778Ssam#define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */ 63146778Ssam 64146778Ssam#ifdef TW_OSL_ENCLOSURE_SUPPORT 65146778Ssam#define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support 66146778Ssam -- enclosure target id is 64 */ 67146778Ssam#else /* TW_OSL_ENCLOSURE_SUPPORT */ 68146778Ssam#define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */ 69146778Ssam#endif /* TW_OSL_ENCLOSURE_SUPPORT */ 70146778Ssam 71146778Ssam#define TW_CL_MAX_NUM_LUNS 16 /* max # of LUN's we support */ 72146778Ssam#define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */ 73146778Ssam 74146778Ssam/* 75146778Ssam * Though we can support 256 simultaneous requests, we advertise as capable 76146778Ssam * of supporting only 255, since we want to keep one CL internal request 77146778Ssam * context packet always available for internal requests. 78146778Ssam */ 79146778Ssam#define TW_CL_MAX_SIMULTANEOUS_REQUESTS 0xFF /* max simult reqs supported */ 80146778Ssam 81146778Ssam#define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */ 82146778Ssam#define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */ 83146778Ssam 84146778Ssam 85146778Ssam/* Possible values of ctlr->flags */ 86146778Ssam#define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */ 87146778Ssam#define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */ 88146778Ssam#define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */ 89146778Ssam#define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */ 90146778Ssam#define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */ 91146778Ssam 92146778Ssam/* Possible error values from the Common Layer. */ 93146778Ssam#define TW_CL_ERR_REQ_SUCCESS 0 94146778Ssam#define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0) 95146778Ssam#define TW_CL_ERR_REQ_INVALID_TARGET (1<<1) 9617680Spst#define TW_CL_ERR_REQ_INVALID_LUN (1<<2) 97127675Sbms#define TW_CL_ERR_REQ_SCSI_ERROR (1<<3) 98127675Sbms#define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4) 99127675Sbms#define TW_CL_ERR_REQ_BUS_RESET (1<<5) 100127675Sbms#define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6) 101127675Sbms 102127675Sbms 103127675Sbms/* Possible values of req_pkt->flags */ 104127675Sbms#define TW_CL_REQ_RETRY_ON_BUSY (1<<0) 105127675Sbms#define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1) 106127675Sbms 107127675Sbms 108127675Sbms#define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3 109127675Sbms#define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4 110127675Sbms#define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21 111162021Ssam#define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22 112127675Sbms#define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5 113127675Sbms#define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8 114127675Sbms#define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7 115127675Sbms#define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10 116127675Sbms 117127675Sbms#define TW_CL_SEVERITY_ERROR 0x1 118127675Sbms#define TW_CL_SEVERITY_WARNING 0x2 119127675Sbms#define TW_CL_SEVERITY_INFO 0x3 120127675Sbms#define TW_CL_SEVERITY_DEBUG 0x4 121127675Sbms 122127675Sbms#define TW_CL_SEVERITY_ERROR_STRING "ERROR" 123127675Sbms#define TW_CL_SEVERITY_WARNING_STRING "WARNING" 124127675Sbms#define TW_CL_SEVERITY_INFO_STRING "INFO" 125146778Ssam#define TW_CL_SEVERITY_DEBUG_STRING "DEBUG" 12617680Spst 12717680Spst 128127675Sbms#pragma pack(1) 129127675Sbms 13017680Spst/* 13117680Spst * Structure, a pointer to which is used as the controller handle in 13217680Spst * communications between the OS Layer and the Common Layer. 133127675Sbms */ 134127675Sbmsstruct tw_cl_ctlr_handle { 13517680Spst TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */ 13617680Spst TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */ 13717680Spst}; 138127675Sbms 13917680Spst 140127675Sbms/* 141127675Sbms * Structure, a pointer to which is used as the request handle in 142127675Sbms * communications between the OS Layer and the Common Layer. 143127675Sbms */ 144127675Sbmsstruct tw_cl_req_handle { 145127675Sbms TW_VOID *osl_req_ctxt; /* OSL's request context */ 146127675Sbms TW_VOID *cl_req_ctxt; /* CL's request context */ 147127675Sbms}; 148127675Sbms 149127675Sbms 150127675Sbms/* Structure used to describe SCSI requests to CL. */ 151127675Sbmsstruct tw_cl_scsi_req_packet { 152127675Sbms TW_UINT32 unit; /* unit # to send cmd to */ 153127675Sbms TW_UINT32 lun; /* LUN to send cmd to */ 154127675Sbms TW_UINT8 *cdb; /* ptr to SCSI cdb */ 155127675Sbms TW_UINT32 cdb_len; /* # of valid cdb bytes */ 156127675Sbms TW_UINT32 sense_len; /* # of bytes of valid sense info */ 157127675Sbms TW_UINT8 *sense_data; /* ptr to sense data, if any */ 158127675Sbms TW_UINT32 scsi_status; /* SCSI status returned by fw */ 159127675Sbms TW_UINT32 sgl_entries; /* # of SG descriptors */ 160127675Sbms TW_UINT8 *sg_list; /* ptr to SG list */ 161127675Sbms}; 162127675Sbms 163127675Sbms 164127675Sbms/* Structure used to describe pass through command packets to CL. */ 165127675Sbmsstruct tw_cl_passthru_req_packet { 166127675Sbms TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */ 16717680Spst TW_UINT32 cmd_pkt_length; /* size of cmd pkt */ 168127675Sbms TW_UINT32 sgl_entries; /* # of SG descriptors */ 169127675Sbms TW_UINT8 *sg_list; /* ptr to SG list */ 170127675Sbms}; 171127675Sbms 172127675Sbms 17317680Spst/* Request packet submitted to the Common Layer, by the OS Layer. */ 17417680Spststruct tw_cl_req_packet { 17517680Spst TW_UINT32 cmd; /* Common Layer cmd */ 176127675Sbms TW_UINT32 flags; /* flags describing request */ 17717680Spst TW_UINT32 status; /* Common Layer returned status */ 178127675Sbms TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle); 179127675Sbms /* OSL routine to be called by CL on req completion */ 180127675Sbms TW_VOID (*tw_osl_sgl_callback)( 181127675Sbms struct tw_cl_req_handle *req_handle, TW_VOID *sg_list, 182127675Sbms TW_UINT32 *num_sgl_entries); 183127675Sbms /* OSL callback to get SG list. */ 184127675Sbms 185127675Sbms union { 186127675Sbms struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */ 187127675Sbms struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/ 188127675Sbms } gen_req_pkt; 189127675Sbms}; 190127675Sbms 191127675Sbms 192127675Sbms/* 193127675Sbms * Packet that describes an AEN/error generated by the controller, 194127675Sbms * Common Layer, or even the OS Layer. 195127675Sbms */ 196127675Sbmsstruct tw_cl_event_packet { 197127675Sbms TW_UINT32 sequence_id; 198127675Sbms TW_UINT32 time_stamp_sec; 199127675Sbms TW_UINT16 aen_code; 200127675Sbms TW_UINT8 severity; 201127675Sbms TW_UINT8 retrieved; 202127675Sbms TW_UINT8 repeat_count; 203127675Sbms TW_UINT8 parameter_len; 204127675Sbms TW_UINT8 parameter_data[98]; 205127675Sbms TW_UINT32 event_src; 206127675Sbms TW_UINT8 severity_str[20]; 207127675Sbms}; 208127675Sbms 209127675Sbms 210127675Sbms/* Structure to link 2 adjacent elements in a list. */ 211127675Sbmsstruct tw_cl_link { 212127675Sbms struct tw_cl_link *next; 213127675Sbms struct tw_cl_link *prev; 214127675Sbms}; 215127675Sbms 216127675Sbms 217127675Sbms/* Scatter/Gather list entry with 32 bit addresses. */ 218127675Sbmsstruct tw_cl_sg_desc32 { 219127675Sbms TW_UINT32 address; 220127675Sbms TW_UINT32 length; 221127675Sbms}; 222127675Sbms 223127675Sbms 224127675Sbms/* Scatter/Gather list entry with 64 bit addresses. */ 225127675Sbmsstruct tw_cl_sg_desc64 { 226127675Sbms TW_UINT64 address; 227127675Sbms TW_UINT32 length; 228127675Sbms}; 229127675Sbms 230127675Sbms#pragma pack() 231127675Sbms 232127675Sbms 233127675Sbms/* Byte swap functions. Valid only if running on big endian platforms. */ 234127675Sbms#ifdef TW_OSL_BIG_ENDIAN 235127675Sbms 236127675Sbms#define TW_CL_SWAP16_WITH_CAST(x) \ 237127675Sbms ((x << 8) | (x >> 8)) 238127675Sbms 239127675Sbms 240127675Sbms#define TW_CL_SWAP32_WITH_CAST(x) \ 241127675Sbms ((x << 24) | ((x << 8) & (0xFF0000)) | \ 242127675Sbms ((x >> 8) & (0xFF00)) | (x >> 24)) 243127675Sbms 244127675Sbms 24517680Spst#define TW_CL_SWAP64_WITH_CAST(x) \ 246127675Sbms ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\ 24717680Spst ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0])))) 248127675Sbms 249127675Sbms 25017680Spst#else /* TW_OSL_BIG_ENDIAN */ 251127675Sbms 252127675Sbms#define TW_CL_SWAP16_WITH_CAST(x) x 253127675Sbms#define TW_CL_SWAP32_WITH_CAST(x) x 25417680Spst#define TW_CL_SWAP64_WITH_CAST(x) x 255127675Sbms 256127675Sbms#endif /* TW_OSL_BIG_ENDIAN */ 257127675Sbms 25817680Spst#define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x)) 259146778Ssam#define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x)) 260127675Sbms#define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x)) 261147904Ssam 262127675Sbms 26356896Sfenner/* Queue manipulation functions. */ 264127675Sbms 265127675Sbms/* Initialize a queue. */ 266127675Sbms#define TW_CL_Q_INIT(head) do { \ 26717680Spst (head)->prev = (head)->next = head; \ 268127675Sbms} while (0) 269127675Sbms 270127675Sbms 271127675Sbms/* Insert an item at the head of the queue. */ 272127675Sbms#define TW_CL_Q_INSERT_HEAD(head, item) do { \ 273127675Sbms (item)->next = (head)->next; \ 274127675Sbms (item)->prev = head; \ 275127675Sbms (head)->next->prev = item; \ 276127675Sbms (head)->next = item; \ 277127675Sbms} while (0) 278127675Sbms 279127675Sbms 280127675Sbms/* Insert an item at the tail of the queue. */ 281127675Sbms#define TW_CL_Q_INSERT_TAIL(head, item) do { \ 282127675Sbms (item)->next = head; \ 28317680Spst (item)->prev = (head)->prev; \ 28417680Spst (head)->prev->next = item; \ 285127675Sbms (head)->prev = item; \ 286127675Sbms} while (0) 28717680Spst 28817680Spst 28917680Spst/* Remove an item from the head of the queue. */ 290146778Ssam#define TW_CL_Q_REMOVE_ITEM(head, item) do { \ 291146778Ssam (item)->prev->next = (item)->next; \ 292147904Ssam (item)->next->prev = (item)->prev; \ 293146778Ssam} while (0) 294146778Ssam 295146778Ssam 296146778Ssam/* Retrieve the item at the head of the queue. */ 297147904Ssam#define TW_CL_Q_FIRST_ITEM(head) \ 298147904Ssam (((head)->next != head) ? ((head)->next) : TW_CL_NULL) 299146778Ssam 300146778Ssam 301146778Ssam/* Retrieve the item at the tail of the queue. */ 302146778Ssam#define TW_CL_Q_LAST_ITEM(head) \ 303146778Ssam (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL) 304146778Ssam 305146778Ssam 306146778Ssam/* Retrieve the item next to a given item in the queue. */ 307146778Ssam#define TW_CL_Q_NEXT_ITEM(head, item) \ 308146778Ssam (((item)->next != head) ? ((item)->next) : TW_CL_NULL) 309146778Ssam 310146778Ssam 311146778Ssam/* Retrieve the item previous to a given item in the queue. */ 312146778Ssam#define TW_CL_Q_PREV_ITEM(head, item) \ 313146778Ssam (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL) 314146778Ssam 315146778Ssam 316146778Ssam/* Determine the offset of a field from the head of the structure it is in. */ 317146778Ssam#define TW_CL_STRUCT_OFFSET(struct_type, field) \ 318146778Ssam (TW_INT8 *)(&((struct_type *)0)->field) 319146778Ssam 320146778Ssam 321146778Ssam/* 322146778Ssam * Determine the address of the head of a structure, given the address of a 323146778Ssam * field within it. 324146778Ssam */ 325146778Ssam#define TW_CL_STRUCT_HEAD(addr, struct_type, field) \ 326146778Ssam (struct_type *)((TW_INT8 *)addr - \ 327146778Ssam TW_CL_STRUCT_OFFSET(struct_type, field)) 328146778Ssam 329146778Ssam 330146778Ssam 331146778Ssam#ifndef TW_BUILDING_API 332146778Ssam 333146778Ssam#include "tw_osl_inline.h" 334 335 336 337/* 338 * The following are extern declarations of OS Layer defined functions called 339 * by the Common Layer. If any function has been defined as a macro in 340 * tw_osl_share.h, we will not make the extern declaration here. 341 */ 342 343#ifndef tw_osl_breakpoint 344/* Allows setting breakpoints in the CL code for debugging purposes. */ 345extern TW_VOID tw_osl_breakpoint(TW_VOID); 346#endif 347 348 349#ifndef tw_osl_ctlr_busy 350/* Called when CL is too busy to accept new requests. */ 351extern TW_VOID tw_osl_ctlr_busy(struct tw_cl_ctlr_handle *ctlr_handle, 352 struct tw_cl_req_handle *req_handle); 353#endif 354 355 356#ifndef tw_osl_ctlr_ready 357/* Called on cmd interrupt. Allows re-submission of any pending requests. */ 358extern TW_VOID tw_osl_ctlr_ready(struct tw_cl_ctlr_handle *ctlr_handle); 359#endif 360 361 362#ifndef tw_osl_cur_func 363/* Text name of current function. */ 364extern TW_INT8 *tw_osl_cur_func(TW_VOID); 365#endif 366 367 368#ifdef TW_OSL_DEBUG 369#ifndef tw_osl_dbg_printf 370/* Print to syslog/event log/debug console, as applicable. */ 371extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle, 372 const TW_INT8 *fmt, ...); 373#endif 374#endif /* TW_OSL_DEBUG */ 375 376 377#ifndef tw_osl_delay 378/* Cause a delay of usecs micro-seconds. */ 379extern TW_VOID tw_osl_delay(TW_INT32 usecs); 380#endif 381 382 383#ifndef tw_osl_destroy_lock 384/* Create/initialize a lock for CL's use. */ 385extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle, 386 TW_LOCK_HANDLE *lock); 387#endif 388 389 390#ifndef tw_osl_free_lock 391/* Free a previously held lock. */ 392extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle, 393 TW_LOCK_HANDLE *lock); 394#endif 395 396 397#ifndef tw_osl_get_local_time 398/* Get local time. */ 399extern TW_TIME tw_osl_get_local_time(TW_VOID); 400#endif 401 402 403#ifndef tw_osl_get_lock 404/* Acquire a lock. */ 405extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle, 406 TW_LOCK_HANDLE *lock); 407#endif 408 409 410#ifndef tw_osl_init_lock 411/* Create/initialize a lock for CL's use. */ 412extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle, 413 TW_INT8 *lock_name, TW_LOCK_HANDLE *lock); 414#endif 415 416 417#ifndef tw_osl_memcpy 418/* Copy 'size' bytes from 'src' to 'dest'. */ 419extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size); 420#endif 421 422 423#ifndef tw_osl_memzero 424/* Zero 'size' bytes starting at 'addr'. */ 425extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size); 426#endif 427 428 429#ifndef tw_osl_notify_event 430/* Notify OSL of a controller/CL (or even OSL) event. */ 431extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle, 432 struct tw_cl_event_packet *event); 433#endif 434 435 436#ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 437#ifndef tw_osl_read_pci_config 438/* Read 'size' bytes from 'offset' in the PCI config space. */ 439extern TW_UINT32 tw_osl_read_pci_config( 440 struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size); 441#endif 442#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 443 444 445#ifndef tw_osl_read_reg 446/* Read 'size' bytes at 'offset' from base address of this controller. */ 447extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle, 448 TW_INT32 offset, TW_INT32 size); 449#endif 450 451 452#ifndef tw_osl_scan_bus 453/* Request OSL for a bus scan. */ 454extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle); 455#endif 456 457 458#ifdef TW_OSL_CAN_SLEEP 459#ifndef tw_osl_sleep 460/* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */ 461extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle, 462 TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout); 463#endif 464#endif /* TW_OSL_CAN_SLEEP */ 465 466 467#ifndef tw_osl_sprintf 468/* Standard sprintf. */ 469extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...); 470#endif 471 472 473#ifndef tw_osl_strcpy 474/* Copy string 'src' to 'dest'. */ 475extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src); 476#endif 477 478 479#ifndef tw_osl_strlen 480/* Return length of string pointed at by 'str'. */ 481extern TW_INT32 tw_osl_strlen(TW_VOID *str); 482#endif 483 484#ifndef tw_osl_vsprintf 485/* Standard vsprintf. */ 486extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap); 487#endif 488 489 490#ifdef TW_OSL_CAN_SLEEP 491#ifndef tw_osl_wakeup 492/* Wake up a thread sleeping by a call to tw_osl_sleep. */ 493extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle, 494 TW_SLEEP_HANDLE *sleep_handle); 495#endif 496#endif /* TW_OSL_CAN_SLEEP */ 497 498 499#ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 500#ifndef tw_osl_write_pci_config 501/* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */ 502extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle, 503 TW_INT32 offset, TW_INT32 value, TW_INT32 size); 504#endif 505#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 506 507 508#ifndef tw_osl_write_reg 509/* 510 * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of 511 * this controller. 512 */ 513extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle, 514 TW_INT32 offset, TW_INT32 value, TW_INT32 size); 515#endif 516 517 518 519/* Functions in the Common Layer */ 520 521/* Creates and queues AEN's. Also notifies OS Layer. */ 522extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle, 523 TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code, 524 TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc, 525 TW_UINT8 *event_specific_desc, ...); 526 527/* Indicates whether a ctlr is supported by CL. */ 528extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id); 529 530 531/* Deferred interrupt handler. */ 532extern TW_VOID tw_cl_deferred_interrupt(struct tw_cl_ctlr_handle *ctlr_handle); 533 534 535/* Submit a firmware cmd packet. */ 536extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle, 537 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 538 539 540/* Find out how much memory CL needs. */ 541extern TW_INT32 tw_cl_get_mem_requirements( 542 struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags, 543 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens, 544 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor, 545 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size 546 ); 547 548 549/* Return PCI BAR info. */ 550extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type, 551 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size); 552 553 554/* Initialize Common Layer for a given controller. */ 555extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 556 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs, 557 TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem, 558 TW_UINT64 dma_mem_phys 559 ); 560 561 562/* CL's interrupt handler. */ 563extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle); 564 565 566/* CL's ioctl handler. */ 567extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle, 568 u_long cmd, TW_VOID *buf); 569 570 571#ifdef TW_OSL_DEBUG 572/* Print CL's state/statistics for a controller. */ 573extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle); 574 575/* Prints CL internal details of a given request. */ 576extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle); 577#endif /* TW_OSL_DEBUG */ 578 579 580/* Soft reset controller. */ 581extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle); 582 583 584#ifdef TW_OSL_DEBUG 585/* Reset CL's statistics for a controller. */ 586extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle); 587#endif /* TW_OSL_DEBUG */ 588 589 590/* Stop a controller. */ 591extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 592 TW_UINT32 flags); 593 594 595/* Submit a SCSI I/O request. */ 596extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle, 597 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 598 599 600#endif /* TW_BUILDING_API */ 601 602#endif /* TW_CL_SHARE_H */ 603