tw_cl_share.h revision 144966
121308Sache/* 221308Sache * Copyright (c) 2004-05 Applied Micro Circuits Corporation. 321308Sache * Copyright (c) 2004-05 Vinod Kashyap 421308Sache * All rights reserved. 521308Sache * 621308Sache * Redistribution and use in source and binary forms, with or without 721308Sache * modification, are permitted provided that the following conditions 821308Sache * are met: 921308Sache * 1. Redistributions of source code must retain the above copyright 1021308Sache * notice, this list of conditions and the following disclaimer. 1158310Sache * 2. Redistributions in binary form must reproduce the above copyright 1221308Sache * notice, this list of conditions and the following disclaimer in the 1321308Sache * documentation and/or other materials provided with the distribution. 1421308Sache * 1521308Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1621308Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1721308Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1821308Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1921308Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2021308Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2121308Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2258310Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2321308Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2421308Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2521308Sache * SUCH DAMAGE. 2621308Sache * 2721308Sache * $FreeBSD: head/sys/dev/twa/tw_cl_share.h 144966 2005-04-12 22:07:11Z vkashyap $ 2821308Sache */ 2921308Sache 3021308Sache/* 3121308Sache * AMCC'S 3ware driver for 9000 series storage controllers. 3221308Sache * 3321308Sache * Author: Vinod Kashyap 3421308Sache */ 3521308Sache 3621308Sache 3721308Sache 3821308Sache#ifndef TW_CL_SHARE_H 3921308Sache 4021308Sache#define TW_CL_SHARE_H 4121308Sache 4221308Sache 4321308Sache/* 4421308Sache * Macros, structures and functions shared between OSL and CL, 4521308Sache * and defined by CL. 4621308Sache */ 4721308Sache 4821308Sache 4921308Sache#define TW_CL_VERSION_STRING "1.00.00.007" 5021308Sache 5121308Sache#define TW_CL_NULL ((TW_VOID *)0) 5221308Sache#define TW_CL_TRUE 1 5321308Sache#define TW_CL_FALSE 0 5421308Sache 5521308Sache#define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */ 5621308Sache#define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 series device id */ 5758310Sache 5858310Sache#define TW_CL_MAX_NUM_UNITS 16 /* max # of units we support */ 5958310Sache#define TW_CL_MAX_NUM_LUNS 16 /* max # of LUN's we support */ 6021308Sache#define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */ 6121308Sache 6221308Sache/* 6321308Sache * Though we can support 256 simultaneous requests, we advertise as capable 6421308Sache * of supporting only 255, since we want to keep one CL internal request 6521308Sache * context packet always available for internal requests. 6621308Sache */ 6721308Sache#define TW_CL_MAX_SIMULTANEOUS_REQUESTS 0xFF /* max simult reqs supported */ 6821308Sache 6921308Sache#define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */ 7021308Sache#define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */ 7121308Sache 7221308Sache 7321308Sache/* Possible values of ctlr->flags */ 7421308Sache#define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */ 7521308Sache#define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */ 7621308Sache#define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */ 7721308Sache#define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */ 7821308Sache#define TW_CL_FLASH_FIRMWARE (1<<4) /* Flash firmware */ 7921308Sache 8021308Sache/* Possible error values from the Common Layer. */ 8121308Sache#define TW_CL_ERR_REQ_SUCCESS 0 8221308Sache#define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0) 8321308Sache#define TW_CL_ERR_REQ_INVALID_TARGET (1<<1) 8421308Sache#define TW_CL_ERR_REQ_INVALID_LUN (1<<2) 8521308Sache#define TW_CL_ERR_REQ_SCSI_ERROR (1<<3) 8621308Sache#define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4) 8721308Sache#define TW_CL_ERR_REQ_BUS_RESET (1<<5) 8821308Sache#define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6) 8921308Sache 9021308Sache 9121308Sache/* Possible values of req_pkt->flags */ 9221308Sache#ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 9321308Sache#define TW_CL_REQ_RETRY_ON_BUSY (1<<0) 9421308Sache#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 9521308Sache#define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1) 9621308Sache 9721308Sache 9821308Sache#define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3 9921308Sache#define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4 10021308Sache#define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21 10121308Sache#define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22 10221308Sache#define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5 10321308Sache#define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8 10421308Sache#define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7 10521308Sache#define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10 10621308Sache 10721308Sache#define TW_CL_SEVERITY_ERROR 0x1 10821308Sache#define TW_CL_SEVERITY_WARNING 0x2 10921308Sache#define TW_CL_SEVERITY_INFO 0x3 11021308Sache#define TW_CL_SEVERITY_DEBUG 0x4 11121308Sache 11221308Sache#define TW_CL_SEVERITY_ERROR_STRING "ERROR" 11321308Sache#define TW_CL_SEVERITY_WARNING_STRING "WARNING" 11421308Sache#define TW_CL_SEVERITY_INFO_STRING "INFO" 11521308Sache#define TW_CL_SEVERITY_DEBUG_STRING "DEBUG" 11621308Sache 11758310Sache 11821308Sache#pragma pack(1) 11921308Sache 12021308Sache/* 12121308Sache * Structure, a pointer to which is used as the controller handle in 12221308Sache * communications between the OS Layer and the Common Layer. 12321308Sache */ 12421308Sachestruct tw_cl_ctlr_handle { 12521308Sache TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */ 12621308Sache TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */ 12721308Sache}; 12821308Sache 12921308Sache 13021308Sache/* 13121308Sache * Structure, a pointer to which is used as the request handle in 13221308Sache * communications between the OS Layer and the Common Layer. 13321308Sache */ 13421308Sachestruct tw_cl_req_handle { 13521308Sache TW_VOID *osl_req_ctxt; /* OSL's request context */ 13621308Sache TW_VOID *cl_req_ctxt; /* CL's request context */ 13721308Sache}; 13821308Sache 13921308Sache 14021308Sache/* Structure used to describe SCSI requests to CL. */ 14121308Sachestruct tw_cl_scsi_req_packet { 14221308Sache TW_UINT32 unit; /* unit # to send cmd to */ 14321308Sache TW_UINT32 lun; /* LUN to send cmd to */ 14421308Sache TW_UINT8 *cdb; /* ptr to SCSI cdb */ 14521308Sache TW_UINT32 cdb_len; /* # of valid cdb bytes */ 14621308Sache TW_UINT32 sense_len; /* # of bytes of valid sense info */ 14721308Sache TW_UINT8 *sense_data; /* ptr to sense data, if any */ 14821308Sache TW_UINT32 scsi_status; /* SCSI status returned by fw */ 14921308Sache TW_UINT32 sgl_entries; /* # of SG descriptors */ 15021308Sache TW_UINT8 *sg_list; /* ptr to SG list */ 15121308Sache}; 15221308Sache 15321308Sache 15421308Sache/* Structure used to describe pass through command packets to CL. */ 15521308Sachestruct tw_cl_passthru_req_packet { 15621308Sache TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */ 15721308Sache TW_UINT32 cmd_pkt_length; /* size of cmd pkt */ 15821308Sache TW_UINT32 sgl_entries; /* # of SG descriptors */ 15921308Sache TW_UINT8 *sg_list; /* ptr to SG list */ 16021308Sache}; 16121308Sache 16221308Sache 16321308Sache/* Request packet submitted to the Common Layer, by the OS Layer. */ 16421308Sachestruct tw_cl_req_packet { 16521308Sache TW_UINT32 cmd; /* Common Layer cmd */ 16621308Sache TW_UINT32 flags; /* flags describing request */ 16721308Sache TW_UINT32 status; /* Common Layer returned status */ 16821308Sache TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle); 16921308Sache /* OSL routine to be called by CL on req completion */ 17021308Sache TW_VOID (*tw_osl_sgl_callback)( 17121308Sache struct tw_cl_req_handle *req_handle, TW_VOID *sg_list, 17221308Sache TW_UINT32 *num_sgl_entries); 17321308Sache /* OSL callback to get SG list. */ 17421308Sache 17521308Sache#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST 17621308Sache 17721308Sache TW_VOID *dma_mem; 17821308Sache TW_UINT64 dma_mem_phys; 17921308Sache 18021308Sache#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */ 18121308Sache 18221308Sache#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 18321308Sache 18421308Sache TW_VOID *non_dma_mem; 18521308Sache 18621308Sache#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 18721308Sache 18821308Sache union { 18921308Sache struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */ 19021308Sache struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/ 19121308Sache } gen_req_pkt; 19221308Sache}; 19321308Sache 19421308Sache 19521308Sache/* 19621308Sache * Packet that describes an AEN/error generated by the controller, 19721308Sache * Common Layer, or even the OS Layer. 19821308Sache */ 19921308Sachestruct tw_cl_event_packet { 20021308Sache TW_UINT32 sequence_id; 20121308Sache TW_UINT32 time_stamp_sec; 20221308Sache TW_UINT16 aen_code; 20321308Sache TW_UINT8 severity; 20421308Sache TW_UINT8 retrieved; 20521308Sache TW_UINT8 repeat_count; 20621308Sache TW_UINT8 parameter_len; 20721308Sache TW_UINT8 parameter_data[98]; 20821308Sache TW_UINT32 event_src; 20921308Sache TW_UINT8 severity_str[20]; 21021308Sache}; 21121308Sache 21221308Sache 21321308Sache/* Structure to link 2 adjacent elements in a list. */ 21421308Sachestruct tw_cl_link { 21521308Sache struct tw_cl_link *next; 21621308Sache struct tw_cl_link *prev; 21721308Sache}; 21821308Sache 21921308Sache 22021308Sache/* Scatter/Gather list entry with 32 bit addresses. */ 22121308Sachestruct tw_cl_sg_desc32 { 22221308Sache TW_UINT32 address; 22321308Sache TW_UINT32 length; 22421308Sache}; 22521308Sache 22621308Sache 22721308Sache/* Scatter/Gather list entry with 64 bit addresses. */ 22821308Sachestruct tw_cl_sg_desc64 { 22921308Sache TW_UINT64 address; 23021308Sache TW_UINT32 length; 23121308Sache}; 23221308Sache 23321308Sache#pragma pack() 23421308Sache 23521308Sache 23621308Sache/* Byte swap functions. Valid only if running on big endian platforms. */ 23721308Sache#ifdef TW_OSL_BIG_ENDIAN 23821308Sache 23921308Sache#define TW_CL_SWAP16_WITH_CAST(x) \ 24021308Sache ((x << 8) | (x >> 8)) 24121308Sache 24221308Sache 24321308Sache#define TW_CL_SWAP32_WITH_CAST(x) \ 24421308Sache ((x << 24) | ((x << 8) & (0xFF0000)) | \ 24521308Sache ((x >> 8) & (0xFF00)) | (x >> 24)) 24621308Sache 24721308Sache 24821308Sache#define TW_CL_SWAP64_WITH_CAST(x) \ 24921308Sache ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\ 25021308Sache ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0])))) 25121308Sache 25221308Sache 25321308Sache#else /* TW_OSL_BIG_ENDIAN */ 25421308Sache 25521308Sache#define TW_CL_SWAP16_WITH_CAST(x) x 25621308Sache#define TW_CL_SWAP32_WITH_CAST(x) x 25721308Sache#define TW_CL_SWAP64_WITH_CAST(x) x 25821308Sache 25921308Sache#endif /* TW_OSL_BIG_ENDIAN */ 26021308Sache 26121308Sache#define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x)) 26221308Sache#define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x)) 26321308Sache#define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x)) 26421308Sache 26521308Sache 26621308Sache/* Queue manipulation functions. */ 26721308Sache 26821308Sache/* Initialize a queue. */ 26921308Sache#define TW_CL_Q_INIT(head) do { \ 27021308Sache (head)->prev = (head)->next = head; \ 27121308Sache} while (0) 27221308Sache 27321308Sache 27421308Sache/* Insert an item at the head of the queue. */ 27521308Sache#define TW_CL_Q_INSERT_HEAD(head, item) do { \ 27621308Sache (item)->next = (head)->next; \ 27721308Sache (item)->prev = head; \ 27821308Sache (head)->next->prev = item; \ 27921308Sache (head)->next = item; \ 28021308Sache} while (0) 28121308Sache 28221308Sache 28321308Sache/* Insert an item at the tail of the queue. */ 28421308Sache#define TW_CL_Q_INSERT_TAIL(head, item) do { \ 28521308Sache (item)->next = head; \ 28621308Sache (item)->prev = (head)->prev; \ 28721308Sache (head)->prev->next = item; \ 28821308Sache (head)->prev = item; \ 28921308Sache} while (0) 29021308Sache 29121308Sache 29221308Sache/* Remove an item from the head of the queue. */ 29321308Sache#define TW_CL_Q_REMOVE_ITEM(head, item) do { \ 29421308Sache (item)->prev->next = (item)->next; \ 29521308Sache (item)->next->prev = (item)->prev; \ 29621308Sache} while (0) 29721308Sache 29821308Sache 29921308Sache/* Retrieve the item at the head of the queue. */ 30021308Sache#define TW_CL_Q_FIRST_ITEM(head) \ 30121308Sache (((head)->next != head) ? ((head)->next) : TW_CL_NULL) 30221308Sache 30321308Sache 30421308Sache/* Retrieve the item at the tail of the queue. */ 30521308Sache#define TW_CL_Q_LAST_ITEM(head) \ 30621308Sache (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL) 30721308Sache 30821308Sache 30921308Sache/* Retrieve the item next to a given item in the queue. */ 31021308Sache#define TW_CL_Q_NEXT_ITEM(head, item) \ 31121308Sache (((item)->next != head) ? ((item)->next) : TW_CL_NULL) 31221308Sache 31321308Sache 31421308Sache/* Retrieve the item previous to a given item in the queue. */ 31521308Sache#define TW_CL_Q_PREV_ITEM(head, item) \ 31621308Sache (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL) 31721308Sache 31821308Sache 31921308Sache/* Determine the offset of a field from the head of the structure it is in. */ 32021308Sache#define TW_CL_STRUCT_OFFSET(struct_type, field) \ 32121308Sache (TW_INT8 *)(&((struct_type *)0)->field) 32221308Sache 32321308Sache 32421308Sache/* 32521308Sache * Determine the address of the head of a structure, given the address of a 32621308Sache * field within it. 32721308Sache */ 32821308Sache#define TW_CL_STRUCT_HEAD(addr, struct_type, field) \ 32921308Sache (struct_type *)((TW_INT8 *)addr - \ 33021308Sache TW_CL_STRUCT_OFFSET(struct_type, field)) 33121308Sache 33221308Sache 33321308Sache 33421308Sache/* 33521308Sache * The following are extern declarations of OS Layer defined functions called 33621308Sache * by the Common Layer. If any function has been defined as a macro in 33721308Sache * tw_osl_share.h, we will not make the extern declaration here. 33847558Sache */ 33921308Sache 34047558Sache#ifndef tw_osl_breakpoint 34121308Sache/* Allows setting breakpoints in the CL code for debugging purposes. */ 34221308Sacheextern TW_VOID tw_osl_breakpoint(TW_VOID); 34321308Sache#endif 34421308Sache 34521308Sache 34621308Sache#ifndef tw_osl_ctlr_ready 34721308Sache/* Called on cmd interrupt. Allows re-submission of any pending requests. */ 34821308Sacheextern TW_VOID tw_osl_ctlr_ready(struct tw_cl_ctlr_handle *ctlr_handle); 34921308Sache#endif 35021308Sache 35121308Sache 35221308Sache#ifndef tw_osl_cur_func 35321308Sache/* Text name of current function. */ 35421308Sacheextern TW_INT8 *tw_osl_cur_func(TW_VOID); 35521308Sache#endif 35621308Sache 35721308Sache 35821308Sache#ifdef TW_OSL_DEBUG 35921308Sache#ifndef tw_osl_dbg_printf 36047558Sache/* Print to syslog/event log/debug console, as applicable. */ 36121308Sacheextern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle, 36247558Sache const TW_INT8 *fmt, ...); 36321308Sache#endif 36421308Sache#endif /* TW_OSL_DEBUG */ 36521308Sache 36621308Sache 36721308Sache#ifndef tw_osl_delay 36821308Sache/* Cause a delay of usecs micro-seconds. */ 36921308Sacheextern TW_VOID tw_osl_delay(TW_INT32 usecs); 37021308Sache#endif 37121308Sache 37221308Sache 37321308Sache#ifndef tw_osl_destroy_lock 37421308Sache/* Create/initialize a lock for CL's use. */ 37521308Sacheextern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle, 37621308Sache TW_LOCK_HANDLE *lock); 37721308Sache#endif 37847558Sache 37921308Sache 38047558Sache#ifndef tw_osl_free_lock 38121308Sache/* Free a previously held lock. */ 38221308Sacheextern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle, 38321308Sache TW_LOCK_HANDLE *lock); 38421308Sache#endif 38521308Sache 38647558Sache 38747558Sache#ifndef tw_osl_get_local_time 38821308Sache/* Get local time. */ 38921308Sacheextern TW_TIME tw_osl_get_local_time(TW_VOID); 39021308Sache#endif 39121308Sache 39221308Sache 39321308Sache#ifndef tw_osl_get_lock 39421308Sache/* Acquire a lock. */ 39521308Sacheextern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle, 39621308Sache TW_LOCK_HANDLE *lock); 39721308Sache#endif 39821308Sache 39921308Sache 40021308Sache#ifndef tw_osl_init_lock 40121308Sache/* Create/initialize a lock for CL's use. */ 40221308Sacheextern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle, 40347558Sache TW_INT8 *lock_name, TW_LOCK_HANDLE *lock); 40447558Sache#endif 40521308Sache 40621308Sache 40721308Sache#ifndef tw_osl_memcpy 40821308Sache/* Copy 'size' bytes from 'src' to 'dest'. */ 40921308Sacheextern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size); 41021308Sache#endif 41121308Sache 41221308Sache 41321308Sache#ifndef tw_osl_memzero 41421308Sache/* Zero 'size' bytes starting at 'addr'. */ 41521308Sacheextern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size); 41621308Sache#endif 41721308Sache 41821308Sache 41921308Sache#ifndef tw_osl_notify_event 42021308Sache/* Notify OSL of a controller/CL (or even OSL) event. */ 42121308Sacheextern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle, 42221308Sache struct tw_cl_event_packet *event); 42321308Sache#endif 42421308Sache 42521308Sache 42621308Sache#ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 42747558Sache#ifndef tw_osl_read_pci_config 42847558Sache/* Read 'size' bytes from 'offset' in the PCI config space. */ 42921308Sacheextern TW_UINT32 tw_osl_read_pci_config( 43021308Sache struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size); 43121308Sache#endif 43221308Sache#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 43321308Sache 43421308Sache 43521308Sache#ifndef tw_osl_read_reg 43621308Sache/* Read 'size' bytes at 'offset' from base address of this controller. */ 43721308Sacheextern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle, 43821308Sache TW_INT32 offset, TW_INT32 size); 43921308Sache#endif 44021308Sache 44121308Sache 44221308Sache#ifndef tw_osl_scan_bus 44321308Sache/* Request OSL for a bus scan. */ 44421308Sacheextern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle); 44521308Sache#endif 44621308Sache 44721308Sache 44821308Sache#ifdef TW_OSL_CAN_SLEEP 44921308Sache#ifndef tw_osl_sleep 45021308Sache/* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */ 45121308Sacheextern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle, 45221308Sache TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout); 45321308Sache#endif 45421308Sache#endif /* TW_OSL_CAN_SLEEP */ 45521308Sache 45621308Sache 45747558Sache#ifndef tw_osl_sprintf 45847558Sache/* Standard sprintf. */ 45921308Sacheextern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...); 46021308Sache#endif 46121308Sache 46221308Sache 46321308Sache#ifndef tw_osl_strcpy 46421308Sache/* Copy string 'src' to 'dest'. */ 46521308Sacheextern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src); 46621308Sache#endif 46721308Sache 46821308Sache 46921308Sache#ifndef tw_osl_strlen 47021308Sache/* Return length of string pointed at by 'str'. */ 47121308Sacheextern TW_INT32 tw_osl_strlen(TW_VOID *str); 47221308Sache#endif 47321308Sache 47421308Sache 47521308Sache#ifdef TW_OSL_CAN_SLEEP 47621308Sache#ifndef tw_osl_wakeup 47721308Sache/* Wake up a thread sleeping by a call to tw_osl_sleep. */ 47821308Sacheextern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle, 47921308Sache TW_SLEEP_HANDLE *sleep_handle); 48021308Sache#endif 48121308Sache#endif /* TW_OSL_CAN_SLEEP */ 48221308Sache 48347558Sache 48447558Sache#ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE 48521308Sache#ifndef tw_osl_write_pci_config 48621308Sache/* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */ 48721308Sacheextern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle, 48821308Sache TW_INT32 offset, TW_INT32 value, TW_INT32 size); 48921308Sache#endif 49021308Sache#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */ 49121308Sache 49221308Sache 49321308Sache#ifndef tw_osl_write_reg 49421308Sache/* 49521308Sache * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of 49621308Sache * this controller. 49721308Sache */ 49821308Sacheextern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle, 49921308Sache TW_INT32 offset, TW_INT32 value, TW_INT32 size); 50021308Sache#endif 50121308Sache 50221308Sache 50321308Sache 50421308Sache/* Functions in the Common Layer */ 50521308Sache 50621308Sache/* Creates and queues AEN's. Also notifies OS Layer. */ 50721308Sacheextern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle, 50821308Sache TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code, 50921308Sache TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc, 51021308Sache TW_UINT8 *event_specific_desc, ...); 51121308Sache 51221308Sache/* Indicates whether a ctlr is supported by CL. */ 51321308Sacheextern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id); 51421308Sache 51521308Sache 51621308Sache/* Deferred interrupt handler. */ 51721308Sacheextern TW_VOID tw_cl_deferred_interrupt(struct tw_cl_ctlr_handle *ctlr_handle); 51821308Sache 51921308Sache 52021308Sache/* Submit a firmware cmd packet. */ 52121308Sacheextern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle, 52247558Sache struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 52347558Sache 52421308Sache 52521308Sache/* Find out how much memory CL needs. */ 52621308Sacheextern TW_INT32 tw_cl_get_mem_requirements( 52721308Sache struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags, 52821308Sache TW_INT32 max_simult_reqs, TW_INT32 max_aens, 52921308Sache TW_UINT32 *alignment, TW_UINT32 *sg_size_factor, 53021308Sache TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size 53121308Sache#ifdef TW_OSL_FLASH_FIRMWARE 53221308Sache , TW_UINT32 *flash_dma_mem_size 53321308Sache#endif /* TW_OSL_FLASH_FIRMWARE */ 53421308Sache#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST 53521308Sache , TW_UINT32 *per_req_dma_mem_size 53621308Sache#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */ 53721308Sache#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 53821308Sache , TW_UINT32 *per_req_non_dma_mem_size 53921308Sache#endif /* TW_OSL_N0N_DMA_MEM_ALLOC_PER_REQUEST */ 54021308Sache ); 54121308Sache 54221308Sache 54321308Sache/* Initialize Common Layer for a given controller. */ 54421308Sacheextern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 54521308Sache TW_UINT32 flags, TW_INT32 max_simult_reqs, TW_INT32 max_aens, 54621308Sache TW_VOID *non_dma_mem, TW_VOID *dma_mem, TW_UINT64 dma_mem_phys 54721308Sache#ifdef TW_OSL_FLASH_FIRMWARE 54821308Sache , TW_VOID *flash_dma_mem, TW_UINT64 flash_dma_mem_phys 54921308Sache#endif /* TW_OSL_FLASH_FIRMWARE */ 55021308Sache ); 55121308Sache 55221308Sache 55321308Sache/* CL's interrupt handler. */ 55421308Sacheextern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle); 55521308Sache 55621308Sache 55721308Sache/* CL's ioctl handler. */ 55821308Sacheextern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle, 55921308Sache TW_INT32 cmd, TW_VOID *buf); 56021308Sache 56121308Sache 56221308Sache#ifdef TW_OSL_DEBUG 56321308Sache/* Print CL's state/statistics for a controller. */ 56421308Sacheextern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle); 56521308Sache 56621308Sache/* Prints CL internal details of a given request. */ 56721308Sacheextern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle); 56821308Sache#endif /* TW_OSL_DEBUG */ 56921308Sache 57021308Sache 57121308Sache/* Soft reset controller. */ 57221308Sacheextern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle); 57321308Sache 57421308Sache 57521308Sache#ifdef TW_OSL_DEBUG 57621308Sache/* Reset CL's statistics for a controller. */ 57721308Sacheextern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle); 57821308Sache#endif /* TW_OSL_DEBUG */ 57921308Sache 58021308Sache 58121308Sache/* Stop a controller. */ 58221308Sacheextern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, 58321308Sache TW_UINT32 flags); 58421308Sache 58521308Sache 58621308Sache/* Submit a SCSI I/O request. */ 58721308Sacheextern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle, 58821308Sache struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle); 58921308Sache 59021308Sache 59121308Sache#endif /* TW_CL_SHARE_H */ 59221308Sache