trm.h revision 126725
1/* 2 * File Name : trm.h 3 * 4 * Tekram DC395U/UW/F ,DC315/U 5 * PCI SCSI Bus Master Host Adapter Device Driver 6 * (SCSI chip set used Tekram ASIC TRM-S1040) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/trm/trm.h 126725 2004-03-07 17:23:39Z cognet $ 31 */ 32 33#ifndef trm_H 34#define trm_H 35 36/* SCSI CAM */ 37 38#define TRM_TRANS_CUR 0x01 /* Modify current neogtiation status */ 39#define TRM_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 40#define TRM_TRANS_GOAL 0x04 /* Modify negotiation goal */ 41#define TRM_TRANS_USER 0x08 /* Modify user negotiation settings */ 42 43struct trm_transinfo { 44 u_int8_t width; 45 u_int8_t period; 46 u_int8_t offset; 47}; 48 49struct trm_target_info { 50 u_int8_t disc_tag; /* bits define..... */ 51#define TRM_CUR_DISCENB 0x01 /* current setting disconnect enable */ 52#define TRM_CUR_TAGENB 0x02 /* current setting tag command Q enable */ 53#define TRM_USR_DISCENB 0x04 /* user adapter device setting disconnect enable */ 54#define TRM_USR_TAGENB 0x08 /* user adapter device setting tag command Q enable*/ 55 struct trm_transinfo current; /* info of current */ 56 struct trm_transinfo goal; /* info of after negotiating */ 57 struct trm_transinfo user; /* info of user adapter device setting */ 58}; 59/* 60 * SCSI CAM ** 61 */ 62 63/* 64 * bus_dma_segment_t 65 * 66 * Describes a single contiguous DMA transaction. Values 67 * are suitable for programming into DMA registers. 68 * 69 *typedef struct bus_dma_segment 70 *{ 71 * bus_addr_t ds_addr; // DMA address 72 * bus_size_t ds_len; // length of transfer 73 *} bus_dma_segment_t; 74 */ 75 76/*;----------------------Segment Entry------------------------------------*/ 77typedef struct _SGentry { 78 u_int32_t address; 79 u_int32_t length; 80} SGentry, *PSEG; 81/* 82 *----------------------------------------------------------------------- 83 * feature of chip set MAX value 84 *----------------------------------------------------------------------- 85 */ 86 87#define TRM_MAX_ADAPTER_NUM 4 88#define TRM_MAX_DEVICES 16 89#define TRM_MAX_SG_LISTENTRY 32 90#define TRM_MAX_TARGETS 16 91#define TRM_MAX_TAGS_CMD_QUEUE 256 /* MAX_CMD_QUEUE 20*/ 92#define TRM_MAX_CMD_PER_LUN 32 93#define TRM_MAX_SRB_CNT 256 94#define TRM_MAX_START_JOB 256 95#define TRM_NSEG (btoc(MAXPHYS) + 1) 96#define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */ 97#define PAGELEN 4096 98 99#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40MHz) */ 100 101/* 102 * CAM ccb 103 * Union of all CCB types for kernel space allocation. This union should 104 * never be used for manipulating CCBs - its only use is for the allocation 105 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 106 * and the argument to xpt_ccb_free. 107 * 108 *union ccb { 109 * struct ccb_hdr ccb_h; // For convenience 110 * struct ccb_scsiio csio; 111 * struct ccb_getdev cgd; 112 * struct ccb_getdevlist cgdl; 113 * struct ccb_pathinq cpi; 114 * struct ccb_relsim crs; 115 * struct ccb_setasync csa; 116 * struct ccb_setdev csd; 117 * struct ccb_dev_match cdm; 118 * struct ccb_trans_settings cts; 119 * struct ccb_calc_geometry ccg; 120 * struct ccb_abort cab; 121 * struct ccb_resetbus crb; 122 * struct ccb_resetdev crd; 123 * struct ccb_termio tio; 124 * struct ccb_accept_tio atio; 125 * struct ccb_scsiio ctio; 126 * struct ccb_en_lun cel; 127 * struct ccb_immed_notify cin; 128 * struct ccb_notify_ack cna; 129 * struct ccb_eng_inq cei; 130 * struct ccb_eng_exec cee; 131 * struct ccb_rescan crcn; 132 * struct ccb_debug cdbg; 133 * }; 134 */ 135 136/* 137 *----------------------------------------------------------------------- 138 * SCSI Request Block 139 *----------------------------------------------------------------------- 140 */ 141struct _SRB { 142 u_int8_t CmdBlock[12]; 143 u_long Segment0[2]; 144 u_long Segment1[2]; 145 struct _SRB *pNextSRB; 146 struct _DCB *pSRBDCB; 147 SGentry SgSenseTemp; 148 149 PSEG pSRBSGL; /* scatter gather list */ 150 151 u_int32_t SRBSGPhyAddr; /* a segment starting address */ 152 u_int32_t SRBTotalXferLength; 153 154 /* 155 * CAM ccb 156 */ 157 union ccb *pccb; 158 bus_dmamap_t sg_dmamap; 159 bus_dmamap_t dmamap; 160 u_int16_t SRBState; 161 u_int8_t * pMsgPtr; 162 163 u_int8_t SRBSGCount; 164 u_int8_t SRBSGIndex; 165 u_int8_t MsgInBuf[6]; 166 u_int8_t MsgOutBuf[6]; 167 168 u_int8_t AdaptStatus; 169 u_int8_t TargetStatus; 170 u_int8_t MsgCnt; 171 u_int8_t TagNumber; 172 173 u_int8_t SRBStatus; 174 u_int8_t RetryCnt; 175 u_int8_t SRBFlag; 176 u_int8_t ScsiCmdLen; 177 u_int8_t ScsiPhase; 178 u_int8_t Reserved[3]; /*;for dword alignment */ 179}; 180typedef struct _SRB TRM_SRB, *PSRB; 181 182/* 183 *----------------------------------------------------------------------- 184 * Device Control Block 185 *----------------------------------------------------------------------- 186 */ 187struct _DCB 188{ 189 PSRB pWaitingSRB; 190 PSRB pWaitingLastSRB; 191 192 PSRB pGoingSRB; 193 PSRB pGoingLastSRB; 194 195 PSRB pActiveSRB; 196 197 u_int16_t GoingSRBCnt; 198 u_int16_t MaxActiveCommandCnt; 199 200 u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */ 201 u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 202 u_int8_t DCBFlag; 203 u_int8_t DevType; 204 205 u_int8_t SyncMode; /* mode ? (1 sync):(0 async) */ 206 u_int8_t MaxNegoPeriod; /* for nego. */ 207 u_int8_t SyncPeriod; /* for reg. */ 208 u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */ 209 210 u_int8_t DevMode; 211 u_int8_t AdpMode; 212 213 u_int8_t IdentifyMsg; 214 u_int8_t DCBstatus; /* DCB status */ 215 /*u_int8_t Reserved[3]; for dword alignment */ 216 struct trm_target_info tinfo; /* 10 bytes */ 217 struct _DCB *pNextDCB; 218}; 219typedef struct _DCB TRM_DCB, *PDCB; 220 221/* 222 *----------------------------------------------------------------------- 223 * Adapter Control Block 224 *----------------------------------------------------------------------- 225 */ 226struct _ACB 227{ 228 device_t dev; 229 230 bus_space_tag_t tag; 231 bus_space_handle_t bsh; 232 bus_dma_tag_t parent_dmat; 233 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 234 bus_dma_tag_t srb_dmat; 235 bus_dma_tag_t sense_dmat; /* dmat for sense buffer */ 236 bus_dma_tag_t sg_dmat; 237 bus_dmamap_t sense_dmamap; 238 bus_dmamap_t srb_dmamap; 239 bus_addr_t sense_busaddr; 240 struct scsi_sense_data *sense_buffers; 241 struct resource *iores, *irq; 242 void *ih; 243 /* 244 * CAM SIM/XPT 245 */ 246 struct cam_sim *psim; 247 struct cam_path *ppath; 248 249 TRM_SRB TmpSRB; 250 TRM_DCB DCBarray[16][8]; 251 252 u_int32_t srb_physbase; 253 254 PSRB pFreeSRB; 255 PDCB pActiveDCB; 256 257 PDCB pLinkDCB; 258 PDCB pDCBRunRobin; 259 260 u_int16_t max_id; 261 u_int16_t max_lun; 262 263 u_int8_t msgin123[4]; 264 265 u_int8_t scan_devices[16][8]; 266 267 u_int8_t AdaptSCSIID; /*; Adapter SCSI Target ID */ 268 u_int8_t AdaptSCSILUN; /*; Adapter SCSI LUN */ 269 u_int8_t DeviceCnt; 270 u_int8_t ACBFlag; 271 272 u_int8_t TagMaxNum; 273 u_int8_t Config; 274 u_int8_t AdaptType; 275 u_int8_t AdapterUnit; /* nth Adapter this driver */ 276}; 277typedef struct _ACB TRM_ACB, *PACB; 278/* 279 * ----SRB State machine definition 280 */ 281#define SRB_FREE 0x0000 282#define SRB_WAIT 0x0001 283#define SRB_READY 0x0002 284#define SRB_MSGOUT 0x0004 /*arbitration+msg_out 1st byte*/ 285#define SRB_MSGIN 0x0008 286#define SRB_EXTEND_MSGIN 0x0010 287#define SRB_COMMAND 0x0020 288#define SRB_START_ 0x0040 /*arbitration+msg_out+command_out*/ 289#define SRB_DISCONNECT 0x0080 290#define SRB_DATA_XFER 0x0100 291#define SRB_XFERPAD 0x0200 292#define SRB_STATUS 0x0400 293#define SRB_COMPLETED 0x0800 294#define SRB_ABORT_SENT 0x1000 295#define SRB_DO_SYNC_NEGO 0x2000 296#define SRB_DO_WIDE_NEGO 0x4000 297#define SRB_UNEXPECT_RESEL 0x8000 298/* 299 * 300 * ACB Config 301 * 302 */ 303#define HCC_WIDE_CARD 0x20 304#define HCC_SCSI_RESET 0x10 305#define HCC_PARITY 0x08 306#define HCC_AUTOTERM 0x04 307#define HCC_LOW8TERM 0x02 308#define HCC_UP8TERM 0x01 309/* 310 * ---ACB Flag 311 */ 312#define RESET_DEV 0x00000001 313#define RESET_DETECT 0x00000002 314#define RESET_DONE 0x00000004 315 316/* 317 * ---DCB Flag 318 */ 319#define ABORT_DEV_ 0x00000001 320 321/* 322 * ---DCB status 323 */ 324#define DS_IN_QUEUE 0x00000001 325 326/* 327 * ---SRB status 328 */ 329#define SRB_OK 0x00000001 330#define ABORTION 0x00000002 331#define OVER_RUN 0x00000004 332#define UNDER_RUN 0x00000008 333#define PARITY_ERROR 0x00000010 334#define SRB_ERROR 0x00000020 335 336/* 337 * ---SRB Flag 338 */ 339#define DATAOUT 0x00000080 340#define DATAIN 0x00000040 341#define RESIDUAL_VALID 0x00000020 342#define ENABLE_TIMER 0x00000010 343#define RESET_DEV0 0x00000004 344#define ABORT_DEV 0x00000002 345#define AUTO_REQSENSE 0x00000001 346 347/* 348 * ---Adapter status 349 */ 350#define H_STATUS_GOOD 0x00 351#define H_SEL_TIMEOUT 0x11 352#define H_OVER_UNDER_RUN 0x12 353#define H_UNEXP_BUS_FREE 0x13 354#define H_TARGET_PHASE_F 0x14 355#define H_INVALID_CCB_OP 0x16 356#define H_LINK_CCB_BAD 0x17 357#define H_BAD_TARGET_DIR 0x18 358#define H_DUPLICATE_CCB 0x19 359#define H_BAD_CCB_OR_SG 0x1A 360#define H_ABORT 0x0FF 361 362/* 363 * ---SCSI Status byte codes 364 */ 365#define SCSI_STAT_GOOD 0x00 /*; Good status */ 366#define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */ 367#define SCSI_STAT_CONDMET 0x04 /*; Condition Met */ 368#define SCSI_STAT_BUSY 0x08 /*; Target busy status */ 369#define SCSI_STAT_INTER 0x10 /*; Intermediate status */ 370#define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */ 371#define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */ 372#define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */ 373#define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */ 374#define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 375#define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 376#define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 377 378/* 379 * ---Sync_Mode 380 */ 381#define SYNC_WIDE_TAG_ATNT_DISABLE 0x00000000 382#define SYNC_NEGO_ENABLE 0x00000001 383#define SYNC_NEGO_DONE 0x00000002 384#define WIDE_NEGO_ENABLE 0x00000004 385#define WIDE_NEGO_DONE 0x00000008 386#define EN_TAG_QUEUING 0x00000010 387#define EN_ATN_STOP 0x00000020 388 389#define SYNC_NEGO_OFFSET 15 390/* 391 * ---SCSI bus phase 392 */ 393#define SCSI_DATA_OUT_ 0 394#define SCSI_DATA_IN_ 1 395#define SCSI_COMMAND 2 396#define SCSI_STATUS_ 3 397#define SCSI_NOP0 4 398#define SCSI_NOP1 5 399#define SCSI_MSG_OUT 6 400#define SCSI_MSG_IN 7 401 402/* 403 * ----SCSI MSG u_int8_t 404 */ 405#define MSG_COMPLETE 0x00 406#define MSG_EXTENDED 0x01 407#define MSG_SAVE_PTR 0x02 408#define MSG_RESTORE_PTR 0x03 409#define MSG_DISCONNECT 0x04 410#define MSG_INITIATOR_ERROR 0x05 411#define MSG_ABORT 0x06 412#define MSG_REJECT_ 0x07 413#define MSG_NOP 0x08 414#define MSG_PARITY_ERROR 0x09 415#define MSG_LINK_CMD_COMPL 0x0A 416#define MSG_LINK_CMD_COMPL_FLG 0x0B 417#define MSG_BUS_RESET 0x0C 418/* #define MSG_ABORT_TAG 0x0D */ 419#define MSG_SIMPLE_QTAG 0x20 420#define MSG_HEAD_QTAG 0x21 421#define MSG_ORDER_QTAG 0x22 422#define MSG_IGNOREWIDE 0x23 423/* #define MSG_IDENTIFY 0x80 */ 424#define MSG_HOST_ID 0xC0 425/* bus wide length */ 426#define MSG_EXT_WDTR_BUS_8_BIT 0x00 427#define MSG_EXT_WDTR_BUS_16_BIT 0x01 428#define MSG_EXT_WDTR_BUS_32_BIT 0x02 429/* 430 * ----SCSI STATUS u_int8_t 431 */ 432#define STATUS_GOOD 0x00 433#define CHECK_CONDITION_ 0x02 434#define STATUS_BUSY 0x08 435#define STATUS_INTERMEDIATE 0x10 436#define RESERVE_CONFLICT 0x18 437 438/* 439 * ---- cmd->result 440 */ 441#define STATUS_MASK_ 0xFF 442#define MSG_MASK 0xFF00 443#define RETURN_MASK 0xFF0000 444 445/* 446 * Inquiry Data format 447 */ 448 449typedef struct _SCSIInqData { /* INQ */ 450 451 u_int8_t DevType; /* Periph Qualifier & Periph Dev Type */ 452 u_int8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 453 u_int8_t Vers; /* ISO, ECMA, & ANSI versions */ 454 u_int8_t RDF; /* AEN, TRMIOP, & response data format*/ 455 u_int8_t AddLen; /* length of additional data */ 456 u_int8_t Res1; /* reserved */ 457 u_int8_t Res2; /* reserved */ 458 u_int8_t Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ 459 u_int8_t VendorID[8]; /* Vendor Identification */ 460 u_int8_t ProductID[16]; /* Product Identification */ 461 u_int8_t ProductRev[4]; /* Product Revision */ 462} SCSI_INQDATA, *PSCSI_INQDATA; 463 464 465/* 466 * Inquiry byte 0 masks 467 */ 468#define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ 469#define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ 470/* 471 * Inquiry byte 1 mask 472 */ 473#define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ 474/* 475 * Peripheral Device Type definitions 476 */ 477#define SCSI_DASD 0x00 /* Direct-access Device */ 478#define SCSI_SEQACESS 0x01 /* Sequential-access device */ 479#define SCSI_PRINTER 0x02 /* Printer device */ 480#define SCSI_PROCESSOR 0x03 /* Processor device */ 481#define SCSI_WRITEONCE 0x04 /* Write-once device */ 482#define SCSI_CDROM 0x05 /* CD-ROM device */ 483#define SCSI_SCANNER 0x06 /* Scanner device */ 484#define SCSI_OPTICAL 0x07 /* Optical memory device */ 485#define SCSI_MEDCHGR 0x08 /* Medium changer device */ 486#define SCSI_COMM 0x09 /* Communications device */ 487#define SCSI_NODEV 0x1F /* Unknown or no device type */ 488/* 489 * Inquiry flag definitions (Inq data byte 7) 490 */ 491#define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ 492#define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ 493#define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ 494#define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ 495#define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ 496#define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ 497#define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ 498/* 499 *========================================================== 500 * EEPROM byte offset 501 *========================================================== 502 */ 503typedef struct _EEprom { 504 u_int8_t EE_MODE1; 505 u_int8_t EE_SPEED; 506 u_int8_t xx1; 507 u_int8_t xx2; 508} EEprom, *PEEprom; 509 510#define EE_ADAPT_SCSI_ID 64 511#define EE_MODE2 65 512#define EE_DELAY 66 513#define EE_TAG_CMD_NUM 67 514 515/* 516 * EE_MODE1 bits definition 517 */ 518#define PARITY_CHK_ 0x00000001 519#define SYNC_NEGO_ 0x00000002 520#define EN_DISCONNECT_ 0x00000004 521#define SEND_START_ 0x00000008 522#define TAG_QUEUING_ 0x00000010 523 524/* 525 * EE_MODE2 bits definition 526 */ 527#define MORE2_DRV 0x00000001 528#define GREATER_1G 0x00000002 529#define RST_SCSI_BUS 0x00000004 530#define ACTIVE_NEGATION 0x00000008 531#define NO_SEEK 0x00000010 532#define LUN_CHECK 0x00000020 533 534#define ENABLE_CE 0x01 535#define DISABLE_CE 0x00 536#define EEPROM_READ 0x80 537 538/* 539 * The PCI configuration register offset for TRM_S1040 540 * Registers bit Definition 541 */ 542#define TRMREG_ID 0x00 /* Vendor and Device ID */ 543#define TRMREG_COMMAND 0x04 /* PCI command register */ 544#define TRMREG_IOBASE 0x10 /* I/O Space base address */ 545#define TRMREG_ROMBASE 0x30 /* Expansion ROM Base Address */ 546#define TRMREG_INTLINE 0x3C /* Interrupt line */ 547 548/* 549 * 550 * The SCSI register offset for TRM_S1040 551 * 552 */ 553#define TRMREG_SCSI_STATUS 0x80 /* SCSI Status (R) */ 554/* ######### */ 555#define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 556#define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */ 557#define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero*/ 558#define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 559#define COMMANDABORT 0x0040 /* SCSI command abort */ 560#define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 561#define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 562#define PARITYERROR 0x0008 /* SCSI parity error */ 563 564#define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 565#define PH_DATA_OUT 0x00 /* Data out phase */ 566#define PH_DATA_IN 0x01 /* Data in phase */ 567#define PH_COMMAND 0x02 /* Command phase */ 568#define PH_STATUS 0x03 /* Status phase */ 569#define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */ 570#define PH_MSG_OUT 0x06 /* Message out phase */ 571#define PH_MSG_IN 0x07 /* Message in phase */ 572 573#define TRMREG_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 574/* ######### */ 575#define DO_CLRATN 0x0400 /* Clear ATN */ 576#define DO_SETATN 0x0200 /* Set ATN */ 577#define DO_CMDABORT 0x0100 /* Abort SCSI command */ 578#define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 579#define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 580#define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 581#define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 582#define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 583#define TRMREG_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 584#define TRMREG_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 585#define TRMREG_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 586/* ######### */ 587#define INT_SCAM 0x80 /* SCAM selection interrupt */ 588#define INT_SELECT 0x40 /* Selection interrupt */ 589#define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 590#define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 591#define INT_RESELECTED 0x08 /* Reselected interrupt */ 592#define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt*/ 593#define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 594#define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 595#define TRMREG_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 596/* 597 * Bit Name Definition 598 * 07-05 0 RSVD Reversed. Always 0. 599 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 600 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 601 */ 602#define TRMREG_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W)*/ 603/* ######### */ 604#define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ 605#define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ 606#define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ 607/* 608 * SYNCM 7 6 5 4 3 2 1 0 609 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 610 * Default 0 0 0 0 0 0 0 0 611 * 612 * 613 * Bit Name Definition 614 * 07-06 0 RSVD Reversed. Always read 0 615 * 05 0 LVDS Reversed. Always read 0 616 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 617 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 618 * 619 * @@ When this bit is set, 620 * the synchronous period bits 2:0 621 * in the Synchronous Mode register 622 * are used to transfer data 623 * at the Fast-20 rate. 624 * @@ When this bit is reset, 625 * the synchronous period bits 2:0 626 * in the Synchronous Mode Register 627 * are used to transfer data 628 * at the Fast-40 rate. 629 * 630 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 631 * These 3 bits specify 632 * the Synchronous SCSI Transfer Rate 633 * for Fast-20 and Fast-10. 634 * These bits are also reset 635 * by a SCSI Bus reset. 636 * 637 * For Fast-10 bit ALTPD = 0 and LVDS = 0 638 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 639 * 640 * 000 100ns, 10.0 Mbytes/s 641 * 001 150ns, 6.6 Mbytes/s 642 * 010 200ns, 5.0 Mbytes/s 643 * 011 250ns, 4.0 Mbytes/s 644 * 100 300ns, 3.3 Mbytes/s 645 * 101 350ns, 2.8 Mbytes/s 646 * 110 400ns, 2.5 Mbytes/s 647 * 111 450ns, 2.2 Mbytes/s 648 * 649 * For Fast-20 bit ALTPD = 1 and LVDS = 0 650 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 651 * 652 * 000 50ns, 20.0 Mbytes/s 653 * 001 75ns, 13.3 Mbytes/s 654 * 010 100ns, 10.0 Mbytes/s 655 * 011 125ns, 8.0 Mbytes/s 656 * 100 150ns, 6.6 Mbytes/s 657 * 101 175ns, 5.7 Mbytes/s 658 * 110 200ns, 5.0 Mbytes/s 659 * 111 250ns, 4.0 Mbytes/s 660 * 661 * For Fast-40 bit ALTPD = 0 and LVDS = 1 662 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 663 * 664 * 000 25ns, 40.0 Mbytes/s 665 * 001 50ns, 20.0 Mbytes/s 666 * 010 75ns, 13.3 Mbytes/s 667 * 011 100ns, 10.0 Mbytes/s 668 * 100 125ns, 8.0 Mbytes/s 669 * 101 150ns, 6.6 Mbytes/s 670 * 110 175ns, 5.7 Mbytes/s 671 * 111 200ns, 5.0 Mbytes/s 672 */ 673 674/* 675 *************************************** 676 */ 677#define TRMREG_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 678/* 679 *************************************** 680 */ 681#define TRMREG_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 682/* 683 *************************************** 684 */ 685#define TRMREG_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 686/* 687 *************************************** 688 */ 689#define TRMREG_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W)*/ 690/* 691 *************************************** 692 */ 693#define TRMREG_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 694/* ######### */ 695#define EN_SCAM 0x80 /* Enable SCAM selection interrupt*/ 696#define EN_SELECT 0x40 /* Enable selection interrupt */ 697#define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt*/ 698#define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt*/ 699#define EN_RESELECTED 0x08 /* Enable reselected interrupt */ 700#define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/ 701#define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ 702#define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt*/ 703/* 704 *************************************** 705 */ 706#define TRMREG_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 707/* ######### */ 708#define PHASELATCH 0x40 /* Enable phase latch */ 709#define INITIATOR 0x20 /* Enable initiator mode */ 710#define PARITYCHECK 0x10 /* Enable parity check */ 711#define BLOCKRST 0x01 /* Disable SCSI reset1 */ 712/* 713 *************************************** 714 */ 715#define TRMREG_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 716/* ######### */ 717#define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 718#define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 719#define ACTIVE_NEG 0x02 /* Enable active negation */ 720#define ACTIVE_HISLEW 0x01 /* Enable high slew rate (3/6 ns) */ 721/* 722 *************************************** 723 */ 724#define TRMREG_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ 725/* 726 *************************************** 727 */ 728#define TRMREG_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 729/* ######### */ 730#define SCMD_COMP 0x12 /* Command complete */ 731#define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 732#define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 733#define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 734#define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 735#define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 736#define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 737#define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 738#define SCMD_MSGACCEPT 0xD8 /* Message accept */ 739/* 740 * Code Command Description 741 * 742 * 02 Enable reselection with FIFO 743 * 40 Select without ATN with FIFO 744 * 60 Select with ATN with FIFO 745 * 64 Select with ATN3 with FIFO 746 * A0 Select with ATN and stop with FIFO 747 * C0 Transfer information out with FIFO 748 * C1 Transfer information out with DMA 749 * C2 Transfer information in with FIFO 750 * C3 Transfer information in with DMA 751 * 12 Initiator command complete with FIFO 752 * 50 Initiator transfer information out sequence without ATN with FIFO 753 * 70 Initiator transfer information out sequence with ATN with FIFO 754 * 74 Initiator transfer information out sequence with ATN3 with FIFO 755 * 52 Initiator transfer information in sequence without ATN with FIFO 756 * 72 Initiator transfer information in sequence with ATN with FIFO 757 * 76 Initiator transfer information in sequence with ATN3 with FIFO 758 * 90 Initiator transfer information out command complete with FIFO 759 * 92 Initiator transfer information in command complete with FIFO 760 * D2 Enable selection 761 * 08 Reselection 762 * 48 Disconnect command with FIFO 763 * 88 Terminate command with FIFO 764 * C8 Target command complete with FIFO 765 * 18 SCAM Arbitration/ Selection 766 * 5A Enable reselection 767 * 98 Select without ATN with FIFO 768 * B8 Select with ATN with FIFO 769 * D8 Message Accepted 770 * 58 NOP 771 */ 772/* 773 *************************************** 774 */ 775#define TRMREG_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 776/* 777 *************************************** 778 */ 779#define TRMREG_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 780/* 781 *************************************** 782 */ 783#define TRMREG_SCSI_TCR00 0x9C /* SCSI Target Control 0 (R/W) */ 784/* ######### */ 785#define TCR0_DO_WIDE_NEGO 0x80 /* Do wide NEGO */ 786#define TCR0_DO_SYNC_NEGO 0x40 /* Do sync NEGO */ 787#define TCR0_DISCONNECT_EN 0x20 /* Disconnection enable */ 788#define TCR0_OFFSET_MASK 0x1F /* Offset number */ 789/* 790 *************************************** 791 */ 792#define TRMREG_SCSI_TCR01 0x9D /* SCSI Target Control 0 (R/W) */ 793/* ######### */ 794#define TCR0_ENABLE_LVDS 0xF8 /* LVD */ 795#define TCR0_ENABLE_WIDE 0xF9 /* SE */ 796/* 797**************************************** 798*/ 799 800/* 801 *************************************** 802 */ 803#define TRMREG_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 804/* ######### */ 805#define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 806#define NON_TAG_BUSY 0x0080 /* Non tag command active */ 807#define ACTTAG_MASK 0x007F /* Active tags */ 808/* 809 * 810 * The DMA register offset for TRM_S1040 811 * 812 */ 813#define TRMREG_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 814/* ######### */ 815#define XFERDATAIN 0x0103 /* Transfer data in */ 816#define XFERDATAOUT 0x0102 /* Transfer data out */ 817/* 818 *************************************** 819 */ 820#define TRMREG_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 821/* 822 *************************************** 823 */ 824#define TRMREG_DMA_CONTROL 0xA1 /* DMA Control (W) */ 825/* ######### */ 826#define STOPDMAXFER 0x08 /* Stop DMA transfer */ 827#define ABORTXFER 0x04 /* Abort DMA transfer */ 828#define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 829#define STARTDMAXFER 0x01 /* Start DMA transfer */ 830/* 831 *************************************** 832 */ 833#define TRMREG_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 834/* ######### */ 835#define XFERPENDING 0x80 /* Transfer pending */ 836#define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 837#define SCSICOMP 0x01 /* SCSI complete interrupt */ 838/* 839 *************************************** 840 */ 841#define TRMREG_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W)*/ 842/* ######### */ 843#define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 844/* 845 *************************************** 846 */ 847#define TRMREG_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 848/* ######### */ 849#define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 850/* 851 *************************************** 852 */ 853#define TRMREG_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W)*/ 854/* 855 *************************************** 856 */ 857#define TRMREG_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 858/* 859 *************************************** 860 */ 861#define TRMREG_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ 862/* 863 *************************************** 864 */ 865#define TRMREG_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ 866 867/* 868 * 869 * The general register offset for TRM_S1040 870 * 871 */ 872#define TRMREG_GEN_CONTROL 0xD4 /* Global Control */ 873/* ######### */ 874#define EN_EEPROM 0x10 /* Enable EEPROM programming */ 875#define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 876#define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 877#define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 878/* 879 *************************************** 880 */ 881#define TRMREG_GEN_STATUS 0xD5 /* Global Status */ 882/* ######### */ 883#define GTIMEOUT 0x80 /* Global timer reach 0 */ 884#define CON5068 0x10 /* External 50/68 pin connected */ 885#define CON68 0x08 /* Internal 68 pin connected */ 886#define CON50 0x04 /* Internal 50 pin connected */ 887#define WIDESCSI 0x02 /* Wide SCSI card */ 888/* 889 *************************************** 890 */ 891#define TRMREG_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ 892/* ######### */ 893#define NVR_BITOUT 0x08 /* Serial data out */ 894#define NVR_BITIN 0x04 /* Serial data in */ 895#define NVR_CLOCK 0x02 /* Serial clock */ 896#define NVR_SELECT 0x01 /* Serial select */ 897/* 898 *************************************** 899 */ 900#define TRMREG_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ 901/* 902 *************************************** 903 */ 904#define TRMREG_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ 905/* 906 *************************************** 907 */ 908#define TRMREG_GEN_TIMER 0xDB /* Global timer */ 909 910/* 911 * The SEEPROM structure for TRM_S1040 912 */ 913typedef struct NVRAM_TARGET_STRUCT 914{ 915 u_int8_t NvmTarCfg0; /* Target configuration byte 0 */ 916 u_int8_t NvmTarPeriod; /* Target period */ 917 u_int8_t NvmTarCfg2; /* Target configuration byte 2 */ 918 u_int8_t NvmTarCfg3; /* Target configuration byte 3 */ 919} NVRAMTARGETTYPE; 920/* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */ 921#define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 922#define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 923#define NTC_DO_SEND_START 0x08 /* Send start command SPINUP*/ 924#define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 925#define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 926#define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC ) 927 Parity check enable */ 928 929/* 930 * 931 * 932 * 933 */ 934typedef struct NVRAM_STRUC { 935 u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */ 936 u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID*/ 937 u_int8_t NvramSubClass; /*4 Sub Class */ 938 u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */ 939 u_int8_t NvramDeviceID[2]; /*7,8 Device ID */ 940 u_int8_t NvramReserved; /*9 Reserved */ 941 NVRAMTARGETTYPE NvramTarget[TRM_MAX_TARGETS];/* *10,11,12,13 942 *14,15,16,17 * .... 943 * .... 944 *70,71,72,73 945 */ 946 u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */ 947 u_int8_t NvramChannelCfg; /*75 Channel configuration */ 948 u_int8_t NvramDelayTime; /*76 Power on delay time */ 949 u_int8_t NvramMaxTag; /*77 Maximum tags */ 950 u_int8_t NvramReserved0; /*78 */ 951 u_int8_t NvramBootTarget; /*79 */ 952 u_int8_t NvramBootLun; /*80 */ 953 u_int8_t NvramReserved1; /*81 */ 954 u_int16_t Reserved[22]; /*82,..125 */ 955 u_int16_t NvramCheckSum; /*126,127*/ 956} NVRAMTYPE,*PNVRAMTYPE; 957/* Nvram Initiater bits definition */ 958#define MORE2_DRV 0x00000001 959#define GREATER_1G 0x00000002 960#define RST_SCSI_BUS 0x00000004 961#define ACTIVE_NEGATION 0x00000008 962#define NO_SEEK 0x00000010 963#define LUN_CHECK 0x00000020 964 965/* Nvram Adapter NvramChannelCfg bits definition */ 966#define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/ 967#define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 968#define NAC_GREATER_1G 0x02 /* > 1G support enable */ 969#define NAC_GT2DRIVES 0x01 /* Support more than 2 drives*/ 970/* 971 *#define NAC_DO_PARITY_CHK 0x08 // Parity check enable 972 */ 973 974#endif /* trm_H */ 975