trm.c revision 165102
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 */ 12 13#include <sys/cdefs.h> 14__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 165102 2006-12-11 18:28:31Z mjacob $"); 15 16/* 17 * HISTORY: 18 * 19 * REV# DATE NAME DESCRIPTION 20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 27 */ 28 29/*- 30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. The name of the author may not be used to endorse or promote products 41 * derived from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 */ 55 56/* 57 * Imported into FreeBSD source repository, and updated to compile under 58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 59 */ 60 61/* 62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 63 * <doginou@ci0.org>, 2002-03-04 64 */ 65 66#include <sys/param.h> 67 68#include <sys/systm.h> 69#include <sys/malloc.h> 70#include <sys/queue.h> 71#if __FreeBSD_version >= 500000 72#include <sys/bio.h> 73#endif 74#include <sys/buf.h> 75#include <sys/bus.h> 76#include <sys/kernel.h> 77#include <sys/module.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <machine/resource.h> 85#include <machine/bus.h> 86#include <sys/rman.h> 87 88#include <cam/cam.h> 89#include <cam/cam_ccb.h> 90#include <cam/cam_sim.h> 91#include <cam/cam_xpt_sim.h> 92#include <cam/cam_debug.h> 93 94#include <cam/scsi/scsi_all.h> 95#include <cam/scsi/scsi_message.h> 96 97#include <dev/trm/trm.h> 98 99#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 100#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 101#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 102#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 103 reg, value) 104#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 105 reg, value) 106#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 107 reg, value) 108 109#define PCI_Vendor_ID_TEKRAM 0x1DE1 110#define PCI_Device_ID_TRM_S1040 0x0391 111#define PCI_DEVICEID_TRMS1040 0x03911DE1 112#define PCI_DEVICEID_TRMS2080 0x03921DE1 113 114#ifdef trm_DEBUG1 115#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 116#else 117#define TRM_DPRINTF(fmt, arg...) {} 118#endif /* TRM_DEBUG */ 119 120static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 121static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 122static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 123static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 125static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 126static void NVRAM_trm_wait_30us(PACB pACB); 127 128static void trm_Interrupt(void *vpACB); 129static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 130 u_int16_t * pscsi_status); 131static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 154static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 155static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 156static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 157static void trm_Disconnect(PACB pACB); 158static void trm_Reselect(PACB pACB); 159static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 160static void trm_DoingSRB_Done(PACB pACB); 161static void trm_ScsiRstDetect(PACB pACB); 162static void trm_ResetSCSIBus(PACB pACB); 163static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 164static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 165static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 166static void trm_SendSRB(PACB pACB, PSRB pSRB); 167static int trm_probe(device_t tag); 168static int trm_attach(device_t tag); 169static void trm_reset(PACB pACB); 170 171static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 172 173static int trm_initAdapter(PACB pACB, u_int16_t unit); 174static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 175 u_int32_t i, u_int32_t j); 176static int trm_initSRB(PACB pACB); 177static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 178/* CAM SIM entry points */ 179#define ccb_trmsrb_ptr spriv_ptr0 180#define ccb_trmacb_ptr spriv_ptr1 181static void trm_action(struct cam_sim *psim, union ccb *pccb); 182static void trm_poll(struct cam_sim *psim); 183 184 185static void * trm_SCSI_phase0[] = { 186 trm_DataOutPhase0, /* phase:0 */ 187 trm_DataInPhase0, /* phase:1 */ 188 trm_CommandPhase0, /* phase:2 */ 189 trm_StatusPhase0, /* phase:3 */ 190 trm_Nop0, /* phase:4 */ 191 trm_Nop1, /* phase:5 */ 192 trm_MsgOutPhase0, /* phase:6 */ 193 trm_MsgInPhase0, /* phase:7 */ 194}; 195 196/* 197 * 198 * stateV = (void *) trm_SCSI_phase1[phase] 199 * 200 */ 201static void * trm_SCSI_phase1[] = { 202 trm_DataOutPhase1, /* phase:0 */ 203 trm_DataInPhase1, /* phase:1 */ 204 trm_CommandPhase1, /* phase:2 */ 205 trm_StatusPhase1, /* phase:3 */ 206 trm_Nop0, /* phase:4 */ 207 trm_Nop1, /* phase:5 */ 208 trm_MsgOutPhase1, /* phase:6 */ 209 trm_MsgInPhase1, /* phase:7 */ 210}; 211 212 213NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 214/* 215 *Fast20: 000 50ns, 20.0 Mbytes/s 216 * 001 75ns, 13.3 Mbytes/s 217 * 010 100ns, 10.0 Mbytes/s 218 * 011 125ns, 8.0 Mbytes/s 219 * 100 150ns, 6.6 Mbytes/s 220 * 101 175ns, 5.7 Mbytes/s 221 * 110 200ns, 5.0 Mbytes/s 222 * 111 250ns, 4.0 Mbytes/s 223 * 224 *Fast40: 000 25ns, 40.0 Mbytes/s 225 * 001 50ns, 20.0 Mbytes/s 226 * 010 75ns, 13.3 Mbytes/s 227 * 011 100ns, 10.0 Mbytes/s 228 * 100 125ns, 8.0 Mbytes/s 229 * 101 150ns, 6.6 Mbytes/s 230 * 110 175ns, 5.7 Mbytes/s 231 * 111 200ns, 5.0 Mbytes/s 232 */ 233 /* real period: */ 234u_int8_t dc395x_clock_period[] = { 235 12,/* 48 ns 20 MB/sec */ 236 18,/* 72 ns 13.3 MB/sec */ 237 25,/* 100 ns 10.0 MB/sec */ 238 31,/* 124 ns 8.0 MB/sec */ 239 37,/* 148 ns 6.6 MB/sec */ 240 43,/* 172 ns 5.7 MB/sec */ 241 50,/* 200 ns 5.0 MB/sec */ 242 62 /* 248 ns 4.0 MB/sec */ 243}; 244 245u_int8_t dc395u2x_clock_period[]={ 246 10,/* 25 ns 40.0 MB/sec */ 247 12,/* 48 ns 20.0 MB/sec */ 248 18,/* 72 ns 13.3 MB/sec */ 249 25,/* 100 ns 10.0 MB/sec */ 250 31,/* 124 ns 8.0 MB/sec */ 251 37,/* 148 ns 6.6 MB/sec */ 252 43,/* 172 ns 5.7 MB/sec */ 253 50,/* 200 ns 5.0 MB/sec */ 254}; 255 256#define dc395x_tinfo_period dc395x_clock_period 257#define dc395u2x_tinfo_period dc395u2x_clock_period 258 259static PSRB 260trm_GetSRB(PACB pACB) 261{ 262 int intflag; 263 PSRB pSRB; 264 265 intflag = splcam(); 266 pSRB = pACB->pFreeSRB; 267 if (pSRB) { 268 pACB->pFreeSRB = pSRB->pNextSRB; 269 pSRB->pNextSRB = NULL; 270 } 271 splx(intflag); 272 return (pSRB); 273} 274 275static void 276trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 277{ 278 PSRB psrb1; 279 int intflag; 280 281 intflag = splcam(); 282 if ((psrb1 = pDCB->pWaitingSRB)) { 283 pSRB->pNextSRB = psrb1; 284 pDCB->pWaitingSRB = pSRB; 285 } else { 286 pSRB->pNextSRB = NULL; 287 pDCB->pWaitingSRB = pSRB; 288 pDCB->pWaitingLastSRB = pSRB; 289 } 290 splx(intflag); 291} 292 293static void 294trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 295{ 296 PSRB psrb1; 297 int intflag; 298 299 intflag = splcam(); 300 pDCB->GoingSRBCnt--; 301 psrb1 = pDCB->pGoingSRB; 302 if (pSRB == psrb1) 303 /* 304 * if this SRB is GoingSRB 305 * remove this SRB from GoingSRB Q 306 */ 307 pDCB->pGoingSRB = psrb1->pNextSRB; 308 else { 309 /* 310 * if this SRB is not current GoingSRB 311 * remove this SRB from GoingSRB Q 312 */ 313 while (pSRB != psrb1->pNextSRB) 314 psrb1 = psrb1->pNextSRB; 315 psrb1->pNextSRB = pSRB->pNextSRB; 316 if (pSRB == pDCB->pGoingLastSRB) 317 pDCB->pGoingLastSRB = psrb1; 318 } 319 if ((psrb1 = pDCB->pWaitingSRB)) { 320 /* 321 * if WaitingSRB Q is not NULL 322 * Q back this SRB into WaitingSRB 323 */ 324 325 pSRB->pNextSRB = psrb1; 326 pDCB->pWaitingSRB = pSRB; 327 } else { 328 pSRB->pNextSRB = NULL; 329 pDCB->pWaitingSRB = pSRB; 330 pDCB->pWaitingLastSRB = pSRB; 331 } 332 splx(intflag); 333} 334 335static void 336trm_DoWaitingSRB(PACB pACB) 337{ 338 int intflag; 339 PDCB ptr, ptr1; 340 PSRB pSRB; 341 342 intflag = splcam(); 343 if (!(pACB->pActiveDCB) && 344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 345 ptr = pACB->pDCBRunRobin; 346 if (!ptr) { 347 ptr = pACB->pLinkDCB; 348 pACB->pDCBRunRobin = ptr; 349 } 350 ptr1 = ptr; 351 for (;ptr1 ;) { 352 pACB->pDCBRunRobin = ptr1->pNextDCB; 353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 354 || !(pSRB = ptr1->pWaitingSRB)) { 355 if (pACB->pDCBRunRobin == ptr) 356 break; 357 ptr1 = ptr1->pNextDCB; 358 } else { 359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 360 /* 361 * If trm_StartSCSI return 0 : 362 * current interrupt status is interrupt enable 363 * It's said that SCSI processor is unoccupied 364 */ 365 ptr1->GoingSRBCnt++; 366 if (ptr1->pWaitingLastSRB == pSRB) { 367 ptr1->pWaitingSRB = NULL; 368 ptr1->pWaitingLastSRB = NULL; 369 } else 370 ptr1->pWaitingSRB = pSRB->pNextSRB; 371 pSRB->pNextSRB = NULL; 372 if (ptr1->pGoingSRB) 373 ptr1->pGoingLastSRB->pNextSRB = pSRB; 374 else 375 ptr1->pGoingSRB = pSRB; 376 ptr1->pGoingLastSRB = pSRB; 377 } 378 break; 379 } 380 } 381 } 382 splx(intflag); 383 return; 384} 385 386static void 387trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 388{ 389 390 if (pDCB->pWaitingSRB) { 391 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 392 pDCB->pWaitingLastSRB = pSRB; 393 pSRB->pNextSRB = NULL; 394 } else { 395 pDCB->pWaitingSRB = pSRB; 396 pDCB->pWaitingLastSRB = pSRB; 397 } 398} 399 400static u_int32_t 401trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 402{ 403 int offset; 404 405 offset = pSRB->TagNumber; 406 return (pACB->sense_busaddr + 407 (offset * sizeof(struct scsi_sense_data))); 408} 409 410static struct scsi_sense_data * 411trm_get_sense_buf(PACB pACB, PSRB pSRB) 412{ 413 int offset; 414 415 offset = pSRB->TagNumber; 416 return (&pACB->sense_buffers[offset]); 417} 418static void 419trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 420{ 421 int flags; 422 PACB pACB; 423 PSRB pSRB; 424 union ccb *ccb; 425 u_long totalxferlen=0; 426 427 flags = splcam(); 428 pSRB = (PSRB)arg; 429 ccb = pSRB->pccb; 430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 431 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 432 if (nseg != 0) { 433 PSEG psg; 434 bus_dma_segment_t *end_seg; 435 int op; 436 437 /* Copy the segments into our SG list */ 438 end_seg = dm_segs + nseg; 439 psg = pSRB->pSRBSGL; 440 while (dm_segs < end_seg) { 441 psg->address = dm_segs->ds_addr; 442 psg->length = (u_long)dm_segs->ds_len; 443 totalxferlen += dm_segs->ds_len; 444 psg++; 445 dm_segs++; 446 } 447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 448 op = BUS_DMASYNC_PREREAD; 449 } else { 450 op = BUS_DMASYNC_PREWRITE; 451 } 452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 453 } 454 pSRB->RetryCnt = 0; 455 pSRB->SRBTotalXferLength = totalxferlen; 456 pSRB->SRBSGCount = nseg; 457 pSRB->SRBSGIndex = 0; 458 pSRB->AdaptStatus = 0; 459 pSRB->TargetStatus = 0; 460 pSRB->MsgCnt = 0; 461 pSRB->SRBStatus = 0; 462 pSRB->SRBFlag = 0; 463 pSRB->SRBState = 0; 464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 465 466 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 467 if (nseg != 0) 468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 469 pSRB->pNextSRB = pACB->pFreeSRB; 470 pACB->pFreeSRB = pSRB; 471 xpt_done(ccb); 472 splx(flags); 473 return; 474 } 475 ccb->ccb_h.status |= CAM_SIM_QUEUED; 476#if 0 477 /* XXX Need a timeout handler */ 478 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 479#endif 480 trm_SendSRB(pACB, pSRB); 481 splx(flags); 482 return; 483} 484 485static void 486trm_SendSRB(PACB pACB, PSRB pSRB) 487{ 488 PDCB pDCB; 489 490 pDCB = pSRB->pSRBDCB; 491 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 492 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 493 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 494 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 495 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 496 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 497 trm_SRBwaiting(pDCB, pSRB); 498 goto SND_EXIT; 499 } 500 501 if (pDCB->pWaitingSRB) { 502 trm_SRBwaiting(pDCB, pSRB); 503 pSRB = pDCB->pWaitingSRB; 504 pDCB->pWaitingSRB = pSRB->pNextSRB; 505 pSRB->pNextSRB = NULL; 506 } 507 508 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 509 /* 510 * If trm_StartSCSI return 0 : 511 * current interrupt status is interrupt enable 512 * It's said that SCSI processor is unoccupied 513 */ 514 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 515 if (pDCB->pGoingSRB) { 516 pDCB->pGoingLastSRB->pNextSRB = pSRB; 517 pDCB->pGoingLastSRB = pSRB; 518 } else { 519 pDCB->pGoingSRB = pSRB; 520 pDCB->pGoingLastSRB = pSRB; 521 } 522 } else { 523 /* 524 * If trm_StartSCSI return 1 : 525 * current interrupt status is interrupt disreenable 526 * It's said that SCSI processor has more one SRB need to do 527 */ 528 trm_RewaitSRB0(pDCB, pSRB); 529 } 530SND_EXIT: 531 return; 532} 533 534 535static void 536trm_action(struct cam_sim *psim, union ccb *pccb) 537{ 538 PACB pACB; 539 int actionflags; 540 u_int target_id,target_lun; 541 542 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 543 544 actionflags = splcam(); 545 pACB = (PACB) cam_sim_softc(psim); 546 target_id = pccb->ccb_h.target_id; 547 target_lun = pccb->ccb_h.target_lun; 548 549 switch (pccb->ccb_h.func_code) { 550 case XPT_NOOP: 551 TRM_DPRINTF(" XPT_NOOP \n"); 552 pccb->ccb_h.status = CAM_REQ_INVALID; 553 xpt_done(pccb); 554 break; 555 /* 556 * Execute the requested I/O operation 557 */ 558 case XPT_SCSI_IO: { 559 PDCB pDCB = NULL; 560 PSRB pSRB; 561 struct ccb_scsiio *pcsio; 562 563 pcsio = &pccb->csio; 564 TRM_DPRINTF(" XPT_SCSI_IO \n"); 565 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 566 ,target_id, target_lun); 567 TRM_DPRINTF( 568 "pACB->scan_devices[target_id][target_lun]= %d \n" 569 ,pACB->scan_devices[target_id][target_lun]); 570 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 571 CAM_REQ_INPROG) { 572 xpt_done(pccb); 573 splx(actionflags); 574 return; 575 } 576 pDCB = &pACB->DCBarray[target_id][target_lun]; 577 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 578 pACB->scan_devices[target_id][target_lun] = 1; 579 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 580 target_id, target_lun); 581 } 582 /* 583 * Assign an SRB and connect it with this ccb. 584 */ 585 pSRB = trm_GetSRB(pACB); 586 if (!pSRB) { 587 /* Freeze SIMQ */ 588 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 589 xpt_done(pccb); 590 splx(actionflags); 591 return; 592 } 593 pSRB->pSRBDCB = pDCB; 594 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 595 pccb->ccb_h.ccb_trmacb_ptr = pACB; 596 pSRB->pccb = pccb; 597 pSRB->ScsiCmdLen = pcsio->cdb_len; 598 /* 599 * move layer of CAM command block to layer of SCSI 600 * Request Block for SCSI processor command doing 601 */ 602 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 603 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 604 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 605 ,pcsio->cdb_len); 606 } else { 607 pccb->ccb_h.status = CAM_REQ_INVALID; 608 pSRB->pNextSRB = pACB->pFreeSRB; 609 pACB->pFreeSRB= pSRB; 610 xpt_done(pccb); 611 splx(actionflags); 612 return; 613 } 614 } else 615 bcopy(pcsio->cdb_io.cdb_bytes, 616 pSRB->CmdBlock, pcsio->cdb_len); 617 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 618 != CAM_DIR_NONE) { 619 if ((pccb->ccb_h.flags & 620 CAM_SCATTER_VALID) == 0) { 621 if ((pccb->ccb_h.flags 622 & CAM_DATA_PHYS) == 0) { 623 int vmflags; 624 int error; 625 626 vmflags = splsoftvm(); 627 error = bus_dmamap_load( 628 pACB->buffer_dmat, 629 pSRB->dmamap, 630 pcsio->data_ptr, 631 pcsio->dxfer_len, 632 trm_ExecuteSRB, 633 pSRB, 634 0); 635 if (error == EINPROGRESS) { 636 xpt_freeze_simq( 637 pACB->psim, 638 1); 639 pccb->ccb_h.status |= 640 CAM_RELEASE_SIMQ; 641 } 642 splx(vmflags); 643 } else { 644 struct bus_dma_segment seg; 645 646 /* Pointer to physical buffer */ 647 seg.ds_addr = 648 (bus_addr_t)pcsio->data_ptr; 649 seg.ds_len = pcsio->dxfer_len; 650 trm_ExecuteSRB(pSRB, &seg, 1, 651 0); 652 } 653 } else { 654 /* CAM_SCATTER_VALID */ 655 struct bus_dma_segment *segs; 656 657 if ((pccb->ccb_h.flags & 658 CAM_SG_LIST_PHYS) == 0 || 659 (pccb->ccb_h.flags 660 & CAM_DATA_PHYS) != 0) { 661 pSRB->pNextSRB = pACB->pFreeSRB; 662 pACB->pFreeSRB = pSRB; 663 pccb->ccb_h.status = 664 CAM_PROVIDE_FAIL; 665 xpt_done(pccb); 666 splx(actionflags); 667 return; 668 } 669 670 /* cam SG list is physical, 671 * cam data is virtual 672 */ 673 segs = (struct bus_dma_segment *) 674 pcsio->data_ptr; 675 trm_ExecuteSRB(pSRB, segs, 676 pcsio->sglist_cnt, 1); 677 } /* CAM_SCATTER_VALID */ 678 } else 679 trm_ExecuteSRB(pSRB, NULL, 0, 0); 680 } 681 break; 682 case XPT_GDEV_TYPE: 683 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 684 pccb->ccb_h.status = CAM_REQ_INVALID; 685 xpt_done(pccb); 686 break; 687 case XPT_GDEVLIST: 688 TRM_DPRINTF(" XPT_GDEVLIST \n"); 689 pccb->ccb_h.status = CAM_REQ_INVALID; 690 xpt_done(pccb); 691 break; 692 /* 693 * Path routing inquiry 694 * Path Inquiry CCB 695 */ 696 case XPT_PATH_INQ: { 697 struct ccb_pathinq *cpi = &pccb->cpi; 698 699 TRM_DPRINTF(" XPT_PATH_INQ \n"); 700 cpi->version_num = 1; 701 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 702 cpi->target_sprt = 0; 703 cpi->hba_misc = 0; 704 cpi->hba_eng_cnt = 0; 705 cpi->max_target = 15 ; 706 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 707 cpi->initiator_id = pACB->AdaptSCSIID; 708 cpi->bus_id = cam_sim_bus(psim); 709 cpi->base_transfer_speed = 3300; 710 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 711 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 712 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 713 cpi->unit_number = cam_sim_unit(psim); 714 cpi->transport = XPORT_SPI; 715 cpi->transport_version = 2; 716 cpi->protocol = PROTO_SCSI; 717 cpi->protocol_version = SCSI_REV_2; 718 cpi->ccb_h.status = CAM_REQ_CMP; 719 xpt_done(pccb); 720 } 721 break; 722 /* 723 * Release a frozen SIM queue 724 * Release SIM Queue 725 */ 726 case XPT_REL_SIMQ: 727 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 728 pccb->ccb_h.status = CAM_REQ_INVALID; 729 xpt_done(pccb); 730 break; 731 /* 732 * Set Asynchronous Callback Parameters 733 * Set Asynchronous Callback CCB 734 */ 735 case XPT_SASYNC_CB: 736 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 737 pccb->ccb_h.status = CAM_REQ_INVALID; 738 xpt_done(pccb); 739 break; 740 /* 741 * Set device type information 742 * Set Device Type CCB 743 */ 744 case XPT_SDEV_TYPE: 745 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 746 pccb->ccb_h.status = CAM_REQ_INVALID; 747 xpt_done(pccb); 748 break; 749 /* 750 * (Re)Scan the SCSI Bus 751 * Rescan the given bus, or bus/target/lun 752 */ 753 case XPT_SCAN_BUS: 754 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 755 pccb->ccb_h.status = CAM_REQ_INVALID; 756 xpt_done(pccb); 757 break; 758 /* 759 * Get EDT entries matching the given pattern 760 */ 761 case XPT_DEV_MATCH: 762 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 763 pccb->ccb_h.status = CAM_REQ_INVALID; 764 xpt_done(pccb); 765 break; 766 /* 767 * Turn on debugging for a bus, target or lun 768 */ 769 case XPT_DEBUG: 770 TRM_DPRINTF(" XPT_DEBUG \n"); 771 pccb->ccb_h.status = CAM_REQ_INVALID; 772 xpt_done(pccb); 773 break; 774 /* 775 * XPT_ABORT = 0x10, Abort the specified CCB 776 * Abort XPT request CCB 777 */ 778 case XPT_ABORT: 779 TRM_DPRINTF(" XPT_ABORT \n"); 780 pccb->ccb_h.status = CAM_REQ_INVALID; 781 xpt_done(pccb); 782 break; 783 /* 784 * Reset the specified SCSI bus 785 * Reset SCSI Bus CCB 786 */ 787 case XPT_RESET_BUS: { 788 int i; 789 790 TRM_DPRINTF(" XPT_RESET_BUS \n"); 791 trm_reset(pACB); 792 pACB->ACBFlag=0; 793 for (i=0; i<500; i++) 794 DELAY(1000); 795 pccb->ccb_h.status = CAM_REQ_CMP; 796 xpt_done(pccb); 797 } 798 break; 799 /* 800 * Bus Device Reset the specified SCSI device 801 * Reset SCSI Device CCB 802 */ 803 case XPT_RESET_DEV: 804 /* 805 * Don't (yet?) support vendor 806 * specific commands. 807 */ 808 TRM_DPRINTF(" XPT_RESET_DEV \n"); 809 pccb->ccb_h.status = CAM_REQ_INVALID; 810 xpt_done(pccb); 811 break; 812 /* 813 * Terminate the I/O process 814 * Terminate I/O Process Request CCB 815 */ 816 case XPT_TERM_IO: 817 TRM_DPRINTF(" XPT_TERM_IO \n"); 818 pccb->ccb_h.status = CAM_REQ_INVALID; 819 xpt_done(pccb); 820 break; 821 /* 822 * Scan Logical Unit 823 */ 824 case XPT_SCAN_LUN: 825 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 826 pccb->ccb_h.status = CAM_REQ_INVALID; 827 xpt_done(pccb); 828 break; 829 830 /* 831 * Get/Set transfer rate/width/disconnection/tag queueing 832 * settings 833 * (GET) default/user transfer settings for the target 834 */ 835 case XPT_GET_TRAN_SETTINGS: { 836 struct ccb_trans_settings *cts = &pccb->cts; 837 int intflag; 838 struct trm_transinfo *tinfo; 839 PDCB pDCB; 840 struct ccb_trans_settings_scsi *scsi = 841 &cts->proto_specific.scsi; 842 struct ccb_trans_settings_spi *spi = 843 &cts->xport_specific.spi; 844 845 cts->protocol = PROTO_SCSI; 846 cts->protocol_version = SCSI_REV_2; 847 cts->transport = XPORT_SPI; 848 cts->transport_version = 2; 849 850 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 851 pDCB = &pACB->DCBarray[target_id][target_lun]; 852 intflag = splcam(); 853 /* 854 * disable interrupt 855 */ 856 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 857 /* current transfer settings */ 858 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 859 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 860 else 861 spi->flags = 0;/* no tag & disconnect */ 862 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 863 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 864 tinfo = &pDCB->tinfo.current; 865 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 866 cts->flags); 867 } else { 868 /* default(user) transfer settings */ 869 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 870 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 871 else 872 spi->flags = 0; 873 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 874 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 875 tinfo = &pDCB->tinfo.user; 876 TRM_DPRINTF("USER: cts->flags= %2x \n", 877 cts->flags); 878 } 879 spi->sync_period = tinfo->period; 880 spi->sync_offset = tinfo->offset; 881 spi->bus_width = tinfo->width; 882 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 883 pDCB->SyncPeriod); 884 TRM_DPRINTF("period: %d \n", tinfo->period); 885 TRM_DPRINTF("offset: %d \n", tinfo->offset); 886 TRM_DPRINTF("width: %d \n", tinfo->width); 887 888 splx(intflag); 889 spi->valid = CTS_SPI_VALID_SYNC_RATE | 890 CTS_SPI_VALID_SYNC_OFFSET | 891 CTS_SPI_VALID_BUS_WIDTH | 892 CTS_SPI_VALID_DISC; 893 scsi->valid = CTS_SCSI_VALID_TQ; 894 pccb->ccb_h.status = CAM_REQ_CMP; 895 xpt_done(pccb); 896 } 897 break; 898 /* 899 * Get/Set transfer rate/width/disconnection/tag queueing 900 * settings 901 * (Set) transfer rate/width negotiation settings 902 */ 903 case XPT_SET_TRAN_SETTINGS: { 904 struct ccb_trans_settings *cts = &pccb->cts; 905 u_int update_type; 906 int intflag; 907 PDCB pDCB; 908 struct ccb_trans_settings_scsi *scsi = 909 &cts->proto_specific.scsi; 910 struct ccb_trans_settings_spi *spi = 911 &cts->xport_specific.spi; 912 913 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 914 update_type = 0; 915 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 916 update_type |= TRM_TRANS_GOAL; 917 if (cts->type == CTS_TYPE_USER_SETTINGS) 918 update_type |= TRM_TRANS_USER; 919 intflag = splcam(); 920 pDCB = &pACB->DCBarray[target_id][target_lun]; 921 922 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 923 /*ccb disc enables */ 924 if (update_type & TRM_TRANS_GOAL) { 925 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 926 != 0) 927 pDCB->tinfo.disc_tag 928 |= TRM_CUR_DISCENB; 929 else 930 pDCB->tinfo.disc_tag &= 931 ~TRM_CUR_DISCENB; 932 } 933 if (update_type & TRM_TRANS_USER) { 934 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 935 != 0) 936 pDCB->tinfo.disc_tag 937 |= TRM_USR_DISCENB; 938 else 939 pDCB->tinfo.disc_tag &= 940 ~TRM_USR_DISCENB; 941 } 942 } 943 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 944 /* if ccb tag q active */ 945 if (update_type & TRM_TRANS_GOAL) { 946 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 947 != 0) 948 pDCB->tinfo.disc_tag |= 949 TRM_CUR_TAGENB; 950 else 951 pDCB->tinfo.disc_tag &= 952 ~TRM_CUR_TAGENB; 953 } 954 if (update_type & TRM_TRANS_USER) { 955 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 956 != 0) 957 pDCB->tinfo.disc_tag |= 958 TRM_USR_TAGENB; 959 else 960 pDCB->tinfo.disc_tag &= 961 ~TRM_USR_TAGENB; 962 } 963 } 964 /* Minimum sync period factor */ 965 966 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 967 /* if ccb sync active */ 968 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 969 if ((spi->sync_period != 0) && 970 (spi->sync_period < 125)) 971 spi->sync_period = 125; 972 /* 1/(125*4) minsync 2 MByte/sec */ 973 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) 974 != 0) { 975 if (spi->sync_offset == 0) 976 spi->sync_period = 0; 977 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 978 if (spi->sync_offset > 15) 979 spi->sync_offset = 15; 980 } 981 } 982 if ((update_type & TRM_TRANS_USER) != 0) { 983 pDCB->tinfo.user.period = spi->sync_period; 984 pDCB->tinfo.user.offset = spi->sync_offset; 985 pDCB->tinfo.user.width = spi->bus_width; 986 } 987 if ((update_type & TRM_TRANS_GOAL) != 0) { 988 pDCB->tinfo.goal.period = spi->sync_period; 989 pDCB->tinfo.goal.offset = spi->sync_offset; 990 pDCB->tinfo.goal.width = spi->bus_width; 991 } 992 splx(intflag); 993 pccb->ccb_h.status = CAM_REQ_CMP; 994 xpt_done(pccb); 995 break; 996 } 997 /* 998 * Calculate the geometry parameters for a device give 999 * the sector size and volume size. 1000 */ 1001 case XPT_CALC_GEOMETRY: 1002 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 1003 cam_calc_geometry(&pccb->ccg, /*extended*/1); 1004 xpt_done(pccb); 1005 break; 1006 case XPT_ENG_INQ: 1007 TRM_DPRINTF(" XPT_ENG_INQ \n"); 1008 pccb->ccb_h.status = CAM_REQ_INVALID; 1009 xpt_done(pccb); 1010 break; 1011 /* 1012 * HBA execute engine request 1013 * This structure must match SCSIIO size 1014 */ 1015 case XPT_ENG_EXEC: 1016 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1017 pccb->ccb_h.status = CAM_REQ_INVALID; 1018 xpt_done(pccb); 1019 break; 1020 /* 1021 * XPT_EN_LUN = 0x30, Enable LUN as a target 1022 * Target mode structures. 1023 */ 1024 case XPT_EN_LUN: 1025 /* 1026 * Don't (yet?) support vendor 1027 * specific commands. 1028 */ 1029 TRM_DPRINTF(" XPT_EN_LUN \n"); 1030 pccb->ccb_h.status = CAM_REQ_INVALID; 1031 xpt_done(pccb); 1032 break; 1033 /* 1034 * Execute target I/O request 1035 */ 1036 case XPT_TARGET_IO: 1037 /* 1038 * Don't (yet?) support vendor 1039 * specific commands. 1040 */ 1041 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1042 pccb->ccb_h.status = CAM_REQ_INVALID; 1043 xpt_done(pccb); 1044 break; 1045 /* 1046 * Accept Host Target Mode CDB 1047 */ 1048 case XPT_ACCEPT_TARGET_IO: 1049 /* 1050 * Don't (yet?) support vendor 1051 * specific commands. 1052 */ 1053 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1054 pccb->ccb_h.status = CAM_REQ_INVALID; 1055 xpt_done(pccb); 1056 break; 1057 /* 1058 * Continue Host Target I/O Connection 1059 */ 1060 case XPT_CONT_TARGET_IO: 1061 /* 1062 * Don't (yet?) support vendor 1063 * specific commands. 1064 */ 1065 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1066 pccb->ccb_h.status = CAM_REQ_INVALID; 1067 xpt_done(pccb); 1068 break; 1069 /* 1070 * Notify Host Target driver of event 1071 */ 1072 case XPT_IMMED_NOTIFY: 1073 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1074 pccb->ccb_h.status = CAM_REQ_INVALID; 1075 xpt_done(pccb); 1076 break; 1077 /* 1078 * Acknowledgement of event 1079 */ 1080 case XPT_NOTIFY_ACK: 1081 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1082 pccb->ccb_h.status = CAM_REQ_INVALID; 1083 xpt_done(pccb); 1084 break; 1085 /* 1086 * XPT_VUNIQUE = 0x80 1087 */ 1088 case XPT_VUNIQUE: 1089 pccb->ccb_h.status = CAM_REQ_INVALID; 1090 xpt_done(pccb); 1091 break; 1092 default: 1093 pccb->ccb_h.status = CAM_REQ_INVALID; 1094 xpt_done(pccb); 1095 break; 1096 } 1097 splx(actionflags); 1098} 1099 1100static void 1101trm_poll(struct cam_sim *psim) 1102{ 1103 trm_Interrupt(cam_sim_softc(psim)); 1104} 1105 1106static void 1107trm_ResetDevParam(PACB pACB) 1108{ 1109 PDCB pDCB, pdcb; 1110 PNVRAMTYPE pEEpromBuf; 1111 u_int8_t PeriodIndex; 1112 1113 pDCB = pACB->pLinkDCB; 1114 if (pDCB == NULL) 1115 return; 1116 pdcb = pDCB; 1117 do { 1118 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1119 pDCB->SyncPeriod = 0; 1120 pDCB->SyncOffset = 0; 1121 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1122 pDCB->DevMode = 1123 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1124 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1125 PeriodIndex = 1126 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1127 if (pACB->AdaptType == 1) /* is U2? */ 1128 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1129 else 1130 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1131 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1132 (pACB->Config & HCC_WIDE_CARD)) 1133 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1134 pDCB = pDCB->pNextDCB; 1135 } 1136 while (pdcb != pDCB); 1137} 1138 1139static void 1140trm_RecoverSRB(PACB pACB) 1141{ 1142 PDCB pDCB, pdcb; 1143 PSRB psrb, psrb2; 1144 u_int16_t cnt, i; 1145 1146 pDCB = pACB->pLinkDCB; 1147 if (pDCB == NULL) 1148 return; 1149 pdcb = pDCB; 1150 do { 1151 cnt = pdcb->GoingSRBCnt; 1152 psrb = pdcb->pGoingSRB; 1153 for (i = 0; i < cnt; i++) { 1154 psrb2 = psrb; 1155 psrb = psrb->pNextSRB; 1156 if (pdcb->pWaitingSRB) { 1157 psrb2->pNextSRB = pdcb->pWaitingSRB; 1158 pdcb->pWaitingSRB = psrb2; 1159 } else { 1160 pdcb->pWaitingSRB = psrb2; 1161 pdcb->pWaitingLastSRB = psrb2; 1162 psrb2->pNextSRB = NULL; 1163 } 1164 } 1165 pdcb->GoingSRBCnt = 0; 1166 pdcb->pGoingSRB = NULL; 1167 pdcb = pdcb->pNextDCB; 1168 } 1169 while (pdcb != pDCB); 1170} 1171 1172static void 1173trm_reset(PACB pACB) 1174{ 1175 int intflag; 1176 u_int16_t i; 1177 1178 TRM_DPRINTF("trm: RESET"); 1179 intflag = splcam(); 1180 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1181 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1182 1183 trm_ResetSCSIBus(pACB); 1184 for (i = 0; i < 500; i++) 1185 DELAY(1000); 1186 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1187 /* Enable DMA interrupt */ 1188 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1189 /* Clear DMA FIFO */ 1190 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1191 /* Clear SCSI FIFO */ 1192 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1193 trm_ResetDevParam(pACB); 1194 trm_DoingSRB_Done(pACB); 1195 pACB->pActiveDCB = NULL; 1196 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1197 trm_DoWaitingSRB(pACB); 1198 /* Tell the XPT layer that a bus reset occured */ 1199 if (pACB->ppath != NULL) 1200 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1201 splx(intflag); 1202 return; 1203} 1204 1205static u_int16_t 1206trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1207{ 1208 u_int16_t return_code; 1209 u_int8_t scsicommand, i,command,identify_message; 1210 u_int8_t * ptr; 1211 union ccb *pccb; 1212 struct ccb_scsiio *pcsio; 1213 1214 pccb = pSRB->pccb; 1215 pcsio = &pccb->csio; 1216 1217 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1218 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1219 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1220 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1221 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1222 /* Flush FIFO */ 1223 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1224 1225 identify_message = pDCB->IdentifyMsg; 1226 1227 if ((pSRB->CmdBlock[0] == INQUIRY) || 1228 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1229 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1230 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1231 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1232 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1233 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1234 if (!(pDCB->IdentifyMsg & 7) || 1235 (pSRB->CmdBlock[0] != INQUIRY)) { 1236 scsicommand = SCMD_SEL_ATNSTOP; 1237 pSRB->SRBState = SRB_MSGOUT; 1238 goto polling; 1239 } 1240 } 1241 /* 1242 * Send identify message 1243 */ 1244 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1245 scsicommand = SCMD_SEL_ATN; 1246 pSRB->SRBState = SRB_START_; 1247 } else { 1248 /* not inquiry,request sense,auto request sense */ 1249 /* 1250 * Send identify message 1251 */ 1252 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1253 scsicommand = SCMD_SEL_ATN; 1254 pSRB->SRBState = SRB_START_; 1255 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1256 /* Send Tag message */ 1257 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1258 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1259 scsicommand = SCMD_SEL_ATN3; 1260 } 1261 } 1262polling: 1263 /* 1264 * Send CDB ..command block ......... 1265 */ 1266 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1267 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1268 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1269 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1270 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1271 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1272 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1273 } else { 1274 ptr = (u_int8_t *) pSRB->CmdBlock; 1275 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1276 command = *ptr++; 1277 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1278 } 1279 } 1280 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1281 /* 1282 * If trm_StartSCSI return 1 : 1283 * current interrupt status is interrupt disreenable 1284 * It's said that SCSI processor has more one SRB need to do, 1285 * SCSI processor has been occupied by one SRB. 1286 */ 1287 pSRB->SRBState = SRB_READY; 1288 return_code = 1; 1289 } else { 1290 /* 1291 * If trm_StartSCSI return 0 : 1292 * current interrupt status is interrupt enable 1293 * It's said that SCSI processor is unoccupied 1294 */ 1295 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1296 pACB->pActiveDCB = pDCB; 1297 pDCB->pActiveSRB = pSRB; 1298 return_code = 0; 1299 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1300 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1301 /* 1302 * SCSI cammand 1303 */ 1304 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1305 } 1306 return (return_code); 1307} 1308 1309static void 1310trm_Interrupt(vpACB) 1311void *vpACB; 1312{ 1313 PACB pACB; 1314 PDCB pDCB; 1315 PSRB pSRB; 1316 u_int16_t phase; 1317 void (*stateV)(PACB, PSRB, u_int16_t *); 1318 u_int16_t scsi_status=0; 1319 u_int8_t scsi_intstatus; 1320 1321 pACB = vpACB; 1322 1323 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1324 if (!(scsi_status & SCSIINTERRUPT)) { 1325 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1326 return; 1327 } 1328 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1329 1330 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1331 1332 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1333 1334 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1335 trm_Disconnect(pACB); 1336 return; 1337 } 1338 1339 if (scsi_intstatus & INT_RESELECTED) { 1340 trm_Reselect(pACB); 1341 return; 1342 } 1343 if (scsi_intstatus & INT_SCSIRESET) { 1344 trm_ScsiRstDetect(pACB); 1345 return; 1346 } 1347 1348 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1349 pDCB = pACB->pActiveDCB; 1350 KASSERT(pDCB != NULL, ("no active DCB")); 1351 pSRB = pDCB->pActiveSRB; 1352 if (pDCB->DCBFlag & ABORT_DEV_) 1353 trm_EnableMsgOutAbort1(pACB, pSRB); 1354 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1355 stateV = (void *) trm_SCSI_phase0[phase]; 1356 stateV(pACB, pSRB, &scsi_status); 1357 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1358 /* phase:0,1,2,3,4,5,6,7 */ 1359 phase = (u_int16_t) scsi_status & PHASEMASK; 1360 stateV = (void *) trm_SCSI_phase1[phase]; 1361 stateV(pACB, pSRB, &scsi_status); 1362 } 1363} 1364 1365static void 1366trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1367{ 1368 1369 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1370 *pscsi_status = PH_BUS_FREE; 1371 /*.. initial phase*/ 1372} 1373 1374static void 1375trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1376{ 1377 u_int8_t bval; 1378 u_int16_t i, cnt; 1379 u_int8_t * ptr; 1380 PDCB pDCB; 1381 1382 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1383 pDCB = pACB->pActiveDCB; 1384 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1385 cnt = pSRB->MsgCnt; 1386 if (cnt) { 1387 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1388 for (i = 0; i < cnt; i++) { 1389 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1390 ptr++; 1391 } 1392 pSRB->MsgCnt = 0; 1393 if ((pDCB->DCBFlag & ABORT_DEV_) && 1394 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1395 pSRB->SRBState = SRB_ABORT_SENT; 1396 } 1397 } else { 1398 bval = MSG_ABORT; 1399 if ((pSRB->CmdBlock[0] == INQUIRY) || 1400 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1401 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1402 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1403 goto mop1; 1404 } 1405 } 1406 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1407 } 1408 } else { 1409mop1: /* message out phase */ 1410 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1411 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1412 /* 1413 * WIDE DATA TRANSFER REQUEST code (03h) 1414 */ 1415 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1416 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1417 TRMREG_SCSI_FIFO); 1418 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1419 /* (01h) */ 1420 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1421 /* Message length (02h) */ 1422 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1423 /* wide data xfer (03h) */ 1424 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1425 /* width:0(8bit),1(16bit),2(32bit) */ 1426 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1427 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1428 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1429 /* 1430 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1431 */ 1432 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1433 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1434 TRMREG_SCSI_FIFO); 1435 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1436 /* (01h) */ 1437 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1438 /* Message length (03h) */ 1439 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1440 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1441 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1442 /* Transfer peeriod factor */ 1443 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1444 TRMREG_SCSI_FIFO); 1445 /* REQ/ACK offset */ 1446 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1447 } 1448 } 1449 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1450 /* it's important for atn stop */ 1451 /* 1452 * SCSI cammand 1453 */ 1454 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1455} 1456 1457static void 1458trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1459{ 1460 1461} 1462 1463static void 1464trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1465{ 1466 PDCB pDCB; 1467 u_int8_t * ptr; 1468 u_int16_t i, cnt; 1469 union ccb *pccb; 1470 struct ccb_scsiio *pcsio; 1471 1472 pccb = pSRB->pccb; 1473 pcsio = &pccb->csio; 1474 1475 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1476 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1477 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1478 ptr = (u_int8_t *) pSRB->CmdBlock; 1479 for (i = 0; i < cnt; i++) { 1480 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1481 ptr++; 1482 } 1483 } else { 1484 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1485 pDCB = pACB->pActiveDCB; 1486 /* target id */ 1487 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1488 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1489 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1490 /* sizeof(struct scsi_sense_data) */ 1491 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1492 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1493 } 1494 pSRB->SRBState = SRB_COMMAND; 1495 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1496 /* it's important for atn stop*/ 1497 /* 1498 * SCSI cammand 1499 */ 1500 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1501} 1502 1503static void 1504trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1505{ 1506 PDCB pDCB; 1507 u_int8_t TempDMAstatus,SGIndexTemp; 1508 u_int16_t scsi_status; 1509 PSEG pseg; 1510 u_long TempSRBXferredLength,dLeftCounter=0; 1511 1512 pDCB = pSRB->pSRBDCB; 1513 scsi_status = *pscsi_status; 1514 1515 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1516 if (scsi_status & PARITYERROR) 1517 pSRB->SRBStatus |= PARITY_ERROR; 1518 if (!(scsi_status & SCSIXFERDONE)) { 1519 /* 1520 * when data transfer from DMA FIFO to SCSI FIFO 1521 * if there was some data left in SCSI FIFO 1522 */ 1523 dLeftCounter = (u_long) 1524 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1525 if (pDCB->SyncPeriod & WIDE_SYNC) { 1526 /* 1527 * if WIDE scsi SCSI FIFOCNT unit is word 1528 * so need to * 2 1529 */ 1530 dLeftCounter <<= 1; 1531 } 1532 } 1533 /* 1534 * caculate all the residue data that not yet tranfered 1535 * SCSI transfer counter + left in SCSI FIFO data 1536 * 1537 * .....TRM_SCSI_COUNTER (24bits) 1538 * The counter always decrement by one for every SCSI byte 1539 *transfer. 1540 * .....TRM_SCSI_FIFOCNT (5bits) 1541 * The counter is SCSI FIFO offset counter 1542 */ 1543 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1544 if (dLeftCounter == 1) { 1545 dLeftCounter = 0; 1546 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1547 } 1548 if ((dLeftCounter == 0) || 1549 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1550 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1551 while (!(TempDMAstatus & DMAXFERCOMP)) { 1552 TempDMAstatus = 1553 trm_reg_read8(TRMREG_DMA_STATUS); 1554 } 1555 pSRB->SRBTotalXferLength = 0; 1556 } else { 1557 /* Update SG list */ 1558 /* 1559 * if transfer not yet complete 1560 * there were some data residue in SCSI FIFO or 1561 * SCSI transfer counter not empty 1562 */ 1563 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1564 /* 1565 * data that had transferred length 1566 */ 1567 TempSRBXferredLength = 1568 pSRB->SRBTotalXferLength - dLeftCounter; 1569 /* 1570 * next time to be transferred length 1571 */ 1572 pSRB->SRBTotalXferLength = dLeftCounter; 1573 /* 1574 * parsing from last time disconnect SRBSGIndex 1575 */ 1576 pseg = 1577 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1578 for (SGIndexTemp = pSRB->SRBSGIndex; 1579 SGIndexTemp < pSRB->SRBSGCount; 1580 SGIndexTemp++) { 1581 /* 1582 * find last time which SG transfer be 1583 * disconnect 1584 */ 1585 if (TempSRBXferredLength >= 1586 pseg->length) 1587 TempSRBXferredLength -= 1588 pseg->length; 1589 else { 1590 /* 1591 * update last time disconnected SG 1592 * list 1593 */ 1594 pseg->length -= 1595 TempSRBXferredLength; 1596 /* residue data length */ 1597 pseg->address += 1598 TempSRBXferredLength; 1599 /* residue data pointer */ 1600 pSRB->SRBSGIndex = SGIndexTemp; 1601 break; 1602 } 1603 pseg++; 1604 } 1605 } 1606 } 1607 } 1608 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1609} 1610 1611 1612static void 1613trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1614{ 1615 u_int16_t ioDir; 1616 /* 1617 * do prepare befor transfer when data out phase 1618 */ 1619 1620 ioDir = XFERDATAOUT; 1621 trm_DataIO_transfer(pACB, pSRB, ioDir); 1622} 1623 1624static void 1625trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1626{ 1627 u_int8_t TempDMAstatus, SGIndexTemp; 1628 u_int16_t scsi_status; 1629 PSEG pseg; 1630 u_long TempSRBXferredLength,dLeftCounter = 0; 1631 1632 scsi_status = *pscsi_status; 1633 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1634 if (scsi_status & PARITYERROR) 1635 pSRB->SRBStatus |= PARITY_ERROR; 1636 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1637 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1638 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1639 while (!(TempDMAstatus & DMAXFERCOMP)) 1640 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1641 pSRB->SRBTotalXferLength = 0; 1642 } else { 1643 /* 1644 * parsing the case: 1645 * when a transfer not yet complete 1646 * but be disconnected by uper layer 1647 * if transfer not yet complete 1648 * there were some data residue in SCSI FIFO or 1649 * SCSI transfer counter not empty 1650 */ 1651 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1652 /* 1653 * data that had transferred length 1654 */ 1655 TempSRBXferredLength = 1656 pSRB->SRBTotalXferLength - dLeftCounter; 1657 /* 1658 * next time to be transferred length 1659 */ 1660 pSRB->SRBTotalXferLength = dLeftCounter; 1661 /* 1662 * parsing from last time disconnect SRBSGIndex 1663 */ 1664 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1665 for (SGIndexTemp = pSRB->SRBSGIndex; 1666 SGIndexTemp < pSRB->SRBSGCount; 1667 SGIndexTemp++) { 1668 /* 1669 * find last time which SG transfer be disconnect 1670 */ 1671 if (TempSRBXferredLength >= pseg->length) 1672 TempSRBXferredLength -= pseg->length; 1673 else { 1674 /* 1675 * update last time disconnected SG list 1676 */ 1677 pseg->length -= TempSRBXferredLength; 1678 /* residue data length */ 1679 pseg->address += TempSRBXferredLength; 1680 /* residue data pointer */ 1681 pSRB->SRBSGIndex = SGIndexTemp; 1682 break; 1683 } 1684 pseg++; 1685 } 1686 } 1687 } 1688 } 1689} 1690 1691static void 1692trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1693{ 1694 u_int16_t ioDir; 1695 /* 1696 * do prepare befor transfer when data in phase 1697 */ 1698 1699 ioDir = XFERDATAIN; 1700 trm_DataIO_transfer(pACB, pSRB, ioDir); 1701} 1702 1703static void 1704trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1705{ 1706 u_int8_t bval; 1707 PDCB pDCB; 1708 1709 pDCB = pSRB->pSRBDCB; 1710 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1711 if (pSRB->SRBTotalXferLength != 0) { 1712 /* 1713 * load what physical address of Scatter/Gather list 1714 table want to be transfer 1715 */ 1716 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1717 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1718 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1719 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1720 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1721 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1722 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1723 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1724 1725 pSRB->SRBState = SRB_DATA_XFER; 1726 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1727 trm_reg_write32( 1728 (pSRB->SRBSGPhyAddr + 1729 ((u_long)pSRB->SRBSGIndex << 3)), 1730 TRMREG_DMA_XLOWADDR); 1731 /* 1732 * load how many bytes in the Scatter/Gather 1733 * list table 1734 */ 1735 trm_reg_write32( 1736 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1737 TRMREG_DMA_XCNT); 1738 /* 1739 * load total transfer length (24bits) max value 1740 * 16Mbyte 1741 */ 1742 trm_reg_write32(pSRB->SRBTotalXferLength, 1743 TRMREG_SCSI_COUNTER); 1744 /* Start DMA transfer */ 1745 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1746 /* Start SCSI transfer */ 1747 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1748 /* it's important for atn stop */ 1749 /* 1750 * SCSI cammand 1751 */ 1752 bval = (ioDir == XFERDATAOUT) ? 1753 SCMD_DMA_OUT : SCMD_DMA_IN; 1754 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1755 } else { 1756 /* xfer pad */ 1757 if (pSRB->SRBSGCount) { 1758 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1759 pSRB->SRBStatus |= OVER_RUN; 1760 } 1761 if (pDCB->SyncPeriod & WIDE_SYNC) 1762 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1763 else 1764 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1765 if (ioDir == XFERDATAOUT) 1766 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1767 else 1768 trm_reg_read16(TRMREG_SCSI_FIFO); 1769 pSRB->SRBState |= SRB_XFERPAD; 1770 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1771 /* it's important for atn stop */ 1772 /* 1773 * SCSI cammand 1774 */ 1775 bval = (ioDir == XFERDATAOUT) ? 1776 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1777 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1778 } 1779 } 1780} 1781 1782static void 1783trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1784{ 1785 1786 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1787 pSRB->SRBState = SRB_COMPLETED; 1788 *pscsi_status = PH_BUS_FREE; 1789 /*.. initial phase*/ 1790 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1791 /* it's important for atn stop */ 1792 /* 1793 * SCSI cammand 1794 */ 1795 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1796} 1797 1798 1799 1800static void 1801trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1802{ 1803 1804 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1805 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1806 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1807 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1808 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1809 } else { 1810 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1811 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1812 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1813 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1814 } 1815 pSRB->SRBState = SRB_STATUS; 1816 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1817 /* it's important for atn stop */ 1818 /* 1819 * SCSI cammand 1820 */ 1821 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1822} 1823 1824/* 1825 *scsiiom 1826 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1827 * stateV = (void *) trm_SCSI_phase0[phase] 1828 * if phase =7 1829 * extended message codes: 1830 * 1831 * code description 1832 * 1833 * 02h Reserved 1834 * 00h MODIFY DATA POINTER 1835 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1836 * 03h WIDE DATA TRANSFER REQUEST 1837 * 04h - 7Fh Reserved 1838 * 80h - FFh Vendor specific 1839 * 1840 */ 1841 1842static void 1843trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1844{ 1845 u_int8_t message_in_code,bIndex,message_in_tag_id; 1846 PDCB pDCB; 1847 PSRB pSRBTemp; 1848 1849 pDCB = pACB->pActiveDCB; 1850 1851 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1852 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1853 if (message_in_code == MSG_DISCONNECT) { 1854 pSRB->SRBState = SRB_DISCONNECT; 1855 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1856 /* it's important for atn stop */ 1857 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1858 /* 1859 * SCSI command 1860 */ 1861 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1862 return; 1863 } else if (message_in_code == MSG_SAVE_PTR) { 1864 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1865 /* it's important for atn stop */ 1866 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1867 /* 1868 * SCSI command 1869 */ 1870 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1871 return; 1872 } else if ((message_in_code == MSG_EXTENDED) || 1873 ((message_in_code >= MSG_SIMPLE_QTAG) && 1874 (message_in_code <= MSG_ORDER_QTAG))) { 1875 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1876 pSRB->MsgInBuf[0] = message_in_code; 1877 /* extended message (01h) */ 1878 pSRB->MsgCnt = 1; 1879 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1880 /* extended message length (n) */ 1881 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1882 /* it's important for atn stop */ 1883 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1884 /* 1885 * SCSI command 1886 */ 1887 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1888 return; 1889 } else if (message_in_code == MSG_REJECT_) { 1890 /* Reject message */ 1891 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1892 /* do wide nego reject */ 1893 pDCB = pSRB->pSRBDCB; 1894 pDCB->SyncMode |= WIDE_NEGO_DONE; 1895 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1896 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1897 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1898 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1899 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1900 /* Set ATN, in case ATN was clear */ 1901 pSRB->SRBState |= SRB_MSGOUT; 1902 trm_reg_write16( 1903 DO_SETATN, 1904 TRMREG_SCSI_CONTROL); 1905 } else { 1906 /* Clear ATN */ 1907 trm_reg_write16( 1908 DO_CLRATN, 1909 TRMREG_SCSI_CONTROL); 1910 } 1911 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1912 /* do sync nego reject */ 1913 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1914 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1915 pDCB = pSRB->pSRBDCB; 1916 pDCB->SyncMode &= 1917 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1918 pDCB->SyncPeriod = 0; 1919 pDCB->SyncOffset = 0; 1920 /* 1921 * 1922 * program SCSI control register 1923 * 1924 */ 1925 trm_reg_write8(pDCB->SyncPeriod, 1926 TRMREG_SCSI_SYNC); 1927 trm_reg_write8(pDCB->SyncOffset, 1928 TRMREG_SCSI_OFFSET); 1929 trm_SetXferRate(pACB,pSRB,pDCB); 1930 } 1931 } 1932 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1933 /* it's important for atn stop */ 1934 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1935 /* 1936 * SCSI command 1937 */ 1938 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1939 return; 1940 } else if (message_in_code == MSG_IGNOREWIDE) { 1941 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1942 trm_reg_read8(TRMREG_SCSI_FIFO); 1943 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1944 /* it's important for atn stop */ 1945 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1946 /* 1947 * SCSI command 1948 */ 1949 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1950 return; 1951 } else { 1952 /* Restore data pointer message */ 1953 /* Save data pointer message */ 1954 /* Completion message */ 1955 /* NOP message */ 1956 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1957 /* it's important for atn stop */ 1958 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1959 /* 1960 * SCSI command 1961 */ 1962 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1963 return; 1964 } 1965 } else { 1966 /* 1967 * Parsing incomming extented messages 1968 */ 1969 *pSRB->pMsgPtr = message_in_code; 1970 pSRB->MsgCnt++; 1971 pSRB->pMsgPtr++; 1972 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1973 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1974 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1975 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1976 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1977 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1978 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1979 /* 1980 * is QUEUE tag message : 1981 * 1982 * byte 0: 1983 * HEAD QUEUE TAG (20h) 1984 * ORDERED QUEUE TAG (21h) 1985 * SIMPLE QUEUE TAG (22h) 1986 * byte 1: 1987 * Queue tag (00h - FFh) 1988 */ 1989 if (pSRB->MsgCnt == 2) { 1990 pSRB->SRBState = 0; 1991 message_in_tag_id = pSRB->MsgInBuf[1]; 1992 pSRB = pDCB->pGoingSRB; 1993 pSRBTemp = pDCB->pGoingLastSRB; 1994 if (pSRB) { 1995 for (;;) { 1996 if (pSRB->TagNumber != 1997 message_in_tag_id) { 1998 if (pSRB == pSRBTemp) { 1999 goto mingx0; 2000 } 2001 pSRB = pSRB->pNextSRB; 2002 } else 2003 break; 2004 } 2005 if (pDCB->DCBFlag & ABORT_DEV_) { 2006 pSRB->SRBState = SRB_ABORT_SENT; 2007 trm_EnableMsgOutAbort1( 2008 pACB, pSRB); 2009 } 2010 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 2011 TRM_DPRINTF("SRB not yet disconnect........ \n "); 2012 goto mingx0; 2013 } 2014 pDCB->pActiveSRB = pSRB; 2015 pSRB->SRBState = SRB_DATA_XFER; 2016 } else { 2017mingx0: 2018 pSRB = &pACB->TmpSRB; 2019 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2020 pDCB->pActiveSRB = pSRB; 2021 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2022 trm_EnableMsgOutAbort2( 2023 pACB, 2024 pSRB); 2025 } 2026 } 2027 *pscsi_status = PH_BUS_FREE; 2028 /* .. initial phase */ 2029 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2030 /* it's important for atn stop */ 2031 /* 2032 * SCSI command 2033 */ 2034 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2035 return; 2036 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2037 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2038 /* 2039 * is Wide data xfer Extended message : 2040 * ====================================== 2041 * WIDE DATA TRANSFER REQUEST 2042 * ====================================== 2043 * byte 0 : Extended message (01h) 2044 * byte 1 : Extended message length (02h) 2045 * byte 2 : WIDE DATA TRANSFER code (03h) 2046 * byte 3 : Transfer width exponent 2047 */ 2048 pDCB = pSRB->pSRBDCB; 2049 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2050 if ((pSRB->MsgInBuf[1] != 2)) { 2051 /* Length is wrong, reject it */ 2052 pDCB->SyncMode &= 2053 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2054 pSRB->MsgCnt = 1; 2055 pSRB->MsgInBuf[0] = MSG_REJECT_; 2056 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2057 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2058 /* it's important for atn stop */ 2059 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2060 /* 2061 * SCSI command 2062 */ 2063 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2064 return; 2065 } 2066 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2067 /* Do wide negoniation */ 2068 if (pSRB->MsgInBuf[3] > 2) { 2069 /* > 32 bit */ 2070 /* reject_msg: */ 2071 pDCB->SyncMode &= 2072 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2073 pSRB->MsgCnt = 1; 2074 pSRB->MsgInBuf[0] = MSG_REJECT_; 2075 trm_reg_write16(DO_SETATN, 2076 TRMREG_SCSI_CONTROL); 2077 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2078 /* it's important for atn stop */ 2079 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2080 /* 2081 * SCSI command 2082 */ 2083 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2084 return; 2085 } 2086 if (pSRB->MsgInBuf[3] == 2) { 2087 pSRB->MsgInBuf[3] = 1; 2088 /* do 16 bits */ 2089 } else { 2090 if (!(pDCB->SyncMode 2091 & WIDE_NEGO_DONE)) { 2092 pSRB->SRBState &= 2093 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2094 pDCB->SyncMode |= 2095 WIDE_NEGO_DONE; 2096 pDCB->SyncMode &= 2097 ~(SYNC_NEGO_DONE | 2098 EN_ATN_STOP | 2099 WIDE_NEGO_ENABLE); 2100 if (pSRB->MsgInBuf[3] != 0) { 2101 /* is Wide data xfer */ 2102 pDCB->SyncPeriod |= 2103 WIDE_SYNC; 2104 pDCB->tinfo.current.width 2105 = MSG_EXT_WDTR_BUS_16_BIT; 2106 pDCB->tinfo.goal.width 2107 = MSG_EXT_WDTR_BUS_16_BIT; 2108 } 2109 } 2110 } 2111 } else 2112 pSRB->MsgInBuf[3] = 0; 2113 pSRB->SRBState |= SRB_MSGOUT; 2114 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2115 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2116 /* it's important for atn stop */ 2117 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2118 /* 2119 * SCSI command 2120 */ 2121 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2122 return; 2123 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2124 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2125 /* 2126 * is 8bit transfer Extended message : 2127 * ================================= 2128 * SYNCHRONOUS DATA TRANSFER REQUEST 2129 * ================================= 2130 * byte 0 : Extended message (01h) 2131 * byte 1 : Extended message length (03) 2132 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2133 * byte 3 : Transfer period factor 2134 * byte 4 : REQ/ACK offset 2135 */ 2136 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2137 if ((pSRB->MsgInBuf[1] != 3) || 2138 (pSRB->MsgInBuf[2] != 1)) { 2139 /* reject_msg: */ 2140 pSRB->MsgCnt = 1; 2141 pSRB->MsgInBuf[0] = MSG_REJECT_; 2142 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2143 *pscsi_status = PH_BUS_FREE; 2144 /* .. initial phase */ 2145 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2146 /* it's important for atn stop */ 2147 /* 2148 * SCSI cammand 2149 */ 2150 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2151 return; 2152 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2153 /* set async */ 2154 pDCB = pSRB->pSRBDCB; 2155 /* disable sync & sync nego */ 2156 pDCB->SyncMode &= 2157 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2158 pDCB->SyncPeriod = 0; 2159 pDCB->SyncOffset = 0; 2160 pDCB->tinfo.goal.period = 0; 2161 pDCB->tinfo.goal.offset = 0; 2162 pDCB->tinfo.current.period = 0; 2163 pDCB->tinfo.current.offset = 0; 2164 pDCB->tinfo.current.width = 2165 MSG_EXT_WDTR_BUS_8_BIT; 2166 /* 2167 * 2168 * program SCSI control register 2169 * 2170 */ 2171 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2172 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2173 trm_SetXferRate(pACB,pSRB,pDCB); 2174 *pscsi_status = PH_BUS_FREE; 2175 /* .. initial phase */ 2176 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2177 /* it's important for atn stop */ 2178 /* 2179 * SCSI cammand 2180 */ 2181 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2182 return; 2183 } else { 2184 /* set sync */ 2185 pDCB = pSRB->pSRBDCB; 2186 pDCB->SyncMode |= 2187 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2188 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2189 /* Transfer period factor */ 2190 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2191 /* REQ/ACK offset */ 2192 if (pACB->AdaptType == 1) { 2193 for(bIndex = 0; bIndex < 7; bIndex++) { 2194 if (pSRB->MsgInBuf[3] <= 2195 dc395u2x_clock_period[bIndex]) { 2196 pDCB->tinfo.goal.period = 2197 dc395u2x_tinfo_period[bIndex]; 2198 pDCB->tinfo.current.period = 2199 dc395u2x_tinfo_period[bIndex]; 2200 pDCB->tinfo.goal.offset = 2201 pDCB->SyncOffset; 2202 pDCB->tinfo.current.offset = 2203 pDCB->SyncOffset; 2204 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2205 break; 2206 } 2207 } 2208 } else { 2209 for(bIndex = 0; bIndex < 7; bIndex++) { 2210 if (pSRB->MsgInBuf[3] <= 2211 dc395x_clock_period[bIndex]) { 2212 pDCB->tinfo.goal.period = 2213 dc395x_tinfo_period[bIndex]; 2214 pDCB->tinfo.current.period = 2215 dc395x_tinfo_period[bIndex]; 2216 pDCB->tinfo.goal.offset = 2217 pDCB->SyncOffset; 2218 pDCB->tinfo.current.offset = 2219 pDCB->SyncOffset; 2220 pDCB->SyncPeriod |= 2221 (bIndex|ALT_SYNC); 2222 break; 2223 } 2224 } 2225 } 2226 /* 2227 * 2228 * program SCSI control register 2229 * 2230 */ 2231 trm_reg_write8(pDCB->SyncPeriod, 2232 TRMREG_SCSI_SYNC); 2233 trm_reg_write8(pDCB->SyncOffset, 2234 TRMREG_SCSI_OFFSET); 2235 trm_SetXferRate(pACB,pSRB,pDCB); 2236 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2237 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2238 /* 2239 ** SCSI command 2240 */ 2241 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2242 return; 2243 } 2244 } 2245 *pscsi_status = PH_BUS_FREE; 2246 /* .. initial phase */ 2247 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2248 /* it's important for atn stop */ 2249 /* 2250 * SCSI cammand 2251 */ 2252 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2253 } 2254} 2255 2256static void 2257trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2258{ 2259 2260 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2261 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2262 if (!(pSRB->SRBState & SRB_MSGIN)) { 2263 pSRB->SRBState &= SRB_DISCONNECT; 2264 pSRB->SRBState |= SRB_MSGIN; 2265 } 2266 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2267 /* it's important for atn stop*/ 2268 /* 2269 * SCSI cammand 2270 */ 2271 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2272} 2273 2274static void 2275trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2276{ 2277 2278} 2279 2280static void 2281trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2282{ 2283 2284} 2285 2286static void 2287trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2288{ 2289 union ccb *pccb; 2290 struct ccb_trans_settings neg; 2291 u_int16_t cnt, i; 2292 u_int8_t bval; 2293 PDCB pDCBTemp; 2294 2295 /* 2296 * set all lun device's period , offset 2297 */ 2298 TRM_DPRINTF("trm_SetXferRate\n"); 2299 pccb = pSRB->pccb; 2300 memset(&neg, 0, sizeof (neg)); 2301 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period; 2302 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset; 2303 neg.xport_specific.spi.valid = 2304 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET; 2305 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2306 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2307 if (!(pDCB->IdentifyMsg & 0x07)) { 2308 pDCBTemp = pACB->pLinkDCB; 2309 cnt = pACB->DeviceCnt; 2310 bval = pDCB->TargetID; 2311 for (i = 0; i < cnt; i++) { 2312 if (pDCBTemp->TargetID == bval) { 2313 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2314 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2315 pDCBTemp->SyncMode = pDCB->SyncMode; 2316 } 2317 pDCBTemp = pDCBTemp->pNextDCB; 2318 } 2319 } 2320 return; 2321} 2322 2323/* 2324 * scsiiom 2325 * trm_Interrupt 2326 * 2327 * 2328 * ---SCSI bus phase 2329 * 2330 * PH_DATA_OUT 0x00 Data out phase 2331 * PH_DATA_IN 0x01 Data in phase 2332 * PH_COMMAND 0x02 Command phase 2333 * PH_STATUS 0x03 Status phase 2334 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2335 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2336 * PH_MSG_OUT 0x06 Message out phase 2337 * PH_MSG_IN 0x07 Message in phase 2338 * 2339 */ 2340static void 2341trm_Disconnect(PACB pACB) 2342{ 2343 PDCB pDCB; 2344 PSRB pSRB, psrb; 2345 u_int16_t i,j, cnt; 2346 u_int target_id,target_lun; 2347 2348 TRM_DPRINTF("trm_Disconnect...............\n "); 2349 2350 pDCB = pACB->pActiveDCB; 2351 if (!pDCB) { 2352 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2353 j = 400; 2354 while (--j) 2355 DELAY(1); 2356 /* 1 msec */ 2357 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2358 TRMREG_SCSI_CONTROL); 2359 return; 2360 } 2361 pSRB = pDCB->pActiveSRB; 2362 /* bug pSRB=0 */ 2363 target_id = pSRB->pccb->ccb_h.target_id; 2364 target_lun = pSRB->pccb->ccb_h.target_lun; 2365 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2366 pACB->pActiveDCB = 0; 2367 pSRB->ScsiPhase = PH_BUS_FREE; 2368 /* SCSI bus free Phase */ 2369 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2370 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2371 pSRB->SRBState = 0; 2372 trm_DoWaitingSRB(pACB); 2373 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2374 pDCB->DCBFlag = 0; 2375 cnt = pDCB->GoingSRBCnt; 2376 pDCB->GoingSRBCnt = 0; 2377 pSRB = pDCB->pGoingSRB; 2378 for (i = 0; i < cnt; i++) { 2379 psrb = pSRB->pNextSRB; 2380 pSRB->pNextSRB = pACB->pFreeSRB; 2381 pACB->pFreeSRB = pSRB; 2382 pSRB = psrb; 2383 } 2384 pDCB->pGoingSRB = 0; 2385 trm_DoWaitingSRB(pACB); 2386 } else { 2387 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2388 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2389 /* Selection time out */ 2390 if (!(pACB->scan_devices[target_id][target_lun]) && 2391 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2392 pSRB->CmdBlock[0] != INQUIRY) { 2393 pSRB->SRBState = SRB_READY; 2394 trm_RewaitSRB(pDCB, pSRB); 2395 } else { 2396 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2397 goto disc1; 2398 } 2399 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2400 /* 2401 * SRB_DISCONNECT 2402 */ 2403 trm_DoWaitingSRB(pACB); 2404 } else if (pSRB->SRBState & SRB_COMPLETED) { 2405disc1: 2406 /* 2407 * SRB_COMPLETED 2408 */ 2409 pDCB->pActiveSRB = 0; 2410 pSRB->SRBState = SRB_FREE; 2411 trm_SRBdone(pACB, pDCB, pSRB); 2412 } 2413 } 2414 return; 2415} 2416 2417static void 2418trm_Reselect(PACB pACB) 2419{ 2420 PDCB pDCB; 2421 PSRB pSRB; 2422 u_int16_t RselTarLunId; 2423 2424 TRM_DPRINTF("trm_Reselect................. \n"); 2425 pDCB = pACB->pActiveDCB; 2426 if (pDCB) { 2427 /* Arbitration lost but Reselection win */ 2428 pSRB = pDCB->pActiveSRB; 2429 pSRB->SRBState = SRB_READY; 2430 trm_RewaitSRB(pDCB, pSRB); 2431 } 2432 /* Read Reselected Target Id and LUN */ 2433 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2434 pDCB = pACB->pLinkDCB; 2435 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2436 /* get pDCB of the reselect id */ 2437 pDCB = pDCB->pNextDCB; 2438 } 2439 2440 pACB->pActiveDCB = pDCB; 2441 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2442 pSRB = &pACB->TmpSRB; 2443 pDCB->pActiveSRB = pSRB; 2444 } else { 2445 pSRB = pDCB->pActiveSRB; 2446 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2447 /* 2448 * abort command 2449 */ 2450 pSRB = &pACB->TmpSRB; 2451 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2452 pDCB->pActiveSRB = pSRB; 2453 trm_EnableMsgOutAbort1(pACB, pSRB); 2454 } else { 2455 if (pDCB->DCBFlag & ABORT_DEV_) { 2456 pSRB->SRBState = SRB_ABORT_SENT; 2457 trm_EnableMsgOutAbort1(pACB, pSRB); 2458 } else 2459 pSRB->SRBState = SRB_DATA_XFER; 2460 } 2461 } 2462 pSRB->ScsiPhase = PH_BUS_FREE; 2463 /* SCSI bus free Phase */ 2464 /* 2465 * Program HA ID, target ID, period and offset 2466 */ 2467 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2468 /* target ID */ 2469 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2470 /* host ID */ 2471 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2472 /* period */ 2473 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2474 /* offset */ 2475 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2476 /* it's important for atn stop*/ 2477 /* 2478 * SCSI cammand 2479 */ 2480 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2481 /* to rls the /ACK signal */ 2482} 2483 2484static void 2485trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2486{ 2487 PSRB psrb; 2488 u_int8_t bval, bval1,status; 2489 union ccb *pccb; 2490 struct ccb_scsiio *pcsio; 2491 PSCSI_INQDATA ptr; 2492 int intflag; 2493 u_int target_id,target_lun; 2494 PDCB pTempDCB; 2495 2496 pccb = pSRB->pccb; 2497 if (pccb == NULL) 2498 return; 2499 pcsio = &pccb->csio; 2500 target_id = pSRB->pccb->ccb_h.target_id; 2501 target_lun = pSRB->pccb->ccb_h.target_lun; 2502 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2503 bus_dmasync_op_t op; 2504 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2505 op = BUS_DMASYNC_POSTREAD; 2506 else 2507 op = BUS_DMASYNC_POSTWRITE; 2508 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2509 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2510 } 2511 /* 2512 * 2513 * target status 2514 * 2515 */ 2516 status = pSRB->TargetStatus; 2517 pcsio->scsi_status=SCSI_STAT_GOOD; 2518 pccb->ccb_h.status = CAM_REQ_CMP; 2519 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2520 /* 2521 * status of auto request sense 2522 */ 2523 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2524 pSRB->AdaptStatus = 0; 2525 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2526 2527 if (status == SCSI_STATUS_CHECK_COND) { 2528 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2529 goto ckc_e; 2530 } 2531 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2532 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2533 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2534 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2535 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2536 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2537 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2538 pcsio->sense_len); 2539 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2540 | CAM_AUTOSNS_VALID; 2541 goto ckc_e; 2542 } 2543 /* 2544 * target status 2545 */ 2546 if (status) { 2547 if (status == SCSI_STATUS_CHECK_COND) { 2548 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2549 TRM_DPRINTF("trm_RequestSense..................\n"); 2550 trm_RequestSense(pACB, pDCB, pSRB); 2551 return; 2552 } 2553 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2554 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2555 goto ckc_e; 2556 } else if (status == SCSI_STAT_QUEUEFULL) { 2557 bval = (u_int8_t) pDCB->GoingSRBCnt; 2558 bval--; 2559 pDCB->MaxActiveCommandCnt = bval; 2560 trm_RewaitSRB(pDCB, pSRB); 2561 pSRB->AdaptStatus = 0; 2562 pSRB->TargetStatus = 0; 2563 return; 2564 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2565 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2566 pSRB->TargetStatus = 0; 2567 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2568 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2569 } else if (status == SCSI_STAT_BUSY) { 2570 TRM_DPRINTF("trm: target busy at %s %d\n", 2571 __FILE__, __LINE__); 2572 pcsio->scsi_status = SCSI_STAT_BUSY; 2573 pccb->ccb_h.status = CAM_SCSI_BUSY; 2574 return; 2575 /* The device busy, try again later? */ 2576 } else if (status == SCSI_STAT_RESCONFLICT) { 2577 TRM_DPRINTF("trm: target reserved at %s %d\n", 2578 __FILE__, __LINE__); 2579 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2580 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2581 return; 2582 } else { 2583 pSRB->AdaptStatus = 0; 2584 if (pSRB->RetryCnt) { 2585 pSRB->RetryCnt--; 2586 pSRB->TargetStatus = 0; 2587 pSRB->SRBSGIndex = 0; 2588 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2589 /* 2590 * If trm_StartSCSI return 1 : 2591 * current interrupt status is interrupt 2592 * disreenable 2593 * It's said that SCSI processor has more 2594 * one SRB need to do 2595 */ 2596 trm_RewaitSRB(pDCB, pSRB); 2597 } 2598 return; 2599 } else { 2600 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2601 __FILE__, __LINE__); 2602 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2603 } 2604 } 2605 } else { 2606 /* 2607 * process initiator status.......................... 2608 * Adapter (initiator) status 2609 */ 2610 status = pSRB->AdaptStatus; 2611 if (status & H_OVER_UNDER_RUN) { 2612 pSRB->TargetStatus = 0; 2613 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2614 /* Illegal length (over/under run) */ 2615 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2616 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2617 __FILE__, __LINE__); 2618 pDCB->tinfo.goal.period = 0; 2619 pDCB->tinfo.goal.offset = 0; 2620 /* Driver failed to perform operation */ 2621 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2622 } else { 2623 /* no error */ 2624 pSRB->AdaptStatus = 0; 2625 pSRB->TargetStatus = 0; 2626 pccb->ccb_h.status = CAM_REQ_CMP; 2627 /* there is no error, (sense is invalid) */ 2628 } 2629 } 2630ckc_e: 2631 if (pACB->scan_devices[target_id][target_lun]) { 2632 /* 2633 * if SCSI command in "scan devices" duty 2634 */ 2635 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2636 pACB->scan_devices[target_id][target_lun] = 0; 2637 /* SCSI command phase :test unit ready */ 2638 else if (pSRB->CmdBlock[0] == INQUIRY) { 2639 /* 2640 * SCSI command phase :inquiry scsi device data 2641 * (type,capacity,manufacture.... 2642 */ 2643 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2644 goto NO_DEV; 2645 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2646 /* page fault */ 2647 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2648 ptr->DevType); 2649 bval1 = ptr->DevType & SCSI_DEVTYPE; 2650 if (bval1 == SCSI_NODEV) { 2651NO_DEV: 2652 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2653 target_id, 2654 target_lun); 2655 intflag = splcam(); 2656 pACB->scan_devices[target_id][target_lun] = 0; 2657 /* no device set scan device flag =0*/ 2658 /* pDCB Q link */ 2659 /* move the head of DCB to tempDCB*/ 2660 pTempDCB=pACB->pLinkDCB; 2661 /* search current DCB for pass link */ 2662 while (pTempDCB->pNextDCB != pDCB) { 2663 pTempDCB = pTempDCB->pNextDCB; 2664 } 2665 /* 2666 * when the current DCB found than connect 2667 * current DCB tail 2668 */ 2669 /* to the DCB tail that before current DCB */ 2670 pTempDCB->pNextDCB = pDCB->pNextDCB; 2671 /* 2672 * if there was only one DCB ,connect his tail 2673 * to his head 2674 */ 2675 if (pACB->pLinkDCB == pDCB) 2676 pACB->pLinkDCB = pTempDCB->pNextDCB; 2677 if (pACB->pDCBRunRobin == pDCB) 2678 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2679 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2680 pACB->DeviceCnt--; 2681 if (pACB->DeviceCnt == 0) { 2682 pACB->pLinkDCB = NULL; 2683 pACB->pDCBRunRobin = NULL; 2684 } 2685 splx(intflag); 2686 } else { 2687#ifdef trm_DEBUG1 2688 int j; 2689 for (j = 0; j < 28; j++) { 2690 TRM_DPRINTF("ptr=%2x ", 2691 ((u_int8_t *)ptr)[j]); 2692 } 2693#endif 2694 pDCB->DevType = bval1; 2695 if (bval1 == SCSI_DASD || 2696 bval1 == SCSI_OPTICAL) { 2697 if ((((ptr->Vers & 0x07) >= 2) || 2698 ((ptr->RDF & 0x0F) == 2)) && 2699 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2700 (pDCB->DevMode & TAG_QUEUING_) && 2701 (pDCB->DevMode & EN_DISCONNECT_)) { 2702 if (pDCB->DevMode & 2703 TAG_QUEUING_) { 2704 pDCB-> 2705 MaxActiveCommandCnt = 2706 pACB->TagMaxNum; 2707 pDCB->SyncMode |= 2708 EN_TAG_QUEUING; 2709 pDCB->tinfo.disc_tag |= 2710 TRM_CUR_TAGENB; 2711 } else { 2712 pDCB->SyncMode |= 2713 EN_ATN_STOP; 2714 pDCB->tinfo.disc_tag &= 2715 ~TRM_CUR_TAGENB; 2716 } 2717 } 2718 } 2719 } 2720 /* pSRB->CmdBlock[0] == INQUIRY */ 2721 } 2722 /* pACB->scan_devices[target_id][target_lun] */ 2723 } 2724 intflag = splcam(); 2725 /* ReleaseSRB(pDCB, pSRB); */ 2726 if (pSRB == pDCB->pGoingSRB) 2727 pDCB->pGoingSRB = pSRB->pNextSRB; 2728 else { 2729 psrb = pDCB->pGoingSRB; 2730 while (psrb->pNextSRB != pSRB) { 2731 psrb = psrb->pNextSRB; 2732 } 2733 psrb->pNextSRB = pSRB->pNextSRB; 2734 if (pSRB == pDCB->pGoingLastSRB) { 2735 pDCB->pGoingLastSRB = psrb; 2736 } 2737 } 2738 pSRB->pNextSRB = pACB->pFreeSRB; 2739 pACB->pFreeSRB = pSRB; 2740 pDCB->GoingSRBCnt--; 2741 trm_DoWaitingSRB(pACB); 2742 2743 splx(intflag); 2744 /* Notify cmd done */ 2745 xpt_done (pccb); 2746} 2747 2748static void 2749trm_DoingSRB_Done(PACB pACB) 2750{ 2751 PDCB pDCB, pdcb; 2752 PSRB psrb, psrb2; 2753 u_int16_t cnt, i; 2754 union ccb *pccb; 2755 2756 pDCB = pACB->pLinkDCB; 2757 if (pDCB == NULL) 2758 return; 2759 pdcb = pDCB; 2760 do { 2761 cnt = pdcb->GoingSRBCnt; 2762 psrb = pdcb->pGoingSRB; 2763 for (i = 0; i < cnt; i++) { 2764 psrb2 = psrb->pNextSRB; 2765 pccb = psrb->pccb; 2766 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2767 /* ReleaseSRB(pDCB, pSRB); */ 2768 psrb->pNextSRB = pACB->pFreeSRB; 2769 pACB->pFreeSRB = psrb; 2770 xpt_done(pccb); 2771 psrb = psrb2; 2772 } 2773 pdcb->GoingSRBCnt = 0;; 2774 pdcb->pGoingSRB = NULL; 2775 pdcb = pdcb->pNextDCB; 2776 } 2777 while (pdcb != pDCB); 2778} 2779 2780static void 2781trm_ResetSCSIBus(PACB pACB) 2782{ 2783 int intflag; 2784 2785 intflag = splcam(); 2786 pACB->ACBFlag |= RESET_DEV; 2787 2788 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2789 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2790 splx(intflag); 2791 return; 2792} 2793 2794static void 2795trm_ScsiRstDetect(PACB pACB) 2796{ 2797 int intflag; 2798 u_long wlval; 2799 2800 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2801 wlval = 1000; 2802 while (--wlval) 2803 DELAY(1000); 2804 intflag = splcam(); 2805 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2806 2807 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2808 2809 if (pACB->ACBFlag & RESET_DEV) 2810 pACB->ACBFlag |= RESET_DONE; 2811 else { 2812 pACB->ACBFlag |= RESET_DETECT; 2813 trm_ResetDevParam(pACB); 2814 /* trm_DoingSRB_Done(pACB); ???? */ 2815 trm_RecoverSRB(pACB); 2816 pACB->pActiveDCB = NULL; 2817 pACB->ACBFlag = 0; 2818 trm_DoWaitingSRB(pACB); 2819 } 2820 splx(intflag); 2821 return; 2822} 2823 2824static void 2825trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2826{ 2827 union ccb *pccb; 2828 struct ccb_scsiio *pcsio; 2829 2830 pccb = pSRB->pccb; 2831 pcsio = &pccb->csio; 2832 2833 pSRB->SRBFlag |= AUTO_REQSENSE; 2834 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2835 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2836 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2837 pSRB->SRBSGCount); 2838 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2839 2840 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2841 pSRB->AdaptStatus = 0; 2842 pSRB->TargetStatus = 0; 2843 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2844 2845 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2846 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2847 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2848 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2849 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2850 pSRB->SRBSGCount = 1; 2851 pSRB->SRBSGIndex = 0; 2852 2853 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2854 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2855 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2856 pSRB->ScsiCmdLen = 6; 2857 2858 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2859 /* 2860 * If trm_StartSCSI return 1 : 2861 * current interrupt status is interrupt disreenable 2862 * It's said that SCSI processor has more one SRB need to do 2863 */ 2864 trm_RewaitSRB(pDCB, pSRB); 2865} 2866 2867static void 2868trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2869{ 2870 2871 pSRB->MsgCnt = 1; 2872 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2873} 2874 2875static void 2876trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2877{ 2878 2879 pSRB->MsgOutBuf[0] = MSG_ABORT; 2880 trm_EnableMsgOutAbort2(pACB, pSRB); 2881} 2882 2883static void 2884trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2885{ 2886 PNVRAMTYPE pEEpromBuf; 2887 u_int8_t bval,PeriodIndex; 2888 u_int target_id,target_lun; 2889 PDCB pTempDCB; 2890 int intflag; 2891 2892 target_id = i; 2893 target_lun = j; 2894 2895 /* 2896 * Using the lun 0 device to init other DCB first, if the device 2897 * has been initialized. 2898 * I don't want init sync arguments one by one, it is the same. 2899 */ 2900 if (target_lun != 0 && 2901 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2902 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2903 sizeof(TRM_DCB)); 2904 intflag = splcam(); 2905 if (pACB->pLinkDCB == 0) { 2906 pACB->pLinkDCB = pDCB; 2907 /* 2908 * RunRobin impersonate the role 2909 * that let each device had good proportion 2910 * about SCSI command proceeding 2911 */ 2912 pACB->pDCBRunRobin = pDCB; 2913 pDCB->pNextDCB = pDCB; 2914 } else { 2915 pTempDCB=pACB->pLinkDCB; 2916 /* search the last nod of DCB link */ 2917 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2918 pTempDCB = pTempDCB->pNextDCB; 2919 /* connect current DCB with last DCB tail */ 2920 pTempDCB->pNextDCB = pDCB; 2921 /* connect current DCB tail to this DCB Q head */ 2922 pDCB->pNextDCB=pACB->pLinkDCB; 2923 } 2924 splx(intflag); 2925 2926 pACB->DeviceCnt++; 2927 pDCB->TargetID = target_id; 2928 pDCB->TargetLUN = target_lun; 2929 pDCB->pWaitingSRB = NULL; 2930 pDCB->pGoingSRB = NULL; 2931 pDCB->GoingSRBCnt = 0; 2932 pDCB->pActiveSRB = NULL; 2933 pDCB->MaxActiveCommandCnt = 1; 2934 pDCB->DCBFlag = 0; 2935 pDCB->DCBstatus |= DS_IN_QUEUE; 2936 /* $$$$$$$ */ 2937 pEEpromBuf = &trm_eepromBuf[unit]; 2938 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2939 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2940 /* $$$$$$$ */ 2941 /* 2942 * disconnect enable ? 2943 */ 2944 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2945 bval = 0xC0; 2946 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2947 } else { 2948 bval = 0x80; 2949 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2950 } 2951 bval |= target_lun; 2952 pDCB->IdentifyMsg = bval; 2953 if (target_lun != 0 && 2954 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2955 return; 2956 /* $$$$$$$ */ 2957 /* 2958 * tag Qing enable ? 2959 */ 2960 if (pDCB->DevMode & TAG_QUEUING_) { 2961 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2962 } else 2963 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2964 /* $$$$$$$ */ 2965 /* 2966 * wide nego ,sync nego enable ? 2967 */ 2968 pDCB->SyncPeriod = 0; 2969 pDCB->SyncOffset = 0; 2970 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2971 if (pACB->AdaptType==1) {/* is U2? */ 2972 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2973 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2974 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2975 } else { 2976 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2977 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2978 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2979 } 2980 pDCB->SyncMode = 0; 2981 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2982 (pACB->Config & HCC_WIDE_CARD)) 2983 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2984 /* enable wide nego */ 2985 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2986 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2987 /* enable sync nego */ 2988 /* $$$$$$$ */ 2989 /* 2990 * Fill in tinfo structure. 2991 */ 2992 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2993 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2994 2995 pDCB->tinfo.current.period = 0; 2996 pDCB->tinfo.current.offset = 0; 2997 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2998} 2999 3000static void 3001trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3002{ 3003 PSRB pSRB; 3004 3005 pSRB=(PSRB) arg; 3006 pSRB->SRBSGPhyAddr=segs->ds_addr; 3007 return; 3008} 3009 3010static void 3011trm_destroySRB(PACB pACB) 3012{ 3013 PSRB pSRB; 3014 3015 pSRB = pACB->pFreeSRB; 3016 while (pSRB) { 3017 if (pSRB->sg_dmamap) { 3018 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 3019 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 3020 pSRB->sg_dmamap); 3021 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap); 3022 } 3023 if (pSRB->dmamap) 3024 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 3025 pSRB = pSRB->pNextSRB; 3026 } 3027} 3028 3029static int 3030trm_initSRB(PACB pACB) 3031{ 3032 u_int16_t i; 3033 PSRB pSRB; 3034 int error; 3035 3036 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 3037 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3038 3039 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 3040 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3041 return ENXIO; 3042 } 3043 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3044 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3045 trm_srbmapSG, pSRB, /*flags*/0); 3046 if (i != TRM_MAX_SRB_CNT - 1) { 3047 /* 3048 * link all SRB 3049 */ 3050 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3051 } else { 3052 /* 3053 * load NULL to NextSRB of the last SRB 3054 */ 3055 pSRB->pNextSRB = NULL; 3056 } 3057 pSRB->TagNumber = i; 3058 3059 /* 3060 * Create the dmamap. This is no longer optional! 3061 */ 3062 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 3063 &pSRB->dmamap)) != 0) 3064 return (error); 3065 3066 } 3067 return (0); 3068} 3069 3070 3071 3072 3073static void 3074trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3075{ 3076 PNVRAMTYPE pEEpromBuf; 3077 3078 pEEpromBuf = &trm_eepromBuf[unit]; 3079 pACB->max_id = 15; 3080 3081 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3082 pACB->max_lun = 7; 3083 else 3084 pACB->max_lun = 0; 3085 3086 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3087 pACB->max_id, pACB->max_lun); 3088 pACB->pLinkDCB = NULL; 3089 pACB->pDCBRunRobin = NULL; 3090 pACB->pActiveDCB = NULL; 3091 pACB->AdapterUnit = (u_int8_t)unit; 3092 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3093 pACB->AdaptSCSILUN = 0; 3094 pACB->DeviceCnt = 0; 3095 pACB->AdaptType = adaptType; 3096 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3097 pACB->ACBFlag = 0; 3098 return; 3099} 3100 3101static void 3102NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3103{ 3104 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3105 u_int8_t bAddr; 3106 3107 /* Enable SEEPROM */ 3108 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3109 TRMREG_GEN_CONTROL); 3110 /* 3111 * Write enable 3112 */ 3113 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3114 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3115 NVRAM_trm_wait_30us(pACB); 3116 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3117 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3118 } 3119 /* 3120 * Write disable 3121 */ 3122 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3123 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3124 NVRAM_trm_wait_30us(pACB); 3125 /* Disable SEEPROM */ 3126 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3127 TRMREG_GEN_CONTROL); 3128 return; 3129} 3130 3131static void 3132NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3133{ 3134 int i; 3135 u_int8_t bSendData; 3136 /* 3137 * Send write command & address 3138 */ 3139 3140 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3141 /* 3142 * Write data 3143 */ 3144 for (i = 0; i < 8; i++, bData <<= 1) { 3145 bSendData = NVR_SELECT; 3146 if (bData & 0x80) 3147 /* Start from bit 7 */ 3148 bSendData |= NVR_BITOUT; 3149 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3150 NVRAM_trm_wait_30us(pACB); 3151 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3152 NVRAM_trm_wait_30us(pACB); 3153 } 3154 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3155 NVRAM_trm_wait_30us(pACB); 3156 /* 3157 * Disable chip select 3158 */ 3159 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3160 NVRAM_trm_wait_30us(pACB); 3161 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3162 NVRAM_trm_wait_30us(pACB); 3163 /* 3164 * Wait for write ready 3165 */ 3166 while (1) { 3167 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3168 NVRAM_trm_wait_30us(pACB); 3169 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3170 NVRAM_trm_wait_30us(pACB); 3171 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3172 break; 3173 } 3174 } 3175 /* 3176 * Disable chip select 3177 */ 3178 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3179 return; 3180} 3181 3182static void 3183NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3184{ 3185 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3186 u_int8_t bAddr; 3187 3188 /* 3189 * Enable SEEPROM 3190 */ 3191 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3192 TRMREG_GEN_CONTROL); 3193 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3194 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3195 /* 3196 * Disable SEEPROM 3197 */ 3198 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3199 TRMREG_GEN_CONTROL); 3200 return; 3201} 3202 3203static u_int8_t 3204NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3205{ 3206 int i; 3207 u_int8_t bReadData, bData = 0; 3208 /* 3209 * Send read command & address 3210 */ 3211 3212 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3213 3214 for (i = 0; i < 8; i++) { 3215 /* 3216 * Read data 3217 */ 3218 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3219 NVRAM_trm_wait_30us(pACB); 3220 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3221 /* 3222 * Get data bit while falling edge 3223 */ 3224 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3225 bData <<= 1; 3226 if (bReadData & NVR_BITIN) { 3227 bData |= 1; 3228 } 3229 NVRAM_trm_wait_30us(pACB); 3230 } 3231 /* 3232 * Disable chip select 3233 */ 3234 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3235 return (bData); 3236} 3237 3238static void 3239NVRAM_trm_wait_30us(PACB pACB) 3240{ 3241 3242 /* ScsiPortStallExecution(30); wait 30 us */ 3243 trm_reg_write8(5, TRMREG_GEN_TIMER); 3244 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3245 return; 3246} 3247 3248static void 3249NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3250{ 3251 int i; 3252 u_int8_t bSendData; 3253 3254 for (i = 0; i < 3; i++, bCmd <<= 1) { 3255 /* 3256 * Program SB+OP code 3257 */ 3258 bSendData = NVR_SELECT; 3259 if (bCmd & 0x04) 3260 bSendData |= NVR_BITOUT; 3261 /* start from bit 2 */ 3262 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3263 NVRAM_trm_wait_30us(pACB); 3264 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3265 NVRAM_trm_wait_30us(pACB); 3266 } 3267 for (i = 0; i < 7; i++, bAddr <<= 1) { 3268 /* 3269 * Program address 3270 */ 3271 bSendData = NVR_SELECT; 3272 if (bAddr & 0x40) 3273 /* Start from bit 6 */ 3274 bSendData |= NVR_BITOUT; 3275 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3276 NVRAM_trm_wait_30us(pACB); 3277 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3278 NVRAM_trm_wait_30us(pACB); 3279 } 3280 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3281 NVRAM_trm_wait_30us(pACB); 3282} 3283 3284static void 3285trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3286{ 3287 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3288 u_int16_t wAddr, wCheckSum; 3289 u_long dAddr, *dpEeprom; 3290 3291 NVRAM_trm_read_all(pEEpromBuf,pACB); 3292 wCheckSum = 0; 3293 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3294 wAddr < 64; wAddr++, wpEeprom++) { 3295 wCheckSum += *wpEeprom; 3296 } 3297 if (wCheckSum != 0x1234) { 3298 /* 3299 * Checksum error, load default 3300 */ 3301 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3302 pEEpromBuf->NvramSubVendorID[1] = 3303 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3304 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3305 pEEpromBuf->NvramSubSysID[1] = 3306 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3307 pEEpromBuf->NvramSubClass = 0x00; 3308 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3309 pEEpromBuf->NvramVendorID[1] = 3310 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3311 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3312 pEEpromBuf->NvramDeviceID[1] = 3313 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3314 pEEpromBuf->NvramReserved = 0x00; 3315 3316 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3317 dAddr < 16; dAddr++, dpEeprom++) { 3318 *dpEeprom = 0x00000077; 3319 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3320 } 3321 3322 *dpEeprom++ = 0x04000F07; 3323 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3324 *dpEeprom++ = 0x00000015; 3325 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3326 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3327 *dpEeprom = 0x00; 3328 pEEpromBuf->NvramCheckSum = 0x00; 3329 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3330 wAddr < 63; wAddr++, wpEeprom++) 3331 wCheckSum += *wpEeprom; 3332 *wpEeprom = 0x1234 - wCheckSum; 3333 NVRAM_trm_write_all(pEEpromBuf,pACB); 3334 } 3335 return; 3336} 3337static int 3338trm_initAdapter(PACB pACB, u_int16_t unit) 3339{ 3340 PNVRAMTYPE pEEpromBuf; 3341 u_int16_t wval; 3342 u_int8_t bval; 3343 3344 pEEpromBuf = &trm_eepromBuf[unit]; 3345 3346 /* 250ms selection timeout */ 3347 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3348 /* Mask all the interrupt */ 3349 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3350 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3351 /* Reset SCSI module */ 3352 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3353 /* program configuration 0 */ 3354 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3355 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3356 pACB->Config |= HCC_WIDE_CARD; 3357 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3358 pACB->Config |= HCC_SCSI_RESET; 3359 if (pACB->Config & HCC_PARITY) 3360 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3361 else 3362 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3363 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3364 /* program configuration 1 */ 3365 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3366 /* program Host ID */ 3367 bval = pEEpromBuf->NvramScsiId; 3368 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3369 /* set ansynchronous transfer */ 3370 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3371 /* Trun LED control off*/ 3372 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3373 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3374 /* DMA config */ 3375 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3376 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3377 /* Clear pending interrupt status */ 3378 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3379 /* Enable SCSI interrupt */ 3380 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3381 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3382 return (0); 3383} 3384 3385static void 3386trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3387{ 3388 PACB pACB; 3389 3390 pACB = (PACB)arg; 3391 pACB->srb_physbase = segs->ds_addr; 3392} 3393 3394static void 3395trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3396{ 3397 bus_addr_t *baddr; 3398 3399 baddr = (bus_addr_t *)arg; 3400 *baddr = segs->ds_addr; 3401} 3402 3403static PACB 3404trm_init(u_int16_t unit, device_t dev) 3405{ 3406 PACB pACB; 3407 int rid = PCIR_BAR(0), i = 0, j = 0; 3408 u_int16_t adaptType = 0; 3409 3410 pACB = (PACB) device_get_softc(dev); 3411 if (!pACB) { 3412 printf("trm%d: cannot allocate ACB !\n", unit); 3413 return (NULL); 3414 } 3415 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3416 &rid, RF_ACTIVE); 3417 if (pACB->iores == NULL) { 3418 printf("trm_init: bus_alloc_resource failed!\n"); 3419 return (NULL); 3420 } 3421 switch (pci_get_devid(dev)) { 3422 case PCI_DEVICEID_TRMS1040: 3423 adaptType = 0; 3424 break; 3425 case PCI_DEVICEID_TRMS2080: 3426 adaptType = 1; 3427 break; 3428 default: 3429 printf("trm_init %d: unknown adapter type!\n", unit); 3430 goto bad; 3431 } 3432 pACB->dev = dev; 3433 pACB->tag = rman_get_bustag(pACB->iores); 3434 pACB->bsh = rman_get_bushandle(pACB->iores); 3435 if (bus_dma_tag_create( 3436 /*parent_dmat*/ pACB->parent_dmat, 3437 /*alignment*/ 1, 3438 /*boundary*/ 0, 3439 /*lowaddr*/ BUS_SPACE_MAXADDR, 3440 /*highaddr*/ BUS_SPACE_MAXADDR, 3441 /*filter*/ NULL, 3442 /*filterarg*/ NULL, 3443 /*maxsize*/ MAXBSIZE, 3444 /*nsegments*/ TRM_NSEG, 3445 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3446 /*flags*/ BUS_DMA_ALLOCNOW, 3447 /*lockfunc*/ busdma_lock_mutex, 3448 /*lockarg*/ &Giant, 3449 /* dmat */ &pACB->buffer_dmat) != 0) 3450 goto bad; 3451 /* DMA tag for our ccb structures */ 3452 if (bus_dma_tag_create( 3453 /*parent_dmat*/pACB->parent_dmat, 3454 /*alignment*/ 1, 3455 /*boundary*/ 0, 3456 /*lowaddr*/ BUS_SPACE_MAXADDR, 3457 /*highaddr*/ BUS_SPACE_MAXADDR, 3458 /*filter*/ NULL, 3459 /*filterarg*/ NULL, 3460 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3461 /*nsegments*/ 1, 3462 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3463 /*flags*/ 0, 3464 /*lockfunc*/ busdma_lock_mutex, 3465 /*lockarg*/ &Giant, 3466 /*dmat*/ &pACB->srb_dmat) != 0) { 3467 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3468 goto bad; 3469 } 3470 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3471 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3472 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3473 goto bad; 3474 } 3475 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3476 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3477 /* flags */0); 3478 /* Create, allocate, and map DMA buffers for autosense data */ 3479 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3480 /*boundary*/0, 3481 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3482 /*highaddr*/BUS_SPACE_MAXADDR, 3483 /*filter*/NULL, /*filterarg*/NULL, 3484 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3485 /*nsegments*/1, 3486 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3487 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3488 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3489 if (bootverbose) 3490 device_printf(dev, "cannot create sense buffer dmat\n"); 3491 goto bad; 3492 } 3493 3494 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3495 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3496 goto bad; 3497 3498 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3499 pACB->sense_buffers, 3500 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3501 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3502 3503 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3504 trm_initACB(pACB, adaptType, unit); 3505 for (i = 0; i < (pACB->max_id + 1); i++) { 3506 if (pACB->AdaptSCSIID == i) 3507 continue; 3508 for(j = 0; j < (pACB->max_lun + 1); j++) { 3509 pACB->scan_devices[i][j] = 1; 3510 /* we assume we need to scan all devices */ 3511 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3512 } 3513 } 3514 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3515 if (bus_dma_tag_create( 3516 /*parent_dmat*/NULL, 3517 /*alignment*/ 1, 3518 /*boundary*/ 0, 3519 /*lowaddr*/ BUS_SPACE_MAXADDR, 3520 /*highaddr*/ BUS_SPACE_MAXADDR, 3521 /*filter*/ NULL, 3522 /*filterarg*/ NULL, 3523 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3524 /*nsegments*/ 1, 3525 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3526 /*flags*/ 0, 3527 /*lockfunc*/ busdma_lock_mutex, 3528 /*lockarg*/ &Giant, 3529 /*dmat*/ &pACB->sg_dmat) != 0) 3530 goto bad; 3531 3532 if (trm_initSRB(pACB)) { 3533 printf("trm_initSRB: error\n"); 3534 goto bad; 3535 } 3536 if (trm_initAdapter(pACB, unit)) { 3537 printf("trm_initAdapter: initial ERROR\n"); 3538 goto bad; 3539 } 3540 return (pACB); 3541bad: 3542 if (pACB->iores) 3543 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3544 pACB->iores); 3545 if (pACB->sense_dmamap) { 3546 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3547 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3548 pACB->sense_dmamap); 3549 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3550 } 3551 if (pACB->sense_dmat) 3552 bus_dma_tag_destroy(pACB->sense_dmat); 3553 if (pACB->sg_dmat) { 3554 trm_destroySRB(pACB); 3555 bus_dma_tag_destroy(pACB->sg_dmat); 3556 } 3557 if (pACB->srb_dmamap) { 3558 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3559 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3560 pACB->srb_dmamap); 3561 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3562 } 3563 if (pACB->srb_dmat) 3564 bus_dma_tag_destroy(pACB->srb_dmat); 3565 if (pACB->buffer_dmat) 3566 bus_dma_tag_destroy(pACB->buffer_dmat); 3567 return (NULL); 3568} 3569 3570static int 3571trm_attach(device_t dev) 3572{ 3573 struct cam_devq *device_Q; 3574 u_long device_id; 3575 PACB pACB = 0; 3576 int rid = 0; 3577 int unit = device_get_unit(dev); 3578 3579 device_id = pci_get_devid(dev); 3580 /* 3581 * These cards do not allow memory mapped accesses 3582 */ 3583 if ((pACB = trm_init((u_int16_t) unit, 3584 dev)) == NULL) { 3585 printf("trm%d: trm_init error!\n",unit); 3586 return (ENXIO); 3587 } 3588 /* After setting up the adapter, map our interrupt */ 3589 /* 3590 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3591 * start queue to reset to the idle loop. 3592 * Create device queue of SIM(s) 3593 * (MAX_START_JOB - 1) : max_sim_transactions 3594 */ 3595 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3596 RF_SHAREABLE | RF_ACTIVE); 3597 if (pACB->irq == NULL || 3598 bus_setup_intr(dev, pACB->irq, 3599 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3600 printf("trm%d: register Interrupt handler error!\n", unit); 3601 goto bad; 3602 } 3603 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3604 if (device_Q == NULL){ 3605 printf("trm%d: device_Q == NULL !\n",unit); 3606 goto bad; 3607 } 3608 /* 3609 * Now tell the generic SCSI layer 3610 * about our bus. 3611 * If this is the xpt layer creating a sim, then it's OK 3612 * to wait for an allocation. 3613 * XXX Should we pass in a flag to indicate that wait is OK? 3614 * 3615 * SIM allocation 3616 * 3617 * SCSI Interface Modules 3618 * The sim driver creates a sim for each controller. The sim device 3619 * queue is separately created in order to allow resource sharing betwee 3620 * sims. For instance, a driver may create one sim for each channel of 3621 * a multi-channel controller and use the same queue for each channel. 3622 * In this way, the queue resources are shared across all the channels 3623 * of the multi-channel controller. 3624 * trm_action : sim_action_func 3625 * trm_poll : sim_poll_func 3626 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3627 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3628 * pACB->unit : unit 3629 * 1 : max_dev_transactions 3630 * MAX_TAGS : max_tagged_dev_transactions 3631 * 3632 * *******Construct our first channel SIM entry 3633 */ 3634 pACB->psim = cam_sim_alloc(trm_action, 3635 trm_poll, 3636 "trm", 3637 pACB, 3638 unit, 3639 1, 3640 TRM_MAX_TAGS_CMD_QUEUE, 3641 device_Q); 3642 if (pACB->psim == NULL) { 3643 printf("trm%d: SIM allocate fault !\n",unit); 3644 cam_simq_free(device_Q); /* SIM allocate fault*/ 3645 goto bad; 3646 } 3647 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3648 printf("trm%d: xpt_bus_register fault !\n",unit); 3649 goto bad; 3650 } 3651 if (xpt_create_path(&pACB->ppath, 3652 NULL, 3653 cam_sim_path(pACB->psim), 3654 CAM_TARGET_WILDCARD, 3655 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3656 printf("trm%d: xpt_create_path fault !\n",unit); 3657 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3658 goto bad; 3659 } 3660 return (0); 3661bad: 3662 if (pACB->iores) 3663 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3664 pACB->iores); 3665 if (pACB->sg_dmat) { 3666 trm_destroySRB(pACB); 3667 bus_dma_tag_destroy(pACB->sg_dmat); 3668 } 3669 3670 if (pACB->srb_dmamap) { 3671 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3672 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3673 pACB->srb_dmamap); 3674 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3675 } 3676 if (pACB->srb_dmat) 3677 bus_dma_tag_destroy(pACB->srb_dmat); 3678 if (pACB->sense_dmamap) { 3679 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3680 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3681 pACB->sense_dmamap); 3682 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3683 } 3684 if (pACB->sense_dmat) 3685 bus_dma_tag_destroy(pACB->sense_dmat); 3686 if (pACB->buffer_dmat) 3687 bus_dma_tag_destroy(pACB->buffer_dmat); 3688 if (pACB->ih) 3689 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3690 if (pACB->irq) 3691 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3692 if (pACB->psim) 3693 cam_sim_free(pACB->psim, TRUE); 3694 3695 return (ENXIO); 3696 3697} 3698 3699/* 3700* pci_device 3701* trm_probe (device_t tag, pcidi_t type) 3702* 3703*/ 3704static int 3705trm_probe(device_t dev) 3706{ 3707 switch (pci_get_devid(dev)) { 3708 case PCI_DEVICEID_TRMS1040: 3709 device_set_desc(dev, 3710 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3711 return (BUS_PROBE_DEFAULT); 3712 case PCI_DEVICEID_TRMS2080: 3713 device_set_desc(dev, 3714 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3715 return (BUS_PROBE_DEFAULT); 3716 default: 3717 return (ENXIO); 3718 } 3719} 3720 3721static int 3722trm_detach(device_t dev) 3723{ 3724 PACB pACB = device_get_softc(dev); 3725 3726 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3727 trm_destroySRB(pACB); 3728 bus_dma_tag_destroy(pACB->sg_dmat); 3729 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3730 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3731 pACB->srb_dmamap); 3732 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3733 bus_dma_tag_destroy(pACB->srb_dmat); 3734 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3735 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3736 pACB->sense_dmamap); 3737 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3738 bus_dma_tag_destroy(pACB->sense_dmat); 3739 bus_dma_tag_destroy(pACB->buffer_dmat); 3740 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3741 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3742 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3743 xpt_free_path(pACB->ppath); 3744 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3745 cam_sim_free(pACB->psim, TRUE); 3746 return (0); 3747} 3748static device_method_t trm_methods[] = { 3749 /* Device interface */ 3750 DEVMETHOD(device_probe, trm_probe), 3751 DEVMETHOD(device_attach, trm_attach), 3752 DEVMETHOD(device_detach, trm_detach), 3753 { 0, 0 } 3754}; 3755 3756static driver_t trm_driver = { 3757 "trm", trm_methods, sizeof(struct _ACB) 3758}; 3759 3760static devclass_t trm_devclass; 3761DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3762MODULE_DEPEND(trm, pci, 1, 1, 1); 3763MODULE_DEPEND(trm, cam, 1, 1, 1); 3764