trm.c revision 158651
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 */ 12 13#include <sys/cdefs.h> 14__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 158651 2006-05-16 14:37:58Z phk $"); 15 16/* 17 * HISTORY: 18 * 19 * REV# DATE NAME DESCRIPTION 20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 27 */ 28 29/*- 30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. The name of the author may not be used to endorse or promote products 41 * derived from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 */ 55 56/* 57 * Imported into FreeBSD source repository, and updated to compile under 58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 59 */ 60 61/* 62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 63 * <doginou@ci0.org>, 2002-03-04 64 */ 65 66#include <sys/param.h> 67 68#include <sys/systm.h> 69#include <sys/malloc.h> 70#include <sys/queue.h> 71#if __FreeBSD_version >= 500000 72#include <sys/bio.h> 73#endif 74#include <sys/buf.h> 75#include <sys/bus.h> 76#include <sys/kernel.h> 77#include <sys/module.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <machine/resource.h> 85#include <machine/bus.h> 86#include <sys/rman.h> 87 88#include <cam/cam.h> 89#include <cam/cam_ccb.h> 90#include <cam/cam_sim.h> 91#include <cam/cam_xpt_sim.h> 92#include <cam/cam_debug.h> 93 94#include <cam/scsi/scsi_all.h> 95#include <cam/scsi/scsi_message.h> 96 97#include <dev/trm/trm.h> 98 99#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 100#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 101#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 102#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 103 reg, value) 104#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 105 reg, value) 106#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 107 reg, value) 108 109#define PCI_Vendor_ID_TEKRAM 0x1DE1 110#define PCI_Device_ID_TRM_S1040 0x0391 111#define PCI_DEVICEID_TRMS1040 0x03911DE1 112#define PCI_DEVICEID_TRMS2080 0x03921DE1 113 114#ifdef trm_DEBUG1 115#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 116#else 117#define TRM_DPRINTF(fmt, arg...) {} 118#endif /* TRM_DEBUG */ 119 120static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 121static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 122static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 123static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 125static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 126static void NVRAM_trm_wait_30us(PACB pACB); 127 128static void trm_Interrupt(void *vpACB); 129static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 130 u_int16_t * pscsi_status); 131static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 154static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 155static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 156static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 157static void trm_Disconnect(PACB pACB); 158static void trm_Reselect(PACB pACB); 159static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 160static void trm_DoingSRB_Done(PACB pACB); 161static void trm_ScsiRstDetect(PACB pACB); 162static void trm_ResetSCSIBus(PACB pACB); 163static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 164static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 165static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 166static void trm_SendSRB(PACB pACB, PSRB pSRB); 167static int trm_probe(device_t tag); 168static int trm_attach(device_t tag); 169static void trm_reset(PACB pACB); 170 171static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 172 173static int trm_initAdapter(PACB pACB, u_int16_t unit); 174static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 175 u_int32_t i, u_int32_t j); 176static int trm_initSRB(PACB pACB); 177static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 178/* CAM SIM entry points */ 179#define ccb_trmsrb_ptr spriv_ptr0 180#define ccb_trmacb_ptr spriv_ptr1 181static void trm_action(struct cam_sim *psim, union ccb *pccb); 182static void trm_poll(struct cam_sim *psim); 183 184 185static void * trm_SCSI_phase0[] = { 186 trm_DataOutPhase0, /* phase:0 */ 187 trm_DataInPhase0, /* phase:1 */ 188 trm_CommandPhase0, /* phase:2 */ 189 trm_StatusPhase0, /* phase:3 */ 190 trm_Nop0, /* phase:4 */ 191 trm_Nop1, /* phase:5 */ 192 trm_MsgOutPhase0, /* phase:6 */ 193 trm_MsgInPhase0, /* phase:7 */ 194}; 195 196/* 197 * 198 * stateV = (void *) trm_SCSI_phase1[phase] 199 * 200 */ 201static void * trm_SCSI_phase1[] = { 202 trm_DataOutPhase1, /* phase:0 */ 203 trm_DataInPhase1, /* phase:1 */ 204 trm_CommandPhase1, /* phase:2 */ 205 trm_StatusPhase1, /* phase:3 */ 206 trm_Nop0, /* phase:4 */ 207 trm_Nop1, /* phase:5 */ 208 trm_MsgOutPhase1, /* phase:6 */ 209 trm_MsgInPhase1, /* phase:7 */ 210}; 211 212 213NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 214/* 215 *Fast20: 000 50ns, 20.0 Mbytes/s 216 * 001 75ns, 13.3 Mbytes/s 217 * 010 100ns, 10.0 Mbytes/s 218 * 011 125ns, 8.0 Mbytes/s 219 * 100 150ns, 6.6 Mbytes/s 220 * 101 175ns, 5.7 Mbytes/s 221 * 110 200ns, 5.0 Mbytes/s 222 * 111 250ns, 4.0 Mbytes/s 223 * 224 *Fast40: 000 25ns, 40.0 Mbytes/s 225 * 001 50ns, 20.0 Mbytes/s 226 * 010 75ns, 13.3 Mbytes/s 227 * 011 100ns, 10.0 Mbytes/s 228 * 100 125ns, 8.0 Mbytes/s 229 * 101 150ns, 6.6 Mbytes/s 230 * 110 175ns, 5.7 Mbytes/s 231 * 111 200ns, 5.0 Mbytes/s 232 */ 233 /* real period: */ 234u_int8_t dc395x_clock_period[] = { 235 12,/* 48 ns 20 MB/sec */ 236 18,/* 72 ns 13.3 MB/sec */ 237 25,/* 100 ns 10.0 MB/sec */ 238 31,/* 124 ns 8.0 MB/sec */ 239 37,/* 148 ns 6.6 MB/sec */ 240 43,/* 172 ns 5.7 MB/sec */ 241 50,/* 200 ns 5.0 MB/sec */ 242 62 /* 248 ns 4.0 MB/sec */ 243}; 244 245u_int8_t dc395u2x_clock_period[]={ 246 10,/* 25 ns 40.0 MB/sec */ 247 12,/* 48 ns 20.0 MB/sec */ 248 18,/* 72 ns 13.3 MB/sec */ 249 25,/* 100 ns 10.0 MB/sec */ 250 31,/* 124 ns 8.0 MB/sec */ 251 37,/* 148 ns 6.6 MB/sec */ 252 43,/* 172 ns 5.7 MB/sec */ 253 50,/* 200 ns 5.0 MB/sec */ 254}; 255 256#define dc395x_tinfo_period dc395x_clock_period 257#define dc395u2x_tinfo_period dc395u2x_clock_period 258 259static PSRB 260trm_GetSRB(PACB pACB) 261{ 262 int intflag; 263 PSRB pSRB; 264 265 intflag = splcam(); 266 pSRB = pACB->pFreeSRB; 267 if (pSRB) { 268 pACB->pFreeSRB = pSRB->pNextSRB; 269 pSRB->pNextSRB = NULL; 270 } 271 splx(intflag); 272 return (pSRB); 273} 274 275static void 276trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 277{ 278 PSRB psrb1; 279 int intflag; 280 281 intflag = splcam(); 282 if ((psrb1 = pDCB->pWaitingSRB)) { 283 pSRB->pNextSRB = psrb1; 284 pDCB->pWaitingSRB = pSRB; 285 } else { 286 pSRB->pNextSRB = NULL; 287 pDCB->pWaitingSRB = pSRB; 288 pDCB->pWaitingLastSRB = pSRB; 289 } 290 splx(intflag); 291} 292 293static void 294trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 295{ 296 PSRB psrb1; 297 int intflag; 298 299 intflag = splcam(); 300 pDCB->GoingSRBCnt--; 301 psrb1 = pDCB->pGoingSRB; 302 if (pSRB == psrb1) 303 /* 304 * if this SRB is GoingSRB 305 * remove this SRB from GoingSRB Q 306 */ 307 pDCB->pGoingSRB = psrb1->pNextSRB; 308 else { 309 /* 310 * if this SRB is not current GoingSRB 311 * remove this SRB from GoingSRB Q 312 */ 313 while (pSRB != psrb1->pNextSRB) 314 psrb1 = psrb1->pNextSRB; 315 psrb1->pNextSRB = pSRB->pNextSRB; 316 if (pSRB == pDCB->pGoingLastSRB) 317 pDCB->pGoingLastSRB = psrb1; 318 } 319 if ((psrb1 = pDCB->pWaitingSRB)) { 320 /* 321 * if WaitingSRB Q is not NULL 322 * Q back this SRB into WaitingSRB 323 */ 324 325 pSRB->pNextSRB = psrb1; 326 pDCB->pWaitingSRB = pSRB; 327 } else { 328 pSRB->pNextSRB = NULL; 329 pDCB->pWaitingSRB = pSRB; 330 pDCB->pWaitingLastSRB = pSRB; 331 } 332 splx(intflag); 333} 334 335static void 336trm_DoWaitingSRB(PACB pACB) 337{ 338 int intflag; 339 PDCB ptr, ptr1; 340 PSRB pSRB; 341 342 intflag = splcam(); 343 if (!(pACB->pActiveDCB) && 344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 345 ptr = pACB->pDCBRunRobin; 346 if (!ptr) { 347 ptr = pACB->pLinkDCB; 348 pACB->pDCBRunRobin = ptr; 349 } 350 ptr1 = ptr; 351 for (;ptr1 ;) { 352 pACB->pDCBRunRobin = ptr1->pNextDCB; 353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 354 || !(pSRB = ptr1->pWaitingSRB)) { 355 if (pACB->pDCBRunRobin == ptr) 356 break; 357 ptr1 = ptr1->pNextDCB; 358 } else { 359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 360 /* 361 * If trm_StartSCSI return 0 : 362 * current interrupt status is interrupt enable 363 * It's said that SCSI processor is unoccupied 364 */ 365 ptr1->GoingSRBCnt++; 366 if (ptr1->pWaitingLastSRB == pSRB) { 367 ptr1->pWaitingSRB = NULL; 368 ptr1->pWaitingLastSRB = NULL; 369 } else 370 ptr1->pWaitingSRB = pSRB->pNextSRB; 371 pSRB->pNextSRB = NULL; 372 if (ptr1->pGoingSRB) 373 ptr1->pGoingLastSRB->pNextSRB = pSRB; 374 else 375 ptr1->pGoingSRB = pSRB; 376 ptr1->pGoingLastSRB = pSRB; 377 } 378 break; 379 } 380 } 381 } 382 splx(intflag); 383 return; 384} 385 386static void 387trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 388{ 389 390 if (pDCB->pWaitingSRB) { 391 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 392 pDCB->pWaitingLastSRB = pSRB; 393 pSRB->pNextSRB = NULL; 394 } else { 395 pDCB->pWaitingSRB = pSRB; 396 pDCB->pWaitingLastSRB = pSRB; 397 } 398} 399 400static u_int32_t 401trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 402{ 403 int offset; 404 405 offset = pSRB->TagNumber; 406 return (pACB->sense_busaddr + 407 (offset * sizeof(struct scsi_sense_data))); 408} 409 410static struct scsi_sense_data * 411trm_get_sense_buf(PACB pACB, PSRB pSRB) 412{ 413 int offset; 414 415 offset = pSRB->TagNumber; 416 return (&pACB->sense_buffers[offset]); 417} 418static void 419trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 420{ 421 int flags; 422 PACB pACB; 423 PSRB pSRB; 424 union ccb *ccb; 425 u_long totalxferlen=0; 426 427 flags = splcam(); 428 pSRB = (PSRB)arg; 429 ccb = pSRB->pccb; 430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 431 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 432 if (nseg != 0) { 433 PSEG psg; 434 bus_dma_segment_t *end_seg; 435 int op; 436 437 /* Copy the segments into our SG list */ 438 end_seg = dm_segs + nseg; 439 psg = pSRB->pSRBSGL; 440 while (dm_segs < end_seg) { 441 psg->address = dm_segs->ds_addr; 442 psg->length = (u_long)dm_segs->ds_len; 443 totalxferlen += dm_segs->ds_len; 444 psg++; 445 dm_segs++; 446 } 447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 448 op = BUS_DMASYNC_PREREAD; 449 } else { 450 op = BUS_DMASYNC_PREWRITE; 451 } 452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 453 } 454 pSRB->RetryCnt = 0; 455 pSRB->SRBTotalXferLength = totalxferlen; 456 pSRB->SRBSGCount = nseg; 457 pSRB->SRBSGIndex = 0; 458 pSRB->AdaptStatus = 0; 459 pSRB->TargetStatus = 0; 460 pSRB->MsgCnt = 0; 461 pSRB->SRBStatus = 0; 462 pSRB->SRBFlag = 0; 463 pSRB->SRBState = 0; 464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 465 466 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 467 if (nseg != 0) 468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 469 pSRB->pNextSRB = pACB->pFreeSRB; 470 pACB->pFreeSRB = pSRB; 471 xpt_done(ccb); 472 splx(flags); 473 return; 474 } 475 ccb->ccb_h.status |= CAM_SIM_QUEUED; 476#if 0 477 /* XXX Need a timeout handler */ 478 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 479#endif 480 trm_SendSRB(pACB, pSRB); 481 splx(flags); 482 return; 483} 484 485static void 486trm_SendSRB(PACB pACB, PSRB pSRB) 487{ 488 PDCB pDCB; 489 490 pDCB = pSRB->pSRBDCB; 491 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 492 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 493 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 494 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 495 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 496 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 497 trm_SRBwaiting(pDCB, pSRB); 498 goto SND_EXIT; 499 } 500 501 if (pDCB->pWaitingSRB) { 502 trm_SRBwaiting(pDCB, pSRB); 503 pSRB = pDCB->pWaitingSRB; 504 pDCB->pWaitingSRB = pSRB->pNextSRB; 505 pSRB->pNextSRB = NULL; 506 } 507 508 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 509 /* 510 * If trm_StartSCSI return 0 : 511 * current interrupt status is interrupt enable 512 * It's said that SCSI processor is unoccupied 513 */ 514 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 515 if (pDCB->pGoingSRB) { 516 pDCB->pGoingLastSRB->pNextSRB = pSRB; 517 pDCB->pGoingLastSRB = pSRB; 518 } else { 519 pDCB->pGoingSRB = pSRB; 520 pDCB->pGoingLastSRB = pSRB; 521 } 522 } else { 523 /* 524 * If trm_StartSCSI return 1 : 525 * current interrupt status is interrupt disreenable 526 * It's said that SCSI processor has more one SRB need to do 527 */ 528 trm_RewaitSRB0(pDCB, pSRB); 529 } 530SND_EXIT: 531 return; 532} 533 534 535static void 536trm_action(struct cam_sim *psim, union ccb *pccb) 537{ 538 PACB pACB; 539 int actionflags; 540 u_int target_id,target_lun; 541 542 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 543 544 actionflags = splcam(); 545 pACB = (PACB) cam_sim_softc(psim); 546 target_id = pccb->ccb_h.target_id; 547 target_lun = pccb->ccb_h.target_lun; 548 549 switch (pccb->ccb_h.func_code) { 550 case XPT_NOOP: 551 TRM_DPRINTF(" XPT_NOOP \n"); 552 pccb->ccb_h.status = CAM_REQ_INVALID; 553 xpt_done(pccb); 554 break; 555 /* 556 * Execute the requested I/O operation 557 */ 558 case XPT_SCSI_IO: { 559 PDCB pDCB = NULL; 560 PSRB pSRB; 561 struct ccb_scsiio *pcsio; 562 563 pcsio = &pccb->csio; 564 TRM_DPRINTF(" XPT_SCSI_IO \n"); 565 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 566 ,target_id, target_lun); 567 TRM_DPRINTF( 568 "pACB->scan_devices[target_id][target_lun]= %d \n" 569 ,pACB->scan_devices[target_id][target_lun]); 570 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 571 CAM_REQ_INPROG) { 572 xpt_done(pccb); 573 splx(actionflags); 574 return; 575 } 576 pDCB = &pACB->DCBarray[target_id][target_lun]; 577 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 578 pACB->scan_devices[target_id][target_lun] = 1; 579 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 580 target_id, target_lun); 581 } 582 /* 583 * Assign an SRB and connect it with this ccb. 584 */ 585 pSRB = trm_GetSRB(pACB); 586 if (!pSRB) { 587 /* Freeze SIMQ */ 588 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 589 xpt_done(pccb); 590 splx(actionflags); 591 return; 592 } 593 pSRB->pSRBDCB = pDCB; 594 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 595 pccb->ccb_h.ccb_trmacb_ptr = pACB; 596 pSRB->pccb = pccb; 597 pSRB->ScsiCmdLen = pcsio->cdb_len; 598 /* 599 * move layer of CAM command block to layer of SCSI 600 * Request Block for SCSI processor command doing 601 */ 602 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 603 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 604 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 605 ,pcsio->cdb_len); 606 } else { 607 pccb->ccb_h.status = CAM_REQ_INVALID; 608 pSRB->pNextSRB = pACB->pFreeSRB; 609 pACB->pFreeSRB= pSRB; 610 xpt_done(pccb); 611 splx(actionflags); 612 return; 613 } 614 } else 615 bcopy(pcsio->cdb_io.cdb_bytes, 616 pSRB->CmdBlock, pcsio->cdb_len); 617 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 618 != CAM_DIR_NONE) { 619 if ((pccb->ccb_h.flags & 620 CAM_SCATTER_VALID) == 0) { 621 if ((pccb->ccb_h.flags 622 & CAM_DATA_PHYS) == 0) { 623 int vmflags; 624 int error; 625 626 vmflags = splsoftvm(); 627 error = bus_dmamap_load( 628 pACB->buffer_dmat, 629 pSRB->dmamap, 630 pcsio->data_ptr, 631 pcsio->dxfer_len, 632 trm_ExecuteSRB, 633 pSRB, 634 0); 635 if (error == EINPROGRESS) { 636 xpt_freeze_simq( 637 pACB->psim, 638 1); 639 pccb->ccb_h.status |= 640 CAM_RELEASE_SIMQ; 641 } 642 splx(vmflags); 643 } else { 644 struct bus_dma_segment seg; 645 646 /* Pointer to physical buffer */ 647 seg.ds_addr = 648 (bus_addr_t)pcsio->data_ptr; 649 seg.ds_len = pcsio->dxfer_len; 650 trm_ExecuteSRB(pSRB, &seg, 1, 651 0); 652 } 653 } else { 654 /* CAM_SCATTER_VALID */ 655 struct bus_dma_segment *segs; 656 657 if ((pccb->ccb_h.flags & 658 CAM_SG_LIST_PHYS) == 0 || 659 (pccb->ccb_h.flags 660 & CAM_DATA_PHYS) != 0) { 661 pSRB->pNextSRB = pACB->pFreeSRB; 662 pACB->pFreeSRB = pSRB; 663 pccb->ccb_h.status = 664 CAM_PROVIDE_FAIL; 665 xpt_done(pccb); 666 splx(actionflags); 667 return; 668 } 669 670 /* cam SG list is physical, 671 * cam data is virtual 672 */ 673 segs = (struct bus_dma_segment *) 674 pcsio->data_ptr; 675 trm_ExecuteSRB(pSRB, segs, 676 pcsio->sglist_cnt, 1); 677 } /* CAM_SCATTER_VALID */ 678 } else 679 trm_ExecuteSRB(pSRB, NULL, 0, 0); 680 } 681 break; 682 case XPT_GDEV_TYPE: 683 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 684 pccb->ccb_h.status = CAM_REQ_INVALID; 685 xpt_done(pccb); 686 break; 687 case XPT_GDEVLIST: 688 TRM_DPRINTF(" XPT_GDEVLIST \n"); 689 pccb->ccb_h.status = CAM_REQ_INVALID; 690 xpt_done(pccb); 691 break; 692 /* 693 * Path routing inquiry 694 * Path Inquiry CCB 695 */ 696 case XPT_PATH_INQ: { 697 struct ccb_pathinq *cpi = &pccb->cpi; 698 699 TRM_DPRINTF(" XPT_PATH_INQ \n"); 700 cpi->version_num = 1; 701 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 702 cpi->target_sprt = 0; 703 cpi->hba_misc = 0; 704 cpi->hba_eng_cnt = 0; 705 cpi->max_target = 15 ; 706 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 707 cpi->initiator_id = pACB->AdaptSCSIID; 708 cpi->bus_id = cam_sim_bus(psim); 709 cpi->base_transfer_speed = 3300; 710 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 711 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 712 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 713 cpi->unit_number = cam_sim_unit(psim); 714 cpi->ccb_h.status = CAM_REQ_CMP; 715 xpt_done(pccb); 716 } 717 break; 718 /* 719 * Release a frozen SIM queue 720 * Release SIM Queue 721 */ 722 case XPT_REL_SIMQ: 723 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 724 pccb->ccb_h.status = CAM_REQ_INVALID; 725 xpt_done(pccb); 726 break; 727 /* 728 * Set Asynchronous Callback Parameters 729 * Set Asynchronous Callback CCB 730 */ 731 case XPT_SASYNC_CB: 732 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 733 pccb->ccb_h.status = CAM_REQ_INVALID; 734 xpt_done(pccb); 735 break; 736 /* 737 * Set device type information 738 * Set Device Type CCB 739 */ 740 case XPT_SDEV_TYPE: 741 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 742 pccb->ccb_h.status = CAM_REQ_INVALID; 743 xpt_done(pccb); 744 break; 745 /* 746 * (Re)Scan the SCSI Bus 747 * Rescan the given bus, or bus/target/lun 748 */ 749 case XPT_SCAN_BUS: 750 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 751 pccb->ccb_h.status = CAM_REQ_INVALID; 752 xpt_done(pccb); 753 break; 754 /* 755 * Get EDT entries matching the given pattern 756 */ 757 case XPT_DEV_MATCH: 758 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 759 pccb->ccb_h.status = CAM_REQ_INVALID; 760 xpt_done(pccb); 761 break; 762 /* 763 * Turn on debugging for a bus, target or lun 764 */ 765 case XPT_DEBUG: 766 TRM_DPRINTF(" XPT_DEBUG \n"); 767 pccb->ccb_h.status = CAM_REQ_INVALID; 768 xpt_done(pccb); 769 break; 770 /* 771 * XPT_ABORT = 0x10, Abort the specified CCB 772 * Abort XPT request CCB 773 */ 774 case XPT_ABORT: 775 TRM_DPRINTF(" XPT_ABORT \n"); 776 pccb->ccb_h.status = CAM_REQ_INVALID; 777 xpt_done(pccb); 778 break; 779 /* 780 * Reset the specified SCSI bus 781 * Reset SCSI Bus CCB 782 */ 783 case XPT_RESET_BUS: { 784 int i; 785 786 TRM_DPRINTF(" XPT_RESET_BUS \n"); 787 trm_reset(pACB); 788 pACB->ACBFlag=0; 789 for (i=0; i<500; i++) 790 DELAY(1000); 791 pccb->ccb_h.status = CAM_REQ_CMP; 792 xpt_done(pccb); 793 } 794 break; 795 /* 796 * Bus Device Reset the specified SCSI device 797 * Reset SCSI Device CCB 798 */ 799 case XPT_RESET_DEV: 800 /* 801 * Don't (yet?) support vendor 802 * specific commands. 803 */ 804 TRM_DPRINTF(" XPT_RESET_DEV \n"); 805 pccb->ccb_h.status = CAM_REQ_INVALID; 806 xpt_done(pccb); 807 break; 808 /* 809 * Terminate the I/O process 810 * Terminate I/O Process Request CCB 811 */ 812 case XPT_TERM_IO: 813 TRM_DPRINTF(" XPT_TERM_IO \n"); 814 pccb->ccb_h.status = CAM_REQ_INVALID; 815 xpt_done(pccb); 816 break; 817 /* 818 * Scan Logical Unit 819 */ 820 case XPT_SCAN_LUN: 821 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 822 pccb->ccb_h.status = CAM_REQ_INVALID; 823 xpt_done(pccb); 824 break; 825 826 /* 827 * Get/Set transfer rate/width/disconnection/tag queueing 828 * settings 829 * (GET) default/user transfer settings for the target 830 */ 831 case XPT_GET_TRAN_SETTINGS: { 832 struct ccb_trans_settings *cts; 833 int intflag; 834 struct trm_transinfo *tinfo; 835 PDCB pDCB; 836 837 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 838 cts = &pccb->cts; 839 pDCB = &pACB->DCBarray[target_id][target_lun]; 840 intflag = splcam(); 841 /* 842 * disable interrupt 843 */ 844 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 845 /* current transfer settings */ 846 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 847 cts->flags = CCB_TRANS_DISC_ENB; 848 else 849 cts->flags = 0;/* no tag & disconnect */ 850 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 851 cts->flags |= CCB_TRANS_TAG_ENB; 852 tinfo = &pDCB->tinfo.current; 853 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 854 cts->flags); 855 } else { 856 /* default(user) transfer settings */ 857 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 858 cts->flags = CCB_TRANS_DISC_ENB; 859 else 860 cts->flags = 0; 861 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 862 cts->flags |= CCB_TRANS_TAG_ENB; 863 tinfo = &pDCB->tinfo.user; 864 TRM_DPRINTF("USER: cts->flags= %2x \n", 865 cts->flags); 866 } 867 cts->sync_period = tinfo->period; 868 cts->sync_offset = tinfo->offset; 869 cts->bus_width = tinfo->width; 870 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 871 pDCB->SyncPeriod); 872 TRM_DPRINTF("period: %d \n", tinfo->period); 873 TRM_DPRINTF("offset: %d \n", tinfo->offset); 874 TRM_DPRINTF("width: %d \n", tinfo->width); 875 876 splx(intflag); 877 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 878 CCB_TRANS_SYNC_OFFSET_VALID | 879 CCB_TRANS_BUS_WIDTH_VALID | 880 CCB_TRANS_DISC_VALID | 881 CCB_TRANS_TQ_VALID; 882 pccb->ccb_h.status = CAM_REQ_CMP; 883 xpt_done(pccb); 884 } 885 break; 886 /* 887 * Get/Set transfer rate/width/disconnection/tag queueing 888 * settings 889 * (Set) transfer rate/width negotiation settings 890 */ 891 case XPT_SET_TRAN_SETTINGS: { 892 struct ccb_trans_settings *cts; 893 u_int update_type; 894 int intflag; 895 PDCB pDCB; 896 897 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 898 cts = &pccb->cts; 899 update_type = 0; 900 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 901 update_type |= TRM_TRANS_GOAL; 902 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 903 update_type |= TRM_TRANS_USER; 904 intflag = splcam(); 905 pDCB = &pACB->DCBarray[target_id][target_lun]; 906 907 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 908 /*ccb disc enables */ 909 if (update_type & TRM_TRANS_GOAL) { 910 if ((cts->flags & CCB_TRANS_DISC_ENB) 911 != 0) 912 pDCB->tinfo.disc_tag 913 |= TRM_CUR_DISCENB; 914 else 915 pDCB->tinfo.disc_tag &= 916 ~TRM_CUR_DISCENB; 917 } 918 if (update_type & TRM_TRANS_USER) { 919 if ((cts->flags & CCB_TRANS_DISC_ENB) 920 != 0) 921 pDCB->tinfo.disc_tag 922 |= TRM_USR_DISCENB; 923 else 924 pDCB->tinfo.disc_tag &= 925 ~TRM_USR_DISCENB; 926 } 927 } 928 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 929 /* if ccb tag q active */ 930 if (update_type & TRM_TRANS_GOAL) { 931 if ((cts->flags & CCB_TRANS_TAG_ENB) 932 != 0) 933 pDCB->tinfo.disc_tag |= 934 TRM_CUR_TAGENB; 935 else 936 pDCB->tinfo.disc_tag &= 937 ~TRM_CUR_TAGENB; 938 } 939 if (update_type & TRM_TRANS_USER) { 940 if ((cts->flags & CCB_TRANS_TAG_ENB) 941 != 0) 942 pDCB->tinfo.disc_tag |= 943 TRM_USR_TAGENB; 944 else 945 pDCB->tinfo.disc_tag &= 946 ~TRM_USR_TAGENB; 947 } 948 } 949 /* Minimum sync period factor */ 950 951 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 952 /* if ccb sync active */ 953 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 954 if ((cts->sync_period != 0) && 955 (cts->sync_period < 125)) 956 cts->sync_period = 125; 957 /* 1/(125*4) minsync 2 MByte/sec */ 958 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 959 != 0) { 960 if (cts->sync_offset == 0) 961 cts->sync_period = 0; 962 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 963 if (cts->sync_offset > 15) 964 cts->sync_offset = 15; 965 } 966 } 967 if ((update_type & TRM_TRANS_USER) != 0) { 968 pDCB->tinfo.user.period = cts->sync_period; 969 pDCB->tinfo.user.offset = cts->sync_offset; 970 pDCB->tinfo.user.width = cts->bus_width; 971 } 972 if ((update_type & TRM_TRANS_GOAL) != 0) { 973 pDCB->tinfo.goal.period = cts->sync_period; 974 pDCB->tinfo.goal.offset = cts->sync_offset; 975 pDCB->tinfo.goal.width = cts->bus_width; 976 } 977 splx(intflag); 978 pccb->ccb_h.status = CAM_REQ_CMP; 979 xpt_done(pccb); 980 break; 981 } 982 /* 983 * Calculate the geometry parameters for a device give 984 * the sector size and volume size. 985 */ 986 case XPT_CALC_GEOMETRY: 987 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 988 cam_calc_geometry(&pccb->ccg, /*extended*/1); 989 xpt_done(pccb); 990 break; 991 case XPT_ENG_INQ: 992 TRM_DPRINTF(" XPT_ENG_INQ \n"); 993 pccb->ccb_h.status = CAM_REQ_INVALID; 994 xpt_done(pccb); 995 break; 996 /* 997 * HBA execute engine request 998 * This structure must match SCSIIO size 999 */ 1000 case XPT_ENG_EXEC: 1001 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1002 pccb->ccb_h.status = CAM_REQ_INVALID; 1003 xpt_done(pccb); 1004 break; 1005 /* 1006 * XPT_EN_LUN = 0x30, Enable LUN as a target 1007 * Target mode structures. 1008 */ 1009 case XPT_EN_LUN: 1010 /* 1011 * Don't (yet?) support vendor 1012 * specific commands. 1013 */ 1014 TRM_DPRINTF(" XPT_EN_LUN \n"); 1015 pccb->ccb_h.status = CAM_REQ_INVALID; 1016 xpt_done(pccb); 1017 break; 1018 /* 1019 * Execute target I/O request 1020 */ 1021 case XPT_TARGET_IO: 1022 /* 1023 * Don't (yet?) support vendor 1024 * specific commands. 1025 */ 1026 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1027 pccb->ccb_h.status = CAM_REQ_INVALID; 1028 xpt_done(pccb); 1029 break; 1030 /* 1031 * Accept Host Target Mode CDB 1032 */ 1033 case XPT_ACCEPT_TARGET_IO: 1034 /* 1035 * Don't (yet?) support vendor 1036 * specific commands. 1037 */ 1038 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1039 pccb->ccb_h.status = CAM_REQ_INVALID; 1040 xpt_done(pccb); 1041 break; 1042 /* 1043 * Continue Host Target I/O Connection 1044 */ 1045 case XPT_CONT_TARGET_IO: 1046 /* 1047 * Don't (yet?) support vendor 1048 * specific commands. 1049 */ 1050 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1051 pccb->ccb_h.status = CAM_REQ_INVALID; 1052 xpt_done(pccb); 1053 break; 1054 /* 1055 * Notify Host Target driver of event 1056 */ 1057 case XPT_IMMED_NOTIFY: 1058 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1059 pccb->ccb_h.status = CAM_REQ_INVALID; 1060 xpt_done(pccb); 1061 break; 1062 /* 1063 * Acknowledgement of event 1064 */ 1065 case XPT_NOTIFY_ACK: 1066 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1067 pccb->ccb_h.status = CAM_REQ_INVALID; 1068 xpt_done(pccb); 1069 break; 1070 /* 1071 * XPT_VUNIQUE = 0x80 1072 */ 1073 case XPT_VUNIQUE: 1074 pccb->ccb_h.status = CAM_REQ_INVALID; 1075 xpt_done(pccb); 1076 break; 1077 default: 1078 pccb->ccb_h.status = CAM_REQ_INVALID; 1079 xpt_done(pccb); 1080 break; 1081 } 1082 splx(actionflags); 1083} 1084 1085static void 1086trm_poll(struct cam_sim *psim) 1087{ 1088 trm_Interrupt(cam_sim_softc(psim)); 1089} 1090 1091static void 1092trm_ResetDevParam(PACB pACB) 1093{ 1094 PDCB pDCB, pdcb; 1095 PNVRAMTYPE pEEpromBuf; 1096 u_int8_t PeriodIndex; 1097 1098 pDCB = pACB->pLinkDCB; 1099 if (pDCB == NULL) 1100 return; 1101 pdcb = pDCB; 1102 do { 1103 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1104 pDCB->SyncPeriod = 0; 1105 pDCB->SyncOffset = 0; 1106 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1107 pDCB->DevMode = 1108 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1109 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1110 PeriodIndex = 1111 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1112 if (pACB->AdaptType == 1) /* is U2? */ 1113 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1114 else 1115 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1116 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1117 (pACB->Config & HCC_WIDE_CARD)) 1118 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1119 pDCB = pDCB->pNextDCB; 1120 } 1121 while (pdcb != pDCB); 1122} 1123 1124static void 1125trm_RecoverSRB(PACB pACB) 1126{ 1127 PDCB pDCB, pdcb; 1128 PSRB psrb, psrb2; 1129 u_int16_t cnt, i; 1130 1131 pDCB = pACB->pLinkDCB; 1132 if (pDCB == NULL) 1133 return; 1134 pdcb = pDCB; 1135 do { 1136 cnt = pdcb->GoingSRBCnt; 1137 psrb = pdcb->pGoingSRB; 1138 for (i = 0; i < cnt; i++) { 1139 psrb2 = psrb; 1140 psrb = psrb->pNextSRB; 1141 if (pdcb->pWaitingSRB) { 1142 psrb2->pNextSRB = pdcb->pWaitingSRB; 1143 pdcb->pWaitingSRB = psrb2; 1144 } else { 1145 pdcb->pWaitingSRB = psrb2; 1146 pdcb->pWaitingLastSRB = psrb2; 1147 psrb2->pNextSRB = NULL; 1148 } 1149 } 1150 pdcb->GoingSRBCnt = 0; 1151 pdcb->pGoingSRB = NULL; 1152 pdcb = pdcb->pNextDCB; 1153 } 1154 while (pdcb != pDCB); 1155} 1156 1157static void 1158trm_reset(PACB pACB) 1159{ 1160 int intflag; 1161 u_int16_t i; 1162 1163 TRM_DPRINTF("trm: RESET"); 1164 intflag = splcam(); 1165 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1166 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1167 1168 trm_ResetSCSIBus(pACB); 1169 for (i = 0; i < 500; i++) 1170 DELAY(1000); 1171 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1172 /* Enable DMA interrupt */ 1173 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1174 /* Clear DMA FIFO */ 1175 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1176 /* Clear SCSI FIFO */ 1177 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1178 trm_ResetDevParam(pACB); 1179 trm_DoingSRB_Done(pACB); 1180 pACB->pActiveDCB = NULL; 1181 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1182 trm_DoWaitingSRB(pACB); 1183 /* Tell the XPT layer that a bus reset occured */ 1184 if (pACB->ppath != NULL) 1185 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1186 splx(intflag); 1187 return; 1188} 1189 1190static u_int16_t 1191trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1192{ 1193 u_int16_t return_code; 1194 u_int8_t scsicommand, i,command,identify_message; 1195 u_int8_t * ptr; 1196 union ccb *pccb; 1197 struct ccb_scsiio *pcsio; 1198 1199 pccb = pSRB->pccb; 1200 pcsio = &pccb->csio; 1201 1202 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1203 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1204 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1205 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1206 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1207 /* Flush FIFO */ 1208 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1209 1210 identify_message = pDCB->IdentifyMsg; 1211 1212 if ((pSRB->CmdBlock[0] == INQUIRY) || 1213 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1214 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1215 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1216 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1217 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1218 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1219 if (!(pDCB->IdentifyMsg & 7) || 1220 (pSRB->CmdBlock[0] != INQUIRY)) { 1221 scsicommand = SCMD_SEL_ATNSTOP; 1222 pSRB->SRBState = SRB_MSGOUT; 1223 goto polling; 1224 } 1225 } 1226 /* 1227 * Send identify message 1228 */ 1229 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1230 scsicommand = SCMD_SEL_ATN; 1231 pSRB->SRBState = SRB_START_; 1232 } else { 1233 /* not inquiry,request sense,auto request sense */ 1234 /* 1235 * Send identify message 1236 */ 1237 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1238 scsicommand = SCMD_SEL_ATN; 1239 pSRB->SRBState = SRB_START_; 1240 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1241 /* Send Tag message */ 1242 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1243 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1244 scsicommand = SCMD_SEL_ATN3; 1245 } 1246 } 1247polling: 1248 /* 1249 * Send CDB ..command block ......... 1250 */ 1251 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1252 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1253 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1254 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1255 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1256 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1257 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1258 } else { 1259 ptr = (u_int8_t *) pSRB->CmdBlock; 1260 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1261 command = *ptr++; 1262 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1263 } 1264 } 1265 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1266 /* 1267 * If trm_StartSCSI return 1 : 1268 * current interrupt status is interrupt disreenable 1269 * It's said that SCSI processor has more one SRB need to do, 1270 * SCSI processor has been occupied by one SRB. 1271 */ 1272 pSRB->SRBState = SRB_READY; 1273 return_code = 1; 1274 } else { 1275 /* 1276 * If trm_StartSCSI return 0 : 1277 * current interrupt status is interrupt enable 1278 * It's said that SCSI processor is unoccupied 1279 */ 1280 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1281 pACB->pActiveDCB = pDCB; 1282 pDCB->pActiveSRB = pSRB; 1283 return_code = 0; 1284 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1285 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1286 /* 1287 * SCSI cammand 1288 */ 1289 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1290 } 1291 return (return_code); 1292} 1293 1294static void 1295trm_Interrupt(vpACB) 1296void *vpACB; 1297{ 1298 PACB pACB; 1299 PDCB pDCB; 1300 PSRB pSRB; 1301 u_int16_t phase; 1302 void (*stateV)(PACB, PSRB, u_int16_t *); 1303 u_int16_t scsi_status=0; 1304 u_int8_t scsi_intstatus; 1305 1306 pACB = vpACB; 1307 1308 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1309 if (!(scsi_status & SCSIINTERRUPT)) { 1310 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1311 return; 1312 } 1313 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1314 1315 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1316 1317 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1318 1319 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1320 trm_Disconnect(pACB); 1321 return; 1322 } 1323 1324 if (scsi_intstatus & INT_RESELECTED) { 1325 trm_Reselect(pACB); 1326 return; 1327 } 1328 if (scsi_intstatus & INT_SCSIRESET) { 1329 trm_ScsiRstDetect(pACB); 1330 return; 1331 } 1332 1333 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1334 pDCB = pACB->pActiveDCB; 1335 KASSERT(pDCB != NULL, ("no active DCB")); 1336 pSRB = pDCB->pActiveSRB; 1337 if (pDCB->DCBFlag & ABORT_DEV_) 1338 trm_EnableMsgOutAbort1(pACB, pSRB); 1339 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1340 stateV = (void *) trm_SCSI_phase0[phase]; 1341 stateV(pACB, pSRB, &scsi_status); 1342 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1343 /* phase:0,1,2,3,4,5,6,7 */ 1344 phase = (u_int16_t) scsi_status & PHASEMASK; 1345 stateV = (void *) trm_SCSI_phase1[phase]; 1346 stateV(pACB, pSRB, &scsi_status); 1347 } 1348} 1349 1350static void 1351trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1352{ 1353 1354 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1355 *pscsi_status = PH_BUS_FREE; 1356 /*.. initial phase*/ 1357} 1358 1359static void 1360trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1361{ 1362 u_int8_t bval; 1363 u_int16_t i, cnt; 1364 u_int8_t * ptr; 1365 PDCB pDCB; 1366 1367 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1368 pDCB = pACB->pActiveDCB; 1369 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1370 cnt = pSRB->MsgCnt; 1371 if (cnt) { 1372 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1373 for (i = 0; i < cnt; i++) { 1374 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1375 ptr++; 1376 } 1377 pSRB->MsgCnt = 0; 1378 if ((pDCB->DCBFlag & ABORT_DEV_) && 1379 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1380 pSRB->SRBState = SRB_ABORT_SENT; 1381 } 1382 } else { 1383 bval = MSG_ABORT; 1384 if ((pSRB->CmdBlock[0] == INQUIRY) || 1385 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1386 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1387 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1388 goto mop1; 1389 } 1390 } 1391 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1392 } 1393 } else { 1394mop1: /* message out phase */ 1395 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1396 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1397 /* 1398 * WIDE DATA TRANSFER REQUEST code (03h) 1399 */ 1400 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1401 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1402 TRMREG_SCSI_FIFO); 1403 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1404 /* (01h) */ 1405 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1406 /* Message length (02h) */ 1407 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1408 /* wide data xfer (03h) */ 1409 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1410 /* width:0(8bit),1(16bit),2(32bit) */ 1411 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1412 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1413 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1414 /* 1415 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1416 */ 1417 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1418 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1419 TRMREG_SCSI_FIFO); 1420 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1421 /* (01h) */ 1422 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1423 /* Message length (03h) */ 1424 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1425 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1426 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1427 /* Transfer peeriod factor */ 1428 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1429 TRMREG_SCSI_FIFO); 1430 /* REQ/ACK offset */ 1431 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1432 } 1433 } 1434 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1435 /* it's important for atn stop */ 1436 /* 1437 * SCSI cammand 1438 */ 1439 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1440} 1441 1442static void 1443trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1444{ 1445 1446} 1447 1448static void 1449trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1450{ 1451 PDCB pDCB; 1452 u_int8_t * ptr; 1453 u_int16_t i, cnt; 1454 union ccb *pccb; 1455 struct ccb_scsiio *pcsio; 1456 1457 pccb = pSRB->pccb; 1458 pcsio = &pccb->csio; 1459 1460 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1461 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1462 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1463 ptr = (u_int8_t *) pSRB->CmdBlock; 1464 for (i = 0; i < cnt; i++) { 1465 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1466 ptr++; 1467 } 1468 } else { 1469 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1470 pDCB = pACB->pActiveDCB; 1471 /* target id */ 1472 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1473 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1474 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1475 /* sizeof(struct scsi_sense_data) */ 1476 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1477 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1478 } 1479 pSRB->SRBState = SRB_COMMAND; 1480 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1481 /* it's important for atn stop*/ 1482 /* 1483 * SCSI cammand 1484 */ 1485 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1486} 1487 1488static void 1489trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1490{ 1491 PDCB pDCB; 1492 u_int8_t TempDMAstatus,SGIndexTemp; 1493 u_int16_t scsi_status; 1494 PSEG pseg; 1495 u_long TempSRBXferredLength,dLeftCounter=0; 1496 1497 pDCB = pSRB->pSRBDCB; 1498 scsi_status = *pscsi_status; 1499 1500 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1501 if (scsi_status & PARITYERROR) 1502 pSRB->SRBStatus |= PARITY_ERROR; 1503 if (!(scsi_status & SCSIXFERDONE)) { 1504 /* 1505 * when data transfer from DMA FIFO to SCSI FIFO 1506 * if there was some data left in SCSI FIFO 1507 */ 1508 dLeftCounter = (u_long) 1509 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1510 if (pDCB->SyncPeriod & WIDE_SYNC) { 1511 /* 1512 * if WIDE scsi SCSI FIFOCNT unit is word 1513 * so need to * 2 1514 */ 1515 dLeftCounter <<= 1; 1516 } 1517 } 1518 /* 1519 * caculate all the residue data that not yet tranfered 1520 * SCSI transfer counter + left in SCSI FIFO data 1521 * 1522 * .....TRM_SCSI_COUNTER (24bits) 1523 * The counter always decrement by one for every SCSI byte 1524 *transfer. 1525 * .....TRM_SCSI_FIFOCNT (5bits) 1526 * The counter is SCSI FIFO offset counter 1527 */ 1528 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1529 if (dLeftCounter == 1) { 1530 dLeftCounter = 0; 1531 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1532 } 1533 if ((dLeftCounter == 0) || 1534 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1535 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1536 while (!(TempDMAstatus & DMAXFERCOMP)) { 1537 TempDMAstatus = 1538 trm_reg_read8(TRMREG_DMA_STATUS); 1539 } 1540 pSRB->SRBTotalXferLength = 0; 1541 } else { 1542 /* Update SG list */ 1543 /* 1544 * if transfer not yet complete 1545 * there were some data residue in SCSI FIFO or 1546 * SCSI transfer counter not empty 1547 */ 1548 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1549 /* 1550 * data that had transferred length 1551 */ 1552 TempSRBXferredLength = 1553 pSRB->SRBTotalXferLength - dLeftCounter; 1554 /* 1555 * next time to be transferred length 1556 */ 1557 pSRB->SRBTotalXferLength = dLeftCounter; 1558 /* 1559 * parsing from last time disconnect SRBSGIndex 1560 */ 1561 pseg = 1562 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1563 for (SGIndexTemp = pSRB->SRBSGIndex; 1564 SGIndexTemp < pSRB->SRBSGCount; 1565 SGIndexTemp++) { 1566 /* 1567 * find last time which SG transfer be 1568 * disconnect 1569 */ 1570 if (TempSRBXferredLength >= 1571 pseg->length) 1572 TempSRBXferredLength -= 1573 pseg->length; 1574 else { 1575 /* 1576 * update last time disconnected SG 1577 * list 1578 */ 1579 pseg->length -= 1580 TempSRBXferredLength; 1581 /* residue data length */ 1582 pseg->address += 1583 TempSRBXferredLength; 1584 /* residue data pointer */ 1585 pSRB->SRBSGIndex = SGIndexTemp; 1586 break; 1587 } 1588 pseg++; 1589 } 1590 } 1591 } 1592 } 1593 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1594} 1595 1596 1597static void 1598trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1599{ 1600 u_int16_t ioDir; 1601 /* 1602 * do prepare befor transfer when data out phase 1603 */ 1604 1605 ioDir = XFERDATAOUT; 1606 trm_DataIO_transfer(pACB, pSRB, ioDir); 1607} 1608 1609static void 1610trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1611{ 1612 u_int8_t TempDMAstatus, SGIndexTemp; 1613 u_int16_t scsi_status; 1614 PSEG pseg; 1615 u_long TempSRBXferredLength,dLeftCounter = 0; 1616 1617 scsi_status = *pscsi_status; 1618 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1619 if (scsi_status & PARITYERROR) 1620 pSRB->SRBStatus |= PARITY_ERROR; 1621 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1622 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1623 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1624 while (!(TempDMAstatus & DMAXFERCOMP)) 1625 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1626 pSRB->SRBTotalXferLength = 0; 1627 } else { 1628 /* 1629 * parsing the case: 1630 * when a transfer not yet complete 1631 * but be disconnected by uper layer 1632 * if transfer not yet complete 1633 * there were some data residue in SCSI FIFO or 1634 * SCSI transfer counter not empty 1635 */ 1636 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1637 /* 1638 * data that had transferred length 1639 */ 1640 TempSRBXferredLength = 1641 pSRB->SRBTotalXferLength - dLeftCounter; 1642 /* 1643 * next time to be transferred length 1644 */ 1645 pSRB->SRBTotalXferLength = dLeftCounter; 1646 /* 1647 * parsing from last time disconnect SRBSGIndex 1648 */ 1649 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1650 for (SGIndexTemp = pSRB->SRBSGIndex; 1651 SGIndexTemp < pSRB->SRBSGCount; 1652 SGIndexTemp++) { 1653 /* 1654 * find last time which SG transfer be disconnect 1655 */ 1656 if (TempSRBXferredLength >= pseg->length) 1657 TempSRBXferredLength -= pseg->length; 1658 else { 1659 /* 1660 * update last time disconnected SG list 1661 */ 1662 pseg->length -= TempSRBXferredLength; 1663 /* residue data length */ 1664 pseg->address += TempSRBXferredLength; 1665 /* residue data pointer */ 1666 pSRB->SRBSGIndex = SGIndexTemp; 1667 break; 1668 } 1669 pseg++; 1670 } 1671 } 1672 } 1673 } 1674} 1675 1676static void 1677trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1678{ 1679 u_int16_t ioDir; 1680 /* 1681 * do prepare befor transfer when data in phase 1682 */ 1683 1684 ioDir = XFERDATAIN; 1685 trm_DataIO_transfer(pACB, pSRB, ioDir); 1686} 1687 1688static void 1689trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1690{ 1691 u_int8_t bval; 1692 PDCB pDCB; 1693 1694 pDCB = pSRB->pSRBDCB; 1695 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1696 if (pSRB->SRBTotalXferLength != 0) { 1697 /* 1698 * load what physical address of Scatter/Gather list 1699 table want to be transfer 1700 */ 1701 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1702 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1703 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1704 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1705 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1706 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1707 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1708 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1709 1710 pSRB->SRBState = SRB_DATA_XFER; 1711 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1712 trm_reg_write32( 1713 (pSRB->SRBSGPhyAddr + 1714 ((u_long)pSRB->SRBSGIndex << 3)), 1715 TRMREG_DMA_XLOWADDR); 1716 /* 1717 * load how many bytes in the Scatter/Gather 1718 * list table 1719 */ 1720 trm_reg_write32( 1721 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1722 TRMREG_DMA_XCNT); 1723 /* 1724 * load total transfer length (24bits) max value 1725 * 16Mbyte 1726 */ 1727 trm_reg_write32(pSRB->SRBTotalXferLength, 1728 TRMREG_SCSI_COUNTER); 1729 /* Start DMA transfer */ 1730 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1731 /* Start SCSI transfer */ 1732 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1733 /* it's important for atn stop */ 1734 /* 1735 * SCSI cammand 1736 */ 1737 bval = (ioDir == XFERDATAOUT) ? 1738 SCMD_DMA_OUT : SCMD_DMA_IN; 1739 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1740 } else { 1741 /* xfer pad */ 1742 if (pSRB->SRBSGCount) { 1743 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1744 pSRB->SRBStatus |= OVER_RUN; 1745 } 1746 if (pDCB->SyncPeriod & WIDE_SYNC) 1747 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1748 else 1749 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1750 if (ioDir == XFERDATAOUT) 1751 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1752 else 1753 trm_reg_read16(TRMREG_SCSI_FIFO); 1754 pSRB->SRBState |= SRB_XFERPAD; 1755 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1756 /* it's important for atn stop */ 1757 /* 1758 * SCSI cammand 1759 */ 1760 bval = (ioDir == XFERDATAOUT) ? 1761 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1762 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1763 } 1764 } 1765} 1766 1767static void 1768trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1769{ 1770 1771 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1772 pSRB->SRBState = SRB_COMPLETED; 1773 *pscsi_status = PH_BUS_FREE; 1774 /*.. initial phase*/ 1775 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1776 /* it's important for atn stop */ 1777 /* 1778 * SCSI cammand 1779 */ 1780 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1781} 1782 1783 1784 1785static void 1786trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1787{ 1788 1789 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1790 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1791 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1792 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1793 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1794 } else { 1795 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1796 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1797 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1798 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1799 } 1800 pSRB->SRBState = SRB_STATUS; 1801 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1802 /* it's important for atn stop */ 1803 /* 1804 * SCSI cammand 1805 */ 1806 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1807} 1808 1809/* 1810 *scsiiom 1811 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1812 * stateV = (void *) trm_SCSI_phase0[phase] 1813 * if phase =7 1814 * extended message codes: 1815 * 1816 * code description 1817 * 1818 * 02h Reserved 1819 * 00h MODIFY DATA POINTER 1820 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1821 * 03h WIDE DATA TRANSFER REQUEST 1822 * 04h - 7Fh Reserved 1823 * 80h - FFh Vendor specific 1824 * 1825 */ 1826 1827static void 1828trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1829{ 1830 u_int8_t message_in_code,bIndex,message_in_tag_id; 1831 PDCB pDCB; 1832 PSRB pSRBTemp; 1833 1834 pDCB = pACB->pActiveDCB; 1835 1836 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1837 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1838 if (message_in_code == MSG_DISCONNECT) { 1839 pSRB->SRBState = SRB_DISCONNECT; 1840 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1841 /* it's important for atn stop */ 1842 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1843 /* 1844 * SCSI command 1845 */ 1846 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1847 return; 1848 } else if (message_in_code == MSG_SAVE_PTR) { 1849 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1850 /* it's important for atn stop */ 1851 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1852 /* 1853 * SCSI command 1854 */ 1855 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1856 return; 1857 } else if ((message_in_code == MSG_EXTENDED) || 1858 ((message_in_code >= MSG_SIMPLE_QTAG) && 1859 (message_in_code <= MSG_ORDER_QTAG))) { 1860 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1861 pSRB->MsgInBuf[0] = message_in_code; 1862 /* extended message (01h) */ 1863 pSRB->MsgCnt = 1; 1864 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1865 /* extended message length (n) */ 1866 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1867 /* it's important for atn stop */ 1868 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1869 /* 1870 * SCSI command 1871 */ 1872 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1873 return; 1874 } else if (message_in_code == MSG_REJECT_) { 1875 /* Reject message */ 1876 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1877 /* do wide nego reject */ 1878 pDCB = pSRB->pSRBDCB; 1879 pDCB->SyncMode |= WIDE_NEGO_DONE; 1880 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1881 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1882 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1883 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1884 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1885 /* Set ATN, in case ATN was clear */ 1886 pSRB->SRBState |= SRB_MSGOUT; 1887 trm_reg_write16( 1888 DO_SETATN, 1889 TRMREG_SCSI_CONTROL); 1890 } else { 1891 /* Clear ATN */ 1892 trm_reg_write16( 1893 DO_CLRATN, 1894 TRMREG_SCSI_CONTROL); 1895 } 1896 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1897 /* do sync nego reject */ 1898 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1899 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1900 pDCB = pSRB->pSRBDCB; 1901 pDCB->SyncMode &= 1902 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1903 pDCB->SyncPeriod = 0; 1904 pDCB->SyncOffset = 0; 1905 /* 1906 * 1907 * program SCSI control register 1908 * 1909 */ 1910 trm_reg_write8(pDCB->SyncPeriod, 1911 TRMREG_SCSI_SYNC); 1912 trm_reg_write8(pDCB->SyncOffset, 1913 TRMREG_SCSI_OFFSET); 1914 trm_SetXferRate(pACB,pSRB,pDCB); 1915 } 1916 } 1917 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1918 /* it's important for atn stop */ 1919 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1920 /* 1921 * SCSI command 1922 */ 1923 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1924 return; 1925 } else if (message_in_code == MSG_IGNOREWIDE) { 1926 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1927 trm_reg_read8(TRMREG_SCSI_FIFO); 1928 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1929 /* it's important for atn stop */ 1930 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1931 /* 1932 * SCSI command 1933 */ 1934 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1935 return; 1936 } else { 1937 /* Restore data pointer message */ 1938 /* Save data pointer message */ 1939 /* Completion message */ 1940 /* NOP message */ 1941 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1942 /* it's important for atn stop */ 1943 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1944 /* 1945 * SCSI command 1946 */ 1947 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1948 return; 1949 } 1950 } else { 1951 /* 1952 * Parsing incomming extented messages 1953 */ 1954 *pSRB->pMsgPtr = message_in_code; 1955 pSRB->MsgCnt++; 1956 pSRB->pMsgPtr++; 1957 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1958 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1959 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1960 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1961 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1962 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1963 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1964 /* 1965 * is QUEUE tag message : 1966 * 1967 * byte 0: 1968 * HEAD QUEUE TAG (20h) 1969 * ORDERED QUEUE TAG (21h) 1970 * SIMPLE QUEUE TAG (22h) 1971 * byte 1: 1972 * Queue tag (00h - FFh) 1973 */ 1974 if (pSRB->MsgCnt == 2) { 1975 pSRB->SRBState = 0; 1976 message_in_tag_id = pSRB->MsgInBuf[1]; 1977 pSRB = pDCB->pGoingSRB; 1978 pSRBTemp = pDCB->pGoingLastSRB; 1979 if (pSRB) { 1980 for (;;) { 1981 if (pSRB->TagNumber != 1982 message_in_tag_id) { 1983 if (pSRB == pSRBTemp) { 1984 goto mingx0; 1985 } 1986 pSRB = pSRB->pNextSRB; 1987 } else 1988 break; 1989 } 1990 if (pDCB->DCBFlag & ABORT_DEV_) { 1991 pSRB->SRBState = SRB_ABORT_SENT; 1992 trm_EnableMsgOutAbort1( 1993 pACB, pSRB); 1994 } 1995 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1996 TRM_DPRINTF("SRB not yet disconnect........ \n "); 1997 goto mingx0; 1998 } 1999 pDCB->pActiveSRB = pSRB; 2000 pSRB->SRBState = SRB_DATA_XFER; 2001 } else { 2002mingx0: 2003 pSRB = &pACB->TmpSRB; 2004 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2005 pDCB->pActiveSRB = pSRB; 2006 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2007 trm_EnableMsgOutAbort2( 2008 pACB, 2009 pSRB); 2010 } 2011 } 2012 *pscsi_status = PH_BUS_FREE; 2013 /* .. initial phase */ 2014 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2015 /* it's important for atn stop */ 2016 /* 2017 * SCSI command 2018 */ 2019 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2020 return; 2021 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2022 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2023 /* 2024 * is Wide data xfer Extended message : 2025 * ====================================== 2026 * WIDE DATA TRANSFER REQUEST 2027 * ====================================== 2028 * byte 0 : Extended message (01h) 2029 * byte 1 : Extended message length (02h) 2030 * byte 2 : WIDE DATA TRANSFER code (03h) 2031 * byte 3 : Transfer width exponent 2032 */ 2033 pDCB = pSRB->pSRBDCB; 2034 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2035 if ((pSRB->MsgInBuf[1] != 2)) { 2036 /* Length is wrong, reject it */ 2037 pDCB->SyncMode &= 2038 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2039 pSRB->MsgCnt = 1; 2040 pSRB->MsgInBuf[0] = MSG_REJECT_; 2041 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2042 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2043 /* it's important for atn stop */ 2044 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2045 /* 2046 * SCSI command 2047 */ 2048 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2049 return; 2050 } 2051 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2052 /* Do wide negoniation */ 2053 if (pSRB->MsgInBuf[3] > 2) { 2054 /* > 32 bit */ 2055 /* reject_msg: */ 2056 pDCB->SyncMode &= 2057 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2058 pSRB->MsgCnt = 1; 2059 pSRB->MsgInBuf[0] = MSG_REJECT_; 2060 trm_reg_write16(DO_SETATN, 2061 TRMREG_SCSI_CONTROL); 2062 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2063 /* it's important for atn stop */ 2064 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2065 /* 2066 * SCSI command 2067 */ 2068 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2069 return; 2070 } 2071 if (pSRB->MsgInBuf[3] == 2) { 2072 pSRB->MsgInBuf[3] = 1; 2073 /* do 16 bits */ 2074 } else { 2075 if (!(pDCB->SyncMode 2076 & WIDE_NEGO_DONE)) { 2077 pSRB->SRBState &= 2078 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2079 pDCB->SyncMode |= 2080 WIDE_NEGO_DONE; 2081 pDCB->SyncMode &= 2082 ~(SYNC_NEGO_DONE | 2083 EN_ATN_STOP | 2084 WIDE_NEGO_ENABLE); 2085 if (pSRB->MsgInBuf[3] != 0) { 2086 /* is Wide data xfer */ 2087 pDCB->SyncPeriod |= 2088 WIDE_SYNC; 2089 pDCB->tinfo.current.width 2090 = MSG_EXT_WDTR_BUS_16_BIT; 2091 pDCB->tinfo.goal.width 2092 = MSG_EXT_WDTR_BUS_16_BIT; 2093 } 2094 } 2095 } 2096 } else 2097 pSRB->MsgInBuf[3] = 0; 2098 pSRB->SRBState |= SRB_MSGOUT; 2099 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2100 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2101 /* it's important for atn stop */ 2102 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2103 /* 2104 * SCSI command 2105 */ 2106 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2107 return; 2108 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2109 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2110 /* 2111 * is 8bit transfer Extended message : 2112 * ================================= 2113 * SYNCHRONOUS DATA TRANSFER REQUEST 2114 * ================================= 2115 * byte 0 : Extended message (01h) 2116 * byte 1 : Extended message length (03) 2117 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2118 * byte 3 : Transfer period factor 2119 * byte 4 : REQ/ACK offset 2120 */ 2121 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2122 if ((pSRB->MsgInBuf[1] != 3) || 2123 (pSRB->MsgInBuf[2] != 1)) { 2124 /* reject_msg: */ 2125 pSRB->MsgCnt = 1; 2126 pSRB->MsgInBuf[0] = MSG_REJECT_; 2127 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2128 *pscsi_status = PH_BUS_FREE; 2129 /* .. initial phase */ 2130 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2131 /* it's important for atn stop */ 2132 /* 2133 * SCSI cammand 2134 */ 2135 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2136 return; 2137 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2138 /* set async */ 2139 pDCB = pSRB->pSRBDCB; 2140 /* disable sync & sync nego */ 2141 pDCB->SyncMode &= 2142 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2143 pDCB->SyncPeriod = 0; 2144 pDCB->SyncOffset = 0; 2145 pDCB->tinfo.goal.period = 0; 2146 pDCB->tinfo.goal.offset = 0; 2147 pDCB->tinfo.current.period = 0; 2148 pDCB->tinfo.current.offset = 0; 2149 pDCB->tinfo.current.width = 2150 MSG_EXT_WDTR_BUS_8_BIT; 2151 /* 2152 * 2153 * program SCSI control register 2154 * 2155 */ 2156 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2157 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2158 trm_SetXferRate(pACB,pSRB,pDCB); 2159 *pscsi_status = PH_BUS_FREE; 2160 /* .. initial phase */ 2161 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2162 /* it's important for atn stop */ 2163 /* 2164 * SCSI cammand 2165 */ 2166 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2167 return; 2168 } else { 2169 /* set sync */ 2170 pDCB = pSRB->pSRBDCB; 2171 pDCB->SyncMode |= 2172 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2173 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2174 /* Transfer period factor */ 2175 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2176 /* REQ/ACK offset */ 2177 if (pACB->AdaptType == 1) { 2178 for(bIndex = 0; bIndex < 7; bIndex++) { 2179 if (pSRB->MsgInBuf[3] <= 2180 dc395u2x_clock_period[bIndex]) { 2181 pDCB->tinfo.goal.period = 2182 dc395u2x_tinfo_period[bIndex]; 2183 pDCB->tinfo.current.period = 2184 dc395u2x_tinfo_period[bIndex]; 2185 pDCB->tinfo.goal.offset = 2186 pDCB->SyncOffset; 2187 pDCB->tinfo.current.offset = 2188 pDCB->SyncOffset; 2189 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2190 break; 2191 } 2192 } 2193 } else { 2194 for(bIndex = 0; bIndex < 7; bIndex++) { 2195 if (pSRB->MsgInBuf[3] <= 2196 dc395x_clock_period[bIndex]) { 2197 pDCB->tinfo.goal.period = 2198 dc395x_tinfo_period[bIndex]; 2199 pDCB->tinfo.current.period = 2200 dc395x_tinfo_period[bIndex]; 2201 pDCB->tinfo.goal.offset = 2202 pDCB->SyncOffset; 2203 pDCB->tinfo.current.offset = 2204 pDCB->SyncOffset; 2205 pDCB->SyncPeriod |= 2206 (bIndex|ALT_SYNC); 2207 break; 2208 } 2209 } 2210 } 2211 /* 2212 * 2213 * program SCSI control register 2214 * 2215 */ 2216 trm_reg_write8(pDCB->SyncPeriod, 2217 TRMREG_SCSI_SYNC); 2218 trm_reg_write8(pDCB->SyncOffset, 2219 TRMREG_SCSI_OFFSET); 2220 trm_SetXferRate(pACB,pSRB,pDCB); 2221 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2222 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2223 /* 2224 ** SCSI command 2225 */ 2226 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2227 return; 2228 } 2229 } 2230 *pscsi_status = PH_BUS_FREE; 2231 /* .. initial phase */ 2232 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2233 /* it's important for atn stop */ 2234 /* 2235 * SCSI cammand 2236 */ 2237 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2238 } 2239} 2240 2241static void 2242trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2243{ 2244 2245 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2246 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2247 if (!(pSRB->SRBState & SRB_MSGIN)) { 2248 pSRB->SRBState &= SRB_DISCONNECT; 2249 pSRB->SRBState |= SRB_MSGIN; 2250 } 2251 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2252 /* it's important for atn stop*/ 2253 /* 2254 * SCSI cammand 2255 */ 2256 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2257} 2258 2259static void 2260trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2261{ 2262 2263} 2264 2265static void 2266trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2267{ 2268 2269} 2270 2271static void 2272trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2273{ 2274 union ccb *pccb; 2275 struct ccb_trans_settings neg; 2276 u_int16_t cnt, i; 2277 u_int8_t bval; 2278 PDCB pDCBTemp; 2279 2280 /* 2281 * set all lun device's period , offset 2282 */ 2283 TRM_DPRINTF("trm_SetXferRate\n"); 2284 pccb = pSRB->pccb; 2285 neg.sync_period = pDCB->tinfo.goal.period; 2286 neg.sync_offset = pDCB->tinfo.goal.offset; 2287 neg.valid = CCB_TRANS_SYNC_RATE_VALID | CCB_TRANS_SYNC_OFFSET_VALID; 2288 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2289 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2290 if (!(pDCB->IdentifyMsg & 0x07)) { 2291 pDCBTemp = pACB->pLinkDCB; 2292 cnt = pACB->DeviceCnt; 2293 bval = pDCB->TargetID; 2294 for (i = 0; i < cnt; i++) { 2295 if (pDCBTemp->TargetID == bval) { 2296 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2297 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2298 pDCBTemp->SyncMode = pDCB->SyncMode; 2299 } 2300 pDCBTemp = pDCBTemp->pNextDCB; 2301 } 2302 } 2303 return; 2304} 2305 2306/* 2307 * scsiiom 2308 * trm_Interrupt 2309 * 2310 * 2311 * ---SCSI bus phase 2312 * 2313 * PH_DATA_OUT 0x00 Data out phase 2314 * PH_DATA_IN 0x01 Data in phase 2315 * PH_COMMAND 0x02 Command phase 2316 * PH_STATUS 0x03 Status phase 2317 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2318 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2319 * PH_MSG_OUT 0x06 Message out phase 2320 * PH_MSG_IN 0x07 Message in phase 2321 * 2322 */ 2323static void 2324trm_Disconnect(PACB pACB) 2325{ 2326 PDCB pDCB; 2327 PSRB pSRB, psrb; 2328 u_int16_t i,j, cnt; 2329 u_int target_id,target_lun; 2330 2331 TRM_DPRINTF("trm_Disconnect...............\n "); 2332 2333 pDCB = pACB->pActiveDCB; 2334 if (!pDCB) { 2335 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2336 j = 400; 2337 while (--j) 2338 DELAY(1); 2339 /* 1 msec */ 2340 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2341 TRMREG_SCSI_CONTROL); 2342 return; 2343 } 2344 pSRB = pDCB->pActiveSRB; 2345 /* bug pSRB=0 */ 2346 target_id = pSRB->pccb->ccb_h.target_id; 2347 target_lun = pSRB->pccb->ccb_h.target_lun; 2348 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2349 pACB->pActiveDCB = 0; 2350 pSRB->ScsiPhase = PH_BUS_FREE; 2351 /* SCSI bus free Phase */ 2352 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2353 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2354 pSRB->SRBState = 0; 2355 trm_DoWaitingSRB(pACB); 2356 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2357 pDCB->DCBFlag = 0; 2358 cnt = pDCB->GoingSRBCnt; 2359 pDCB->GoingSRBCnt = 0; 2360 pSRB = pDCB->pGoingSRB; 2361 for (i = 0; i < cnt; i++) { 2362 psrb = pSRB->pNextSRB; 2363 pSRB->pNextSRB = pACB->pFreeSRB; 2364 pACB->pFreeSRB = pSRB; 2365 pSRB = psrb; 2366 } 2367 pDCB->pGoingSRB = 0; 2368 trm_DoWaitingSRB(pACB); 2369 } else { 2370 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2371 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2372 /* Selection time out */ 2373 if (!(pACB->scan_devices[target_id][target_lun]) && 2374 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2375 pSRB->CmdBlock[0] != INQUIRY) { 2376 pSRB->SRBState = SRB_READY; 2377 trm_RewaitSRB(pDCB, pSRB); 2378 } else { 2379 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2380 goto disc1; 2381 } 2382 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2383 /* 2384 * SRB_DISCONNECT 2385 */ 2386 trm_DoWaitingSRB(pACB); 2387 } else if (pSRB->SRBState & SRB_COMPLETED) { 2388disc1: 2389 /* 2390 * SRB_COMPLETED 2391 */ 2392 pDCB->pActiveSRB = 0; 2393 pSRB->SRBState = SRB_FREE; 2394 trm_SRBdone(pACB, pDCB, pSRB); 2395 } 2396 } 2397 return; 2398} 2399 2400static void 2401trm_Reselect(PACB pACB) 2402{ 2403 PDCB pDCB; 2404 PSRB pSRB; 2405 u_int16_t RselTarLunId; 2406 2407 TRM_DPRINTF("trm_Reselect................. \n"); 2408 pDCB = pACB->pActiveDCB; 2409 if (pDCB) { 2410 /* Arbitration lost but Reselection win */ 2411 pSRB = pDCB->pActiveSRB; 2412 pSRB->SRBState = SRB_READY; 2413 trm_RewaitSRB(pDCB, pSRB); 2414 } 2415 /* Read Reselected Target Id and LUN */ 2416 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2417 pDCB = pACB->pLinkDCB; 2418 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2419 /* get pDCB of the reselect id */ 2420 pDCB = pDCB->pNextDCB; 2421 } 2422 2423 pACB->pActiveDCB = pDCB; 2424 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2425 pSRB = &pACB->TmpSRB; 2426 pDCB->pActiveSRB = pSRB; 2427 } else { 2428 pSRB = pDCB->pActiveSRB; 2429 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2430 /* 2431 * abort command 2432 */ 2433 pSRB = &pACB->TmpSRB; 2434 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2435 pDCB->pActiveSRB = pSRB; 2436 trm_EnableMsgOutAbort1(pACB, pSRB); 2437 } else { 2438 if (pDCB->DCBFlag & ABORT_DEV_) { 2439 pSRB->SRBState = SRB_ABORT_SENT; 2440 trm_EnableMsgOutAbort1(pACB, pSRB); 2441 } else 2442 pSRB->SRBState = SRB_DATA_XFER; 2443 } 2444 } 2445 pSRB->ScsiPhase = PH_BUS_FREE; 2446 /* SCSI bus free Phase */ 2447 /* 2448 * Program HA ID, target ID, period and offset 2449 */ 2450 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2451 /* target ID */ 2452 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2453 /* host ID */ 2454 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2455 /* period */ 2456 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2457 /* offset */ 2458 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2459 /* it's important for atn stop*/ 2460 /* 2461 * SCSI cammand 2462 */ 2463 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2464 /* to rls the /ACK signal */ 2465} 2466 2467static void 2468trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2469{ 2470 PSRB psrb; 2471 u_int8_t bval, bval1,status; 2472 union ccb *pccb; 2473 struct ccb_scsiio *pcsio; 2474 PSCSI_INQDATA ptr; 2475 int intflag; 2476 u_int target_id,target_lun; 2477 PDCB pTempDCB; 2478 2479 pccb = pSRB->pccb; 2480 if (pccb == NULL) 2481 return; 2482 pcsio = &pccb->csio; 2483 target_id = pSRB->pccb->ccb_h.target_id; 2484 target_lun = pSRB->pccb->ccb_h.target_lun; 2485 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2486 bus_dmasync_op_t op; 2487 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2488 op = BUS_DMASYNC_POSTREAD; 2489 else 2490 op = BUS_DMASYNC_POSTWRITE; 2491 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2492 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2493 } 2494 /* 2495 * 2496 * target status 2497 * 2498 */ 2499 status = pSRB->TargetStatus; 2500 pcsio->scsi_status=SCSI_STAT_GOOD; 2501 pccb->ccb_h.status = CAM_REQ_CMP; 2502 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2503 /* 2504 * status of auto request sense 2505 */ 2506 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2507 pSRB->AdaptStatus = 0; 2508 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2509 2510 if (status == SCSI_STATUS_CHECK_COND) { 2511 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2512 goto ckc_e; 2513 } 2514 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2515 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2516 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2517 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2518 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2519 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2520 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2521 pcsio->sense_len); 2522 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2523 | CAM_AUTOSNS_VALID; 2524 goto ckc_e; 2525 } 2526 /* 2527 * target status 2528 */ 2529 if (status) { 2530 if (status == SCSI_STATUS_CHECK_COND) { 2531 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2532 TRM_DPRINTF("trm_RequestSense..................\n"); 2533 trm_RequestSense(pACB, pDCB, pSRB); 2534 return; 2535 } 2536 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2537 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2538 goto ckc_e; 2539 } else if (status == SCSI_STAT_QUEUEFULL) { 2540 bval = (u_int8_t) pDCB->GoingSRBCnt; 2541 bval--; 2542 pDCB->MaxActiveCommandCnt = bval; 2543 trm_RewaitSRB(pDCB, pSRB); 2544 pSRB->AdaptStatus = 0; 2545 pSRB->TargetStatus = 0; 2546 return; 2547 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2548 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2549 pSRB->TargetStatus = 0; 2550 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2551 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2552 } else if (status == SCSI_STAT_BUSY) { 2553 TRM_DPRINTF("trm: target busy at %s %d\n", 2554 __FILE__, __LINE__); 2555 pcsio->scsi_status = SCSI_STAT_BUSY; 2556 pccb->ccb_h.status = CAM_SCSI_BUSY; 2557 return; 2558 /* The device busy, try again later? */ 2559 } else if (status == SCSI_STAT_RESCONFLICT) { 2560 TRM_DPRINTF("trm: target reserved at %s %d\n", 2561 __FILE__, __LINE__); 2562 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2563 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2564 return; 2565 } else { 2566 pSRB->AdaptStatus = 0; 2567 if (pSRB->RetryCnt) { 2568 pSRB->RetryCnt--; 2569 pSRB->TargetStatus = 0; 2570 pSRB->SRBSGIndex = 0; 2571 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2572 /* 2573 * If trm_StartSCSI return 1 : 2574 * current interrupt status is interrupt 2575 * disreenable 2576 * It's said that SCSI processor has more 2577 * one SRB need to do 2578 */ 2579 trm_RewaitSRB(pDCB, pSRB); 2580 } 2581 return; 2582 } else { 2583 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2584 __FILE__, __LINE__); 2585 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2586 } 2587 } 2588 } else { 2589 /* 2590 * process initiator status.......................... 2591 * Adapter (initiator) status 2592 */ 2593 status = pSRB->AdaptStatus; 2594 if (status & H_OVER_UNDER_RUN) { 2595 pSRB->TargetStatus = 0; 2596 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2597 /* Illegal length (over/under run) */ 2598 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2599 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2600 __FILE__, __LINE__); 2601 pDCB->tinfo.goal.period = 0; 2602 pDCB->tinfo.goal.offset = 0; 2603 /* Driver failed to perform operation */ 2604 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2605 } else { 2606 /* no error */ 2607 pSRB->AdaptStatus = 0; 2608 pSRB->TargetStatus = 0; 2609 pccb->ccb_h.status = CAM_REQ_CMP; 2610 /* there is no error, (sense is invalid) */ 2611 } 2612 } 2613ckc_e: 2614 if (pACB->scan_devices[target_id][target_lun]) { 2615 /* 2616 * if SCSI command in "scan devices" duty 2617 */ 2618 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2619 pACB->scan_devices[target_id][target_lun] = 0; 2620 /* SCSI command phase :test unit ready */ 2621 else if (pSRB->CmdBlock[0] == INQUIRY) { 2622 /* 2623 * SCSI command phase :inquiry scsi device data 2624 * (type,capacity,manufacture.... 2625 */ 2626 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2627 goto NO_DEV; 2628 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2629 /* page fault */ 2630 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2631 ptr->DevType); 2632 bval1 = ptr->DevType & SCSI_DEVTYPE; 2633 if (bval1 == SCSI_NODEV) { 2634NO_DEV: 2635 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2636 target_id, 2637 target_lun); 2638 intflag = splcam(); 2639 pACB->scan_devices[target_id][target_lun] = 0; 2640 /* no device set scan device flag =0*/ 2641 /* pDCB Q link */ 2642 /* move the head of DCB to tempDCB*/ 2643 pTempDCB=pACB->pLinkDCB; 2644 /* search current DCB for pass link */ 2645 while (pTempDCB->pNextDCB != pDCB) { 2646 pTempDCB = pTempDCB->pNextDCB; 2647 } 2648 /* 2649 * when the current DCB found than connect 2650 * current DCB tail 2651 */ 2652 /* to the DCB tail that before current DCB */ 2653 pTempDCB->pNextDCB = pDCB->pNextDCB; 2654 /* 2655 * if there was only one DCB ,connect his tail 2656 * to his head 2657 */ 2658 if (pACB->pLinkDCB == pDCB) 2659 pACB->pLinkDCB = pTempDCB->pNextDCB; 2660 if (pACB->pDCBRunRobin == pDCB) 2661 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2662 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2663 pACB->DeviceCnt--; 2664 if (pACB->DeviceCnt == 0) { 2665 pACB->pLinkDCB = NULL; 2666 pACB->pDCBRunRobin = NULL; 2667 } 2668 splx(intflag); 2669 } else { 2670#ifdef trm_DEBUG1 2671 int j; 2672 for (j = 0; j < 28; j++) { 2673 TRM_DPRINTF("ptr=%2x ", 2674 ((u_int8_t *)ptr)[j]); 2675 } 2676#endif 2677 pDCB->DevType = bval1; 2678 if (bval1 == SCSI_DASD || 2679 bval1 == SCSI_OPTICAL) { 2680 if ((((ptr->Vers & 0x07) >= 2) || 2681 ((ptr->RDF & 0x0F) == 2)) && 2682 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2683 (pDCB->DevMode & TAG_QUEUING_) && 2684 (pDCB->DevMode & EN_DISCONNECT_)) { 2685 if (pDCB->DevMode & 2686 TAG_QUEUING_) { 2687 pDCB-> 2688 MaxActiveCommandCnt = 2689 pACB->TagMaxNum; 2690 pDCB->SyncMode |= 2691 EN_TAG_QUEUING; 2692 pDCB->tinfo.disc_tag |= 2693 TRM_CUR_TAGENB; 2694 } else { 2695 pDCB->SyncMode |= 2696 EN_ATN_STOP; 2697 pDCB->tinfo.disc_tag &= 2698 ~TRM_CUR_TAGENB; 2699 } 2700 } 2701 } 2702 } 2703 /* pSRB->CmdBlock[0] == INQUIRY */ 2704 } 2705 /* pACB->scan_devices[target_id][target_lun] */ 2706 } 2707 intflag = splcam(); 2708 /* ReleaseSRB(pDCB, pSRB); */ 2709 if (pSRB == pDCB->pGoingSRB) 2710 pDCB->pGoingSRB = pSRB->pNextSRB; 2711 else { 2712 psrb = pDCB->pGoingSRB; 2713 while (psrb->pNextSRB != pSRB) { 2714 psrb = psrb->pNextSRB; 2715 } 2716 psrb->pNextSRB = pSRB->pNextSRB; 2717 if (pSRB == pDCB->pGoingLastSRB) { 2718 pDCB->pGoingLastSRB = psrb; 2719 } 2720 } 2721 pSRB->pNextSRB = pACB->pFreeSRB; 2722 pACB->pFreeSRB = pSRB; 2723 pDCB->GoingSRBCnt--; 2724 trm_DoWaitingSRB(pACB); 2725 2726 splx(intflag); 2727 /* Notify cmd done */ 2728 xpt_done (pccb); 2729} 2730 2731static void 2732trm_DoingSRB_Done(PACB pACB) 2733{ 2734 PDCB pDCB, pdcb; 2735 PSRB psrb, psrb2; 2736 u_int16_t cnt, i; 2737 union ccb *pccb; 2738 2739 pDCB = pACB->pLinkDCB; 2740 if (pDCB == NULL) 2741 return; 2742 pdcb = pDCB; 2743 do { 2744 cnt = pdcb->GoingSRBCnt; 2745 psrb = pdcb->pGoingSRB; 2746 for (i = 0; i < cnt; i++) { 2747 psrb2 = psrb->pNextSRB; 2748 pccb = psrb->pccb; 2749 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2750 /* ReleaseSRB(pDCB, pSRB); */ 2751 psrb->pNextSRB = pACB->pFreeSRB; 2752 pACB->pFreeSRB = psrb; 2753 xpt_done(pccb); 2754 psrb = psrb2; 2755 } 2756 pdcb->GoingSRBCnt = 0;; 2757 pdcb->pGoingSRB = NULL; 2758 pdcb = pdcb->pNextDCB; 2759 } 2760 while (pdcb != pDCB); 2761} 2762 2763static void 2764trm_ResetSCSIBus(PACB pACB) 2765{ 2766 int intflag; 2767 2768 intflag = splcam(); 2769 pACB->ACBFlag |= RESET_DEV; 2770 2771 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2772 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2773 splx(intflag); 2774 return; 2775} 2776 2777static void 2778trm_ScsiRstDetect(PACB pACB) 2779{ 2780 int intflag; 2781 u_long wlval; 2782 2783 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2784 wlval = 1000; 2785 while (--wlval) 2786 DELAY(1000); 2787 intflag = splcam(); 2788 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2789 2790 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2791 2792 if (pACB->ACBFlag & RESET_DEV) 2793 pACB->ACBFlag |= RESET_DONE; 2794 else { 2795 pACB->ACBFlag |= RESET_DETECT; 2796 trm_ResetDevParam(pACB); 2797 /* trm_DoingSRB_Done(pACB); ???? */ 2798 trm_RecoverSRB(pACB); 2799 pACB->pActiveDCB = NULL; 2800 pACB->ACBFlag = 0; 2801 trm_DoWaitingSRB(pACB); 2802 } 2803 splx(intflag); 2804 return; 2805} 2806 2807static void 2808trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2809{ 2810 union ccb *pccb; 2811 struct ccb_scsiio *pcsio; 2812 2813 pccb = pSRB->pccb; 2814 pcsio = &pccb->csio; 2815 2816 pSRB->SRBFlag |= AUTO_REQSENSE; 2817 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2818 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2819 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2820 pSRB->SRBSGCount); 2821 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2822 2823 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2824 pSRB->AdaptStatus = 0; 2825 pSRB->TargetStatus = 0; 2826 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2827 2828 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2829 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2830 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2831 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2832 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2833 pSRB->SRBSGCount = 1; 2834 pSRB->SRBSGIndex = 0; 2835 2836 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2837 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2838 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2839 pSRB->ScsiCmdLen = 6; 2840 2841 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2842 /* 2843 * If trm_StartSCSI return 1 : 2844 * current interrupt status is interrupt disreenable 2845 * It's said that SCSI processor has more one SRB need to do 2846 */ 2847 trm_RewaitSRB(pDCB, pSRB); 2848} 2849 2850static void 2851trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2852{ 2853 2854 pSRB->MsgCnt = 1; 2855 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2856} 2857 2858static void 2859trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2860{ 2861 2862 pSRB->MsgOutBuf[0] = MSG_ABORT; 2863 trm_EnableMsgOutAbort2(pACB, pSRB); 2864} 2865 2866static void 2867trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2868{ 2869 PNVRAMTYPE pEEpromBuf; 2870 u_int8_t bval,PeriodIndex; 2871 u_int target_id,target_lun; 2872 PDCB pTempDCB; 2873 int intflag; 2874 2875 target_id = i; 2876 target_lun = j; 2877 2878 /* 2879 * Using the lun 0 device to init other DCB first, if the device 2880 * has been initialized. 2881 * I don't want init sync arguments one by one, it is the same. 2882 */ 2883 if (target_lun != 0 && 2884 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2885 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2886 sizeof(TRM_DCB)); 2887 intflag = splcam(); 2888 if (pACB->pLinkDCB == 0) { 2889 pACB->pLinkDCB = pDCB; 2890 /* 2891 * RunRobin impersonate the role 2892 * that let each device had good proportion 2893 * about SCSI command proceeding 2894 */ 2895 pACB->pDCBRunRobin = pDCB; 2896 pDCB->pNextDCB = pDCB; 2897 } else { 2898 pTempDCB=pACB->pLinkDCB; 2899 /* search the last nod of DCB link */ 2900 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2901 pTempDCB = pTempDCB->pNextDCB; 2902 /* connect current DCB with last DCB tail */ 2903 pTempDCB->pNextDCB = pDCB; 2904 /* connect current DCB tail to this DCB Q head */ 2905 pDCB->pNextDCB=pACB->pLinkDCB; 2906 } 2907 splx(intflag); 2908 2909 pACB->DeviceCnt++; 2910 pDCB->TargetID = target_id; 2911 pDCB->TargetLUN = target_lun; 2912 pDCB->pWaitingSRB = NULL; 2913 pDCB->pGoingSRB = NULL; 2914 pDCB->GoingSRBCnt = 0; 2915 pDCB->pActiveSRB = NULL; 2916 pDCB->MaxActiveCommandCnt = 1; 2917 pDCB->DCBFlag = 0; 2918 pDCB->DCBstatus |= DS_IN_QUEUE; 2919 /* $$$$$$$ */ 2920 pEEpromBuf = &trm_eepromBuf[unit]; 2921 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2922 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2923 /* $$$$$$$ */ 2924 /* 2925 * disconnect enable ? 2926 */ 2927 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2928 bval = 0xC0; 2929 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2930 } else { 2931 bval = 0x80; 2932 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2933 } 2934 bval |= target_lun; 2935 pDCB->IdentifyMsg = bval; 2936 if (target_lun != 0 && 2937 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2938 return; 2939 /* $$$$$$$ */ 2940 /* 2941 * tag Qing enable ? 2942 */ 2943 if (pDCB->DevMode & TAG_QUEUING_) { 2944 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2945 } else 2946 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2947 /* $$$$$$$ */ 2948 /* 2949 * wide nego ,sync nego enable ? 2950 */ 2951 pDCB->SyncPeriod = 0; 2952 pDCB->SyncOffset = 0; 2953 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2954 if (pACB->AdaptType==1) {/* is U2? */ 2955 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2956 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2957 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2958 } else { 2959 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2960 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2961 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2962 } 2963 pDCB->SyncMode = 0; 2964 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2965 (pACB->Config & HCC_WIDE_CARD)) 2966 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2967 /* enable wide nego */ 2968 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2969 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2970 /* enable sync nego */ 2971 /* $$$$$$$ */ 2972 /* 2973 * Fill in tinfo structure. 2974 */ 2975 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2976 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2977 2978 pDCB->tinfo.current.period = 0; 2979 pDCB->tinfo.current.offset = 0; 2980 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2981} 2982 2983static void 2984trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2985{ 2986 PSRB pSRB; 2987 2988 pSRB=(PSRB) arg; 2989 pSRB->SRBSGPhyAddr=segs->ds_addr; 2990 return; 2991} 2992 2993static void 2994trm_destroySRB(PACB pACB) 2995{ 2996 PSRB pSRB; 2997 2998 pSRB = pACB->pFreeSRB; 2999 while (pSRB) { 3000 if (pSRB->sg_dmamap) { 3001 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 3002 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 3003 pSRB->sg_dmamap); 3004 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap); 3005 } 3006 if (pSRB->dmamap) 3007 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 3008 pSRB = pSRB->pNextSRB; 3009 } 3010} 3011 3012static int 3013trm_initSRB(PACB pACB) 3014{ 3015 u_int16_t i; 3016 PSRB pSRB; 3017 int error; 3018 3019 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 3020 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3021 3022 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 3023 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3024 return ENXIO; 3025 } 3026 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3027 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3028 trm_srbmapSG, pSRB, /*flags*/0); 3029 if (i != TRM_MAX_SRB_CNT - 1) { 3030 /* 3031 * link all SRB 3032 */ 3033 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3034 } else { 3035 /* 3036 * load NULL to NextSRB of the last SRB 3037 */ 3038 pSRB->pNextSRB = NULL; 3039 } 3040 pSRB->TagNumber = i; 3041 3042 /* 3043 * Create the dmamap. This is no longer optional! 3044 */ 3045 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 3046 &pSRB->dmamap)) != 0) 3047 return (error); 3048 3049 } 3050 return (0); 3051} 3052 3053 3054 3055 3056static void 3057trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3058{ 3059 PNVRAMTYPE pEEpromBuf; 3060 3061 pEEpromBuf = &trm_eepromBuf[unit]; 3062 pACB->max_id = 15; 3063 3064 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3065 pACB->max_lun = 7; 3066 else 3067 pACB->max_lun = 0; 3068 3069 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3070 pACB->max_id, pACB->max_lun); 3071 pACB->pLinkDCB = NULL; 3072 pACB->pDCBRunRobin = NULL; 3073 pACB->pActiveDCB = NULL; 3074 pACB->AdapterUnit = (u_int8_t)unit; 3075 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3076 pACB->AdaptSCSILUN = 0; 3077 pACB->DeviceCnt = 0; 3078 pACB->AdaptType = adaptType; 3079 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3080 pACB->ACBFlag = 0; 3081 return; 3082} 3083 3084static void 3085NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3086{ 3087 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3088 u_int8_t bAddr; 3089 3090 /* Enable SEEPROM */ 3091 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3092 TRMREG_GEN_CONTROL); 3093 /* 3094 * Write enable 3095 */ 3096 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3097 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3098 NVRAM_trm_wait_30us(pACB); 3099 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3100 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3101 } 3102 /* 3103 * Write disable 3104 */ 3105 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3106 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3107 NVRAM_trm_wait_30us(pACB); 3108 /* Disable SEEPROM */ 3109 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3110 TRMREG_GEN_CONTROL); 3111 return; 3112} 3113 3114static void 3115NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3116{ 3117 int i; 3118 u_int8_t bSendData; 3119 /* 3120 * Send write command & address 3121 */ 3122 3123 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3124 /* 3125 * Write data 3126 */ 3127 for (i = 0; i < 8; i++, bData <<= 1) { 3128 bSendData = NVR_SELECT; 3129 if (bData & 0x80) 3130 /* Start from bit 7 */ 3131 bSendData |= NVR_BITOUT; 3132 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3133 NVRAM_trm_wait_30us(pACB); 3134 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3135 NVRAM_trm_wait_30us(pACB); 3136 } 3137 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3138 NVRAM_trm_wait_30us(pACB); 3139 /* 3140 * Disable chip select 3141 */ 3142 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3143 NVRAM_trm_wait_30us(pACB); 3144 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3145 NVRAM_trm_wait_30us(pACB); 3146 /* 3147 * Wait for write ready 3148 */ 3149 while (1) { 3150 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3151 NVRAM_trm_wait_30us(pACB); 3152 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3153 NVRAM_trm_wait_30us(pACB); 3154 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3155 break; 3156 } 3157 } 3158 /* 3159 * Disable chip select 3160 */ 3161 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3162 return; 3163} 3164 3165static void 3166NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3167{ 3168 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3169 u_int8_t bAddr; 3170 3171 /* 3172 * Enable SEEPROM 3173 */ 3174 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3175 TRMREG_GEN_CONTROL); 3176 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3177 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3178 /* 3179 * Disable SEEPROM 3180 */ 3181 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3182 TRMREG_GEN_CONTROL); 3183 return; 3184} 3185 3186static u_int8_t 3187NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3188{ 3189 int i; 3190 u_int8_t bReadData, bData = 0; 3191 /* 3192 * Send read command & address 3193 */ 3194 3195 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3196 3197 for (i = 0; i < 8; i++) { 3198 /* 3199 * Read data 3200 */ 3201 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3202 NVRAM_trm_wait_30us(pACB); 3203 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3204 /* 3205 * Get data bit while falling edge 3206 */ 3207 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3208 bData <<= 1; 3209 if (bReadData & NVR_BITIN) { 3210 bData |= 1; 3211 } 3212 NVRAM_trm_wait_30us(pACB); 3213 } 3214 /* 3215 * Disable chip select 3216 */ 3217 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3218 return (bData); 3219} 3220 3221static void 3222NVRAM_trm_wait_30us(PACB pACB) 3223{ 3224 3225 /* ScsiPortStallExecution(30); wait 30 us */ 3226 trm_reg_write8(5, TRMREG_GEN_TIMER); 3227 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3228 return; 3229} 3230 3231static void 3232NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3233{ 3234 int i; 3235 u_int8_t bSendData; 3236 3237 for (i = 0; i < 3; i++, bCmd <<= 1) { 3238 /* 3239 * Program SB+OP code 3240 */ 3241 bSendData = NVR_SELECT; 3242 if (bCmd & 0x04) 3243 bSendData |= NVR_BITOUT; 3244 /* start from bit 2 */ 3245 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3246 NVRAM_trm_wait_30us(pACB); 3247 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3248 NVRAM_trm_wait_30us(pACB); 3249 } 3250 for (i = 0; i < 7; i++, bAddr <<= 1) { 3251 /* 3252 * Program address 3253 */ 3254 bSendData = NVR_SELECT; 3255 if (bAddr & 0x40) 3256 /* Start from bit 6 */ 3257 bSendData |= NVR_BITOUT; 3258 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3259 NVRAM_trm_wait_30us(pACB); 3260 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3261 NVRAM_trm_wait_30us(pACB); 3262 } 3263 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3264 NVRAM_trm_wait_30us(pACB); 3265} 3266 3267static void 3268trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3269{ 3270 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3271 u_int16_t wAddr, wCheckSum; 3272 u_long dAddr, *dpEeprom; 3273 3274 NVRAM_trm_read_all(pEEpromBuf,pACB); 3275 wCheckSum = 0; 3276 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3277 wAddr < 64; wAddr++, wpEeprom++) { 3278 wCheckSum += *wpEeprom; 3279 } 3280 if (wCheckSum != 0x1234) { 3281 /* 3282 * Checksum error, load default 3283 */ 3284 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3285 pEEpromBuf->NvramSubVendorID[1] = 3286 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3287 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3288 pEEpromBuf->NvramSubSysID[1] = 3289 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3290 pEEpromBuf->NvramSubClass = 0x00; 3291 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3292 pEEpromBuf->NvramVendorID[1] = 3293 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3294 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3295 pEEpromBuf->NvramDeviceID[1] = 3296 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3297 pEEpromBuf->NvramReserved = 0x00; 3298 3299 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3300 dAddr < 16; dAddr++, dpEeprom++) { 3301 *dpEeprom = 0x00000077; 3302 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3303 } 3304 3305 *dpEeprom++ = 0x04000F07; 3306 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3307 *dpEeprom++ = 0x00000015; 3308 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3309 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3310 *dpEeprom = 0x00; 3311 pEEpromBuf->NvramCheckSum = 0x00; 3312 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3313 wAddr < 63; wAddr++, wpEeprom++) 3314 wCheckSum += *wpEeprom; 3315 *wpEeprom = 0x1234 - wCheckSum; 3316 NVRAM_trm_write_all(pEEpromBuf,pACB); 3317 } 3318 return; 3319} 3320static int 3321trm_initAdapter(PACB pACB, u_int16_t unit) 3322{ 3323 PNVRAMTYPE pEEpromBuf; 3324 u_int16_t wval; 3325 u_int8_t bval; 3326 3327 pEEpromBuf = &trm_eepromBuf[unit]; 3328 3329 /* 250ms selection timeout */ 3330 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3331 /* Mask all the interrupt */ 3332 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3333 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3334 /* Reset SCSI module */ 3335 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3336 /* program configuration 0 */ 3337 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3338 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3339 pACB->Config |= HCC_WIDE_CARD; 3340 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3341 pACB->Config |= HCC_SCSI_RESET; 3342 if (pACB->Config & HCC_PARITY) 3343 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3344 else 3345 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3346 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3347 /* program configuration 1 */ 3348 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3349 /* program Host ID */ 3350 bval = pEEpromBuf->NvramScsiId; 3351 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3352 /* set ansynchronous transfer */ 3353 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3354 /* Trun LED control off*/ 3355 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3356 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3357 /* DMA config */ 3358 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3359 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3360 /* Clear pending interrupt status */ 3361 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3362 /* Enable SCSI interrupt */ 3363 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3364 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3365 return (0); 3366} 3367 3368static void 3369trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3370{ 3371 PACB pACB; 3372 3373 pACB = (PACB)arg; 3374 pACB->srb_physbase = segs->ds_addr; 3375} 3376 3377static void 3378trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3379{ 3380 bus_addr_t *baddr; 3381 3382 baddr = (bus_addr_t *)arg; 3383 *baddr = segs->ds_addr; 3384} 3385 3386static PACB 3387trm_init(u_int16_t unit, device_t dev) 3388{ 3389 PACB pACB; 3390 int rid = PCIR_BAR(0), i = 0, j = 0; 3391 u_int16_t adaptType = 0; 3392 3393 pACB = (PACB) device_get_softc(dev); 3394 if (!pACB) { 3395 printf("trm%d: cannot allocate ACB !\n", unit); 3396 return (NULL); 3397 } 3398 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3399 &rid, RF_ACTIVE); 3400 if (pACB->iores == NULL) { 3401 printf("trm_init: bus_alloc_resource failed!\n"); 3402 return (NULL); 3403 } 3404 switch (pci_get_devid(dev)) { 3405 case PCI_DEVICEID_TRMS1040: 3406 adaptType = 0; 3407 break; 3408 case PCI_DEVICEID_TRMS2080: 3409 adaptType = 1; 3410 break; 3411 default: 3412 printf("trm_init %d: unknown adapter type!\n", unit); 3413 goto bad; 3414 } 3415 pACB->dev = dev; 3416 pACB->tag = rman_get_bustag(pACB->iores); 3417 pACB->bsh = rman_get_bushandle(pACB->iores); 3418 if (bus_dma_tag_create( 3419 /*parent_dmat*/ pACB->parent_dmat, 3420 /*alignment*/ 1, 3421 /*boundary*/ 0, 3422 /*lowaddr*/ BUS_SPACE_MAXADDR, 3423 /*highaddr*/ BUS_SPACE_MAXADDR, 3424 /*filter*/ NULL, 3425 /*filterarg*/ NULL, 3426 /*maxsize*/ MAXBSIZE, 3427 /*nsegments*/ TRM_NSEG, 3428 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3429 /*flags*/ BUS_DMA_ALLOCNOW, 3430 /*lockfunc*/ busdma_lock_mutex, 3431 /*lockarg*/ &Giant, 3432 /* dmat */ &pACB->buffer_dmat) != 0) 3433 goto bad; 3434 /* DMA tag for our ccb structures */ 3435 if (bus_dma_tag_create( 3436 /*parent_dmat*/pACB->parent_dmat, 3437 /*alignment*/ 1, 3438 /*boundary*/ 0, 3439 /*lowaddr*/ BUS_SPACE_MAXADDR, 3440 /*highaddr*/ BUS_SPACE_MAXADDR, 3441 /*filter*/ NULL, 3442 /*filterarg*/ NULL, 3443 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3444 /*nsegments*/ 1, 3445 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3446 /*flags*/ 0, 3447 /*lockfunc*/ busdma_lock_mutex, 3448 /*lockarg*/ &Giant, 3449 /*dmat*/ &pACB->srb_dmat) != 0) { 3450 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3451 goto bad; 3452 } 3453 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3454 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3455 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3456 goto bad; 3457 } 3458 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3459 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3460 /* flags */0); 3461 /* Create, allocate, and map DMA buffers for autosense data */ 3462 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3463 /*boundary*/0, 3464 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3465 /*highaddr*/BUS_SPACE_MAXADDR, 3466 /*filter*/NULL, /*filterarg*/NULL, 3467 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3468 /*nsegments*/1, 3469 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3470 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3471 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3472 if (bootverbose) 3473 device_printf(dev, "cannot create sense buffer dmat\n"); 3474 goto bad; 3475 } 3476 3477 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3478 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3479 goto bad; 3480 3481 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3482 pACB->sense_buffers, 3483 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3484 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3485 3486 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3487 trm_initACB(pACB, adaptType, unit); 3488 for (i = 0; i < (pACB->max_id + 1); i++) { 3489 if (pACB->AdaptSCSIID == i) 3490 continue; 3491 for(j = 0; j < (pACB->max_lun + 1); j++) { 3492 pACB->scan_devices[i][j] = 1; 3493 /* we assume we need to scan all devices */ 3494 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3495 } 3496 } 3497 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3498 if (bus_dma_tag_create( 3499 /*parent_dmat*/NULL, 3500 /*alignment*/ 1, 3501 /*boundary*/ 0, 3502 /*lowaddr*/ BUS_SPACE_MAXADDR, 3503 /*highaddr*/ BUS_SPACE_MAXADDR, 3504 /*filter*/ NULL, 3505 /*filterarg*/ NULL, 3506 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3507 /*nsegments*/ 1, 3508 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3509 /*flags*/ 0, 3510 /*lockfunc*/ busdma_lock_mutex, 3511 /*lockarg*/ &Giant, 3512 /*dmat*/ &pACB->sg_dmat) != 0) 3513 goto bad; 3514 3515 if (trm_initSRB(pACB)) { 3516 printf("trm_initSRB: error\n"); 3517 goto bad; 3518 } 3519 if (trm_initAdapter(pACB, unit)) { 3520 printf("trm_initAdapter: initial ERROR\n"); 3521 goto bad; 3522 } 3523 return (pACB); 3524bad: 3525 if (pACB->iores) 3526 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3527 pACB->iores); 3528 if (pACB->sense_dmamap) { 3529 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3530 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3531 pACB->sense_dmamap); 3532 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3533 } 3534 if (pACB->sense_dmat) 3535 bus_dma_tag_destroy(pACB->sense_dmat); 3536 if (pACB->sg_dmat) { 3537 trm_destroySRB(pACB); 3538 bus_dma_tag_destroy(pACB->sg_dmat); 3539 } 3540 if (pACB->srb_dmamap) { 3541 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3542 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3543 pACB->srb_dmamap); 3544 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3545 } 3546 if (pACB->srb_dmat) 3547 bus_dma_tag_destroy(pACB->srb_dmat); 3548 if (pACB->buffer_dmat) 3549 bus_dma_tag_destroy(pACB->buffer_dmat); 3550 return (NULL); 3551} 3552 3553static int 3554trm_attach(device_t dev) 3555{ 3556 struct cam_devq *device_Q; 3557 u_long device_id; 3558 PACB pACB = 0; 3559 int rid = 0; 3560 int unit = device_get_unit(dev); 3561 3562 device_id = pci_get_devid(dev); 3563 /* 3564 * These cards do not allow memory mapped accesses 3565 */ 3566 if ((pACB = trm_init((u_int16_t) unit, 3567 dev)) == NULL) { 3568 printf("trm%d: trm_init error!\n",unit); 3569 return (ENXIO); 3570 } 3571 /* After setting up the adapter, map our interrupt */ 3572 /* 3573 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3574 * start queue to reset to the idle loop. 3575 * Create device queue of SIM(s) 3576 * (MAX_START_JOB - 1) : max_sim_transactions 3577 */ 3578 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3579 RF_SHAREABLE | RF_ACTIVE); 3580 if (pACB->irq == NULL || 3581 bus_setup_intr(dev, pACB->irq, 3582 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3583 printf("trm%d: register Interrupt handler error!\n", unit); 3584 goto bad; 3585 } 3586 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3587 if (device_Q == NULL){ 3588 printf("trm%d: device_Q == NULL !\n",unit); 3589 goto bad; 3590 } 3591 /* 3592 * Now tell the generic SCSI layer 3593 * about our bus. 3594 * If this is the xpt layer creating a sim, then it's OK 3595 * to wait for an allocation. 3596 * XXX Should we pass in a flag to indicate that wait is OK? 3597 * 3598 * SIM allocation 3599 * 3600 * SCSI Interface Modules 3601 * The sim driver creates a sim for each controller. The sim device 3602 * queue is separately created in order to allow resource sharing betwee 3603 * sims. For instance, a driver may create one sim for each channel of 3604 * a multi-channel controller and use the same queue for each channel. 3605 * In this way, the queue resources are shared across all the channels 3606 * of the multi-channel controller. 3607 * trm_action : sim_action_func 3608 * trm_poll : sim_poll_func 3609 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3610 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3611 * pACB->unit : unit 3612 * 1 : max_dev_transactions 3613 * MAX_TAGS : max_tagged_dev_transactions 3614 * 3615 * *******Construct our first channel SIM entry 3616 */ 3617 pACB->psim = cam_sim_alloc(trm_action, 3618 trm_poll, 3619 "trm", 3620 pACB, 3621 unit, 3622 1, 3623 TRM_MAX_TAGS_CMD_QUEUE, 3624 device_Q); 3625 if (pACB->psim == NULL) { 3626 printf("trm%d: SIM allocate fault !\n",unit); 3627 cam_simq_free(device_Q); /* SIM allocate fault*/ 3628 goto bad; 3629 } 3630 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3631 printf("trm%d: xpt_bus_register fault !\n",unit); 3632 goto bad; 3633 } 3634 if (xpt_create_path(&pACB->ppath, 3635 NULL, 3636 cam_sim_path(pACB->psim), 3637 CAM_TARGET_WILDCARD, 3638 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3639 printf("trm%d: xpt_create_path fault !\n",unit); 3640 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3641 goto bad; 3642 } 3643 return (0); 3644bad: 3645 if (pACB->iores) 3646 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3647 pACB->iores); 3648 if (pACB->sg_dmat) { 3649 trm_destroySRB(pACB); 3650 bus_dma_tag_destroy(pACB->sg_dmat); 3651 } 3652 3653 if (pACB->srb_dmamap) { 3654 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3655 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3656 pACB->srb_dmamap); 3657 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3658 } 3659 if (pACB->srb_dmat) 3660 bus_dma_tag_destroy(pACB->srb_dmat); 3661 if (pACB->sense_dmamap) { 3662 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3663 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3664 pACB->sense_dmamap); 3665 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3666 } 3667 if (pACB->sense_dmat) 3668 bus_dma_tag_destroy(pACB->sense_dmat); 3669 if (pACB->buffer_dmat) 3670 bus_dma_tag_destroy(pACB->buffer_dmat); 3671 if (pACB->ih) 3672 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3673 if (pACB->irq) 3674 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3675 if (pACB->psim) 3676 cam_sim_free(pACB->psim, TRUE); 3677 3678 return (ENXIO); 3679 3680} 3681 3682/* 3683* pci_device 3684* trm_probe (device_t tag, pcidi_t type) 3685* 3686*/ 3687static int 3688trm_probe(device_t dev) 3689{ 3690 switch (pci_get_devid(dev)) { 3691 case PCI_DEVICEID_TRMS1040: 3692 device_set_desc(dev, 3693 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3694 return (BUS_PROBE_DEFAULT); 3695 case PCI_DEVICEID_TRMS2080: 3696 device_set_desc(dev, 3697 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3698 return (BUS_PROBE_DEFAULT); 3699 default: 3700 return (ENXIO); 3701 } 3702} 3703 3704static int 3705trm_detach(device_t dev) 3706{ 3707 PACB pACB = device_get_softc(dev); 3708 3709 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3710 trm_destroySRB(pACB); 3711 bus_dma_tag_destroy(pACB->sg_dmat); 3712 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3713 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3714 pACB->srb_dmamap); 3715 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3716 bus_dma_tag_destroy(pACB->srb_dmat); 3717 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3718 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3719 pACB->sense_dmamap); 3720 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3721 bus_dma_tag_destroy(pACB->sense_dmat); 3722 bus_dma_tag_destroy(pACB->buffer_dmat); 3723 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3724 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3725 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3726 xpt_free_path(pACB->ppath); 3727 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3728 cam_sim_free(pACB->psim, TRUE); 3729 return (0); 3730} 3731static device_method_t trm_methods[] = { 3732 /* Device interface */ 3733 DEVMETHOD(device_probe, trm_probe), 3734 DEVMETHOD(device_attach, trm_attach), 3735 DEVMETHOD(device_detach, trm_detach), 3736 { 0, 0 } 3737}; 3738 3739static driver_t trm_driver = { 3740 "trm", trm_methods, sizeof(struct _ACB) 3741}; 3742 3743static devclass_t trm_devclass; 3744DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3745MODULE_DEPEND(trm, cam, 1, 1, 1); 3746