trm.c revision 119690
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 *(C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 12 */ 13 14#include <sys/cdefs.h> 15__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 119690 2003-09-02 17:30:40Z jhb $"); 16 17/* 18 * HISTORY: 19 * 20 * REV# DATE NAME DESCRIPTION 21 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 22 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 23 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 24 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 25 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 26 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 27 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 28 */ 29 30/* 31 * 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 */ 56 57/* 58 * Imported into FreeBSD source repository, and updated to compile under 59 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 60 */ 61 62/* 63 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 64 * <doginou@ci0.org>, 2002-03-04 65 */ 66 67#include <sys/cdefs.h> 68__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 119690 2003-09-02 17:30:40Z jhb $"); 69 70#include <sys/param.h> 71 72#include <sys/systm.h> 73#include <sys/malloc.h> 74#include <sys/queue.h> 75#if __FreeBSD_version >= 500000 76#include <sys/bio.h> 77#endif 78#include <sys/buf.h> 79#include <sys/bus.h> 80#include <sys/kernel.h> 81 82#include <vm/vm.h> 83#include <vm/pmap.h> 84 85#include <dev/pci/pcivar.h> 86#include <dev/pci/pcireg.h> 87#include <machine/resource.h> 88#include <machine/bus_pio.h> 89#include <machine/bus.h> 90#include <machine/clock.h> 91#include <sys/rman.h> 92 93#include <cam/cam.h> 94#include <cam/cam_ccb.h> 95#include <cam/cam_sim.h> 96#include <cam/cam_xpt_sim.h> 97#include <cam/cam_debug.h> 98 99#include <cam/scsi/scsi_all.h> 100#include <cam/scsi/scsi_message.h> 101 102#include <dev/trm/trm.h> 103 104#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 105#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 106#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 107#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 108 reg, value) 109#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 110 reg, value) 111#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 112 reg, value) 113 114#define PCI_Vendor_ID_TEKRAM 0x1DE1 115#define PCI_Device_ID_TRM_S1040 0x0391 116#define PCI_DEVICEID_TRMS1040 0x03911DE1 117#define PCI_DEVICEID_TRMS2080 0x03921DE1 118 119#ifdef trm_DEBUG1 120#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 121#else 122#define TRM_DPRINTF(fmt, arg...) {} 123#endif /* TRM_DEBUG */ 124 125static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 126static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 127static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 128static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 129static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 130static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 131static void NVRAM_trm_wait_30us(PACB pACB); 132 133static void trm_Interrupt(void *vpACB); 134static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 135 u_int16_t * pscsi_status); 136static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 137 u_int16_t * pscsi_status); 138static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 139 u_int16_t * pscsi_status); 140static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 141 u_int16_t * pscsi_status); 142static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 143 u_int16_t * pscsi_status); 144static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 145 u_int16_t * pscsi_status); 146static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 147 u_int16_t * pscsi_status); 148static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 149 u_int16_t * pscsi_status); 150static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 151 u_int16_t * pscsi_status); 152static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 153 u_int16_t * pscsi_status); 154static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 155 u_int16_t * pscsi_status); 156static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 157 u_int16_t * pscsi_status); 158static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 159static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 160static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 161static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 162static void trm_Disconnect(PACB pACB); 163static void trm_Reselect(PACB pACB); 164static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 165static void trm_DoingSRB_Done(PACB pACB); 166static void trm_ScsiRstDetect(PACB pACB); 167static void trm_ResetSCSIBus(PACB pACB); 168static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 169static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 170static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 171static void trm_SendSRB(PACB pACB, PSRB pSRB); 172static int trm_probe(device_t tag); 173static int trm_attach(device_t tag); 174static void trm_reset(PACB pACB); 175 176static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 177 178static int trm_initAdapter(PACB pACB, u_int16_t unit); 179static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 180 u_int32_t i, u_int32_t j); 181static int trm_initSRB(PACB pACB); 182static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 183/* CAM SIM entry points */ 184#define ccb_trmsrb_ptr spriv_ptr0 185#define ccb_trmacb_ptr spriv_ptr1 186static void trm_action(struct cam_sim *psim, union ccb *pccb); 187static void trm_poll(struct cam_sim *psim); 188 189 190static void * trm_SCSI_phase0[] = { 191 trm_DataOutPhase0, /* phase:0 */ 192 trm_DataInPhase0, /* phase:1 */ 193 trm_CommandPhase0, /* phase:2 */ 194 trm_StatusPhase0, /* phase:3 */ 195 trm_Nop0, /* phase:4 */ 196 trm_Nop1, /* phase:5 */ 197 trm_MsgOutPhase0, /* phase:6 */ 198 trm_MsgInPhase0, /* phase:7 */ 199}; 200 201/* 202 * 203 * stateV = (void *) trm_SCSI_phase1[phase] 204 * 205 */ 206static void * trm_SCSI_phase1[] = { 207 trm_DataOutPhase1, /* phase:0 */ 208 trm_DataInPhase1, /* phase:1 */ 209 trm_CommandPhase1, /* phase:2 */ 210 trm_StatusPhase1, /* phase:3 */ 211 trm_Nop0, /* phase:4 */ 212 trm_Nop1, /* phase:5 */ 213 trm_MsgOutPhase1, /* phase:6 */ 214 trm_MsgInPhase1, /* phase:7 */ 215}; 216 217 218NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 219/* 220 *Fast20: 000 50ns, 20.0 Mbytes/s 221 * 001 75ns, 13.3 Mbytes/s 222 * 010 100ns, 10.0 Mbytes/s 223 * 011 125ns, 8.0 Mbytes/s 224 * 100 150ns, 6.6 Mbytes/s 225 * 101 175ns, 5.7 Mbytes/s 226 * 110 200ns, 5.0 Mbytes/s 227 * 111 250ns, 4.0 Mbytes/s 228 * 229 *Fast40: 000 25ns, 40.0 Mbytes/s 230 * 001 50ns, 20.0 Mbytes/s 231 * 010 75ns, 13.3 Mbytes/s 232 * 011 100ns, 10.0 Mbytes/s 233 * 100 125ns, 8.0 Mbytes/s 234 * 101 150ns, 6.6 Mbytes/s 235 * 110 175ns, 5.7 Mbytes/s 236 * 111 200ns, 5.0 Mbytes/s 237 */ 238 /* real period: */ 239u_int8_t dc395x_clock_period[] = { 240 12,/* 48 ns 20 MB/sec */ 241 18,/* 72 ns 13.3 MB/sec */ 242 25,/* 100 ns 10.0 MB/sec */ 243 31,/* 124 ns 8.0 MB/sec */ 244 37,/* 148 ns 6.6 MB/sec */ 245 43,/* 172 ns 5.7 MB/sec */ 246 50,/* 200 ns 5.0 MB/sec */ 247 62 /* 248 ns 4.0 MB/sec */ 248}; 249 250u_int8_t dc395u2x_clock_period[]={ 251 10,/* 25 ns 40.0 MB/sec */ 252 12,/* 48 ns 20.0 MB/sec */ 253 18,/* 72 ns 13.3 MB/sec */ 254 25,/* 100 ns 10.0 MB/sec */ 255 31,/* 124 ns 8.0 MB/sec */ 256 37,/* 148 ns 6.6 MB/sec */ 257 43,/* 172 ns 5.7 MB/sec */ 258 50,/* 200 ns 5.0 MB/sec */ 259}; 260 261#define dc395x_tinfo_period dc395x_clock_period 262#define dc395u2x_tinfo_period dc395u2x_clock_period 263 264static PSRB 265trm_GetSRB(PACB pACB) 266{ 267 int intflag; 268 PSRB pSRB; 269 270 intflag = splcam(); 271 pSRB = pACB->pFreeSRB; 272 if (pSRB) { 273 pACB->pFreeSRB = pSRB->pNextSRB; 274 pSRB->pNextSRB = NULL; 275 } 276 splx(intflag); 277 return (pSRB); 278} 279 280static void 281trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 282{ 283 PSRB psrb1; 284 int intflag; 285 286 intflag = splcam(); 287 if ((psrb1 = pDCB->pWaitingSRB)) { 288 pSRB->pNextSRB = psrb1; 289 pDCB->pWaitingSRB = pSRB; 290 } else { 291 pSRB->pNextSRB = NULL; 292 pDCB->pWaitingSRB = pSRB; 293 pDCB->pWaitingLastSRB = pSRB; 294 } 295 splx(intflag); 296} 297 298static void 299trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 300{ 301 PSRB psrb1; 302 int intflag; 303 304 intflag = splcam(); 305 pDCB->GoingSRBCnt--; 306 psrb1 = pDCB->pGoingSRB; 307 if (pSRB == psrb1) 308 /* 309 * if this SRB is GoingSRB 310 * remove this SRB from GoingSRB Q 311 */ 312 pDCB->pGoingSRB = psrb1->pNextSRB; 313 else { 314 /* 315 * if this SRB is not current GoingSRB 316 * remove this SRB from GoingSRB Q 317 */ 318 while (pSRB != psrb1->pNextSRB) 319 psrb1 = psrb1->pNextSRB; 320 psrb1->pNextSRB = pSRB->pNextSRB; 321 if (pSRB == pDCB->pGoingLastSRB) 322 pDCB->pGoingLastSRB = psrb1; 323 } 324 if ((psrb1 = pDCB->pWaitingSRB)) { 325 /* 326 * if WaitingSRB Q is not NULL 327 * Q back this SRB into WaitingSRB 328 */ 329 330 pSRB->pNextSRB = psrb1; 331 pDCB->pWaitingSRB = pSRB; 332 } else { 333 pSRB->pNextSRB = NULL; 334 pDCB->pWaitingSRB = pSRB; 335 pDCB->pWaitingLastSRB = pSRB; 336 } 337 splx(intflag); 338} 339 340static void 341trm_DoWaitingSRB(PACB pACB) 342{ 343 int intflag; 344 PDCB ptr, ptr1; 345 PSRB pSRB; 346 347 intflag = splcam(); 348 if (!(pACB->pActiveDCB) && 349 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 350 ptr = pACB->pDCBRunRobin; 351 if (!ptr) { 352 ptr = pACB->pLinkDCB; 353 pACB->pDCBRunRobin = ptr; 354 } 355 ptr1 = ptr; 356 for (;ptr1 ;) { 357 pACB->pDCBRunRobin = ptr1->pNextDCB; 358 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 359 || !(pSRB = ptr1->pWaitingSRB)) { 360 if (pACB->pDCBRunRobin == ptr) 361 break; 362 ptr1 = ptr1->pNextDCB; 363 } else { 364 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 365 /* 366 * If trm_StartSCSI return 0 : 367 * current interrupt status is interrupt enable 368 * It's said that SCSI processor is unoccupied 369 */ 370 ptr1->GoingSRBCnt++; 371 if (ptr1->pWaitingLastSRB == pSRB) { 372 ptr1->pWaitingSRB = NULL; 373 ptr1->pWaitingLastSRB = NULL; 374 } else 375 ptr1->pWaitingSRB = pSRB->pNextSRB; 376 pSRB->pNextSRB = NULL; 377 if (ptr1->pGoingSRB) 378 ptr1->pGoingLastSRB->pNextSRB = pSRB; 379 else 380 ptr1->pGoingSRB = pSRB; 381 ptr1->pGoingLastSRB = pSRB; 382 } 383 break; 384 } 385 } 386 } 387 splx(intflag); 388 return; 389} 390 391static void 392trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 393{ 394 395 if (pDCB->pWaitingSRB) { 396 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 397 pDCB->pWaitingLastSRB = pSRB; 398 pSRB->pNextSRB = NULL; 399 } else { 400 pDCB->pWaitingSRB = pSRB; 401 pDCB->pWaitingLastSRB = pSRB; 402 } 403} 404 405static u_int32_t 406trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 407{ 408 int offset; 409 410 offset = pSRB->TagNumber; 411 return (pACB->sense_busaddr + 412 (offset * sizeof(struct scsi_sense_data))); 413} 414 415static struct scsi_sense_data * 416trm_get_sense_buf(PACB pACB, PSRB pSRB) 417{ 418 int offset; 419 420 offset = pSRB->TagNumber; 421 return (&pACB->sense_buffers[offset]); 422} 423static void 424trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 425{ 426 int flags; 427 PACB pACB; 428 PSRB pSRB; 429 union ccb *ccb; 430 u_long totalxferlen=0; 431 432 flags = splcam(); 433 pSRB = (PSRB)arg; 434 ccb = pSRB->pccb; 435 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 436 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 437 if (nseg != 0) { 438 PSEG psg; 439 bus_dma_segment_t *end_seg; 440 int op; 441 442 /* Copy the segments into our SG list */ 443 end_seg = dm_segs + nseg; 444 psg = pSRB->pSRBSGL; 445 while (dm_segs < end_seg) { 446 psg->address = dm_segs->ds_addr; 447 psg->length = (u_long)dm_segs->ds_len; 448 totalxferlen += dm_segs->ds_len; 449 psg++; 450 dm_segs++; 451 } 452 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 453 op = BUS_DMASYNC_PREREAD; 454 } else { 455 op = BUS_DMASYNC_PREWRITE; 456 } 457 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 458 } 459 pSRB->RetryCnt = 0; 460 pSRB->SRBTotalXferLength = totalxferlen; 461 pSRB->SRBSGCount = nseg; 462 pSRB->SRBSGIndex = 0; 463 pSRB->AdaptStatus = 0; 464 pSRB->TargetStatus = 0; 465 pSRB->MsgCnt = 0; 466 pSRB->SRBStatus = 0; 467 pSRB->SRBFlag = 0; 468 pSRB->SRBState = 0; 469 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 470 471 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 472 if (nseg != 0) 473 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 474 pSRB->pNextSRB = pACB->pFreeSRB; 475 pACB->pFreeSRB = pSRB; 476 xpt_done(ccb); 477 splx(flags); 478 return; 479 } 480 ccb->ccb_h.status |= CAM_SIM_QUEUED; 481#if 0 482 /* XXX Need a timeout handler */ 483 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 484#endif 485 trm_SendSRB(pACB, pSRB); 486 splx(flags); 487 return; 488} 489 490static void 491trm_SendSRB(PACB pACB, PSRB pSRB) 492{ 493 PDCB pDCB; 494 495 pDCB = pSRB->pSRBDCB; 496 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 497 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 498 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 499 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 500 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 501 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 502 trm_SRBwaiting(pDCB, pSRB); 503 goto SND_EXIT; 504 } 505 506 if (pDCB->pWaitingSRB) { 507 trm_SRBwaiting(pDCB, pSRB); 508 pSRB = pDCB->pWaitingSRB; 509 pDCB->pWaitingSRB = pSRB->pNextSRB; 510 pSRB->pNextSRB = NULL; 511 } 512 513 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 514 /* 515 * If trm_StartSCSI return 0 : 516 * current interrupt status is interrupt enable 517 * It's said that SCSI processor is unoccupied 518 */ 519 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 520 if (pDCB->pGoingSRB) { 521 pDCB->pGoingLastSRB->pNextSRB = pSRB; 522 pDCB->pGoingLastSRB = pSRB; 523 } else { 524 pDCB->pGoingSRB = pSRB; 525 pDCB->pGoingLastSRB = pSRB; 526 } 527 } else { 528 /* 529 * If trm_StartSCSI return 1 : 530 * current interrupt status is interrupt disreenable 531 * It's said that SCSI processor has more one SRB need to do 532 */ 533 trm_RewaitSRB0(pDCB, pSRB); 534 } 535SND_EXIT: 536 return; 537} 538 539 540static void 541trm_action(struct cam_sim *psim, union ccb *pccb) 542{ 543 PACB pACB; 544 int actionflags; 545 u_int target_id,target_lun; 546 547 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 548 549 actionflags = splcam(); 550 pACB = (PACB) cam_sim_softc(psim); 551 target_id = pccb->ccb_h.target_id; 552 target_lun = pccb->ccb_h.target_lun; 553 554 switch (pccb->ccb_h.func_code) { 555 case XPT_NOOP: 556 TRM_DPRINTF(" XPT_NOOP \n"); 557 pccb->ccb_h.status = CAM_REQ_INVALID; 558 xpt_done(pccb); 559 break; 560 /* 561 * Execute the requested I/O operation 562 */ 563 case XPT_SCSI_IO: { 564 PDCB pDCB = NULL; 565 PSRB pSRB; 566 struct ccb_scsiio *pcsio; 567 568 pcsio = &pccb->csio; 569 TRM_DPRINTF(" XPT_SCSI_IO \n"); 570 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 571 ,target_id, target_lun); 572 TRM_DPRINTF( 573 "pACB->scan_devices[target_id][target_lun]= %d \n" 574 ,pACB->scan_devices[target_id][target_lun]); 575 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 576 CAM_REQ_INPROG) { 577 xpt_done(pccb); 578 splx(actionflags); 579 return; 580 } 581 pDCB = &pACB->DCBarray[target_id][target_lun]; 582 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 583 pACB->scan_devices[target_id][target_lun] = 1; 584 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 585 target_id, target_lun); 586 } 587 /* 588 * Assign an SRB and connect it with this ccb. 589 */ 590 pSRB = trm_GetSRB(pACB); 591 if (!pSRB) { 592 /* Freeze SIMQ */ 593 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 594 xpt_done(pccb); 595 splx(actionflags); 596 return; 597 } 598 pSRB->pSRBDCB = pDCB; 599 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 600 pccb->ccb_h.ccb_trmacb_ptr = pACB; 601 pSRB->pccb = pccb; 602 pSRB->ScsiCmdLen = pcsio->cdb_len; 603 /* 604 * move layer of CAM command block to layer of SCSI 605 * Request Block for SCSI processor command doing 606 */ 607 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 608 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 609 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 610 ,pcsio->cdb_len); 611 } else { 612 pccb->ccb_h.status = CAM_REQ_INVALID; 613 pSRB->pNextSRB = pACB->pFreeSRB; 614 pACB->pFreeSRB= pSRB; 615 xpt_done(pccb); 616 splx(actionflags); 617 return; 618 } 619 } else 620 bcopy(pcsio->cdb_io.cdb_bytes, 621 pSRB->CmdBlock, pcsio->cdb_len); 622 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 623 != CAM_DIR_NONE) { 624 if ((pccb->ccb_h.flags & 625 CAM_SCATTER_VALID) == 0) { 626 if ((pccb->ccb_h.flags 627 & CAM_DATA_PHYS) == 0) { 628 int vmflags; 629 int error; 630 631 vmflags = splsoftvm(); 632 error = bus_dmamap_load( 633 pACB->buffer_dmat, 634 pSRB->dmamap, 635 pcsio->data_ptr, 636 pcsio->dxfer_len, 637 trm_ExecuteSRB, 638 pSRB, 639 0); 640 if (error == EINPROGRESS) { 641 xpt_freeze_simq( 642 pACB->psim, 643 1); 644 pccb->ccb_h.status |= 645 CAM_RELEASE_SIMQ; 646 } 647 splx(vmflags); 648 } else { 649 struct bus_dma_segment seg; 650 651 /* Pointer to physical buffer */ 652 seg.ds_addr = 653 (bus_addr_t)pcsio->data_ptr; 654 seg.ds_len = pcsio->dxfer_len; 655 trm_ExecuteSRB(pSRB, &seg, 1, 656 0); 657 } 658 } else { 659 /* CAM_SCATTER_VALID */ 660 struct bus_dma_segment *segs; 661 662 if ((pccb->ccb_h.flags & 663 CAM_SG_LIST_PHYS) == 0 || 664 (pccb->ccb_h.flags 665 & CAM_DATA_PHYS) != 0) { 666 pSRB->pNextSRB = pACB->pFreeSRB; 667 pACB->pFreeSRB = pSRB; 668 pccb->ccb_h.status = 669 CAM_PROVIDE_FAIL; 670 xpt_done(pccb); 671 splx(actionflags); 672 return; 673 } 674 675 /* cam SG list is physical, 676 * cam data is virtual 677 */ 678 segs = (struct bus_dma_segment *) 679 pcsio->data_ptr; 680 trm_ExecuteSRB(pSRB, segs, 681 pcsio->sglist_cnt, 1); 682 } /* CAM_SCATTER_VALID */ 683 } else 684 trm_ExecuteSRB(pSRB, NULL, 0, 0); 685 } 686 break; 687 case XPT_GDEV_TYPE: 688 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 689 pccb->ccb_h.status = CAM_REQ_INVALID; 690 xpt_done(pccb); 691 break; 692 case XPT_GDEVLIST: 693 TRM_DPRINTF(" XPT_GDEVLIST \n"); 694 pccb->ccb_h.status = CAM_REQ_INVALID; 695 xpt_done(pccb); 696 break; 697 /* 698 * Path routing inquiry 699 * Path Inquiry CCB 700 */ 701 case XPT_PATH_INQ: { 702 struct ccb_pathinq *cpi = &pccb->cpi; 703 704 TRM_DPRINTF(" XPT_PATH_INQ \n"); 705 cpi->version_num = 1; 706 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 707 cpi->target_sprt = 0; 708 cpi->hba_misc = 0; 709 cpi->hba_eng_cnt = 0; 710 cpi->max_target = 15 ; 711 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 712 cpi->initiator_id = pACB->AdaptSCSIID; 713 cpi->bus_id = cam_sim_bus(psim); 714 cpi->base_transfer_speed = 3300; 715 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 716 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 717 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 718 cpi->unit_number = cam_sim_unit(psim); 719 cpi->ccb_h.status = CAM_REQ_CMP; 720 xpt_done(pccb); 721 } 722 break; 723 /* 724 * Release a frozen SIM queue 725 * Release SIM Queue 726 */ 727 case XPT_REL_SIMQ: 728 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 729 pccb->ccb_h.status = CAM_REQ_INVALID; 730 xpt_done(pccb); 731 break; 732 /* 733 * Set Asynchronous Callback Parameters 734 * Set Asynchronous Callback CCB 735 */ 736 case XPT_SASYNC_CB: 737 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 738 pccb->ccb_h.status = CAM_REQ_INVALID; 739 xpt_done(pccb); 740 break; 741 /* 742 * Set device type information 743 * Set Device Type CCB 744 */ 745 case XPT_SDEV_TYPE: 746 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 747 pccb->ccb_h.status = CAM_REQ_INVALID; 748 xpt_done(pccb); 749 break; 750 /* 751 * (Re)Scan the SCSI Bus 752 * Rescan the given bus, or bus/target/lun 753 */ 754 case XPT_SCAN_BUS: 755 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 756 pccb->ccb_h.status = CAM_REQ_INVALID; 757 xpt_done(pccb); 758 break; 759 /* 760 * Get EDT entries matching the given pattern 761 */ 762 case XPT_DEV_MATCH: 763 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 764 pccb->ccb_h.status = CAM_REQ_INVALID; 765 xpt_done(pccb); 766 break; 767 /* 768 * Turn on debugging for a bus, target or lun 769 */ 770 case XPT_DEBUG: 771 TRM_DPRINTF(" XPT_DEBUG \n"); 772 pccb->ccb_h.status = CAM_REQ_INVALID; 773 xpt_done(pccb); 774 break; 775 /* 776 * XPT_ABORT = 0x10, Abort the specified CCB 777 * Abort XPT request CCB 778 */ 779 case XPT_ABORT: 780 TRM_DPRINTF(" XPT_ABORT \n"); 781 pccb->ccb_h.status = CAM_REQ_INVALID; 782 xpt_done(pccb); 783 break; 784 /* 785 * Reset the specified SCSI bus 786 * Reset SCSI Bus CCB 787 */ 788 case XPT_RESET_BUS: { 789 int i; 790 791 TRM_DPRINTF(" XPT_RESET_BUS \n"); 792 trm_reset(pACB); 793 pACB->ACBFlag=0; 794 for (i=0; i<500; i++) 795 DELAY(1000); 796 pccb->ccb_h.status = CAM_REQ_CMP; 797 xpt_done(pccb); 798 } 799 break; 800 /* 801 * Bus Device Reset the specified SCSI device 802 * Reset SCSI Device CCB 803 */ 804 case XPT_RESET_DEV: 805 /* 806 * Don't (yet?) support vendor 807 * specific commands. 808 */ 809 TRM_DPRINTF(" XPT_RESET_DEV \n"); 810 pccb->ccb_h.status = CAM_REQ_INVALID; 811 xpt_done(pccb); 812 break; 813 /* 814 * Terminate the I/O process 815 * Terminate I/O Process Request CCB 816 */ 817 case XPT_TERM_IO: 818 TRM_DPRINTF(" XPT_TERM_IO \n"); 819 pccb->ccb_h.status = CAM_REQ_INVALID; 820 xpt_done(pccb); 821 break; 822 /* 823 * Scan Logical Unit 824 */ 825 case XPT_SCAN_LUN: 826 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 827 pccb->ccb_h.status = CAM_REQ_INVALID; 828 xpt_done(pccb); 829 break; 830 831 /* 832 * Get/Set transfer rate/width/disconnection/tag queueing 833 * settings 834 * (GET) default/user transfer settings for the target 835 */ 836 case XPT_GET_TRAN_SETTINGS: { 837 struct ccb_trans_settings *cts; 838 int intflag; 839 struct trm_transinfo *tinfo; 840 PDCB pDCB; 841 842 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 843 cts = &pccb->cts; 844 pDCB = &pACB->DCBarray[target_id][target_lun]; 845 intflag = splcam(); 846 /* 847 * disable interrupt 848 */ 849 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 850 /* current transfer settings */ 851 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 852 cts->flags = CCB_TRANS_DISC_ENB; 853 else 854 cts->flags = 0;/* no tag & disconnect */ 855 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 856 cts->flags |= CCB_TRANS_TAG_ENB; 857 tinfo = &pDCB->tinfo.current; 858 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 859 cts->flags); 860 } else { 861 /* default(user) transfer settings */ 862 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 863 cts->flags = CCB_TRANS_DISC_ENB; 864 else 865 cts->flags = 0; 866 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 867 cts->flags |= CCB_TRANS_TAG_ENB; 868 tinfo = &pDCB->tinfo.user; 869 TRM_DPRINTF("USER: cts->flags= %2x \n", 870 cts->flags); 871 } 872 cts->sync_period = tinfo->period; 873 cts->sync_offset = tinfo->offset; 874 cts->bus_width = tinfo->width; 875 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 876 pDCB->SyncPeriod); 877 TRM_DPRINTF("period: %d \n", tinfo->period); 878 TRM_DPRINTF("offset: %d \n", tinfo->offset); 879 TRM_DPRINTF("width: %d \n", tinfo->width); 880 881 splx(intflag); 882 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 883 CCB_TRANS_SYNC_OFFSET_VALID | 884 CCB_TRANS_BUS_WIDTH_VALID | 885 CCB_TRANS_DISC_VALID | 886 CCB_TRANS_TQ_VALID; 887 pccb->ccb_h.status = CAM_REQ_CMP; 888 xpt_done(pccb); 889 } 890 break; 891 /* 892 * Get/Set transfer rate/width/disconnection/tag queueing 893 * settings 894 * (Set) transfer rate/width negotiation settings 895 */ 896 case XPT_SET_TRAN_SETTINGS: { 897 struct ccb_trans_settings *cts; 898 u_int update_type; 899 int intflag; 900 PDCB pDCB; 901 902 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 903 cts = &pccb->cts; 904 update_type = 0; 905 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 906 update_type |= TRM_TRANS_GOAL; 907 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 908 update_type |= TRM_TRANS_USER; 909 intflag = splcam(); 910 pDCB = &pACB->DCBarray[target_id][target_lun]; 911 912 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 913 /*ccb disc enables */ 914 if (update_type & TRM_TRANS_GOAL) { 915 if ((cts->flags & CCB_TRANS_DISC_ENB) 916 != 0) 917 pDCB->tinfo.disc_tag 918 |= TRM_CUR_DISCENB; 919 else 920 pDCB->tinfo.disc_tag &= 921 ~TRM_CUR_DISCENB; 922 } 923 if (update_type & TRM_TRANS_USER) { 924 if ((cts->flags & CCB_TRANS_DISC_ENB) 925 != 0) 926 pDCB->tinfo.disc_tag 927 |= TRM_USR_DISCENB; 928 else 929 pDCB->tinfo.disc_tag &= 930 ~TRM_USR_DISCENB; 931 } 932 } 933 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 934 /* if ccb tag q active */ 935 if (update_type & TRM_TRANS_GOAL) { 936 if ((cts->flags & CCB_TRANS_TAG_ENB) 937 != 0) 938 pDCB->tinfo.disc_tag |= 939 TRM_CUR_TAGENB; 940 else 941 pDCB->tinfo.disc_tag &= 942 ~TRM_CUR_TAGENB; 943 } 944 if (update_type & TRM_TRANS_USER) { 945 if ((cts->flags & CCB_TRANS_TAG_ENB) 946 != 0) 947 pDCB->tinfo.disc_tag |= 948 TRM_USR_TAGENB; 949 else 950 pDCB->tinfo.disc_tag &= 951 ~TRM_USR_TAGENB; 952 } 953 } 954 /* Minimum sync period factor */ 955 956 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 957 /* if ccb sync active */ 958 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 959 if ((cts->sync_period != 0) && 960 (cts->sync_period < 125)) 961 cts->sync_period = 125; 962 /* 1/(125*4) minsync 2 MByte/sec */ 963 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 964 != 0) { 965 if (cts->sync_offset == 0) 966 cts->sync_period = 0; 967 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 968 if (cts->sync_offset > 15) 969 cts->sync_offset = 15; 970 } 971 } 972 if ((update_type & TRM_TRANS_USER) != 0) { 973 pDCB->tinfo.user.period = cts->sync_period; 974 pDCB->tinfo.user.offset = cts->sync_offset; 975 pDCB->tinfo.user.width = cts->bus_width; 976 } 977 if ((update_type & TRM_TRANS_GOAL) != 0) { 978 pDCB->tinfo.goal.period = cts->sync_period; 979 pDCB->tinfo.goal.offset = cts->sync_offset; 980 pDCB->tinfo.goal.width = cts->bus_width; 981 } 982 splx(intflag); 983 pccb->ccb_h.status = CAM_REQ_CMP; 984 xpt_done(pccb); 985 break; 986 } 987 /* 988 * Calculate the geometry parameters for a device give 989 * the sector size and volume size. 990 */ 991 case XPT_CALC_GEOMETRY: 992 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 993 cam_calc_geometry(&pccb->ccg, /*extended*/1); 994 xpt_done(pccb); 995 break; 996 case XPT_ENG_INQ: 997 TRM_DPRINTF(" XPT_ENG_INQ \n"); 998 pccb->ccb_h.status = CAM_REQ_INVALID; 999 xpt_done(pccb); 1000 break; 1001 /* 1002 * HBA execute engine request 1003 * This structure must match SCSIIO size 1004 */ 1005 case XPT_ENG_EXEC: 1006 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1007 pccb->ccb_h.status = CAM_REQ_INVALID; 1008 xpt_done(pccb); 1009 break; 1010 /* 1011 * XPT_EN_LUN = 0x30, Enable LUN as a target 1012 * Target mode structures. 1013 */ 1014 case XPT_EN_LUN: 1015 /* 1016 * Don't (yet?) support vendor 1017 * specific commands. 1018 */ 1019 TRM_DPRINTF(" XPT_EN_LUN \n"); 1020 pccb->ccb_h.status = CAM_REQ_INVALID; 1021 xpt_done(pccb); 1022 break; 1023 /* 1024 * Execute target I/O request 1025 */ 1026 case XPT_TARGET_IO: 1027 /* 1028 * Don't (yet?) support vendor 1029 * specific commands. 1030 */ 1031 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1032 pccb->ccb_h.status = CAM_REQ_INVALID; 1033 xpt_done(pccb); 1034 break; 1035 /* 1036 * Accept Host Target Mode CDB 1037 */ 1038 case XPT_ACCEPT_TARGET_IO: 1039 /* 1040 * Don't (yet?) support vendor 1041 * specific commands. 1042 */ 1043 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1044 pccb->ccb_h.status = CAM_REQ_INVALID; 1045 xpt_done(pccb); 1046 break; 1047 /* 1048 * Continue Host Target I/O Connection 1049 */ 1050 case XPT_CONT_TARGET_IO: 1051 /* 1052 * Don't (yet?) support vendor 1053 * specific commands. 1054 */ 1055 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1056 pccb->ccb_h.status = CAM_REQ_INVALID; 1057 xpt_done(pccb); 1058 break; 1059 /* 1060 * Notify Host Target driver of event 1061 */ 1062 case XPT_IMMED_NOTIFY: 1063 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1064 pccb->ccb_h.status = CAM_REQ_INVALID; 1065 xpt_done(pccb); 1066 break; 1067 /* 1068 * Acknowledgement of event 1069 */ 1070 case XPT_NOTIFY_ACK: 1071 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1072 pccb->ccb_h.status = CAM_REQ_INVALID; 1073 xpt_done(pccb); 1074 break; 1075 /* 1076 * XPT_VUNIQUE = 0x80 1077 */ 1078 case XPT_VUNIQUE: 1079 pccb->ccb_h.status = CAM_REQ_INVALID; 1080 xpt_done(pccb); 1081 break; 1082 default: 1083 pccb->ccb_h.status = CAM_REQ_INVALID; 1084 xpt_done(pccb); 1085 break; 1086 } 1087 splx(actionflags); 1088} 1089 1090static void 1091trm_poll(struct cam_sim *psim) 1092{ 1093 1094} 1095 1096static void 1097trm_ResetDevParam(PACB pACB) 1098{ 1099 PDCB pDCB, pdcb; 1100 PNVRAMTYPE pEEpromBuf; 1101 u_int8_t PeriodIndex; 1102 1103 pDCB = pACB->pLinkDCB; 1104 if (pDCB == NULL) 1105 return; 1106 pdcb = pDCB; 1107 do { 1108 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1109 pDCB->SyncPeriod = 0; 1110 pDCB->SyncOffset = 0; 1111 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1112 pDCB->DevMode = 1113 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1114 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1115 PeriodIndex = 1116 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1117 if (pACB->AdaptType == 1) /* is U2? */ 1118 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1119 else 1120 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1121 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1122 (pACB->Config & HCC_WIDE_CARD)) 1123 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1124 pDCB = pDCB->pNextDCB; 1125 } 1126 while (pdcb != pDCB); 1127} 1128 1129static void 1130trm_RecoverSRB(PACB pACB) 1131{ 1132 PDCB pDCB, pdcb; 1133 PSRB psrb, psrb2; 1134 u_int16_t cnt, i; 1135 1136 pDCB = pACB->pLinkDCB; 1137 if (pDCB == NULL) 1138 return; 1139 pdcb = pDCB; 1140 do { 1141 cnt = pdcb->GoingSRBCnt; 1142 psrb = pdcb->pGoingSRB; 1143 for (i = 0; i < cnt; i++) { 1144 psrb2 = psrb; 1145 psrb = psrb->pNextSRB; 1146 if (pdcb->pWaitingSRB) { 1147 psrb2->pNextSRB = pdcb->pWaitingSRB; 1148 pdcb->pWaitingSRB = psrb2; 1149 } else { 1150 pdcb->pWaitingSRB = psrb2; 1151 pdcb->pWaitingLastSRB = psrb2; 1152 psrb2->pNextSRB = NULL; 1153 } 1154 } 1155 pdcb->GoingSRBCnt = 0; 1156 pdcb->pGoingSRB = NULL; 1157 pdcb = pdcb->pNextDCB; 1158 } 1159 while (pdcb != pDCB); 1160} 1161 1162static void 1163trm_reset(PACB pACB) 1164{ 1165 int intflag; 1166 u_int16_t i; 1167 1168 TRM_DPRINTF("trm: RESET"); 1169 intflag = splcam(); 1170 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1171 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1172 1173 trm_ResetSCSIBus(pACB); 1174 for (i = 0; i < 500; i++) 1175 DELAY(1000); 1176 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1177 /* Enable DMA interrupt */ 1178 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1179 /* Clear DMA FIFO */ 1180 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1181 /* Clear SCSI FIFO */ 1182 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1183 trm_ResetDevParam(pACB); 1184 trm_DoingSRB_Done(pACB); 1185 pACB->pActiveDCB = NULL; 1186 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1187 trm_DoWaitingSRB(pACB); 1188 /* Tell the XPT layer that a bus reset occured */ 1189 if (pACB->ppath != NULL) 1190 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1191 splx(intflag); 1192 return; 1193} 1194 1195static u_int16_t 1196trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1197{ 1198 u_int16_t return_code; 1199 u_int8_t scsicommand, i,command,identify_message; 1200 u_int8_t * ptr; 1201 union ccb *pccb; 1202 struct ccb_scsiio *pcsio; 1203 1204 pccb = pSRB->pccb; 1205 pcsio = &pccb->csio; 1206 1207 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1208 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1209 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1210 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1211 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1212 /* Flush FIFO */ 1213 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1214 1215 identify_message = pDCB->IdentifyMsg; 1216 1217 if ((pSRB->CmdBlock[0] == INQUIRY) || 1218 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1219 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1220 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1221 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1222 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1223 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1224 if (!(pDCB->IdentifyMsg & 7) || 1225 (pSRB->CmdBlock[0] != INQUIRY)) { 1226 scsicommand = SCMD_SEL_ATNSTOP; 1227 pSRB->SRBState = SRB_MSGOUT; 1228 goto polling; 1229 } 1230 } 1231 /* 1232 * Send identify message 1233 */ 1234 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1235 scsicommand = SCMD_SEL_ATN; 1236 pSRB->SRBState = SRB_START_; 1237 } else { 1238 /* not inquiry,request sense,auto request sense */ 1239 /* 1240 * Send identify message 1241 */ 1242 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1243 scsicommand = SCMD_SEL_ATN; 1244 pSRB->SRBState = SRB_START_; 1245 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1246 /* Send Tag message */ 1247 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1248 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1249 scsicommand = SCMD_SEL_ATN3; 1250 } 1251 } 1252polling: 1253 /* 1254 * Send CDB ..command block ......... 1255 */ 1256 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1257 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1258 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1259 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1260 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1261 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1262 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1263 } else { 1264 ptr = (u_int8_t *) pSRB->CmdBlock; 1265 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1266 command = *ptr++; 1267 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1268 } 1269 } 1270 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1271 /* 1272 * If trm_StartSCSI return 1 : 1273 * current interrupt status is interrupt disreenable 1274 * It's said that SCSI processor has more one SRB need to do, 1275 * SCSI processor has been occupied by one SRB. 1276 */ 1277 pSRB->SRBState = SRB_READY; 1278 return_code = 1; 1279 } else { 1280 /* 1281 * If trm_StartSCSI return 0 : 1282 * current interrupt status is interrupt enable 1283 * It's said that SCSI processor is unoccupied 1284 */ 1285 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1286 pACB->pActiveDCB = pDCB; 1287 pDCB->pActiveSRB = pSRB; 1288 return_code = 0; 1289 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1290 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1291 /* 1292 * SCSI cammand 1293 */ 1294 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1295 } 1296 return (return_code); 1297} 1298 1299static void 1300trm_Interrupt(vpACB) 1301void *vpACB; 1302{ 1303 PACB pACB; 1304 PDCB pDCB; 1305 PSRB pSRB; 1306 u_int16_t phase; 1307 void (*stateV)(PACB, PSRB, u_int16_t *); 1308 u_int16_t scsi_status=0; 1309 u_int8_t scsi_intstatus; 1310 1311 pACB = vpACB; 1312 1313 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1314 if (!(scsi_status & SCSIINTERRUPT)) { 1315 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1316 return; 1317 } 1318 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1319 1320 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1321 1322 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1323 1324 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1325 trm_Disconnect(pACB); 1326 return; 1327 } 1328 1329 if (scsi_intstatus & INT_RESELECTED) { 1330 trm_Reselect(pACB); 1331 return; 1332 } 1333 if (scsi_intstatus & INT_SCSIRESET) { 1334 trm_ScsiRstDetect(pACB); 1335 return; 1336 } 1337 1338 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1339 pDCB = pACB->pActiveDCB; 1340 pSRB = pDCB->pActiveSRB; 1341 if (pDCB) { 1342 if (pDCB->DCBFlag & ABORT_DEV_) 1343 trm_EnableMsgOutAbort1(pACB, pSRB); 1344 } 1345 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1346 stateV = (void *) trm_SCSI_phase0[phase]; 1347 stateV(pACB, pSRB, &scsi_status); 1348 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1349 /* phase:0,1,2,3,4,5,6,7 */ 1350 phase = (u_int16_t) scsi_status & PHASEMASK; 1351 stateV = (void *) trm_SCSI_phase1[phase]; 1352 stateV(pACB, pSRB, &scsi_status); 1353 } 1354} 1355 1356static void 1357trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1358{ 1359 1360 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1361 *pscsi_status = PH_BUS_FREE; 1362 /*.. initial phase*/ 1363} 1364 1365static void 1366trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1367{ 1368 u_int8_t bval; 1369 u_int16_t i, cnt; 1370 u_int8_t * ptr; 1371 PDCB pDCB; 1372 1373 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1374 pDCB = pACB->pActiveDCB; 1375 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1376 cnt = pSRB->MsgCnt; 1377 if (cnt) { 1378 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1379 for (i = 0; i < cnt; i++) { 1380 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1381 ptr++; 1382 } 1383 pSRB->MsgCnt = 0; 1384 if ((pDCB->DCBFlag & ABORT_DEV_) && 1385 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1386 pSRB->SRBState = SRB_ABORT_SENT; 1387 } 1388 } else { 1389 bval = MSG_ABORT; 1390 if ((pSRB->CmdBlock[0] == INQUIRY) || 1391 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1392 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1393 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1394 goto mop1; 1395 } 1396 } 1397 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1398 } 1399 } else { 1400mop1: /* message out phase */ 1401 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1402 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1403 /* 1404 * WIDE DATA TRANSFER REQUEST code (03h) 1405 */ 1406 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1407 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1408 TRMREG_SCSI_FIFO); 1409 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1410 /* (01h) */ 1411 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1412 /* Message length (02h) */ 1413 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1414 /* wide data xfer (03h) */ 1415 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1416 /* width:0(8bit),1(16bit),2(32bit) */ 1417 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1418 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1419 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1420 /* 1421 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1422 */ 1423 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1424 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1425 TRMREG_SCSI_FIFO); 1426 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1427 /* (01h) */ 1428 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1429 /* Message length (03h) */ 1430 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1431 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1432 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1433 /* Transfer peeriod factor */ 1434 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1435 TRMREG_SCSI_FIFO); 1436 /* REQ/ACK offset */ 1437 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1438 } 1439 } 1440 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1441 /* it's important for atn stop */ 1442 /* 1443 * SCSI cammand 1444 */ 1445 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1446} 1447 1448static void 1449trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1450{ 1451 1452} 1453 1454static void 1455trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1456{ 1457 PDCB pDCB; 1458 u_int8_t * ptr; 1459 u_int16_t i, cnt; 1460 union ccb *pccb; 1461 struct ccb_scsiio *pcsio; 1462 1463 pccb = pSRB->pccb; 1464 pcsio = &pccb->csio; 1465 1466 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1467 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1468 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1469 ptr = (u_int8_t *) pSRB->CmdBlock; 1470 for (i = 0; i < cnt; i++) { 1471 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1472 ptr++; 1473 } 1474 } else { 1475 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1476 pDCB = pACB->pActiveDCB; 1477 /* target id */ 1478 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1479 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1480 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1481 /* sizeof(struct scsi_sense_data) */ 1482 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1483 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1484 } 1485 pSRB->SRBState = SRB_COMMAND; 1486 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1487 /* it's important for atn stop*/ 1488 /* 1489 * SCSI cammand 1490 */ 1491 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1492} 1493 1494static void 1495trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1496{ 1497 PDCB pDCB; 1498 u_int8_t TempDMAstatus,SGIndexTemp; 1499 u_int16_t scsi_status; 1500 PSEG pseg; 1501 u_long TempSRBXferredLength,dLeftCounter=0; 1502 1503 pDCB = pSRB->pSRBDCB; 1504 scsi_status = *pscsi_status; 1505 1506 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1507 if (scsi_status & PARITYERROR) 1508 pSRB->SRBStatus |= PARITY_ERROR; 1509 if (!(scsi_status & SCSIXFERDONE)) { 1510 /* 1511 * when data transfer from DMA FIFO to SCSI FIFO 1512 * if there was some data left in SCSI FIFO 1513 */ 1514 dLeftCounter = (u_long) 1515 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1516 if (pDCB->SyncPeriod & WIDE_SYNC) { 1517 /* 1518 * if WIDE scsi SCSI FIFOCNT unit is word 1519 * so need to * 2 1520 */ 1521 dLeftCounter <<= 1; 1522 } 1523 } 1524 /* 1525 * caculate all the residue data that not yet tranfered 1526 * SCSI transfer counter + left in SCSI FIFO data 1527 * 1528 * .....TRM_SCSI_COUNTER (24bits) 1529 * The counter always decrement by one for every SCSI byte 1530 *transfer. 1531 * .....TRM_SCSI_FIFOCNT (5bits) 1532 * The counter is SCSI FIFO offset counter 1533 */ 1534 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1535 if (dLeftCounter == 1) { 1536 dLeftCounter = 0; 1537 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1538 } 1539 if ((dLeftCounter == 0) || 1540 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1541 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1542 while (!(TempDMAstatus & DMAXFERCOMP)) { 1543 TempDMAstatus = 1544 trm_reg_read8(TRMREG_DMA_STATUS); 1545 } 1546 pSRB->SRBTotalXferLength = 0; 1547 } else { 1548 /* Update SG list */ 1549 /* 1550 * if transfer not yet complete 1551 * there were some data residue in SCSI FIFO or 1552 * SCSI transfer counter not empty 1553 */ 1554 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1555 /* 1556 * data that had transferred length 1557 */ 1558 TempSRBXferredLength = 1559 pSRB->SRBTotalXferLength - dLeftCounter; 1560 /* 1561 * next time to be transferred length 1562 */ 1563 pSRB->SRBTotalXferLength = dLeftCounter; 1564 /* 1565 * parsing from last time disconnect SRBSGIndex 1566 */ 1567 pseg = 1568 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1569 for (SGIndexTemp = pSRB->SRBSGIndex; 1570 SGIndexTemp < pSRB->SRBSGCount; 1571 SGIndexTemp++) { 1572 /* 1573 * find last time which SG transfer be 1574 * disconnect 1575 */ 1576 if (TempSRBXferredLength >= 1577 pseg->length) 1578 TempSRBXferredLength -= 1579 pseg->length; 1580 else { 1581 /* 1582 * update last time disconnected SG 1583 * list 1584 */ 1585 pseg->length -= 1586 TempSRBXferredLength; 1587 /* residue data length */ 1588 pseg->address += 1589 TempSRBXferredLength; 1590 /* residue data pointer */ 1591 pSRB->SRBSGIndex = SGIndexTemp; 1592 break; 1593 } 1594 pseg++; 1595 } 1596 } 1597 } 1598 } 1599 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1600} 1601 1602 1603static void 1604trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1605{ 1606 u_int16_t ioDir; 1607 /* 1608 * do prepare befor transfer when data out phase 1609 */ 1610 1611 ioDir = XFERDATAOUT; 1612 trm_DataIO_transfer(pACB, pSRB, ioDir); 1613} 1614 1615static void 1616trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1617{ 1618 u_int8_t TempDMAstatus, SGIndexTemp; 1619 u_int16_t scsi_status; 1620 PSEG pseg; 1621 u_long TempSRBXferredLength,dLeftCounter = 0; 1622 1623 scsi_status = *pscsi_status; 1624 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1625 if (scsi_status & PARITYERROR) 1626 pSRB->SRBStatus |= PARITY_ERROR; 1627 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1628 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1629 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1630 while (!(TempDMAstatus & DMAXFERCOMP)) 1631 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1632 pSRB->SRBTotalXferLength = 0; 1633 } else { 1634 /* 1635 * parsing the case: 1636 * when a transfer not yet complete 1637 * but be disconnected by uper layer 1638 * if transfer not yet complete 1639 * there were some data residue in SCSI FIFO or 1640 * SCSI transfer counter not empty 1641 */ 1642 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1643 /* 1644 * data that had transferred length 1645 */ 1646 TempSRBXferredLength = 1647 pSRB->SRBTotalXferLength - dLeftCounter; 1648 /* 1649 * next time to be transferred length 1650 */ 1651 pSRB->SRBTotalXferLength = dLeftCounter; 1652 /* 1653 * parsing from last time disconnect SRBSGIndex 1654 */ 1655 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1656 for (SGIndexTemp = pSRB->SRBSGIndex; 1657 SGIndexTemp < pSRB->SRBSGCount; 1658 SGIndexTemp++) { 1659 /* 1660 * find last time which SG transfer be disconnect 1661 */ 1662 if (TempSRBXferredLength >= pseg->length) 1663 TempSRBXferredLength -= pseg->length; 1664 else { 1665 /* 1666 * update last time disconnected SG list 1667 */ 1668 pseg->length -= TempSRBXferredLength; 1669 /* residue data length */ 1670 pseg->address += TempSRBXferredLength; 1671 /* residue data pointer */ 1672 pSRB->SRBSGIndex = SGIndexTemp; 1673 break; 1674 } 1675 pseg++; 1676 } 1677 } 1678 } 1679 } 1680} 1681 1682static void 1683trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1684{ 1685 u_int16_t ioDir; 1686 /* 1687 * do prepare befor transfer when data in phase 1688 */ 1689 1690 ioDir = XFERDATAIN; 1691 trm_DataIO_transfer(pACB, pSRB, ioDir); 1692} 1693 1694static void 1695trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1696{ 1697 u_int8_t bval; 1698 PDCB pDCB; 1699 1700 pDCB = pSRB->pSRBDCB; 1701 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1702 if (pSRB->SRBTotalXferLength != 0) { 1703 /* 1704 * load what physical address of Scatter/Gather list 1705 table want to be transfer 1706 */ 1707 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1708 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1709 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1710 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1711 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1712 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1713 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1714 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1715 1716 pSRB->SRBState = SRB_DATA_XFER; 1717 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1718 trm_reg_write32( 1719 (pSRB->SRBSGPhyAddr + 1720 ((u_long)pSRB->SRBSGIndex << 3)), 1721 TRMREG_DMA_XLOWADDR); 1722 /* 1723 * load how many bytes in the Scatter/Gather 1724 * list table 1725 */ 1726 trm_reg_write32( 1727 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1728 TRMREG_DMA_XCNT); 1729 /* 1730 * load total transfer length (24bits) max value 1731 * 16Mbyte 1732 */ 1733 trm_reg_write32(pSRB->SRBTotalXferLength, 1734 TRMREG_SCSI_COUNTER); 1735 /* Start DMA transfer */ 1736 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1737 /* Start SCSI transfer */ 1738 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1739 /* it's important for atn stop */ 1740 /* 1741 * SCSI cammand 1742 */ 1743 bval = (ioDir == XFERDATAOUT) ? 1744 SCMD_DMA_OUT : SCMD_DMA_IN; 1745 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1746 } else { 1747 /* xfer pad */ 1748 if (pSRB->SRBSGCount) { 1749 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1750 pSRB->SRBStatus |= OVER_RUN; 1751 } 1752 if (pDCB->SyncPeriod & WIDE_SYNC) 1753 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1754 else 1755 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1756 if (ioDir == XFERDATAOUT) 1757 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1758 else 1759 trm_reg_read16(TRMREG_SCSI_FIFO); 1760 pSRB->SRBState |= SRB_XFERPAD; 1761 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1762 /* it's important for atn stop */ 1763 /* 1764 * SCSI cammand 1765 */ 1766 bval = (ioDir == XFERDATAOUT) ? 1767 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1768 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1769 } 1770 } 1771} 1772 1773static void 1774trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1775{ 1776 1777 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1778 pSRB->SRBState = SRB_COMPLETED; 1779 *pscsi_status = PH_BUS_FREE; 1780 /*.. initial phase*/ 1781 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1782 /* it's important for atn stop */ 1783 /* 1784 * SCSI cammand 1785 */ 1786 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1787} 1788 1789 1790 1791static void 1792trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1793{ 1794 1795 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1796 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1797 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1798 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1799 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1800 } else { 1801 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1802 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1803 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1804 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1805 } 1806 pSRB->SRBState = SRB_STATUS; 1807 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1808 /* it's important for atn stop */ 1809 /* 1810 * SCSI cammand 1811 */ 1812 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1813} 1814 1815/* 1816 *scsiiom 1817 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1818 * stateV = (void *) trm_SCSI_phase0[phase] 1819 * if phase =7 1820 * extended message codes: 1821 * 1822 * code description 1823 * 1824 * 02h Reserved 1825 * 00h MODIFY DATA POINTER 1826 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1827 * 03h WIDE DATA TRANSFER REQUEST 1828 * 04h - 7Fh Reserved 1829 * 80h - FFh Vendor specific 1830 * 1831 */ 1832 1833static void 1834trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1835{ 1836 u_int8_t message_in_code,bIndex,message_in_tag_id; 1837 PDCB pDCB; 1838 PSRB pSRBTemp; 1839 1840 pDCB = pACB->pActiveDCB; 1841 1842 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1843 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1844 if (message_in_code == MSG_DISCONNECT) { 1845 pSRB->SRBState = SRB_DISCONNECT; 1846 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1847 /* it's important for atn stop */ 1848 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1849 /* 1850 * SCSI command 1851 */ 1852 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1853 return; 1854 } else if (message_in_code == MSG_SAVE_PTR) { 1855 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1856 /* it's important for atn stop */ 1857 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1858 /* 1859 * SCSI command 1860 */ 1861 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1862 return; 1863 } else if ((message_in_code == MSG_EXTENDED) || 1864 ((message_in_code >= MSG_SIMPLE_QTAG) && 1865 (message_in_code <= MSG_ORDER_QTAG))) { 1866 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1867 pSRB->MsgInBuf[0] = message_in_code; 1868 /* extended message (01h) */ 1869 pSRB->MsgCnt = 1; 1870 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1871 /* extended message length (n) */ 1872 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1873 /* it's important for atn stop */ 1874 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1875 /* 1876 * SCSI command 1877 */ 1878 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1879 return; 1880 } else if (message_in_code == MSG_REJECT_) { 1881 /* Reject message */ 1882 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1883 /* do wide nego reject */ 1884 pDCB = pSRB->pSRBDCB; 1885 pDCB->SyncMode |= WIDE_NEGO_DONE; 1886 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1887 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1888 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1889 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1890 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1891 /* Set ATN, in case ATN was clear */ 1892 pSRB->SRBState |= SRB_MSGOUT; 1893 trm_reg_write16( 1894 DO_SETATN, 1895 TRMREG_SCSI_CONTROL); 1896 } else { 1897 /* Clear ATN */ 1898 trm_reg_write16( 1899 DO_CLRATN, 1900 TRMREG_SCSI_CONTROL); 1901 } 1902 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1903 /* do sync nego reject */ 1904 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1905 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1906 pDCB = pSRB->pSRBDCB; 1907 pDCB->SyncMode &= 1908 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1909 pDCB->SyncPeriod = 0; 1910 pDCB->SyncOffset = 0; 1911 /* 1912 * 1913 * program SCSI control register 1914 * 1915 */ 1916 trm_reg_write8(pDCB->SyncPeriod, 1917 TRMREG_SCSI_SYNC); 1918 trm_reg_write8(pDCB->SyncOffset, 1919 TRMREG_SCSI_OFFSET); 1920 trm_SetXferRate(pACB,pSRB,pDCB); 1921 } 1922 } 1923 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1924 /* it's important for atn stop */ 1925 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1926 /* 1927 * SCSI command 1928 */ 1929 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1930 return; 1931 } else if (message_in_code == MSG_IGNOREWIDE) { 1932 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1933 trm_reg_read8(TRMREG_SCSI_FIFO); 1934 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1935 /* it's important for atn stop */ 1936 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1937 /* 1938 * SCSI command 1939 */ 1940 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1941 return; 1942 } else { 1943 /* Restore data pointer message */ 1944 /* Save data pointer message */ 1945 /* Completion message */ 1946 /* NOP message */ 1947 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1948 /* it's important for atn stop */ 1949 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1950 /* 1951 * SCSI command 1952 */ 1953 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1954 return; 1955 } 1956 } else { 1957 /* 1958 * Parsing incomming extented messages 1959 */ 1960 *pSRB->pMsgPtr = message_in_code; 1961 pSRB->MsgCnt++; 1962 pSRB->pMsgPtr++; 1963 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1964 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1965 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1966 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1967 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1968 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1969 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1970 /* 1971 * is QUEUE tag message : 1972 * 1973 * byte 0: 1974 * HEAD QUEUE TAG (20h) 1975 * ORDERED QUEUE TAG (21h) 1976 * SIMPLE QUEUE TAG (22h) 1977 * byte 1: 1978 * Queue tag (00h - FFh) 1979 */ 1980 if (pSRB->MsgCnt == 2) { 1981 pSRB->SRBState = 0; 1982 message_in_tag_id = pSRB->MsgInBuf[1]; 1983 pSRB = pDCB->pGoingSRB; 1984 pSRBTemp = pDCB->pGoingLastSRB; 1985 if (pSRB) { 1986 for (;;) { 1987 if (pSRB->TagNumber != 1988 message_in_tag_id) { 1989 if (pSRB == pSRBTemp) { 1990 goto mingx0; 1991 } 1992 pSRB = pSRB->pNextSRB; 1993 } else 1994 break; 1995 } 1996 if (pDCB->DCBFlag & ABORT_DEV_) { 1997 pSRB->SRBState = SRB_ABORT_SENT; 1998 trm_EnableMsgOutAbort1( 1999 pACB, pSRB); 2000 } 2001 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 2002 TRM_DPRINTF("SRB not yet disconnect........ \n "); 2003 goto mingx0; 2004 } 2005 pDCB->pActiveSRB = pSRB; 2006 pSRB->SRBState = SRB_DATA_XFER; 2007 } else { 2008mingx0: 2009 pSRB = &pACB->TmpSRB; 2010 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2011 pDCB->pActiveSRB = pSRB; 2012 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2013 trm_EnableMsgOutAbort2( 2014 pACB, 2015 pSRB); 2016 } 2017 } 2018 *pscsi_status = PH_BUS_FREE; 2019 /* .. initial phase */ 2020 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2021 /* it's important for atn stop */ 2022 /* 2023 * SCSI command 2024 */ 2025 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2026 return; 2027 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2028 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2029 /* 2030 * is Wide data xfer Extended message : 2031 * ====================================== 2032 * WIDE DATA TRANSFER REQUEST 2033 * ====================================== 2034 * byte 0 : Extended message (01h) 2035 * byte 1 : Extended message length (02h) 2036 * byte 2 : WIDE DATA TRANSFER code (03h) 2037 * byte 3 : Transfer width exponent 2038 */ 2039 pDCB = pSRB->pSRBDCB; 2040 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2041 if ((pSRB->MsgInBuf[1] != 2)) { 2042 /* Length is wrong, reject it */ 2043 pDCB->SyncMode &= 2044 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2045 pSRB->MsgCnt = 1; 2046 pSRB->MsgInBuf[0] = MSG_REJECT_; 2047 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2048 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2049 /* it's important for atn stop */ 2050 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2051 /* 2052 * SCSI command 2053 */ 2054 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2055 return; 2056 } 2057 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2058 /* Do wide negoniation */ 2059 if (pSRB->MsgInBuf[3] > 2) { 2060 /* > 32 bit */ 2061 /* reject_msg: */ 2062 pDCB->SyncMode &= 2063 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2064 pSRB->MsgCnt = 1; 2065 pSRB->MsgInBuf[0] = MSG_REJECT_; 2066 trm_reg_write16(DO_SETATN, 2067 TRMREG_SCSI_CONTROL); 2068 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2069 /* it's important for atn stop */ 2070 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2071 /* 2072 * SCSI command 2073 */ 2074 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2075 return; 2076 } 2077 if (pSRB->MsgInBuf[3] == 2) { 2078 pSRB->MsgInBuf[3] = 1; 2079 /* do 16 bits */ 2080 } else { 2081 if (!(pDCB->SyncMode 2082 & WIDE_NEGO_DONE)) { 2083 pSRB->SRBState &= 2084 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2085 pDCB->SyncMode |= 2086 WIDE_NEGO_DONE; 2087 pDCB->SyncMode &= 2088 ~(SYNC_NEGO_DONE | 2089 EN_ATN_STOP | 2090 WIDE_NEGO_ENABLE); 2091 if (pSRB->MsgInBuf[3] != 0) { 2092 /* is Wide data xfer */ 2093 pDCB->SyncPeriod |= 2094 WIDE_SYNC; 2095 pDCB->tinfo.current.width 2096 = MSG_EXT_WDTR_BUS_16_BIT; 2097 pDCB->tinfo.goal.width 2098 = MSG_EXT_WDTR_BUS_16_BIT; 2099 } 2100 } 2101 } 2102 } else 2103 pSRB->MsgInBuf[3] = 0; 2104 pSRB->SRBState |= SRB_MSGOUT; 2105 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2106 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2107 /* it's important for atn stop */ 2108 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2109 /* 2110 * SCSI command 2111 */ 2112 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2113 return; 2114 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2115 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2116 /* 2117 * is 8bit transfer Extended message : 2118 * ================================= 2119 * SYNCHRONOUS DATA TRANSFER REQUEST 2120 * ================================= 2121 * byte 0 : Extended message (01h) 2122 * byte 1 : Extended message length (03) 2123 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2124 * byte 3 : Transfer period factor 2125 * byte 4 : REQ/ACK offset 2126 */ 2127 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2128 if ((pSRB->MsgInBuf[1] != 3) || 2129 (pSRB->MsgInBuf[2] != 1)) { 2130 /* reject_msg: */ 2131 pSRB->MsgCnt = 1; 2132 pSRB->MsgInBuf[0] = MSG_REJECT_; 2133 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2134 *pscsi_status = PH_BUS_FREE; 2135 /* .. initial phase */ 2136 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2137 /* it's important for atn stop */ 2138 /* 2139 * SCSI cammand 2140 */ 2141 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2142 return; 2143 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2144 /* set async */ 2145 pDCB = pSRB->pSRBDCB; 2146 /* disable sync & sync nego */ 2147 pDCB->SyncMode &= 2148 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2149 pDCB->SyncPeriod = 0; 2150 pDCB->SyncOffset = 0; 2151 pDCB->tinfo.goal.period = 0; 2152 pDCB->tinfo.goal.offset = 0; 2153 pDCB->tinfo.current.period = 0; 2154 pDCB->tinfo.current.offset = 0; 2155 pDCB->tinfo.current.width = 2156 MSG_EXT_WDTR_BUS_8_BIT; 2157 /* 2158 * 2159 * program SCSI control register 2160 * 2161 */ 2162 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2163 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2164 trm_SetXferRate(pACB,pSRB,pDCB); 2165 *pscsi_status = PH_BUS_FREE; 2166 /* .. initial phase */ 2167 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2168 /* it's important for atn stop */ 2169 /* 2170 * SCSI cammand 2171 */ 2172 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2173 return; 2174 } else { 2175 /* set sync */ 2176 pDCB = pSRB->pSRBDCB; 2177 pDCB->SyncMode |= 2178 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2179 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2180 /* Transfer period factor */ 2181 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2182 /* REQ/ACK offset */ 2183 if (pACB->AdaptType == 1) { 2184 for(bIndex = 0; bIndex < 7; bIndex++) { 2185 if (pSRB->MsgInBuf[3] <= 2186 dc395u2x_clock_period[bIndex]) { 2187 pDCB->tinfo.goal.period = 2188 dc395u2x_tinfo_period[bIndex]; 2189 pDCB->tinfo.current.period = 2190 dc395u2x_tinfo_period[bIndex]; 2191 pDCB->tinfo.goal.offset = 2192 pDCB->SyncOffset; 2193 pDCB->tinfo.current.offset = 2194 pDCB->SyncOffset; 2195 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2196 break; 2197 } 2198 } 2199 } else { 2200 for(bIndex = 0; bIndex < 7; bIndex++) { 2201 if (pSRB->MsgInBuf[3] <= 2202 dc395x_clock_period[bIndex]) { 2203 pDCB->tinfo.goal.period = 2204 dc395x_tinfo_period[bIndex]; 2205 pDCB->tinfo.current.period = 2206 dc395x_tinfo_period[bIndex]; 2207 pDCB->tinfo.goal.offset = 2208 pDCB->SyncOffset; 2209 pDCB->tinfo.current.offset = 2210 pDCB->SyncOffset; 2211 pDCB->SyncPeriod |= 2212 (bIndex|ALT_SYNC); 2213 break; 2214 } 2215 } 2216 } 2217 /* 2218 * 2219 * program SCSI control register 2220 * 2221 */ 2222 trm_reg_write8(pDCB->SyncPeriod, 2223 TRMREG_SCSI_SYNC); 2224 trm_reg_write8(pDCB->SyncOffset, 2225 TRMREG_SCSI_OFFSET); 2226 trm_SetXferRate(pACB,pSRB,pDCB); 2227 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2228 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2229 /* 2230 ** SCSI command 2231 */ 2232 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2233 return; 2234 } 2235 } 2236 *pscsi_status = PH_BUS_FREE; 2237 /* .. initial phase */ 2238 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2239 /* it's important for atn stop */ 2240 /* 2241 * SCSI cammand 2242 */ 2243 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2244 } 2245} 2246 2247static void 2248trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2249{ 2250 2251 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2252 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2253 if (!(pSRB->SRBState & SRB_MSGIN)) { 2254 pSRB->SRBState &= SRB_DISCONNECT; 2255 pSRB->SRBState |= SRB_MSGIN; 2256 } 2257 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2258 /* it's important for atn stop*/ 2259 /* 2260 * SCSI cammand 2261 */ 2262 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2263} 2264 2265static void 2266trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2267{ 2268 2269} 2270 2271static void 2272trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2273{ 2274 2275} 2276 2277static void 2278trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2279{ 2280 union ccb *pccb; 2281 struct ccb_trans_settings neg; 2282 u_int16_t cnt, i; 2283 u_int8_t bval; 2284 PDCB pDCBTemp; 2285 2286 /* 2287 * set all lun device's period , offset 2288 */ 2289 TRM_DPRINTF("trm_SetXferRate\n"); 2290 pccb = pSRB->pccb; 2291 neg.sync_period = pDCB->tinfo.goal.period; 2292 neg.sync_offset = pDCB->tinfo.goal.offset; 2293 neg.valid = CCB_TRANS_SYNC_RATE_VALID | CCB_TRANS_SYNC_OFFSET_VALID; 2294 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2295 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2296 if (!(pDCB->IdentifyMsg & 0x07)) { 2297 pDCBTemp = pACB->pLinkDCB; 2298 cnt = pACB->DeviceCnt; 2299 bval = pDCB->TargetID; 2300 for (i = 0; i < cnt; i++) { 2301 if (pDCBTemp->TargetID == bval) { 2302 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2303 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2304 pDCBTemp->SyncMode = pDCB->SyncMode; 2305 } 2306 pDCBTemp = pDCBTemp->pNextDCB; 2307 } 2308 } 2309 return; 2310} 2311 2312/* 2313 * scsiiom 2314 * trm_Interrupt 2315 * 2316 * 2317 * ---SCSI bus phase 2318 * 2319 * PH_DATA_OUT 0x00 Data out phase 2320 * PH_DATA_IN 0x01 Data in phase 2321 * PH_COMMAND 0x02 Command phase 2322 * PH_STATUS 0x03 Status phase 2323 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2324 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2325 * PH_MSG_OUT 0x06 Message out phase 2326 * PH_MSG_IN 0x07 Message in phase 2327 * 2328 */ 2329static void 2330trm_Disconnect(PACB pACB) 2331{ 2332 PDCB pDCB; 2333 PSRB pSRB, psrb; 2334 u_int16_t i,j, cnt; 2335 u_int target_id,target_lun; 2336 2337 TRM_DPRINTF("trm_Disconnect...............\n "); 2338 2339 pDCB = pACB->pActiveDCB; 2340 if (!pDCB) { 2341 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2342 j = 400; 2343 while (--j) 2344 DELAY(1); 2345 /* 1 msec */ 2346 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2347 TRMREG_SCSI_CONTROL); 2348 return; 2349 } 2350 pSRB = pDCB->pActiveSRB; 2351 /* bug pSRB=0 */ 2352 target_id = pSRB->pccb->ccb_h.target_id; 2353 target_lun = pSRB->pccb->ccb_h.target_lun; 2354 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2355 pACB->pActiveDCB = 0; 2356 pSRB->ScsiPhase = PH_BUS_FREE; 2357 /* SCSI bus free Phase */ 2358 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2359 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2360 pSRB->SRBState = 0; 2361 trm_DoWaitingSRB(pACB); 2362 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2363 pDCB->DCBFlag = 0; 2364 cnt = pDCB->GoingSRBCnt; 2365 pDCB->GoingSRBCnt = 0; 2366 pSRB = pDCB->pGoingSRB; 2367 for (i = 0; i < cnt; i++) { 2368 psrb = pSRB->pNextSRB; 2369 pSRB->pNextSRB = pACB->pFreeSRB; 2370 pACB->pFreeSRB = pSRB; 2371 pSRB = psrb; 2372 } 2373 pDCB->pGoingSRB = 0; 2374 trm_DoWaitingSRB(pACB); 2375 } else { 2376 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2377 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2378 /* Selection time out */ 2379 if (!(pACB->scan_devices[target_id][target_lun]) && 2380 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2381 pSRB->CmdBlock[0] != INQUIRY) { 2382 pSRB->SRBState = SRB_READY; 2383 trm_RewaitSRB(pDCB, pSRB); 2384 } else { 2385 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2386 goto disc1; 2387 } 2388 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2389 /* 2390 * SRB_DISCONNECT 2391 */ 2392 trm_DoWaitingSRB(pACB); 2393 } else if (pSRB->SRBState & SRB_COMPLETED) { 2394disc1: 2395 /* 2396 * SRB_COMPLETED 2397 */ 2398 pDCB->pActiveSRB = 0; 2399 pSRB->SRBState = SRB_FREE; 2400 trm_SRBdone(pACB, pDCB, pSRB); 2401 } 2402 } 2403 return; 2404} 2405 2406static void 2407trm_Reselect(PACB pACB) 2408{ 2409 PDCB pDCB; 2410 PSRB pSRB; 2411 u_int16_t RselTarLunId; 2412 2413 TRM_DPRINTF("trm_Reselect................. \n"); 2414 pDCB = pACB->pActiveDCB; 2415 if (pDCB) { 2416 /* Arbitration lost but Reselection win */ 2417 pSRB = pDCB->pActiveSRB; 2418 pSRB->SRBState = SRB_READY; 2419 trm_RewaitSRB(pDCB, pSRB); 2420 } 2421 /* Read Reselected Target Id and LUN */ 2422 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2423 pDCB = pACB->pLinkDCB; 2424 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2425 /* get pDCB of the reselect id */ 2426 pDCB = pDCB->pNextDCB; 2427 } 2428 2429 pACB->pActiveDCB = pDCB; 2430 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2431 pSRB = &pACB->TmpSRB; 2432 pDCB->pActiveSRB = pSRB; 2433 } else { 2434 pSRB = pDCB->pActiveSRB; 2435 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2436 /* 2437 * abort command 2438 */ 2439 pSRB = &pACB->TmpSRB; 2440 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2441 pDCB->pActiveSRB = pSRB; 2442 trm_EnableMsgOutAbort1(pACB, pSRB); 2443 } else { 2444 if (pDCB->DCBFlag & ABORT_DEV_) { 2445 pSRB->SRBState = SRB_ABORT_SENT; 2446 trm_EnableMsgOutAbort1(pACB, pSRB); 2447 } else 2448 pSRB->SRBState = SRB_DATA_XFER; 2449 } 2450 } 2451 pSRB->ScsiPhase = PH_BUS_FREE; 2452 /* SCSI bus free Phase */ 2453 /* 2454 * Program HA ID, target ID, period and offset 2455 */ 2456 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2457 /* target ID */ 2458 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2459 /* host ID */ 2460 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2461 /* period */ 2462 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2463 /* offset */ 2464 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2465 /* it's important for atn stop*/ 2466 /* 2467 * SCSI cammand 2468 */ 2469 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2470 /* to rls the /ACK signal */ 2471} 2472 2473static void 2474trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2475{ 2476 PSRB psrb; 2477 u_int8_t bval, bval1,status; 2478 union ccb *pccb; 2479 struct ccb_scsiio *pcsio; 2480 PSCSI_INQDATA ptr; 2481 int intflag; 2482 u_int target_id,target_lun; 2483 PDCB pTempDCB; 2484 2485 pccb = pSRB->pccb; 2486 if (pccb == NULL) 2487 return; 2488 pcsio = &pccb->csio; 2489 target_id = pSRB->pccb->ccb_h.target_id; 2490 target_lun = pSRB->pccb->ccb_h.target_lun; 2491 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2492 bus_dmasync_op_t op; 2493 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2494 op = BUS_DMASYNC_POSTREAD; 2495 else 2496 op = BUS_DMASYNC_POSTWRITE; 2497 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2498 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2499 } 2500 /* 2501 * 2502 * target status 2503 * 2504 */ 2505 status = pSRB->TargetStatus; 2506 pcsio->scsi_status=SCSI_STAT_GOOD; 2507 pccb->ccb_h.status = CAM_REQ_CMP; 2508 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2509 /* 2510 * status of auto request sense 2511 */ 2512 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2513 pSRB->AdaptStatus = 0; 2514 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2515 2516 if (status == SCSI_STATUS_CHECK_COND) { 2517 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2518 goto ckc_e; 2519 } 2520 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2521 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2522 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2523 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2524 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2525 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2526 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2527 pcsio->sense_len); 2528 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2529 | CAM_AUTOSNS_VALID; 2530 goto ckc_e; 2531 } 2532 /* 2533 * target status 2534 */ 2535 if (status) { 2536 if (status == SCSI_STATUS_CHECK_COND) { 2537 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2538 TRM_DPRINTF("trm_RequestSense..................\n"); 2539 trm_RequestSense(pACB, pDCB, pSRB); 2540 return; 2541 } 2542 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2543 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2544 goto ckc_e; 2545 } else if (status == SCSI_STAT_QUEUEFULL) { 2546 bval = (u_int8_t) pDCB->GoingSRBCnt; 2547 bval--; 2548 pDCB->MaxActiveCommandCnt = bval; 2549 trm_RewaitSRB(pDCB, pSRB); 2550 pSRB->AdaptStatus = 0; 2551 pSRB->TargetStatus = 0; 2552 return; 2553 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2554 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2555 pSRB->TargetStatus = 0; 2556 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2557 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2558 } else if (status == SCSI_STAT_BUSY) { 2559 TRM_DPRINTF("trm: target busy at %s %d\n", 2560 __FILE__, __LINE__); 2561 pcsio->scsi_status = SCSI_STAT_BUSY; 2562 pccb->ccb_h.status = CAM_SCSI_BUSY; 2563 return; 2564 /* The device busy, try again later? */ 2565 } else if (status == SCSI_STAT_RESCONFLICT) { 2566 TRM_DPRINTF("trm: target reserved at %s %d\n", 2567 __FILE__, __LINE__); 2568 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2569 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2570 return; 2571 } else { 2572 pSRB->AdaptStatus = 0; 2573 if (pSRB->RetryCnt) { 2574 pSRB->RetryCnt--; 2575 pSRB->TargetStatus = 0; 2576 pSRB->SRBSGIndex = 0; 2577 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2578 /* 2579 * If trm_StartSCSI return 1 : 2580 * current interrupt status is interrupt 2581 * disreenable 2582 * It's said that SCSI processor has more 2583 * one SRB need to do 2584 */ 2585 trm_RewaitSRB(pDCB, pSRB); 2586 } 2587 return; 2588 } else { 2589 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2590 __FILE__, __LINE__); 2591 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2592 } 2593 } 2594 } else { 2595 /* 2596 * process initiator status.......................... 2597 * Adapter (initiator) status 2598 */ 2599 status = pSRB->AdaptStatus; 2600 if (status & H_OVER_UNDER_RUN) { 2601 pSRB->TargetStatus = 0; 2602 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2603 /* Illegal length (over/under run) */ 2604 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2605 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2606 __FILE__, __LINE__); 2607 pDCB->tinfo.goal.period = 0; 2608 pDCB->tinfo.goal.offset = 0; 2609 /* Driver failed to perform operation */ 2610 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2611 } else { 2612 /* no error */ 2613 pSRB->AdaptStatus = 0; 2614 pSRB->TargetStatus = 0; 2615 pccb->ccb_h.status = CAM_REQ_CMP; 2616 /* there is no error, (sense is invalid) */ 2617 } 2618 } 2619ckc_e: 2620 if (pACB->scan_devices[target_id][target_lun]) { 2621 /* 2622 * if SCSI command in "scan devices" duty 2623 */ 2624 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2625 pACB->scan_devices[target_id][target_lun] = 0; 2626 /* SCSI command phase :test unit ready */ 2627 else if (pSRB->CmdBlock[0] == INQUIRY) { 2628 /* 2629 * SCSI command phase :inquiry scsi device data 2630 * (type,capacity,manufacture.... 2631 */ 2632 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2633 goto NO_DEV; 2634 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2635 /* page fault */ 2636 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2637 ptr->DevType); 2638 bval1 = ptr->DevType & SCSI_DEVTYPE; 2639 if (bval1 == SCSI_NODEV) { 2640NO_DEV: 2641 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2642 target_id, 2643 target_lun); 2644 intflag = splcam(); 2645 pACB->scan_devices[target_id][target_lun] = 0; 2646 /* no device set scan device flag =0*/ 2647 /* pDCB Q link */ 2648 /* move the head of DCB to tempDCB*/ 2649 pTempDCB=pACB->pLinkDCB; 2650 /* search current DCB for pass link */ 2651 while (pTempDCB->pNextDCB != pDCB) { 2652 pTempDCB = pTempDCB->pNextDCB; 2653 } 2654 /* 2655 * when the current DCB found than connect 2656 * current DCB tail 2657 */ 2658 /* to the DCB tail that before current DCB */ 2659 pTempDCB->pNextDCB = pDCB->pNextDCB; 2660 /* 2661 * if there was only one DCB ,connect his tail 2662 * to his head 2663 */ 2664 if (pACB->pLinkDCB == pDCB) 2665 pACB->pLinkDCB = pTempDCB->pNextDCB; 2666 if (pACB->pDCBRunRobin == pDCB) 2667 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2668 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2669 pACB->DeviceCnt--; 2670 if (pACB->DeviceCnt == 0) { 2671 pACB->pLinkDCB = NULL; 2672 pACB->pDCBRunRobin = NULL; 2673 } 2674 splx(intflag); 2675 } else { 2676#ifdef trm_DEBUG1 2677 int j; 2678 for (j = 0; j < 28; j++) { 2679 TRM_DPRINTF("ptr=%2x ", 2680 ((u_int8_t *)ptr)[j]); 2681 } 2682#endif 2683 pDCB->DevType = bval1; 2684 if (bval1 == SCSI_DASD || 2685 bval1 == SCSI_OPTICAL) { 2686 if ((((ptr->Vers & 0x07) >= 2) || 2687 ((ptr->RDF & 0x0F) == 2)) && 2688 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2689 (pDCB->DevMode & TAG_QUEUING_) && 2690 (pDCB->DevMode & EN_DISCONNECT_)) { 2691 if (pDCB->DevMode & 2692 TAG_QUEUING_) { 2693 pDCB-> 2694 MaxActiveCommandCnt = 2695 pACB->TagMaxNum; 2696 pDCB->SyncMode |= 2697 EN_TAG_QUEUING; 2698 pDCB->tinfo.disc_tag |= 2699 TRM_CUR_TAGENB; 2700 } else { 2701 pDCB->SyncMode |= 2702 EN_ATN_STOP; 2703 pDCB->tinfo.disc_tag &= 2704 ~TRM_CUR_TAGENB; 2705 } 2706 } 2707 } 2708 } 2709 /* pSRB->CmdBlock[0] == INQUIRY */ 2710 } 2711 /* pACB->scan_devices[target_id][target_lun] */ 2712 } 2713 intflag = splcam(); 2714 /* ReleaseSRB(pDCB, pSRB); */ 2715 if (pSRB == pDCB->pGoingSRB) 2716 pDCB->pGoingSRB = pSRB->pNextSRB; 2717 else { 2718 psrb = pDCB->pGoingSRB; 2719 while (psrb->pNextSRB != pSRB) { 2720 psrb = psrb->pNextSRB; 2721 } 2722 psrb->pNextSRB = pSRB->pNextSRB; 2723 if (pSRB == pDCB->pGoingLastSRB) { 2724 pDCB->pGoingLastSRB = psrb; 2725 } 2726 } 2727 pSRB->pNextSRB = pACB->pFreeSRB; 2728 pACB->pFreeSRB = pSRB; 2729 pDCB->GoingSRBCnt--; 2730 trm_DoWaitingSRB(pACB); 2731 2732 splx(intflag); 2733 /* Notify cmd done */ 2734 xpt_done (pccb); 2735} 2736 2737static void 2738trm_DoingSRB_Done(PACB pACB) 2739{ 2740 PDCB pDCB, pdcb; 2741 PSRB psrb, psrb2; 2742 u_int16_t cnt, i; 2743 union ccb *pccb; 2744 2745 pDCB = pACB->pLinkDCB; 2746 if (pDCB == NULL) 2747 return; 2748 pdcb = pDCB; 2749 do { 2750 cnt = pdcb->GoingSRBCnt; 2751 psrb = pdcb->pGoingSRB; 2752 for (i = 0; i < cnt; i++) { 2753 psrb2 = psrb->pNextSRB; 2754 pccb = psrb->pccb; 2755 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2756 /* ReleaseSRB(pDCB, pSRB); */ 2757 psrb->pNextSRB = pACB->pFreeSRB; 2758 pACB->pFreeSRB = psrb; 2759 xpt_done(pccb); 2760 psrb = psrb2; 2761 } 2762 pdcb->GoingSRBCnt = 0;; 2763 pdcb->pGoingSRB = NULL; 2764 pdcb = pdcb->pNextDCB; 2765 } 2766 while (pdcb != pDCB); 2767} 2768 2769static void 2770trm_ResetSCSIBus(PACB pACB) 2771{ 2772 int intflag; 2773 2774 intflag = splcam(); 2775 pACB->ACBFlag |= RESET_DEV; 2776 2777 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2778 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2779 splx(intflag); 2780 return; 2781} 2782 2783static void 2784trm_ScsiRstDetect(PACB pACB) 2785{ 2786 int intflag; 2787 u_long wlval; 2788 2789 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2790 wlval = 1000; 2791 while (--wlval) 2792 DELAY(1000); 2793 intflag = splcam(); 2794 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2795 2796 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2797 2798 if (pACB->ACBFlag & RESET_DEV) 2799 pACB->ACBFlag |= RESET_DONE; 2800 else { 2801 pACB->ACBFlag |= RESET_DETECT; 2802 trm_ResetDevParam(pACB); 2803 /* trm_DoingSRB_Done(pACB); ???? */ 2804 trm_RecoverSRB(pACB); 2805 pACB->pActiveDCB = NULL; 2806 pACB->ACBFlag = 0; 2807 trm_DoWaitingSRB(pACB); 2808 } 2809 splx(intflag); 2810 return; 2811} 2812 2813static void 2814trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2815{ 2816 union ccb *pccb; 2817 struct ccb_scsiio *pcsio; 2818 2819 pccb = pSRB->pccb; 2820 pcsio = &pccb->csio; 2821 2822 pSRB->SRBFlag |= AUTO_REQSENSE; 2823 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2824 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2825 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2826 pSRB->SRBSGCount); 2827 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2828 2829 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2830 pSRB->AdaptStatus = 0; 2831 pSRB->TargetStatus = 0; 2832 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2833 2834 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2835 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2836 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2837 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2838 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2839 pSRB->SRBSGCount = 1; 2840 pSRB->SRBSGIndex = 0; 2841 2842 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2843 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2844 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2845 pSRB->ScsiCmdLen = 6; 2846 2847 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2848 /* 2849 * If trm_StartSCSI return 1 : 2850 * current interrupt status is interrupt disreenable 2851 * It's said that SCSI processor has more one SRB need to do 2852 */ 2853 trm_RewaitSRB(pDCB, pSRB); 2854} 2855 2856static void 2857trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2858{ 2859 2860 pSRB->MsgCnt = 1; 2861 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2862} 2863 2864static void 2865trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2866{ 2867 2868 pSRB->MsgOutBuf[0] = MSG_ABORT; 2869 trm_EnableMsgOutAbort2(pACB, pSRB); 2870} 2871 2872static void 2873trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2874{ 2875 PNVRAMTYPE pEEpromBuf; 2876 u_int8_t bval,PeriodIndex; 2877 u_int target_id,target_lun; 2878 PDCB pTempDCB; 2879 int intflag; 2880 2881 target_id = i; 2882 target_lun = j; 2883 2884 /* 2885 * Using the lun 0 device to init other DCB first, if the device 2886 * has been initialized. 2887 * I don't want init sync arguments one by one, it is the same. 2888 */ 2889 if (target_lun != 0 && 2890 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2891 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2892 sizeof(TRM_DCB)); 2893 intflag = splcam(); 2894 if (pACB->pLinkDCB == 0) { 2895 pACB->pLinkDCB = pDCB; 2896 /* 2897 * RunRobin impersonate the role 2898 * that let each device had good proportion 2899 * about SCSI command proceeding 2900 */ 2901 pACB->pDCBRunRobin = pDCB; 2902 pDCB->pNextDCB = pDCB; 2903 } else { 2904 pTempDCB=pACB->pLinkDCB; 2905 /* search the last nod of DCB link */ 2906 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2907 pTempDCB = pTempDCB->pNextDCB; 2908 /* connect current DCB with last DCB tail */ 2909 pTempDCB->pNextDCB = pDCB; 2910 /* connect current DCB tail to this DCB Q head */ 2911 pDCB->pNextDCB=pACB->pLinkDCB; 2912 } 2913 splx(intflag); 2914 2915 pACB->DeviceCnt++; 2916 pDCB->TargetID = target_id; 2917 pDCB->TargetLUN = target_lun; 2918 pDCB->pWaitingSRB = NULL; 2919 pDCB->pGoingSRB = NULL; 2920 pDCB->GoingSRBCnt = 0; 2921 pDCB->pActiveSRB = NULL; 2922 pDCB->MaxActiveCommandCnt = 1; 2923 pDCB->DCBFlag = 0; 2924 pDCB->DCBstatus |= DS_IN_QUEUE; 2925 /* $$$$$$$ */ 2926 pEEpromBuf = &trm_eepromBuf[unit]; 2927 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2928 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2929 /* $$$$$$$ */ 2930 /* 2931 * disconnect enable ? 2932 */ 2933 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2934 bval = 0xC0; 2935 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2936 } else { 2937 bval = 0x80; 2938 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2939 } 2940 bval |= target_lun; 2941 pDCB->IdentifyMsg = bval; 2942 if (target_lun != 0 && 2943 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2944 return; 2945 /* $$$$$$$ */ 2946 /* 2947 * tag Qing enable ? 2948 */ 2949 if (pDCB->DevMode & TAG_QUEUING_) { 2950 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2951 } else 2952 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2953 /* $$$$$$$ */ 2954 /* 2955 * wide nego ,sync nego enable ? 2956 */ 2957 pDCB->SyncPeriod = 0; 2958 pDCB->SyncOffset = 0; 2959 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2960 if (pACB->AdaptType==1) {/* is U2? */ 2961 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2962 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2963 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2964 } else { 2965 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2966 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2967 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2968 } 2969 pDCB->SyncMode = 0; 2970 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2971 (pACB->Config & HCC_WIDE_CARD)) 2972 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2973 /* enable wide nego */ 2974 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2975 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2976 /* enable sync nego */ 2977 /* $$$$$$$ */ 2978 /* 2979 * Fill in tinfo structure. 2980 */ 2981 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2982 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2983 2984 pDCB->tinfo.current.period = 0; 2985 pDCB->tinfo.current.offset = 0; 2986 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2987} 2988 2989static void 2990trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2991{ 2992 PSRB pSRB; 2993 2994 pSRB=(PSRB) arg; 2995 pSRB->SRBSGPhyAddr=segs->ds_addr; 2996 return; 2997} 2998 2999static int 3000trm_initSRB(PACB pACB) 3001{ 3002 u_int16_t i; 3003 PSRB pSRB; 3004 int error; 3005 3006 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 3007 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3008 3009 /* DMA tag for our S/G structures */ 3010 if (bus_dma_tag_create( 3011 /*parent_dmat*/pSRB->parent_dmat, 3012 /*alignment*/ 1, 3013 /*boundary*/ 0, 3014 /*lowaddr*/ BUS_SPACE_MAXADDR, 3015 /*highaddr*/ BUS_SPACE_MAXADDR, 3016 /*filter*/ NULL, 3017 /*filterarg*/ NULL, 3018 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3019 /*nsegments*/ 1, 3020 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3021 /*flags*/ 0, 3022 /*lockfunc*/ busdma_lock_mutex, 3023 /*lockarg*/ &Giant, 3024 /*dmat*/ &pSRB->sg_dmat) != 0) { 3025 return ENXIO; 3026 } 3027 if (bus_dmamem_alloc(pSRB->sg_dmat, (void **)&pSRB->pSRBSGL, 3028 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3029 return ENXIO; 3030 } 3031 bus_dmamap_load(pSRB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3032 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3033 trm_srbmapSG, pSRB, /*flags*/0); 3034 if (i != TRM_MAX_SRB_CNT - 1) { 3035 /* 3036 * link all SRB 3037 */ 3038 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3039 } else { 3040 /* 3041 * load NULL to NextSRB of the last SRB 3042 */ 3043 pSRB->pNextSRB = NULL; 3044 } 3045 pSRB->TagNumber = i; 3046 3047 /* 3048 * Create the dmamap. This is no longer optional! 3049 * 3050 * XXX This is not freed on unload! None of the other 3051 * allocations in this function are either! 3052 */ 3053 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 3054 &pSRB->dmamap)) != 0) 3055 return (error); 3056 3057 } 3058 return (0); 3059} 3060 3061 3062 3063 3064static void 3065trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3066{ 3067 PNVRAMTYPE pEEpromBuf; 3068 3069 pEEpromBuf = &trm_eepromBuf[unit]; 3070 pACB->max_id = 15; 3071 3072 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3073 pACB->max_lun = 7; 3074 else 3075 pACB->max_lun = 0; 3076 3077 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3078 pACB->max_id, pACB->max_lun); 3079 pACB->pLinkDCB = NULL; 3080 pACB->pDCBRunRobin = NULL; 3081 pACB->pActiveDCB = NULL; 3082 pACB->AdapterUnit = (u_int8_t)unit; 3083 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3084 pACB->AdaptSCSILUN = 0; 3085 pACB->DeviceCnt = 0; 3086 pACB->AdaptType = adaptType; 3087 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3088 pACB->ACBFlag = 0; 3089 return; 3090} 3091 3092static void 3093NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3094{ 3095 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3096 u_int8_t bAddr; 3097 3098 /* Enable SEEPROM */ 3099 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3100 TRMREG_GEN_CONTROL); 3101 /* 3102 * Write enable 3103 */ 3104 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3105 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3106 NVRAM_trm_wait_30us(pACB); 3107 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3108 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3109 } 3110 /* 3111 * Write disable 3112 */ 3113 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3114 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3115 NVRAM_trm_wait_30us(pACB); 3116 /* Disable SEEPROM */ 3117 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3118 TRMREG_GEN_CONTROL); 3119 return; 3120} 3121 3122static void 3123NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3124{ 3125 int i; 3126 u_int8_t bSendData; 3127 /* 3128 * Send write command & address 3129 */ 3130 3131 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3132 /* 3133 * Write data 3134 */ 3135 for (i = 0; i < 8; i++, bData <<= 1) { 3136 bSendData = NVR_SELECT; 3137 if (bData & 0x80) 3138 /* Start from bit 7 */ 3139 bSendData |= NVR_BITOUT; 3140 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3141 NVRAM_trm_wait_30us(pACB); 3142 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3143 NVRAM_trm_wait_30us(pACB); 3144 } 3145 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3146 NVRAM_trm_wait_30us(pACB); 3147 /* 3148 * Disable chip select 3149 */ 3150 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3151 NVRAM_trm_wait_30us(pACB); 3152 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3153 NVRAM_trm_wait_30us(pACB); 3154 /* 3155 * Wait for write ready 3156 */ 3157 while (1) { 3158 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3159 NVRAM_trm_wait_30us(pACB); 3160 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3161 NVRAM_trm_wait_30us(pACB); 3162 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3163 break; 3164 } 3165 } 3166 /* 3167 * Disable chip select 3168 */ 3169 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3170 return; 3171} 3172 3173static void 3174NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3175{ 3176 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3177 u_int8_t bAddr; 3178 3179 /* 3180 * Enable SEEPROM 3181 */ 3182 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3183 TRMREG_GEN_CONTROL); 3184 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3185 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3186 /* 3187 * Disable SEEPROM 3188 */ 3189 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3190 TRMREG_GEN_CONTROL); 3191 return; 3192} 3193 3194static u_int8_t 3195NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3196{ 3197 int i; 3198 u_int8_t bReadData, bData = 0; 3199 /* 3200 * Send read command & address 3201 */ 3202 3203 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3204 3205 for (i = 0; i < 8; i++) { 3206 /* 3207 * Read data 3208 */ 3209 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3210 NVRAM_trm_wait_30us(pACB); 3211 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3212 /* 3213 * Get data bit while falling edge 3214 */ 3215 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3216 bData <<= 1; 3217 if (bReadData & NVR_BITIN) { 3218 bData |= 1; 3219 } 3220 NVRAM_trm_wait_30us(pACB); 3221 } 3222 /* 3223 * Disable chip select 3224 */ 3225 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3226 return (bData); 3227} 3228 3229static void 3230NVRAM_trm_wait_30us(PACB pACB) 3231{ 3232 3233 /* ScsiPortStallExecution(30); wait 30 us */ 3234 trm_reg_write8(5, TRMREG_GEN_TIMER); 3235 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3236 return; 3237} 3238 3239static void 3240NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3241{ 3242 int i; 3243 u_int8_t bSendData; 3244 3245 for (i = 0; i < 3; i++, bCmd <<= 1) { 3246 /* 3247 * Program SB+OP code 3248 */ 3249 bSendData = NVR_SELECT; 3250 if (bCmd & 0x04) 3251 bSendData |= NVR_BITOUT; 3252 /* start from bit 2 */ 3253 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3254 NVRAM_trm_wait_30us(pACB); 3255 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3256 NVRAM_trm_wait_30us(pACB); 3257 } 3258 for (i = 0; i < 7; i++, bAddr <<= 1) { 3259 /* 3260 * Program address 3261 */ 3262 bSendData = NVR_SELECT; 3263 if (bAddr & 0x40) 3264 /* Start from bit 6 */ 3265 bSendData |= NVR_BITOUT; 3266 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3267 NVRAM_trm_wait_30us(pACB); 3268 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3269 NVRAM_trm_wait_30us(pACB); 3270 } 3271 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3272 NVRAM_trm_wait_30us(pACB); 3273} 3274 3275static void 3276trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3277{ 3278 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3279 u_int16_t wAddr, wCheckSum; 3280 u_long dAddr, *dpEeprom; 3281 3282 NVRAM_trm_read_all(pEEpromBuf,pACB); 3283 wCheckSum = 0; 3284 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3285 wAddr < 64; wAddr++, wpEeprom++) { 3286 wCheckSum += *wpEeprom; 3287 } 3288 if (wCheckSum != 0x1234) { 3289 /* 3290 * Checksum error, load default 3291 */ 3292 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3293 pEEpromBuf->NvramSubVendorID[1] = 3294 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3295 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3296 pEEpromBuf->NvramSubSysID[1] = 3297 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3298 pEEpromBuf->NvramSubClass = 0x00; 3299 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3300 pEEpromBuf->NvramVendorID[1] = 3301 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3302 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3303 pEEpromBuf->NvramDeviceID[1] = 3304 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3305 pEEpromBuf->NvramReserved = 0x00; 3306 3307 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3308 dAddr < 16; dAddr++, dpEeprom++) { 3309 *dpEeprom = 0x00000077; 3310 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3311 } 3312 3313 *dpEeprom++ = 0x04000F07; 3314 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3315 *dpEeprom++ = 0x00000015; 3316 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3317 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3318 *dpEeprom = 0x00; 3319 pEEpromBuf->NvramCheckSum = 0x00; 3320 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3321 wAddr < 63; wAddr++, wpEeprom++) 3322 wCheckSum += *wpEeprom; 3323 *wpEeprom = 0x1234 - wCheckSum; 3324 NVRAM_trm_write_all(pEEpromBuf,pACB); 3325 } 3326 return; 3327} 3328static int 3329trm_initAdapter(PACB pACB, u_int16_t unit) 3330{ 3331 PNVRAMTYPE pEEpromBuf; 3332 u_int16_t wval; 3333 u_int8_t bval; 3334 3335 pEEpromBuf = &trm_eepromBuf[unit]; 3336 3337 /* 250ms selection timeout */ 3338 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3339 /* Mask all the interrupt */ 3340 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3341 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3342 /* Reset SCSI module */ 3343 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3344 /* program configuration 0 */ 3345 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3346 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3347 pACB->Config |= HCC_WIDE_CARD; 3348 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3349 pACB->Config |= HCC_SCSI_RESET; 3350 if (pACB->Config & HCC_PARITY) 3351 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3352 else 3353 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3354 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3355 /* program configuration 1 */ 3356 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3357 /* program Host ID */ 3358 bval = pEEpromBuf->NvramScsiId; 3359 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3360 /* set ansynchronous transfer */ 3361 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3362 /* Trun LED control off*/ 3363 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3364 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3365 /* DMA config */ 3366 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3367 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3368 /* Clear pending interrupt status */ 3369 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3370 /* Enable SCSI interrupt */ 3371 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3372 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3373 return (0); 3374} 3375 3376static void 3377trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3378{ 3379 PACB pACB; 3380 3381 pACB = (PACB)arg; 3382 pACB->srb_physbase = segs->ds_addr; 3383} 3384 3385static void 3386trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3387{ 3388 bus_addr_t *baddr; 3389 3390 baddr = (bus_addr_t *)arg; 3391 *baddr = segs->ds_addr; 3392} 3393 3394static PACB 3395trm_init(u_int16_t unit, device_t dev) 3396{ 3397 PACB pACB; 3398 int rid = PCIR_BAR(0), i = 0, j = 0; 3399 u_int16_t adaptType = 0; 3400 3401 pACB = (PACB) device_get_softc(dev); 3402 if (!pACB) { 3403 printf("trm%d: cannot allocate ACB !\n", unit); 3404 return (NULL); 3405 } 3406 pACB->iores = bus_alloc_resource(dev, SYS_RES_IOPORT, 3407 &rid, 0, ~0, 1, RF_ACTIVE); 3408 if (pACB->iores == NULL) { 3409 printf("trm_init: bus_alloc_resource failed!\n"); 3410 return (NULL); 3411 } 3412 switch (pci_get_devid(dev)) { 3413 case PCI_DEVICEID_TRMS1040: 3414 adaptType = 0; 3415 break; 3416 case PCI_DEVICEID_TRMS2080: 3417 adaptType = 1; 3418 break; 3419 default: 3420 printf("trm_init %d: unknown adapter type!\n", unit); 3421 goto bad; 3422 } 3423 pACB->dev = dev; 3424 pACB->tag = rman_get_bustag(pACB->iores); 3425 pACB->bsh = rman_get_bushandle(pACB->iores); 3426 if (bus_dma_tag_create( 3427 /*parent_dmat*/ pACB->parent_dmat, 3428 /*alignment*/ 1, 3429 /*boundary*/ 0, 3430 /*lowaddr*/ BUS_SPACE_MAXADDR, 3431 /*highaddr*/ BUS_SPACE_MAXADDR, 3432 /*filter*/ NULL, 3433 /*filterarg*/ NULL, 3434 /*maxsize*/ MAXBSIZE, 3435 /*nsegments*/ TRM_NSEG, 3436 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3437 /*flags*/ BUS_DMA_ALLOCNOW, 3438 /*lockfunc*/ busdma_lock_mutex, 3439 /*lockarg*/ &Giant, 3440 /* dmat */ &pACB->buffer_dmat) != 0) 3441 goto bad; 3442 /* DMA tag for our ccb structures */ 3443 if (bus_dma_tag_create( 3444 /*parent_dmat*/pACB->parent_dmat, 3445 /*alignment*/ 1, 3446 /*boundary*/ 0, 3447 /*lowaddr*/ BUS_SPACE_MAXADDR, 3448 /*highaddr*/ BUS_SPACE_MAXADDR, 3449 /*filter*/ NULL, 3450 /*filterarg*/ NULL, 3451 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3452 /*nsegments*/ 1, 3453 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3454 /*flags*/ 0, 3455 /*lockfunc*/ busdma_lock_mutex, 3456 /*lockarg*/ &Giant, 3457 /*dmat*/ &pACB->srb_dmat) != 0) { 3458 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3459 goto bad; 3460 } 3461 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3462 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3463 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3464 goto bad; 3465 } 3466 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3467 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3468 /* flags */0); 3469 /* Create, allocate, and map DMA buffers for autosense data */ 3470 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3471 /*boundary*/0, 3472 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3473 /*highaddr*/BUS_SPACE_MAXADDR, 3474 /*filter*/NULL, /*filterarg*/NULL, 3475 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3476 /*nsegments*/1, 3477 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3478 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3479 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3480 if (bootverbose) 3481 device_printf(dev, "cannot create sense buffer dmat\n"); 3482 goto bad; 3483 } 3484 3485 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3486 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3487 goto bad; 3488 3489 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3490 pACB->sense_buffers, 3491 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3492 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3493 3494 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3495 trm_initACB(pACB, adaptType, unit); 3496 for (i = 0; i < (pACB->max_id + 1); i++) { 3497 if (pACB->AdaptSCSIID == i) 3498 continue; 3499 for(j = 0; j < (pACB->max_lun + 1); j++) { 3500 pACB->scan_devices[i][j] = 1; 3501 /* we assume we need to scan all devices */ 3502 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3503 } 3504 } 3505 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3506 if (trm_initSRB(pACB)) { 3507 printf("trm_initSRB: error\n"); 3508 goto bad; 3509 } 3510 if (trm_initAdapter(pACB, unit)) { 3511 printf("trm_initAdapter: initial ERROR\n"); 3512 goto bad; 3513 } 3514 return (pACB); 3515bad: 3516 if (pACB->iores) 3517 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3518 pACB->iores); 3519 if (pACB->sense_dmamap) { 3520 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3521 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3522 pACB->sense_dmamap); 3523 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3524 } 3525 if (pACB->sense_dmat) 3526 bus_dma_tag_destroy(pACB->sense_dmat); 3527 if (pACB->srb_dmamap) { 3528 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3529 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3530 pACB->srb_dmamap); 3531 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3532 } 3533 if (pACB->srb_dmat) 3534 bus_dma_tag_destroy(pACB->srb_dmat); 3535 if (pACB->buffer_dmat) 3536 bus_dma_tag_destroy(pACB->buffer_dmat); 3537 return (NULL); 3538} 3539 3540static int 3541trm_attach(device_t dev) 3542{ 3543 struct cam_devq *device_Q; 3544 u_long device_id; 3545 PACB pACB = 0; 3546 int rid = 0; 3547 int unit = device_get_unit(dev); 3548 3549 device_id = pci_get_devid(dev); 3550 /* 3551 * These cards do not allow memory mapped accesses 3552 */ 3553 if ((pACB = trm_init((u_int16_t) unit, 3554 dev)) == NULL) { 3555 printf("trm%d: trm_init error!\n",unit); 3556 return (ENXIO); 3557 } 3558 /* After setting up the adapter, map our interrupt */ 3559 /* 3560 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3561 * start queue to reset to the idle loop. 3562 * Create device queue of SIM(s) 3563 * (MAX_START_JOB - 1) : max_sim_transactions 3564 */ 3565 pACB->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, 3566 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 3567 if (pACB->irq == NULL || 3568 bus_setup_intr(dev, pACB->irq, 3569 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3570 printf("trm%d: register Interrupt handler error!\n", unit); 3571 goto bad; 3572 } 3573 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3574 if (device_Q == NULL){ 3575 printf("trm%d: device_Q == NULL !\n",unit); 3576 goto bad; 3577 } 3578 /* 3579 * Now tell the generic SCSI layer 3580 * about our bus. 3581 * If this is the xpt layer creating a sim, then it's OK 3582 * to wait for an allocation. 3583 * XXX Should we pass in a flag to indicate that wait is OK? 3584 * 3585 * SIM allocation 3586 * 3587 * SCSI Interface Modules 3588 * The sim driver creates a sim for each controller. The sim device 3589 * queue is separately created in order to allow resource sharing betwee 3590 * sims. For instance, a driver may create one sim for each channel of 3591 * a multi-channel controller and use the same queue for each channel. 3592 * In this way, the queue resources are shared across all the channels 3593 * of the multi-channel controller. 3594 * trm_action : sim_action_func 3595 * trm_poll : sim_poll_func 3596 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3597 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3598 * pACB->unit : unit 3599 * 1 : max_dev_transactions 3600 * MAX_TAGS : max_tagged_dev_transactions 3601 * 3602 * *******Construct our first channel SIM entry 3603 */ 3604 pACB->psim = cam_sim_alloc(trm_action, 3605 trm_poll, 3606 "trm", 3607 pACB, 3608 unit, 3609 1, 3610 TRM_MAX_TAGS_CMD_QUEUE, 3611 device_Q); 3612 if (pACB->psim == NULL) { 3613 printf("trm%d: SIM allocate fault !\n",unit); 3614 cam_simq_free(device_Q); /* SIM allocate fault*/ 3615 goto bad; 3616 } 3617 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3618 printf("trm%d: xpt_bus_register fault !\n",unit); 3619 goto bad; 3620 } 3621 if (xpt_create_path(&pACB->ppath, 3622 NULL, 3623 cam_sim_path(pACB->psim), 3624 CAM_TARGET_WILDCARD, 3625 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3626 printf("trm%d: xpt_create_path fault !\n",unit); 3627 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3628 goto bad; 3629 } 3630 return (0); 3631bad: 3632 if (pACB->iores) 3633 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3634 pACB->iores); 3635 if (pACB->srb_dmamap) { 3636 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3637 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3638 pACB->srb_dmamap); 3639 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3640 } 3641 if (pACB->srb_dmat) 3642 bus_dma_tag_destroy(pACB->srb_dmat); 3643 if (pACB->sense_dmamap) { 3644 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3645 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3646 pACB->sense_dmamap); 3647 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3648 } 3649 if (pACB->sense_dmat) 3650 bus_dma_tag_destroy(pACB->sense_dmat); 3651 if (pACB->buffer_dmat) 3652 bus_dma_tag_destroy(pACB->buffer_dmat); 3653 if (pACB->ih) 3654 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3655 if (pACB->irq) 3656 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3657 if (pACB->psim) 3658 cam_sim_free(pACB->psim, TRUE); 3659 3660 return (ENXIO); 3661 3662} 3663 3664/* 3665* pci_device 3666* trm_probe (device_t tag, pcidi_t type) 3667* 3668*/ 3669static int 3670trm_probe(device_t dev) 3671{ 3672 switch (pci_get_devid(dev)) { 3673 case PCI_DEVICEID_TRMS1040: 3674 device_set_desc(dev, 3675 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3676 return (0); 3677 case PCI_DEVICEID_TRMS2080: 3678 device_set_desc(dev, 3679 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3680 return 0; 3681 default: 3682 return (ENXIO); 3683 } 3684} 3685 3686static int 3687trm_detach(device_t dev) 3688{ 3689 PACB pACB = device_get_softc(dev); 3690 3691 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3692 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3693 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3694 pACB->srb_dmamap); 3695 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3696 bus_dma_tag_destroy(pACB->srb_dmat); 3697 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3698 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3699 pACB->sense_dmamap); 3700 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3701 bus_dma_tag_destroy(pACB->sense_dmat); 3702 bus_dma_tag_destroy(pACB->buffer_dmat); 3703 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3704 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3705 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3706 xpt_free_path(pACB->ppath); 3707 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3708 cam_sim_free(pACB->psim, TRUE); 3709 return (0); 3710} 3711static device_method_t trm_methods[] = { 3712 /* Device interface */ 3713 DEVMETHOD(device_probe, trm_probe), 3714 DEVMETHOD(device_attach, trm_attach), 3715 DEVMETHOD(device_detach, trm_detach), 3716 { 0, 0 } 3717}; 3718 3719static driver_t trm_driver = { 3720 "trm", trm_methods, sizeof(struct _ACB) 3721}; 3722 3723static devclass_t trm_devclass; 3724DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3725