trm.c revision 116813
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 *(C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 12 */ 13 14/* 15 * HISTORY: 16 * 17 * REV# DATE NAME DESCRIPTION 18 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 19 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 20 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 21 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 22 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 23 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 24 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 25 */ 26 27/* 28 * 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 */ 53 54/* 55 * Imported into FreeBSD source repository, and updated to compile under 56 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 57 */ 58 59/* 60 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 61 * <doginou@ci0.org>, 2002-03-04 62 */ 63 64#include <sys/cdefs.h> 65__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 116813 2003-06-25 13:33:41Z cognet $"); 66 67#include <sys/param.h> 68 69#include <sys/systm.h> 70#include <sys/malloc.h> 71#include <sys/queue.h> 72#if __FreeBSD_version >= 500000 73#include <sys/bio.h> 74#endif 75#include <sys/buf.h> 76#include <sys/bus.h> 77#include <sys/kernel.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <pci/pcivar.h> 83#include <pci/pcireg.h> 84#include <machine/resource.h> 85#include <machine/bus_pio.h> 86#include <machine/bus.h> 87#include <machine/clock.h> 88#include <sys/rman.h> 89 90#include <cam/cam.h> 91#include <cam/cam_ccb.h> 92#include <cam/cam_sim.h> 93#include <cam/cam_xpt_sim.h> 94#include <cam/cam_debug.h> 95 96#include <cam/scsi/scsi_all.h> 97#include <cam/scsi/scsi_message.h> 98 99#include <dev/trm/trm.h> 100 101#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 102#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 103#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 104#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 105 reg, value) 106#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 107 reg, value) 108#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 109 reg, value) 110 111#define PCI_Vendor_ID_TEKRAM 0x1DE1 112#define PCI_Device_ID_TRM_S1040 0x0391 113#define PCI_DEVICEID_TRMS1040 0x03911DE1 114#define PCI_DEVICEID_TRMS2080 0x03921DE1 115 116#ifdef trm_DEBUG1 117#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 118#else 119#define TRM_DPRINTF(fmt, arg...) {} 120#endif /* TRM_DEBUG */ 121 122static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 123static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 125static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 126static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 127static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 128static void NVRAM_trm_wait_30us(PACB pACB); 129 130static void trm_Interrupt(void *vpACB); 131static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 154 u_int16_t * pscsi_status); 155static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 156static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 157static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 158static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 159static void trm_Disconnect(PACB pACB); 160static void trm_Reselect(PACB pACB); 161static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 162static void trm_DoingSRB_Done(PACB pACB); 163static void trm_ScsiRstDetect(PACB pACB); 164static void trm_ResetSCSIBus(PACB pACB); 165static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 166static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 167static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 168static void trm_SendSRB(PACB pACB, PSRB pSRB); 169static int trm_probe(device_t tag); 170static int trm_attach(device_t tag); 171static void trm_reset(PACB pACB); 172 173static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 174 175static int trm_initAdapter(PACB pACB, u_int16_t unit); 176static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 177 u_int32_t i, u_int32_t j); 178static int trm_initSRB(PACB pACB); 179static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 180/* CAM SIM entry points */ 181#define ccb_trmsrb_ptr spriv_ptr0 182#define ccb_trmacb_ptr spriv_ptr1 183static void trm_action(struct cam_sim *psim, union ccb *pccb); 184static void trm_poll(struct cam_sim *psim); 185 186 187static void * trm_SCSI_phase0[] = { 188 trm_DataOutPhase0, /* phase:0 */ 189 trm_DataInPhase0, /* phase:1 */ 190 trm_CommandPhase0, /* phase:2 */ 191 trm_StatusPhase0, /* phase:3 */ 192 trm_Nop0, /* phase:4 */ 193 trm_Nop1, /* phase:5 */ 194 trm_MsgOutPhase0, /* phase:6 */ 195 trm_MsgInPhase0, /* phase:7 */ 196}; 197 198/* 199 * 200 * stateV = (void *) trm_SCSI_phase1[phase] 201 * 202 */ 203static void * trm_SCSI_phase1[] = { 204 trm_DataOutPhase1, /* phase:0 */ 205 trm_DataInPhase1, /* phase:1 */ 206 trm_CommandPhase1, /* phase:2 */ 207 trm_StatusPhase1, /* phase:3 */ 208 trm_Nop0, /* phase:4 */ 209 trm_Nop1, /* phase:5 */ 210 trm_MsgOutPhase1, /* phase:6 */ 211 trm_MsgInPhase1, /* phase:7 */ 212}; 213 214 215NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 216/* 217 *Fast20: 000 50ns, 20.0 Mbytes/s 218 * 001 75ns, 13.3 Mbytes/s 219 * 010 100ns, 10.0 Mbytes/s 220 * 011 125ns, 8.0 Mbytes/s 221 * 100 150ns, 6.6 Mbytes/s 222 * 101 175ns, 5.7 Mbytes/s 223 * 110 200ns, 5.0 Mbytes/s 224 * 111 250ns, 4.0 Mbytes/s 225 * 226 *Fast40: 000 25ns, 40.0 Mbytes/s 227 * 001 50ns, 20.0 Mbytes/s 228 * 010 75ns, 13.3 Mbytes/s 229 * 011 100ns, 10.0 Mbytes/s 230 * 100 125ns, 8.0 Mbytes/s 231 * 101 150ns, 6.6 Mbytes/s 232 * 110 175ns, 5.7 Mbytes/s 233 * 111 200ns, 5.0 Mbytes/s 234 */ 235 /* real period: */ 236u_int8_t dc395x_clock_period[] = { 237 12,/* 48 ns 20 MB/sec */ 238 18,/* 72 ns 13.3 MB/sec */ 239 25,/* 100 ns 10.0 MB/sec */ 240 31,/* 124 ns 8.0 MB/sec */ 241 37,/* 148 ns 6.6 MB/sec */ 242 43,/* 172 ns 5.7 MB/sec */ 243 50,/* 200 ns 5.0 MB/sec */ 244 62 /* 248 ns 4.0 MB/sec */ 245}; 246 247u_int8_t dc395u2x_clock_period[]={ 248 10,/* 25 ns 40.0 MB/sec */ 249 12,/* 48 ns 20.0 MB/sec */ 250 18,/* 72 ns 13.3 MB/sec */ 251 25,/* 100 ns 10.0 MB/sec */ 252 31,/* 124 ns 8.0 MB/sec */ 253 37,/* 148 ns 6.6 MB/sec */ 254 43,/* 172 ns 5.7 MB/sec */ 255 50,/* 200 ns 5.0 MB/sec */ 256}; 257 258#define dc395x_tinfo_period dc395x_clock_period 259#define dc395u2x_tinfo_period dc395u2x_clock_period 260 261static PSRB 262trm_GetSRB(PACB pACB) 263{ 264 int intflag; 265 PSRB pSRB; 266 267 intflag = splcam(); 268 pSRB = pACB->pFreeSRB; 269 if (pSRB) { 270 pACB->pFreeSRB = pSRB->pNextSRB; 271 pSRB->pNextSRB = NULL; 272 } 273 splx(intflag); 274 return (pSRB); 275} 276 277static void 278trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 279{ 280 PSRB psrb1; 281 int intflag; 282 283 intflag = splcam(); 284 if ((psrb1 = pDCB->pWaitingSRB)) { 285 pSRB->pNextSRB = psrb1; 286 pDCB->pWaitingSRB = pSRB; 287 } else { 288 pSRB->pNextSRB = NULL; 289 pDCB->pWaitingSRB = pSRB; 290 pDCB->pWaitingLastSRB = pSRB; 291 } 292 splx(intflag); 293} 294 295static void 296trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 297{ 298 PSRB psrb1; 299 int intflag; 300 301 intflag = splcam(); 302 pDCB->GoingSRBCnt--; 303 psrb1 = pDCB->pGoingSRB; 304 if (pSRB == psrb1) 305 /* 306 * if this SRB is GoingSRB 307 * remove this SRB from GoingSRB Q 308 */ 309 pDCB->pGoingSRB = psrb1->pNextSRB; 310 else { 311 /* 312 * if this SRB is not current GoingSRB 313 * remove this SRB from GoingSRB Q 314 */ 315 while (pSRB != psrb1->pNextSRB) 316 psrb1 = psrb1->pNextSRB; 317 psrb1->pNextSRB = pSRB->pNextSRB; 318 if (pSRB == pDCB->pGoingLastSRB) 319 pDCB->pGoingLastSRB = psrb1; 320 } 321 if ((psrb1 = pDCB->pWaitingSRB)) { 322 /* 323 * if WaitingSRB Q is not NULL 324 * Q back this SRB into WaitingSRB 325 */ 326 327 pSRB->pNextSRB = psrb1; 328 pDCB->pWaitingSRB = pSRB; 329 } else { 330 pSRB->pNextSRB = NULL; 331 pDCB->pWaitingSRB = pSRB; 332 pDCB->pWaitingLastSRB = pSRB; 333 } 334 splx(intflag); 335} 336 337static void 338trm_DoWaitingSRB(PACB pACB) 339{ 340 int intflag; 341 PDCB ptr, ptr1; 342 PSRB pSRB; 343 344 intflag = splcam(); 345 if (!(pACB->pActiveDCB) && 346 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 347 ptr = pACB->pDCBRunRobin; 348 if (!ptr) { 349 ptr = pACB->pLinkDCB; 350 pACB->pDCBRunRobin = ptr; 351 } 352 ptr1 = ptr; 353 for (;ptr1 ;) { 354 pACB->pDCBRunRobin = ptr1->pNextDCB; 355 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 356 || !(pSRB = ptr1->pWaitingSRB)) { 357 if (pACB->pDCBRunRobin == ptr) 358 break; 359 ptr1 = ptr1->pNextDCB; 360 } else { 361 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 362 /* 363 * If trm_StartSCSI return 0 : 364 * current interrupt status is interrupt enable 365 * It's said that SCSI processor is unoccupied 366 */ 367 ptr1->GoingSRBCnt++; 368 if (ptr1->pWaitingLastSRB == pSRB) { 369 ptr1->pWaitingSRB = NULL; 370 ptr1->pWaitingLastSRB = NULL; 371 } else 372 ptr1->pWaitingSRB = pSRB->pNextSRB; 373 pSRB->pNextSRB = NULL; 374 if (ptr1->pGoingSRB) 375 ptr1->pGoingLastSRB->pNextSRB = pSRB; 376 else 377 ptr1->pGoingSRB = pSRB; 378 ptr1->pGoingLastSRB = pSRB; 379 } 380 break; 381 } 382 } 383 } 384 splx(intflag); 385 return; 386} 387 388static void 389trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 390{ 391 392 if (pDCB->pWaitingSRB) { 393 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 394 pDCB->pWaitingLastSRB = pSRB; 395 pSRB->pNextSRB = NULL; 396 } else { 397 pDCB->pWaitingSRB = pSRB; 398 pDCB->pWaitingLastSRB = pSRB; 399 } 400} 401 402static u_int32_t 403trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 404{ 405 int offset; 406 407 offset = pSRB->TagNumber; 408 return (pACB->sense_busaddr + 409 (offset * sizeof(struct scsi_sense_data))); 410} 411 412static struct scsi_sense_data * 413trm_get_sense_buf(PACB pACB, PSRB pSRB) 414{ 415 int offset; 416 417 offset = pSRB->TagNumber; 418 return (&pACB->sense_buffers[offset]); 419} 420static void 421trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 422{ 423 int flags; 424 PACB pACB; 425 PSRB pSRB; 426 union ccb *ccb; 427 u_long totalxferlen=0; 428 429 flags = splcam(); 430 pSRB = (PSRB)arg; 431 ccb = pSRB->pccb; 432 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 433 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 434 if (nseg != 0) { 435 PSEG psg; 436 bus_dma_segment_t *end_seg; 437 int op; 438 439 /* Copy the segments into our SG list */ 440 end_seg = dm_segs + nseg; 441 psg = pSRB->pSRBSGL; 442 while (dm_segs < end_seg) { 443 psg->address = dm_segs->ds_addr; 444 psg->length = (u_long)dm_segs->ds_len; 445 totalxferlen += dm_segs->ds_len; 446 psg++; 447 dm_segs++; 448 } 449 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 450 op = BUS_DMASYNC_PREREAD; 451 } else { 452 op = BUS_DMASYNC_PREWRITE; 453 } 454 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 455 } 456 pSRB->RetryCnt = 0; 457 pSRB->SRBTotalXferLength = totalxferlen; 458 pSRB->SRBSGCount = nseg; 459 pSRB->SRBSGIndex = 0; 460 pSRB->AdaptStatus = 0; 461 pSRB->TargetStatus = 0; 462 pSRB->MsgCnt = 0; 463 pSRB->SRBStatus = 0; 464 pSRB->SRBFlag = 0; 465 pSRB->SRBState = 0; 466 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 467 468 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 469 if (nseg != 0) 470 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 471 pSRB->pNextSRB = pACB->pFreeSRB; 472 pACB->pFreeSRB = pSRB; 473 xpt_done(ccb); 474 splx(flags); 475 return; 476 } 477 ccb->ccb_h.status |= CAM_SIM_QUEUED; 478#if 0 479 /* XXX Need a timeout handler */ 480 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 481#endif 482 trm_SendSRB(pACB, pSRB); 483 splx(flags); 484 return; 485} 486 487static void 488trm_SendSRB(PACB pACB, PSRB pSRB) 489{ 490 PDCB pDCB; 491 492 pDCB = pSRB->pSRBDCB; 493 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 494 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 495 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 496 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 497 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 498 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 499 trm_SRBwaiting(pDCB, pSRB); 500 goto SND_EXIT; 501 } 502 503 if (pDCB->pWaitingSRB) { 504 trm_SRBwaiting(pDCB, pSRB); 505 pSRB = pDCB->pWaitingSRB; 506 pDCB->pWaitingSRB = pSRB->pNextSRB; 507 pSRB->pNextSRB = NULL; 508 } 509 510 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 511 /* 512 * If trm_StartSCSI return 0 : 513 * current interrupt status is interrupt enable 514 * It's said that SCSI processor is unoccupied 515 */ 516 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 517 if (pDCB->pGoingSRB) { 518 pDCB->pGoingLastSRB->pNextSRB = pSRB; 519 pDCB->pGoingLastSRB = pSRB; 520 } else { 521 pDCB->pGoingSRB = pSRB; 522 pDCB->pGoingLastSRB = pSRB; 523 } 524 } else { 525 /* 526 * If trm_StartSCSI return 1 : 527 * current interrupt status is interrupt disreenable 528 * It's said that SCSI processor has more one SRB need to do 529 */ 530 trm_RewaitSRB0(pDCB, pSRB); 531 } 532SND_EXIT: 533 return; 534} 535 536 537static void 538trm_action(struct cam_sim *psim, union ccb *pccb) 539{ 540 PACB pACB; 541 int actionflags; 542 u_int target_id,target_lun; 543 544 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 545 546 actionflags = splcam(); 547 pACB = (PACB) cam_sim_softc(psim); 548 target_id = pccb->ccb_h.target_id; 549 target_lun = pccb->ccb_h.target_lun; 550 551 switch (pccb->ccb_h.func_code) { 552 case XPT_NOOP: 553 TRM_DPRINTF(" XPT_NOOP \n"); 554 pccb->ccb_h.status = CAM_REQ_INVALID; 555 xpt_done(pccb); 556 break; 557 /* 558 * Execute the requested I/O operation 559 */ 560 case XPT_SCSI_IO: { 561 PDCB pDCB = NULL; 562 PSRB pSRB; 563 struct ccb_scsiio *pcsio; 564 565 pcsio = &pccb->csio; 566 TRM_DPRINTF(" XPT_SCSI_IO \n"); 567 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 568 ,target_id, target_lun); 569 TRM_DPRINTF( 570 "pACB->scan_devices[target_id][target_lun]= %d \n" 571 ,pACB->scan_devices[target_id][target_lun]); 572 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 573 CAM_REQ_INPROG) { 574 xpt_done(pccb); 575 splx(actionflags); 576 return; 577 } 578 pDCB = &pACB->DCBarray[target_id][target_lun]; 579 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 580 pACB->scan_devices[target_id][target_lun] = 1; 581 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 582 target_id, target_lun); 583 } 584 /* 585 * Assign an SRB and connect it with this ccb. 586 */ 587 pSRB = trm_GetSRB(pACB); 588 if (!pSRB) { 589 /* Freeze SIMQ */ 590 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 591 xpt_done(pccb); 592 splx(actionflags); 593 return; 594 } 595 pSRB->pSRBDCB = pDCB; 596 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 597 pccb->ccb_h.ccb_trmacb_ptr = pACB; 598 pSRB->pccb = pccb; 599 pSRB->ScsiCmdLen = pcsio->cdb_len; 600 /* 601 * move layer of CAM command block to layer of SCSI 602 * Request Block for SCSI processor command doing 603 */ 604 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 605 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 606 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 607 ,pcsio->cdb_len); 608 } else { 609 pccb->ccb_h.status = CAM_REQ_INVALID; 610 pSRB->pNextSRB = pACB->pFreeSRB; 611 pACB->pFreeSRB= pSRB; 612 xpt_done(pccb); 613 splx(actionflags); 614 return; 615 } 616 } else 617 bcopy(pcsio->cdb_io.cdb_bytes, 618 pSRB->CmdBlock, pcsio->cdb_len); 619 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 620 != CAM_DIR_NONE) { 621 if ((pccb->ccb_h.flags & 622 CAM_SCATTER_VALID) == 0) { 623 if ((pccb->ccb_h.flags 624 & CAM_DATA_PHYS) == 0) { 625 int vmflags; 626 int error; 627 628 vmflags = splsoftvm(); 629 error = bus_dmamap_load( 630 pACB->buffer_dmat, 631 pSRB->dmamap, 632 pcsio->data_ptr, 633 pcsio->dxfer_len, 634 trm_ExecuteSRB, 635 pSRB, 636 0); 637 if (error == EINPROGRESS) { 638 xpt_freeze_simq( 639 pACB->psim, 640 1); 641 pccb->ccb_h.status |= 642 CAM_RELEASE_SIMQ; 643 } 644 splx(vmflags); 645 } else { 646 struct bus_dma_segment seg; 647 648 /* Pointer to physical buffer */ 649 seg.ds_addr = 650 (bus_addr_t)pcsio->data_ptr; 651 seg.ds_len = pcsio->dxfer_len; 652 trm_ExecuteSRB(pSRB, &seg, 1, 653 0); 654 } 655 } else { 656 /* CAM_SCATTER_VALID */ 657 struct bus_dma_segment *segs; 658 659 if ((pccb->ccb_h.flags & 660 CAM_SG_LIST_PHYS) == 0 || 661 (pccb->ccb_h.flags 662 & CAM_DATA_PHYS) != 0) { 663 pSRB->pNextSRB = pACB->pFreeSRB; 664 pACB->pFreeSRB = pSRB; 665 pccb->ccb_h.status = 666 CAM_PROVIDE_FAIL; 667 xpt_done(pccb); 668 splx(actionflags); 669 return; 670 } 671 672 /* cam SG list is physical, 673 * cam data is virtual 674 */ 675 segs = (struct bus_dma_segment *) 676 pcsio->data_ptr; 677 trm_ExecuteSRB(pSRB, segs, 678 pcsio->sglist_cnt, 1); 679 } /* CAM_SCATTER_VALID */ 680 } else 681 trm_ExecuteSRB(pSRB, NULL, 0, 0); 682 } 683 break; 684 case XPT_GDEV_TYPE: 685 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 686 pccb->ccb_h.status = CAM_REQ_INVALID; 687 xpt_done(pccb); 688 break; 689 case XPT_GDEVLIST: 690 TRM_DPRINTF(" XPT_GDEVLIST \n"); 691 pccb->ccb_h.status = CAM_REQ_INVALID; 692 xpt_done(pccb); 693 break; 694 /* 695 * Path routing inquiry 696 * Path Inquiry CCB 697 */ 698 case XPT_PATH_INQ: { 699 struct ccb_pathinq *cpi = &pccb->cpi; 700 701 TRM_DPRINTF(" XPT_PATH_INQ \n"); 702 cpi->version_num = 1; 703 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 704 cpi->target_sprt = 0; 705 cpi->hba_misc = 0; 706 cpi->hba_eng_cnt = 0; 707 cpi->max_target = 15 ; 708 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 709 cpi->initiator_id = pACB->AdaptSCSIID; 710 cpi->bus_id = cam_sim_bus(psim); 711 cpi->base_transfer_speed = 3300; 712 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 713 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 714 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 715 cpi->unit_number = cam_sim_unit(psim); 716 cpi->ccb_h.status = CAM_REQ_CMP; 717 xpt_done(pccb); 718 } 719 break; 720 /* 721 * Release a frozen SIM queue 722 * Release SIM Queue 723 */ 724 case XPT_REL_SIMQ: 725 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 726 pccb->ccb_h.status = CAM_REQ_INVALID; 727 xpt_done(pccb); 728 break; 729 /* 730 * Set Asynchronous Callback Parameters 731 * Set Asynchronous Callback CCB 732 */ 733 case XPT_SASYNC_CB: 734 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 735 pccb->ccb_h.status = CAM_REQ_INVALID; 736 xpt_done(pccb); 737 break; 738 /* 739 * Set device type information 740 * Set Device Type CCB 741 */ 742 case XPT_SDEV_TYPE: 743 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 744 pccb->ccb_h.status = CAM_REQ_INVALID; 745 xpt_done(pccb); 746 break; 747 /* 748 * (Re)Scan the SCSI Bus 749 * Rescan the given bus, or bus/target/lun 750 */ 751 case XPT_SCAN_BUS: 752 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 753 pccb->ccb_h.status = CAM_REQ_INVALID; 754 xpt_done(pccb); 755 break; 756 /* 757 * Get EDT entries matching the given pattern 758 */ 759 case XPT_DEV_MATCH: 760 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 761 pccb->ccb_h.status = CAM_REQ_INVALID; 762 xpt_done(pccb); 763 break; 764 /* 765 * Turn on debugging for a bus, target or lun 766 */ 767 case XPT_DEBUG: 768 TRM_DPRINTF(" XPT_DEBUG \n"); 769 pccb->ccb_h.status = CAM_REQ_INVALID; 770 xpt_done(pccb); 771 break; 772 /* 773 * XPT_ABORT = 0x10, Abort the specified CCB 774 * Abort XPT request CCB 775 */ 776 case XPT_ABORT: 777 TRM_DPRINTF(" XPT_ABORT \n"); 778 pccb->ccb_h.status = CAM_REQ_INVALID; 779 xpt_done(pccb); 780 break; 781 /* 782 * Reset the specified SCSI bus 783 * Reset SCSI Bus CCB 784 */ 785 case XPT_RESET_BUS: { 786 int i; 787 788 TRM_DPRINTF(" XPT_RESET_BUS \n"); 789 trm_reset(pACB); 790 pACB->ACBFlag=0; 791 for (i=0; i<500; i++) 792 DELAY(1000); 793 pccb->ccb_h.status = CAM_REQ_CMP; 794 xpt_done(pccb); 795 } 796 break; 797 /* 798 * Bus Device Reset the specified SCSI device 799 * Reset SCSI Device CCB 800 */ 801 case XPT_RESET_DEV: 802 /* 803 * Don't (yet?) support vendor 804 * specific commands. 805 */ 806 TRM_DPRINTF(" XPT_RESET_DEV \n"); 807 pccb->ccb_h.status = CAM_REQ_INVALID; 808 xpt_done(pccb); 809 break; 810 /* 811 * Terminate the I/O process 812 * Terminate I/O Process Request CCB 813 */ 814 case XPT_TERM_IO: 815 TRM_DPRINTF(" XPT_TERM_IO \n"); 816 pccb->ccb_h.status = CAM_REQ_INVALID; 817 xpt_done(pccb); 818 break; 819 /* 820 * Scan Logical Unit 821 */ 822 case XPT_SCAN_LUN: 823 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 824 pccb->ccb_h.status = CAM_REQ_INVALID; 825 xpt_done(pccb); 826 break; 827 828 /* 829 * Get/Set transfer rate/width/disconnection/tag queueing 830 * settings 831 * (GET) default/user transfer settings for the target 832 */ 833 case XPT_GET_TRAN_SETTINGS: { 834 struct ccb_trans_settings *cts; 835 int intflag; 836 struct trm_transinfo *tinfo; 837 PDCB pDCB; 838 839 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 840 cts = &pccb->cts; 841 pDCB = &pACB->DCBarray[target_id][target_lun]; 842 intflag = splcam(); 843 /* 844 * disable interrupt 845 */ 846 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 847 /* current transfer settings */ 848 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 849 cts->flags = CCB_TRANS_DISC_ENB; 850 else 851 cts->flags = 0;/* no tag & disconnect */ 852 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 853 cts->flags |= CCB_TRANS_TAG_ENB; 854 tinfo = &pDCB->tinfo.current; 855 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 856 cts->flags); 857 } else { 858 /* default(user) transfer settings */ 859 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 860 cts->flags = CCB_TRANS_DISC_ENB; 861 else 862 cts->flags = 0; 863 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 864 cts->flags |= CCB_TRANS_TAG_ENB; 865 tinfo = &pDCB->tinfo.user; 866 TRM_DPRINTF("USER: cts->flags= %2x \n", 867 cts->flags); 868 } 869 cts->sync_period = tinfo->period; 870 cts->sync_offset = tinfo->offset; 871 cts->bus_width = tinfo->width; 872 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 873 pDCB->SyncPeriod); 874 TRM_DPRINTF("period: %d \n", tinfo->period); 875 TRM_DPRINTF("offset: %d \n", tinfo->offset); 876 TRM_DPRINTF("width: %d \n", tinfo->width); 877 878 splx(intflag); 879 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 880 CCB_TRANS_SYNC_OFFSET_VALID | 881 CCB_TRANS_BUS_WIDTH_VALID | 882 CCB_TRANS_DISC_VALID | 883 CCB_TRANS_TQ_VALID; 884 pccb->ccb_h.status = CAM_REQ_CMP; 885 xpt_done(pccb); 886 } 887 break; 888 /* 889 * Get/Set transfer rate/width/disconnection/tag queueing 890 * settings 891 * (Set) transfer rate/width negotiation settings 892 */ 893 case XPT_SET_TRAN_SETTINGS: { 894 struct ccb_trans_settings *cts; 895 u_int update_type; 896 int intflag; 897 PDCB pDCB; 898 899 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 900 cts = &pccb->cts; 901 update_type = 0; 902 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 903 update_type |= TRM_TRANS_GOAL; 904 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 905 update_type |= TRM_TRANS_USER; 906 intflag = splcam(); 907 pDCB = &pACB->DCBarray[target_id][target_lun]; 908 909 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 910 /*ccb disc enables */ 911 if (update_type & TRM_TRANS_GOAL) { 912 if ((cts->flags & CCB_TRANS_DISC_ENB) 913 != 0) 914 pDCB->tinfo.disc_tag 915 |= TRM_CUR_DISCENB; 916 else 917 pDCB->tinfo.disc_tag &= 918 ~TRM_CUR_DISCENB; 919 } 920 if (update_type & TRM_TRANS_USER) { 921 if ((cts->flags & CCB_TRANS_DISC_ENB) 922 != 0) 923 pDCB->tinfo.disc_tag 924 |= TRM_USR_DISCENB; 925 else 926 pDCB->tinfo.disc_tag &= 927 ~TRM_USR_DISCENB; 928 } 929 } 930 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 931 /* if ccb tag q active */ 932 if (update_type & TRM_TRANS_GOAL) { 933 if ((cts->flags & CCB_TRANS_TAG_ENB) 934 != 0) 935 pDCB->tinfo.disc_tag |= 936 TRM_CUR_TAGENB; 937 else 938 pDCB->tinfo.disc_tag &= 939 ~TRM_CUR_TAGENB; 940 } 941 if (update_type & TRM_TRANS_USER) { 942 if ((cts->flags & CCB_TRANS_TAG_ENB) 943 != 0) 944 pDCB->tinfo.disc_tag |= 945 TRM_USR_TAGENB; 946 else 947 pDCB->tinfo.disc_tag &= 948 ~TRM_USR_TAGENB; 949 } 950 } 951 /* Minimum sync period factor */ 952 953 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 954 /* if ccb sync active */ 955 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 956 if ((cts->sync_period != 0) && 957 (cts->sync_period < 125)) 958 cts->sync_period = 125; 959 /* 1/(125*4) minsync 2 MByte/sec */ 960 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 961 != 0) { 962 if (cts->sync_offset == 0) 963 cts->sync_period = 0; 964 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 965 if (cts->sync_offset > 15) 966 cts->sync_offset = 15; 967 } 968 } 969 if ((update_type & TRM_TRANS_USER) != 0) { 970 pDCB->tinfo.user.period = cts->sync_period; 971 pDCB->tinfo.user.offset = cts->sync_offset; 972 pDCB->tinfo.user.width = cts->bus_width; 973 } 974 if ((update_type & TRM_TRANS_GOAL) != 0) { 975 pDCB->tinfo.goal.period = cts->sync_period; 976 pDCB->tinfo.goal.offset = cts->sync_offset; 977 pDCB->tinfo.goal.width = cts->bus_width; 978 } 979 splx(intflag); 980 pccb->ccb_h.status = CAM_REQ_CMP; 981 xpt_done(pccb); 982 break; 983 } 984 /* 985 * Calculate the geometry parameters for a device give 986 * the sector size and volume size. 987 */ 988 case XPT_CALC_GEOMETRY: 989 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 990 cam_calc_geometry(&pccb->ccg, /*extended*/1); 991 xpt_done(pccb); 992 break; 993 case XPT_ENG_INQ: 994 TRM_DPRINTF(" XPT_ENG_INQ \n"); 995 pccb->ccb_h.status = CAM_REQ_INVALID; 996 xpt_done(pccb); 997 break; 998 /* 999 * HBA execute engine request 1000 * This structure must match SCSIIO size 1001 */ 1002 case XPT_ENG_EXEC: 1003 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1004 pccb->ccb_h.status = CAM_REQ_INVALID; 1005 xpt_done(pccb); 1006 break; 1007 /* 1008 * XPT_EN_LUN = 0x30, Enable LUN as a target 1009 * Target mode structures. 1010 */ 1011 case XPT_EN_LUN: 1012 /* 1013 * Don't (yet?) support vendor 1014 * specific commands. 1015 */ 1016 TRM_DPRINTF(" XPT_EN_LUN \n"); 1017 pccb->ccb_h.status = CAM_REQ_INVALID; 1018 xpt_done(pccb); 1019 break; 1020 /* 1021 * Execute target I/O request 1022 */ 1023 case XPT_TARGET_IO: 1024 /* 1025 * Don't (yet?) support vendor 1026 * specific commands. 1027 */ 1028 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1029 pccb->ccb_h.status = CAM_REQ_INVALID; 1030 xpt_done(pccb); 1031 break; 1032 /* 1033 * Accept Host Target Mode CDB 1034 */ 1035 case XPT_ACCEPT_TARGET_IO: 1036 /* 1037 * Don't (yet?) support vendor 1038 * specific commands. 1039 */ 1040 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1041 pccb->ccb_h.status = CAM_REQ_INVALID; 1042 xpt_done(pccb); 1043 break; 1044 /* 1045 * Continue Host Target I/O Connection 1046 */ 1047 case XPT_CONT_TARGET_IO: 1048 /* 1049 * Don't (yet?) support vendor 1050 * specific commands. 1051 */ 1052 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1053 pccb->ccb_h.status = CAM_REQ_INVALID; 1054 xpt_done(pccb); 1055 break; 1056 /* 1057 * Notify Host Target driver of event 1058 */ 1059 case XPT_IMMED_NOTIFY: 1060 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1061 pccb->ccb_h.status = CAM_REQ_INVALID; 1062 xpt_done(pccb); 1063 break; 1064 /* 1065 * Acknowledgement of event 1066 */ 1067 case XPT_NOTIFY_ACK: 1068 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1069 pccb->ccb_h.status = CAM_REQ_INVALID; 1070 xpt_done(pccb); 1071 break; 1072 /* 1073 * XPT_VUNIQUE = 0x80 1074 */ 1075 case XPT_VUNIQUE: 1076 pccb->ccb_h.status = CAM_REQ_INVALID; 1077 xpt_done(pccb); 1078 break; 1079 default: 1080 pccb->ccb_h.status = CAM_REQ_INVALID; 1081 xpt_done(pccb); 1082 break; 1083 } 1084 splx(actionflags); 1085} 1086 1087static void 1088trm_poll(struct cam_sim *psim) 1089{ 1090 1091} 1092 1093static void 1094trm_ResetDevParam(PACB pACB) 1095{ 1096 PDCB pDCB, pdcb; 1097 PNVRAMTYPE pEEpromBuf; 1098 u_int8_t PeriodIndex; 1099 1100 pDCB = pACB->pLinkDCB; 1101 if (pDCB == NULL) 1102 return; 1103 pdcb = pDCB; 1104 do { 1105 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1106 pDCB->SyncPeriod = 0; 1107 pDCB->SyncOffset = 0; 1108 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1109 pDCB->DevMode = 1110 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1111 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1112 PeriodIndex = 1113 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1114 if (pACB->AdaptType == 1) /* is U2? */ 1115 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1116 else 1117 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1118 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1119 (pACB->Config & HCC_WIDE_CARD)) 1120 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1121 pDCB = pDCB->pNextDCB; 1122 } 1123 while (pdcb != pDCB); 1124} 1125 1126static void 1127trm_RecoverSRB(PACB pACB) 1128{ 1129 PDCB pDCB, pdcb; 1130 PSRB psrb, psrb2; 1131 u_int16_t cnt, i; 1132 1133 pDCB = pACB->pLinkDCB; 1134 if (pDCB == NULL) 1135 return; 1136 pdcb = pDCB; 1137 do { 1138 cnt = pdcb->GoingSRBCnt; 1139 psrb = pdcb->pGoingSRB; 1140 for (i = 0; i < cnt; i++) { 1141 psrb2 = psrb; 1142 psrb = psrb->pNextSRB; 1143 if (pdcb->pWaitingSRB) { 1144 psrb2->pNextSRB = pdcb->pWaitingSRB; 1145 pdcb->pWaitingSRB = psrb2; 1146 } else { 1147 pdcb->pWaitingSRB = psrb2; 1148 pdcb->pWaitingLastSRB = psrb2; 1149 psrb2->pNextSRB = NULL; 1150 } 1151 } 1152 pdcb->GoingSRBCnt = 0; 1153 pdcb->pGoingSRB = NULL; 1154 pdcb = pdcb->pNextDCB; 1155 } 1156 while (pdcb != pDCB); 1157} 1158 1159static void 1160trm_reset(PACB pACB) 1161{ 1162 int intflag; 1163 u_int16_t i; 1164 1165 TRM_DPRINTF("trm: RESET"); 1166 intflag = splcam(); 1167 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1168 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1169 1170 trm_ResetSCSIBus(pACB); 1171 for (i = 0; i < 500; i++) 1172 DELAY(1000); 1173 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1174 /* Enable DMA interrupt */ 1175 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1176 /* Clear DMA FIFO */ 1177 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1178 /* Clear SCSI FIFO */ 1179 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1180 trm_ResetDevParam(pACB); 1181 trm_DoingSRB_Done(pACB); 1182 pACB->pActiveDCB = NULL; 1183 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1184 trm_DoWaitingSRB(pACB); 1185 /* Tell the XPT layer that a bus reset occured */ 1186 if (pACB->ppath != NULL) 1187 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1188 splx(intflag); 1189 return; 1190} 1191 1192static u_int16_t 1193trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1194{ 1195 u_int16_t return_code; 1196 u_int8_t scsicommand, i,command,identify_message; 1197 u_int8_t * ptr; 1198 union ccb *pccb; 1199 struct ccb_scsiio *pcsio; 1200 1201 pccb = pSRB->pccb; 1202 pcsio = &pccb->csio; 1203 1204 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1205 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1206 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1207 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1208 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1209 /* Flush FIFO */ 1210 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1211 1212 identify_message = pDCB->IdentifyMsg; 1213 1214 if ((pSRB->CmdBlock[0] == INQUIRY) || 1215 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1216 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1217 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1218 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1219 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1220 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1221 if (!(pDCB->IdentifyMsg & 7) || 1222 (pSRB->CmdBlock[0] != INQUIRY)) { 1223 scsicommand = SCMD_SEL_ATNSTOP; 1224 pSRB->SRBState = SRB_MSGOUT; 1225 goto polling; 1226 } 1227 } 1228 /* 1229 * Send identify message 1230 */ 1231 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1232 scsicommand = SCMD_SEL_ATN; 1233 pSRB->SRBState = SRB_START_; 1234 } else { 1235 /* not inquiry,request sense,auto request sense */ 1236 /* 1237 * Send identify message 1238 */ 1239 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1240 scsicommand = SCMD_SEL_ATN; 1241 pSRB->SRBState = SRB_START_; 1242 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1243 /* Send Tag message */ 1244 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1245 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1246 scsicommand = SCMD_SEL_ATN3; 1247 } 1248 } 1249polling: 1250 /* 1251 * Send CDB ..command block ......... 1252 */ 1253 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1254 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1255 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1256 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1257 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1258 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1259 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1260 } else { 1261 ptr = (u_int8_t *) pSRB->CmdBlock; 1262 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1263 command = *ptr++; 1264 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1265 } 1266 } 1267 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1268 /* 1269 * If trm_StartSCSI return 1 : 1270 * current interrupt status is interrupt disreenable 1271 * It's said that SCSI processor has more one SRB need to do, 1272 * SCSI processor has been occupied by one SRB. 1273 */ 1274 pSRB->SRBState = SRB_READY; 1275 return_code = 1; 1276 } else { 1277 /* 1278 * If trm_StartSCSI return 0 : 1279 * current interrupt status is interrupt enable 1280 * It's said that SCSI processor is unoccupied 1281 */ 1282 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1283 pACB->pActiveDCB = pDCB; 1284 pDCB->pActiveSRB = pSRB; 1285 return_code = 0; 1286 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1287 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1288 /* 1289 * SCSI cammand 1290 */ 1291 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1292 } 1293 return (return_code); 1294} 1295 1296static void 1297trm_Interrupt(vpACB) 1298void *vpACB; 1299{ 1300 PACB pACB; 1301 PDCB pDCB; 1302 PSRB pSRB; 1303 u_int16_t phase; 1304 void (*stateV)(PACB, PSRB, u_int16_t *); 1305 u_int16_t scsi_status=0; 1306 u_int8_t scsi_intstatus; 1307 1308 pACB = vpACB; 1309 1310 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1311 if (!(scsi_status & SCSIINTERRUPT)) { 1312 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1313 return; 1314 } 1315 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1316 1317 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1318 1319 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1320 1321 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1322 trm_Disconnect(pACB); 1323 return; 1324 } 1325 1326 if (scsi_intstatus & INT_RESELECTED) { 1327 trm_Reselect(pACB); 1328 return; 1329 } 1330 if (scsi_intstatus & INT_SCSIRESET) { 1331 trm_ScsiRstDetect(pACB); 1332 return; 1333 } 1334 1335 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1336 pDCB = pACB->pActiveDCB; 1337 pSRB = pDCB->pActiveSRB; 1338 if (pDCB) { 1339 if (pDCB->DCBFlag & ABORT_DEV_) 1340 trm_EnableMsgOutAbort1(pACB, pSRB); 1341 } 1342 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1343 stateV = (void *) trm_SCSI_phase0[phase]; 1344 stateV(pACB, pSRB, &scsi_status); 1345 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1346 /* phase:0,1,2,3,4,5,6,7 */ 1347 phase = (u_int16_t) scsi_status & PHASEMASK; 1348 stateV = (void *) trm_SCSI_phase1[phase]; 1349 stateV(pACB, pSRB, &scsi_status); 1350 } 1351} 1352 1353static void 1354trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1355{ 1356 1357 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1358 *pscsi_status = PH_BUS_FREE; 1359 /*.. initial phase*/ 1360} 1361 1362static void 1363trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1364{ 1365 u_int8_t bval; 1366 u_int16_t i, cnt; 1367 u_int8_t * ptr; 1368 PDCB pDCB; 1369 1370 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1371 pDCB = pACB->pActiveDCB; 1372 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1373 cnt = pSRB->MsgCnt; 1374 if (cnt) { 1375 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1376 for (i = 0; i < cnt; i++) { 1377 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1378 ptr++; 1379 } 1380 pSRB->MsgCnt = 0; 1381 if ((pDCB->DCBFlag & ABORT_DEV_) && 1382 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1383 pSRB->SRBState = SRB_ABORT_SENT; 1384 } 1385 } else { 1386 bval = MSG_ABORT; 1387 if ((pSRB->CmdBlock[0] == INQUIRY) || 1388 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1389 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1390 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1391 goto mop1; 1392 } 1393 } 1394 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1395 } 1396 } else { 1397mop1: /* message out phase */ 1398 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1399 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1400 /* 1401 * WIDE DATA TRANSFER REQUEST code (03h) 1402 */ 1403 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1404 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1405 TRMREG_SCSI_FIFO); 1406 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1407 /* (01h) */ 1408 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1409 /* Message length (02h) */ 1410 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1411 /* wide data xfer (03h) */ 1412 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1413 /* width:0(8bit),1(16bit),2(32bit) */ 1414 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1415 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1416 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1417 /* 1418 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1419 */ 1420 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1421 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1422 TRMREG_SCSI_FIFO); 1423 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1424 /* (01h) */ 1425 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1426 /* Message length (03h) */ 1427 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1428 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1429 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1430 /* Transfer peeriod factor */ 1431 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1432 TRMREG_SCSI_FIFO); 1433 /* REQ/ACK offset */ 1434 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1435 } 1436 } 1437 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1438 /* it's important for atn stop */ 1439 /* 1440 * SCSI cammand 1441 */ 1442 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1443} 1444 1445static void 1446trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1447{ 1448 1449} 1450 1451static void 1452trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1453{ 1454 PDCB pDCB; 1455 u_int8_t * ptr; 1456 u_int16_t i, cnt; 1457 union ccb *pccb; 1458 struct ccb_scsiio *pcsio; 1459 1460 pccb = pSRB->pccb; 1461 pcsio = &pccb->csio; 1462 1463 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1464 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1465 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1466 ptr = (u_int8_t *) pSRB->CmdBlock; 1467 for (i = 0; i < cnt; i++) { 1468 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1469 ptr++; 1470 } 1471 } else { 1472 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1473 pDCB = pACB->pActiveDCB; 1474 /* target id */ 1475 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1476 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1477 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1478 /* sizeof(struct scsi_sense_data) */ 1479 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1480 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1481 } 1482 pSRB->SRBState = SRB_COMMAND; 1483 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1484 /* it's important for atn stop*/ 1485 /* 1486 * SCSI cammand 1487 */ 1488 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1489} 1490 1491static void 1492trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1493{ 1494 PDCB pDCB; 1495 u_int8_t TempDMAstatus,SGIndexTemp; 1496 u_int16_t scsi_status; 1497 PSEG pseg; 1498 u_long TempSRBXferredLength,dLeftCounter=0; 1499 1500 pDCB = pSRB->pSRBDCB; 1501 scsi_status = *pscsi_status; 1502 1503 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1504 if (scsi_status & PARITYERROR) 1505 pSRB->SRBStatus |= PARITY_ERROR; 1506 if (!(scsi_status & SCSIXFERDONE)) { 1507 /* 1508 * when data transfer from DMA FIFO to SCSI FIFO 1509 * if there was some data left in SCSI FIFO 1510 */ 1511 dLeftCounter = (u_long) 1512 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1513 if (pDCB->SyncPeriod & WIDE_SYNC) { 1514 /* 1515 * if WIDE scsi SCSI FIFOCNT unit is word 1516 * so need to * 2 1517 */ 1518 dLeftCounter <<= 1; 1519 } 1520 } 1521 /* 1522 * caculate all the residue data that not yet tranfered 1523 * SCSI transfer counter + left in SCSI FIFO data 1524 * 1525 * .....TRM_SCSI_COUNTER (24bits) 1526 * The counter always decrement by one for every SCSI byte 1527 *transfer. 1528 * .....TRM_SCSI_FIFOCNT (5bits) 1529 * The counter is SCSI FIFO offset counter 1530 */ 1531 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1532 if (dLeftCounter == 1) { 1533 dLeftCounter = 0; 1534 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1535 } 1536 if ((dLeftCounter == 0) || 1537 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1538 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1539 while (!(TempDMAstatus & DMAXFERCOMP)) { 1540 TempDMAstatus = 1541 trm_reg_read8(TRMREG_DMA_STATUS); 1542 } 1543 pSRB->SRBTotalXferLength = 0; 1544 } else { 1545 /* Update SG list */ 1546 /* 1547 * if transfer not yet complete 1548 * there were some data residue in SCSI FIFO or 1549 * SCSI transfer counter not empty 1550 */ 1551 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1552 /* 1553 * data that had transferred length 1554 */ 1555 TempSRBXferredLength = 1556 pSRB->SRBTotalXferLength - dLeftCounter; 1557 /* 1558 * next time to be transferred length 1559 */ 1560 pSRB->SRBTotalXferLength = dLeftCounter; 1561 /* 1562 * parsing from last time disconnect SRBSGIndex 1563 */ 1564 pseg = 1565 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1566 for (SGIndexTemp = pSRB->SRBSGIndex; 1567 SGIndexTemp < pSRB->SRBSGCount; 1568 SGIndexTemp++) { 1569 /* 1570 * find last time which SG transfer be 1571 * disconnect 1572 */ 1573 if (TempSRBXferredLength >= 1574 pseg->length) 1575 TempSRBXferredLength -= 1576 pseg->length; 1577 else { 1578 /* 1579 * update last time disconnected SG 1580 * list 1581 */ 1582 pseg->length -= 1583 TempSRBXferredLength; 1584 /* residue data length */ 1585 pseg->address += 1586 TempSRBXferredLength; 1587 /* residue data pointer */ 1588 pSRB->SRBSGIndex = SGIndexTemp; 1589 break; 1590 } 1591 pseg++; 1592 } 1593 } 1594 } 1595 } 1596 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1597} 1598 1599 1600static void 1601trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1602{ 1603 u_int16_t ioDir; 1604 /* 1605 * do prepare befor transfer when data out phase 1606 */ 1607 1608 ioDir = XFERDATAOUT; 1609 trm_DataIO_transfer(pACB, pSRB, ioDir); 1610} 1611 1612static void 1613trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1614{ 1615 u_int8_t TempDMAstatus, SGIndexTemp; 1616 u_int16_t scsi_status; 1617 PSEG pseg; 1618 u_long TempSRBXferredLength,dLeftCounter = 0; 1619 1620 scsi_status = *pscsi_status; 1621 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1622 if (scsi_status & PARITYERROR) 1623 pSRB->SRBStatus |= PARITY_ERROR; 1624 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1625 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1626 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1627 while (!(TempDMAstatus & DMAXFERCOMP)) 1628 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1629 pSRB->SRBTotalXferLength = 0; 1630 } else { 1631 /* 1632 * parsing the case: 1633 * when a transfer not yet complete 1634 * but be disconnected by uper layer 1635 * if transfer not yet complete 1636 * there were some data residue in SCSI FIFO or 1637 * SCSI transfer counter not empty 1638 */ 1639 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1640 /* 1641 * data that had transferred length 1642 */ 1643 TempSRBXferredLength = 1644 pSRB->SRBTotalXferLength - dLeftCounter; 1645 /* 1646 * next time to be transferred length 1647 */ 1648 pSRB->SRBTotalXferLength = dLeftCounter; 1649 /* 1650 * parsing from last time disconnect SRBSGIndex 1651 */ 1652 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1653 for (SGIndexTemp = pSRB->SRBSGIndex; 1654 SGIndexTemp < pSRB->SRBSGCount; 1655 SGIndexTemp++) { 1656 /* 1657 * find last time which SG transfer be disconnect 1658 */ 1659 if (TempSRBXferredLength >= pseg->length) 1660 TempSRBXferredLength -= pseg->length; 1661 else { 1662 /* 1663 * update last time disconnected SG list 1664 */ 1665 pseg->length -= TempSRBXferredLength; 1666 /* residue data length */ 1667 pseg->address += TempSRBXferredLength; 1668 /* residue data pointer */ 1669 pSRB->SRBSGIndex = SGIndexTemp; 1670 break; 1671 } 1672 pseg++; 1673 } 1674 } 1675 } 1676 } 1677} 1678 1679static void 1680trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1681{ 1682 u_int16_t ioDir; 1683 /* 1684 * do prepare befor transfer when data in phase 1685 */ 1686 1687 ioDir = XFERDATAIN; 1688 trm_DataIO_transfer(pACB, pSRB, ioDir); 1689} 1690 1691static void 1692trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1693{ 1694 u_int8_t bval; 1695 PDCB pDCB; 1696 1697 pDCB = pSRB->pSRBDCB; 1698 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1699 if (pSRB->SRBTotalXferLength != 0) { 1700 /* 1701 * load what physical address of Scatter/Gather list 1702 table want to be transfer 1703 */ 1704 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1705 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1706 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1707 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1708 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1709 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1710 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1711 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1712 1713 pSRB->SRBState = SRB_DATA_XFER; 1714 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1715 trm_reg_write32( 1716 (pSRB->SRBSGPhyAddr + 1717 ((u_long)pSRB->SRBSGIndex << 3)), 1718 TRMREG_DMA_XLOWADDR); 1719 /* 1720 * load how many bytes in the Scatter/Gather 1721 * list table 1722 */ 1723 trm_reg_write32( 1724 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1725 TRMREG_DMA_XCNT); 1726 /* 1727 * load total transfer length (24bits) max value 1728 * 16Mbyte 1729 */ 1730 trm_reg_write32(pSRB->SRBTotalXferLength, 1731 TRMREG_SCSI_COUNTER); 1732 /* Start DMA transfer */ 1733 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1734 /* Start SCSI transfer */ 1735 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1736 /* it's important for atn stop */ 1737 /* 1738 * SCSI cammand 1739 */ 1740 bval = (ioDir == XFERDATAOUT) ? 1741 SCMD_DMA_OUT : SCMD_DMA_IN; 1742 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1743 } else { 1744 /* xfer pad */ 1745 if (pSRB->SRBSGCount) { 1746 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1747 pSRB->SRBStatus |= OVER_RUN; 1748 } 1749 if (pDCB->SyncPeriod & WIDE_SYNC) 1750 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1751 else 1752 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1753 if (ioDir == XFERDATAOUT) 1754 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1755 else 1756 trm_reg_read16(TRMREG_SCSI_FIFO); 1757 pSRB->SRBState |= SRB_XFERPAD; 1758 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1759 /* it's important for atn stop */ 1760 /* 1761 * SCSI cammand 1762 */ 1763 bval = (ioDir == XFERDATAOUT) ? 1764 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1765 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1766 } 1767 } 1768} 1769 1770static void 1771trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1772{ 1773 1774 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1775 pSRB->SRBState = SRB_COMPLETED; 1776 *pscsi_status = PH_BUS_FREE; 1777 /*.. initial phase*/ 1778 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1779 /* it's important for atn stop */ 1780 /* 1781 * SCSI cammand 1782 */ 1783 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1784} 1785 1786 1787 1788static void 1789trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1790{ 1791 1792 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1793 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1794 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1795 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1796 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1797 } else { 1798 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1799 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1800 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1801 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1802 } 1803 pSRB->SRBState = SRB_STATUS; 1804 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1805 /* it's important for atn stop */ 1806 /* 1807 * SCSI cammand 1808 */ 1809 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1810} 1811 1812/* 1813 *scsiiom 1814 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1815 * stateV = (void *) trm_SCSI_phase0[phase] 1816 * if phase =7 1817 * extended message codes: 1818 * 1819 * code description 1820 * 1821 * 02h Reserved 1822 * 00h MODIFY DATA POINTER 1823 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1824 * 03h WIDE DATA TRANSFER REQUEST 1825 * 04h - 7Fh Reserved 1826 * 80h - FFh Vendor specific 1827 * 1828 */ 1829 1830static void 1831trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1832{ 1833 u_int8_t message_in_code,bIndex,message_in_tag_id; 1834 PDCB pDCB; 1835 PSRB pSRBTemp; 1836 1837 pDCB = pACB->pActiveDCB; 1838 1839 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1840 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1841 if (message_in_code == MSG_DISCONNECT) { 1842 pSRB->SRBState = SRB_DISCONNECT; 1843 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1844 /* it's important for atn stop */ 1845 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1846 /* 1847 * SCSI command 1848 */ 1849 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1850 return; 1851 } else if (message_in_code == MSG_SAVE_PTR) { 1852 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1853 /* it's important for atn stop */ 1854 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1855 /* 1856 * SCSI command 1857 */ 1858 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1859 return; 1860 } else if ((message_in_code == MSG_EXTENDED) || 1861 ((message_in_code >= MSG_SIMPLE_QTAG) && 1862 (message_in_code <= MSG_ORDER_QTAG))) { 1863 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1864 pSRB->MsgInBuf[0] = message_in_code; 1865 /* extended message (01h) */ 1866 pSRB->MsgCnt = 1; 1867 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1868 /* extended message length (n) */ 1869 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1870 /* it's important for atn stop */ 1871 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1872 /* 1873 * SCSI command 1874 */ 1875 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1876 return; 1877 } else if (message_in_code == MSG_REJECT_) { 1878 /* Reject message */ 1879 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1880 /* do wide nego reject */ 1881 pDCB = pSRB->pSRBDCB; 1882 pDCB->SyncMode |= WIDE_NEGO_DONE; 1883 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1884 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1885 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1886 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1887 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1888 /* Set ATN, in case ATN was clear */ 1889 pSRB->SRBState |= SRB_MSGOUT; 1890 trm_reg_write16( 1891 DO_SETATN, 1892 TRMREG_SCSI_CONTROL); 1893 } else { 1894 /* Clear ATN */ 1895 trm_reg_write16( 1896 DO_CLRATN, 1897 TRMREG_SCSI_CONTROL); 1898 } 1899 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1900 /* do sync nego reject */ 1901 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1902 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1903 pDCB = pSRB->pSRBDCB; 1904 pDCB->SyncMode &= 1905 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1906 pDCB->SyncPeriod = 0; 1907 pDCB->SyncOffset = 0; 1908 /* 1909 * 1910 * program SCSI control register 1911 * 1912 */ 1913 trm_reg_write8(pDCB->SyncPeriod, 1914 TRMREG_SCSI_SYNC); 1915 trm_reg_write8(pDCB->SyncOffset, 1916 TRMREG_SCSI_OFFSET); 1917 trm_SetXferRate(pACB,pSRB,pDCB); 1918 } 1919 } 1920 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1921 /* it's important for atn stop */ 1922 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1923 /* 1924 * SCSI command 1925 */ 1926 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1927 return; 1928 } else if (message_in_code == MSG_IGNOREWIDE) { 1929 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1930 trm_reg_read8(TRMREG_SCSI_FIFO); 1931 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1932 /* it's important for atn stop */ 1933 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1934 /* 1935 * SCSI command 1936 */ 1937 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1938 return; 1939 } else { 1940 /* Restore data pointer message */ 1941 /* Save data pointer message */ 1942 /* Completion message */ 1943 /* NOP message */ 1944 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1945 /* it's important for atn stop */ 1946 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1947 /* 1948 * SCSI command 1949 */ 1950 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1951 return; 1952 } 1953 } else { 1954 /* 1955 * Parsing incomming extented messages 1956 */ 1957 *pSRB->pMsgPtr = message_in_code; 1958 pSRB->MsgCnt++; 1959 pSRB->pMsgPtr++; 1960 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1961 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1962 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1963 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1964 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1965 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1966 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1967 /* 1968 * is QUEUE tag message : 1969 * 1970 * byte 0: 1971 * HEAD QUEUE TAG (20h) 1972 * ORDERED QUEUE TAG (21h) 1973 * SIMPLE QUEUE TAG (22h) 1974 * byte 1: 1975 * Queue tag (00h - FFh) 1976 */ 1977 if (pSRB->MsgCnt == 2) { 1978 pSRB->SRBState = 0; 1979 message_in_tag_id = pSRB->MsgInBuf[1]; 1980 pSRB = pDCB->pGoingSRB; 1981 pSRBTemp = pDCB->pGoingLastSRB; 1982 if (pSRB) { 1983 for (;;) { 1984 if (pSRB->TagNumber != 1985 message_in_tag_id) { 1986 if (pSRB == pSRBTemp) { 1987 goto mingx0; 1988 } 1989 pSRB = pSRB->pNextSRB; 1990 } else 1991 break; 1992 } 1993 if (pDCB->DCBFlag & ABORT_DEV_) { 1994 pSRB->SRBState = SRB_ABORT_SENT; 1995 trm_EnableMsgOutAbort1( 1996 pACB, pSRB); 1997 } 1998 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1999 TRM_DPRINTF("SRB not yet disconnect........ \n "); 2000 goto mingx0; 2001 } 2002 pDCB->pActiveSRB = pSRB; 2003 pSRB->SRBState = SRB_DATA_XFER; 2004 } else { 2005mingx0: 2006 pSRB = &pACB->TmpSRB; 2007 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2008 pDCB->pActiveSRB = pSRB; 2009 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2010 trm_EnableMsgOutAbort2( 2011 pACB, 2012 pSRB); 2013 } 2014 } 2015 *pscsi_status = PH_BUS_FREE; 2016 /* .. initial phase */ 2017 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2018 /* it's important for atn stop */ 2019 /* 2020 * SCSI command 2021 */ 2022 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2023 return; 2024 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2025 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2026 /* 2027 * is Wide data xfer Extended message : 2028 * ====================================== 2029 * WIDE DATA TRANSFER REQUEST 2030 * ====================================== 2031 * byte 0 : Extended message (01h) 2032 * byte 1 : Extended message length (02h) 2033 * byte 2 : WIDE DATA TRANSFER code (03h) 2034 * byte 3 : Transfer width exponent 2035 */ 2036 pDCB = pSRB->pSRBDCB; 2037 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2038 if ((pSRB->MsgInBuf[1] != 2)) { 2039 /* Length is wrong, reject it */ 2040 pDCB->SyncMode &= 2041 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2042 pSRB->MsgCnt = 1; 2043 pSRB->MsgInBuf[0] = MSG_REJECT_; 2044 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2045 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2046 /* it's important for atn stop */ 2047 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2048 /* 2049 * SCSI command 2050 */ 2051 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2052 return; 2053 } 2054 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2055 /* Do wide negoniation */ 2056 if (pSRB->MsgInBuf[3] > 2) { 2057 /* > 32 bit */ 2058 /* reject_msg: */ 2059 pDCB->SyncMode &= 2060 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2061 pSRB->MsgCnt = 1; 2062 pSRB->MsgInBuf[0] = MSG_REJECT_; 2063 trm_reg_write16(DO_SETATN, 2064 TRMREG_SCSI_CONTROL); 2065 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2066 /* it's important for atn stop */ 2067 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2068 /* 2069 * SCSI command 2070 */ 2071 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2072 return; 2073 } 2074 if (pSRB->MsgInBuf[3] == 2) { 2075 pSRB->MsgInBuf[3] = 1; 2076 /* do 16 bits */ 2077 } else { 2078 if (!(pDCB->SyncMode 2079 & WIDE_NEGO_DONE)) { 2080 pSRB->SRBState &= 2081 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2082 pDCB->SyncMode |= 2083 WIDE_NEGO_DONE; 2084 pDCB->SyncMode &= 2085 ~(SYNC_NEGO_DONE | 2086 EN_ATN_STOP | 2087 WIDE_NEGO_ENABLE); 2088 if (pSRB->MsgInBuf[3] != 0) { 2089 /* is Wide data xfer */ 2090 pDCB->SyncPeriod |= 2091 WIDE_SYNC; 2092 pDCB->tinfo.current.width 2093 = MSG_EXT_WDTR_BUS_16_BIT; 2094 pDCB->tinfo.goal.width 2095 = MSG_EXT_WDTR_BUS_16_BIT; 2096 } 2097 } 2098 } 2099 } else 2100 pSRB->MsgInBuf[3] = 0; 2101 pSRB->SRBState |= SRB_MSGOUT; 2102 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2103 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2104 /* it's important for atn stop */ 2105 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2106 /* 2107 * SCSI command 2108 */ 2109 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2110 return; 2111 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2112 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2113 /* 2114 * is 8bit transfer Extended message : 2115 * ================================= 2116 * SYNCHRONOUS DATA TRANSFER REQUEST 2117 * ================================= 2118 * byte 0 : Extended message (01h) 2119 * byte 1 : Extended message length (03) 2120 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2121 * byte 3 : Transfer period factor 2122 * byte 4 : REQ/ACK offset 2123 */ 2124 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2125 if ((pSRB->MsgInBuf[1] != 3) || 2126 (pSRB->MsgInBuf[2] != 1)) { 2127 /* reject_msg: */ 2128 pSRB->MsgCnt = 1; 2129 pSRB->MsgInBuf[0] = MSG_REJECT_; 2130 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2131 *pscsi_status = PH_BUS_FREE; 2132 /* .. initial phase */ 2133 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2134 /* it's important for atn stop */ 2135 /* 2136 * SCSI cammand 2137 */ 2138 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2139 return; 2140 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2141 /* set async */ 2142 pDCB = pSRB->pSRBDCB; 2143 /* disable sync & sync nego */ 2144 pDCB->SyncMode &= 2145 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2146 pDCB->SyncPeriod = 0; 2147 pDCB->SyncOffset = 0; 2148 pDCB->tinfo.goal.period = 0; 2149 pDCB->tinfo.goal.offset = 0; 2150 pDCB->tinfo.current.period = 0; 2151 pDCB->tinfo.current.offset = 0; 2152 pDCB->tinfo.current.width = 2153 MSG_EXT_WDTR_BUS_8_BIT; 2154 /* 2155 * 2156 * program SCSI control register 2157 * 2158 */ 2159 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2160 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2161 trm_SetXferRate(pACB,pSRB,pDCB); 2162 *pscsi_status = PH_BUS_FREE; 2163 /* .. initial phase */ 2164 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2165 /* it's important for atn stop */ 2166 /* 2167 * SCSI cammand 2168 */ 2169 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2170 return; 2171 } else { 2172 /* set sync */ 2173 pDCB = pSRB->pSRBDCB; 2174 pDCB->SyncMode |= 2175 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2176 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2177 /* Transfer period factor */ 2178 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2179 /* REQ/ACK offset */ 2180 if (pACB->AdaptType == 1) { 2181 for(bIndex = 0; bIndex < 7; bIndex++) { 2182 if (pSRB->MsgInBuf[3] <= 2183 dc395u2x_clock_period[bIndex]) { 2184 pDCB->tinfo.goal.period = 2185 dc395u2x_tinfo_period[bIndex]; 2186 pDCB->tinfo.current.period = 2187 dc395u2x_tinfo_period[bIndex]; 2188 pDCB->tinfo.goal.offset = 2189 pDCB->SyncOffset; 2190 pDCB->tinfo.current.offset = 2191 pDCB->SyncOffset; 2192 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2193 break; 2194 } 2195 } 2196 } else { 2197 for(bIndex = 0; bIndex < 7; bIndex++) { 2198 if (pSRB->MsgInBuf[3] <= 2199 dc395x_clock_period[bIndex]) { 2200 pDCB->tinfo.goal.period = 2201 dc395x_tinfo_period[bIndex]; 2202 pDCB->tinfo.current.period = 2203 dc395x_tinfo_period[bIndex]; 2204 pDCB->tinfo.goal.offset = 2205 pDCB->SyncOffset; 2206 pDCB->tinfo.current.offset = 2207 pDCB->SyncOffset; 2208 pDCB->SyncPeriod |= 2209 (bIndex|ALT_SYNC); 2210 break; 2211 } 2212 } 2213 } 2214 /* 2215 * 2216 * program SCSI control register 2217 * 2218 */ 2219 trm_reg_write8(pDCB->SyncPeriod, 2220 TRMREG_SCSI_SYNC); 2221 trm_reg_write8(pDCB->SyncOffset, 2222 TRMREG_SCSI_OFFSET); 2223 trm_SetXferRate(pACB,pSRB,pDCB); 2224 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2225 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2226 /* 2227 ** SCSI command 2228 */ 2229 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2230 return; 2231 } 2232 } 2233 *pscsi_status = PH_BUS_FREE; 2234 /* .. initial phase */ 2235 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2236 /* it's important for atn stop */ 2237 /* 2238 * SCSI cammand 2239 */ 2240 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2241 } 2242} 2243 2244static void 2245trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2246{ 2247 2248 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2249 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2250 if (!(pSRB->SRBState & SRB_MSGIN)) { 2251 pSRB->SRBState &= SRB_DISCONNECT; 2252 pSRB->SRBState |= SRB_MSGIN; 2253 } 2254 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2255 /* it's important for atn stop*/ 2256 /* 2257 * SCSI cammand 2258 */ 2259 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2260} 2261 2262static void 2263trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2264{ 2265 2266} 2267 2268static void 2269trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2270{ 2271 2272} 2273 2274static void 2275trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2276{ 2277 union ccb *pccb; 2278 struct ccb_trans_settings neg; 2279 u_int16_t cnt, i; 2280 u_int8_t bval; 2281 PDCB pDCBTemp; 2282 2283 /* 2284 * set all lun device's period , offset 2285 */ 2286 TRM_DPRINTF("trm_SetXferRate\n"); 2287 pccb = pSRB->pccb; 2288 neg.sync_period = pDCB->tinfo.goal.period; 2289 neg.sync_offset = pDCB->tinfo.goal.offset; 2290 neg.valid = CCB_TRANS_SYNC_RATE_VALID | CCB_TRANS_SYNC_OFFSET_VALID; 2291 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2292 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2293 if (!(pDCB->IdentifyMsg & 0x07)) { 2294 pDCBTemp = pACB->pLinkDCB; 2295 cnt = pACB->DeviceCnt; 2296 bval = pDCB->TargetID; 2297 for (i = 0; i < cnt; i++) { 2298 if (pDCBTemp->TargetID == bval) { 2299 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2300 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2301 pDCBTemp->SyncMode = pDCB->SyncMode; 2302 } 2303 pDCBTemp = pDCBTemp->pNextDCB; 2304 } 2305 } 2306 return; 2307} 2308 2309/* 2310 * scsiiom 2311 * trm_Interrupt 2312 * 2313 * 2314 * ---SCSI bus phase 2315 * 2316 * PH_DATA_OUT 0x00 Data out phase 2317 * PH_DATA_IN 0x01 Data in phase 2318 * PH_COMMAND 0x02 Command phase 2319 * PH_STATUS 0x03 Status phase 2320 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2321 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2322 * PH_MSG_OUT 0x06 Message out phase 2323 * PH_MSG_IN 0x07 Message in phase 2324 * 2325 */ 2326static void 2327trm_Disconnect(PACB pACB) 2328{ 2329 PDCB pDCB; 2330 PSRB pSRB, psrb; 2331 u_int16_t i,j, cnt; 2332 u_int target_id,target_lun; 2333 2334 TRM_DPRINTF("trm_Disconnect...............\n "); 2335 2336 pDCB = pACB->pActiveDCB; 2337 if (!pDCB) { 2338 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2339 j = 400; 2340 while (--j) 2341 DELAY(1); 2342 /* 1 msec */ 2343 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2344 TRMREG_SCSI_CONTROL); 2345 return; 2346 } 2347 pSRB = pDCB->pActiveSRB; 2348 /* bug pSRB=0 */ 2349 target_id = pSRB->pccb->ccb_h.target_id; 2350 target_lun = pSRB->pccb->ccb_h.target_lun; 2351 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2352 pACB->pActiveDCB = 0; 2353 pSRB->ScsiPhase = PH_BUS_FREE; 2354 /* SCSI bus free Phase */ 2355 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2356 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2357 pSRB->SRBState = 0; 2358 trm_DoWaitingSRB(pACB); 2359 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2360 pDCB->DCBFlag = 0; 2361 cnt = pDCB->GoingSRBCnt; 2362 pDCB->GoingSRBCnt = 0; 2363 pSRB = pDCB->pGoingSRB; 2364 for (i = 0; i < cnt; i++) { 2365 psrb = pSRB->pNextSRB; 2366 pSRB->pNextSRB = pACB->pFreeSRB; 2367 pACB->pFreeSRB = pSRB; 2368 pSRB = psrb; 2369 } 2370 pDCB->pGoingSRB = 0; 2371 trm_DoWaitingSRB(pACB); 2372 } else { 2373 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2374 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2375 /* Selection time out */ 2376 if (!(pACB->scan_devices[target_id][target_lun]) && 2377 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2378 pSRB->CmdBlock[0] != INQUIRY) { 2379 pSRB->SRBState = SRB_READY; 2380 trm_RewaitSRB(pDCB, pSRB); 2381 } else { 2382 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2383 goto disc1; 2384 } 2385 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2386 /* 2387 * SRB_DISCONNECT 2388 */ 2389 trm_DoWaitingSRB(pACB); 2390 } else if (pSRB->SRBState & SRB_COMPLETED) { 2391disc1: 2392 /* 2393 * SRB_COMPLETED 2394 */ 2395 pDCB->pActiveSRB = 0; 2396 pSRB->SRBState = SRB_FREE; 2397 trm_SRBdone(pACB, pDCB, pSRB); 2398 } 2399 } 2400 return; 2401} 2402 2403static void 2404trm_Reselect(PACB pACB) 2405{ 2406 PDCB pDCB; 2407 PSRB pSRB; 2408 u_int16_t RselTarLunId; 2409 2410 TRM_DPRINTF("trm_Reselect................. \n"); 2411 pDCB = pACB->pActiveDCB; 2412 if (pDCB) { 2413 /* Arbitration lost but Reselection win */ 2414 pSRB = pDCB->pActiveSRB; 2415 pSRB->SRBState = SRB_READY; 2416 trm_RewaitSRB(pDCB, pSRB); 2417 } 2418 /* Read Reselected Target Id and LUN */ 2419 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2420 pDCB = pACB->pLinkDCB; 2421 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2422 /* get pDCB of the reselect id */ 2423 pDCB = pDCB->pNextDCB; 2424 } 2425 2426 pACB->pActiveDCB = pDCB; 2427 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2428 pSRB = &pACB->TmpSRB; 2429 pDCB->pActiveSRB = pSRB; 2430 } else { 2431 pSRB = pDCB->pActiveSRB; 2432 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2433 /* 2434 * abort command 2435 */ 2436 pSRB = &pACB->TmpSRB; 2437 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2438 pDCB->pActiveSRB = pSRB; 2439 trm_EnableMsgOutAbort1(pACB, pSRB); 2440 } else { 2441 if (pDCB->DCBFlag & ABORT_DEV_) { 2442 pSRB->SRBState = SRB_ABORT_SENT; 2443 trm_EnableMsgOutAbort1(pACB, pSRB); 2444 } else 2445 pSRB->SRBState = SRB_DATA_XFER; 2446 } 2447 } 2448 pSRB->ScsiPhase = PH_BUS_FREE; 2449 /* SCSI bus free Phase */ 2450 /* 2451 * Program HA ID, target ID, period and offset 2452 */ 2453 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2454 /* target ID */ 2455 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2456 /* host ID */ 2457 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2458 /* period */ 2459 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2460 /* offset */ 2461 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2462 /* it's important for atn stop*/ 2463 /* 2464 * SCSI cammand 2465 */ 2466 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2467 /* to rls the /ACK signal */ 2468} 2469 2470static void 2471trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2472{ 2473 PSRB psrb; 2474 u_int8_t bval, bval1,status; 2475 union ccb *pccb; 2476 struct ccb_scsiio *pcsio; 2477 PSCSI_INQDATA ptr; 2478 int intflag; 2479 u_int target_id,target_lun; 2480 PDCB pTempDCB; 2481 2482 pccb = pSRB->pccb; 2483 if (pccb == NULL) 2484 return; 2485 pcsio = &pccb->csio; 2486 target_id = pSRB->pccb->ccb_h.target_id; 2487 target_lun = pSRB->pccb->ccb_h.target_lun; 2488 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2489 bus_dmasync_op_t op; 2490 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2491 op = BUS_DMASYNC_POSTREAD; 2492 else 2493 op = BUS_DMASYNC_POSTWRITE; 2494 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2495 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2496 } 2497 /* 2498 * 2499 * target status 2500 * 2501 */ 2502 status = pSRB->TargetStatus; 2503 pcsio->scsi_status=SCSI_STAT_GOOD; 2504 pccb->ccb_h.status = CAM_REQ_CMP; 2505 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2506 /* 2507 * status of auto request sense 2508 */ 2509 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2510 pSRB->AdaptStatus = 0; 2511 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2512 2513 if (status == SCSI_STATUS_CHECK_COND) { 2514 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2515 goto ckc_e; 2516 } 2517 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2518 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2519 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2520 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2521 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2522 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2523 bzero(&pcsio->sense_data, pcsio->sense_len); 2524 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2525 pcsio->sense_len); 2526 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2527 | CAM_AUTOSNS_VALID; 2528 goto ckc_e; 2529 } 2530 /* 2531 * target status 2532 */ 2533 if (status) { 2534 if (status == SCSI_STATUS_CHECK_COND) { 2535 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2536 TRM_DPRINTF("trm_RequestSense..................\n"); 2537 trm_RequestSense(pACB, pDCB, pSRB); 2538 return; 2539 } 2540 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2541 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2542 goto ckc_e; 2543 } else if (status == SCSI_STAT_QUEUEFULL) { 2544 bval = (u_int8_t) pDCB->GoingSRBCnt; 2545 bval--; 2546 pDCB->MaxActiveCommandCnt = bval; 2547 trm_RewaitSRB(pDCB, pSRB); 2548 pSRB->AdaptStatus = 0; 2549 pSRB->TargetStatus = 0; 2550 return; 2551 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2552 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2553 pSRB->TargetStatus = 0; 2554 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2555 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2556 } else if (status == SCSI_STAT_BUSY) { 2557 TRM_DPRINTF("trm: target busy at %s %d\n", 2558 __FILE__, __LINE__); 2559 pcsio->scsi_status = SCSI_STAT_BUSY; 2560 pccb->ccb_h.status = CAM_SCSI_BUSY; 2561 return; 2562 /* The device busy, try again later? */ 2563 } else if (status == SCSI_STAT_RESCONFLICT) { 2564 TRM_DPRINTF("trm: target reserved at %s %d\n", 2565 __FILE__, __LINE__); 2566 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2567 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2568 return; 2569 } else { 2570 pSRB->AdaptStatus = 0; 2571 if (pSRB->RetryCnt) { 2572 pSRB->RetryCnt--; 2573 pSRB->TargetStatus = 0; 2574 pSRB->SRBSGIndex = 0; 2575 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2576 /* 2577 * If trm_StartSCSI return 1 : 2578 * current interrupt status is interrupt 2579 * disreenable 2580 * It's said that SCSI processor has more 2581 * one SRB need to do 2582 */ 2583 trm_RewaitSRB(pDCB, pSRB); 2584 } 2585 return; 2586 } else { 2587 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2588 __FILE__, __LINE__); 2589 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2590 } 2591 } 2592 } else { 2593 /* 2594 * process initiator status.......................... 2595 * Adapter (initiator) status 2596 */ 2597 status = pSRB->AdaptStatus; 2598 if (status & H_OVER_UNDER_RUN) { 2599 pSRB->TargetStatus = 0; 2600 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2601 /* Illegal length (over/under run) */ 2602 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2603 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2604 __FILE__, __LINE__); 2605 pDCB->tinfo.goal.period = 0; 2606 pDCB->tinfo.goal.offset = 0; 2607 /* Driver failed to perform operation */ 2608 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2609 } else { 2610 /* no error */ 2611 pSRB->AdaptStatus = 0; 2612 pSRB->TargetStatus = 0; 2613 pccb->ccb_h.status = CAM_REQ_CMP; 2614 /* there is no error, (sense is invalid) */ 2615 } 2616 } 2617ckc_e: 2618 if (pACB->scan_devices[target_id][target_lun]) { 2619 /* 2620 * if SCSI command in "scan devices" duty 2621 */ 2622 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2623 pACB->scan_devices[target_id][target_lun] = 0; 2624 /* SCSI command phase :test unit ready */ 2625 else if (pSRB->CmdBlock[0] == INQUIRY) { 2626 /* 2627 * SCSI command phase :inquiry scsi device data 2628 * (type,capacity,manufacture.... 2629 */ 2630 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2631 goto NO_DEV; 2632 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2633 /* page fault */ 2634 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2635 ptr->DevType); 2636 bval1 = ptr->DevType & SCSI_DEVTYPE; 2637 if (bval1 == SCSI_NODEV) { 2638NO_DEV: 2639 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2640 target_id, 2641 target_lun); 2642 intflag = splcam(); 2643 pACB->scan_devices[target_id][target_lun] = 0; 2644 /* no device set scan device flag =0*/ 2645 /* pDCB Q link */ 2646 /* move the head of DCB to tempDCB*/ 2647 pTempDCB=pACB->pLinkDCB; 2648 /* search current DCB for pass link */ 2649 while (pTempDCB->pNextDCB != pDCB) { 2650 pTempDCB = pTempDCB->pNextDCB; 2651 } 2652 /* 2653 * when the current DCB found than connect 2654 * current DCB tail 2655 */ 2656 /* to the DCB tail that before current DCB */ 2657 pTempDCB->pNextDCB = pDCB->pNextDCB; 2658 /* 2659 * if there was only one DCB ,connect his tail 2660 * to his head 2661 */ 2662 if (pACB->pLinkDCB == pDCB) 2663 pACB->pLinkDCB = pTempDCB->pNextDCB; 2664 if (pACB->pDCBRunRobin == pDCB) 2665 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2666 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2667 pACB->DeviceCnt--; 2668 if (pACB->DeviceCnt == 0) { 2669 pACB->pLinkDCB = NULL; 2670 pACB->pDCBRunRobin = NULL; 2671 } 2672 splx(intflag); 2673 } else { 2674#ifdef trm_DEBUG1 2675 int j; 2676 for (j = 0; j < 28; j++) { 2677 TRM_DPRINTF("ptr=%2x ", 2678 ((u_int8_t *)ptr)[j]); 2679 } 2680#endif 2681 pDCB->DevType = bval1; 2682 if (bval1 == SCSI_DASD || 2683 bval1 == SCSI_OPTICAL) { 2684 if ((((ptr->Vers & 0x07) >= 2) || 2685 ((ptr->RDF & 0x0F) == 2)) && 2686 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2687 (pDCB->DevMode & TAG_QUEUING_) && 2688 (pDCB->DevMode & EN_DISCONNECT_)) { 2689 if (pDCB->DevMode & 2690 TAG_QUEUING_) { 2691 pDCB-> 2692 MaxActiveCommandCnt = 2693 pACB->TagMaxNum; 2694 pDCB->SyncMode |= 2695 EN_TAG_QUEUING; 2696 pDCB->tinfo.disc_tag |= 2697 TRM_CUR_TAGENB; 2698 } else { 2699 pDCB->SyncMode |= 2700 EN_ATN_STOP; 2701 pDCB->tinfo.disc_tag &= 2702 ~TRM_CUR_TAGENB; 2703 } 2704 } 2705 } 2706 } 2707 /* pSRB->CmdBlock[0] == INQUIRY */ 2708 } 2709 /* pACB->scan_devices[target_id][target_lun] */ 2710 } 2711 intflag = splcam(); 2712 /* ReleaseSRB(pDCB, pSRB); */ 2713 if (pSRB == pDCB->pGoingSRB) 2714 pDCB->pGoingSRB = pSRB->pNextSRB; 2715 else { 2716 psrb = pDCB->pGoingSRB; 2717 while (psrb->pNextSRB != pSRB) { 2718 psrb = psrb->pNextSRB; 2719 } 2720 psrb->pNextSRB = pSRB->pNextSRB; 2721 if (pSRB == pDCB->pGoingLastSRB) { 2722 pDCB->pGoingLastSRB = psrb; 2723 } 2724 } 2725 pSRB->pNextSRB = pACB->pFreeSRB; 2726 pACB->pFreeSRB = pSRB; 2727 pDCB->GoingSRBCnt--; 2728 trm_DoWaitingSRB(pACB); 2729 2730 splx(intflag); 2731 /* Notify cmd done */ 2732 xpt_done (pccb); 2733} 2734 2735static void 2736trm_DoingSRB_Done(PACB pACB) 2737{ 2738 PDCB pDCB, pdcb; 2739 PSRB psrb, psrb2; 2740 u_int16_t cnt, i; 2741 union ccb *pccb; 2742 2743 pDCB = pACB->pLinkDCB; 2744 if (pDCB == NULL) 2745 return; 2746 pdcb = pDCB; 2747 do { 2748 cnt = pdcb->GoingSRBCnt; 2749 psrb = pdcb->pGoingSRB; 2750 for (i = 0; i < cnt; i++) { 2751 psrb2 = psrb->pNextSRB; 2752 pccb = psrb->pccb; 2753 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2754 /* ReleaseSRB(pDCB, pSRB); */ 2755 psrb->pNextSRB = pACB->pFreeSRB; 2756 pACB->pFreeSRB = psrb; 2757 xpt_done(pccb); 2758 psrb = psrb2; 2759 } 2760 pdcb->GoingSRBCnt = 0;; 2761 pdcb->pGoingSRB = NULL; 2762 pdcb = pdcb->pNextDCB; 2763 } 2764 while (pdcb != pDCB); 2765} 2766 2767static void 2768trm_ResetSCSIBus(PACB pACB) 2769{ 2770 int intflag; 2771 2772 intflag = splcam(); 2773 pACB->ACBFlag |= RESET_DEV; 2774 2775 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2776 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2777 splx(intflag); 2778 return; 2779} 2780 2781static void 2782trm_ScsiRstDetect(PACB pACB) 2783{ 2784 int intflag; 2785 u_long wlval; 2786 2787 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2788 wlval = 1000; 2789 while (--wlval) 2790 DELAY(1000); 2791 intflag = splcam(); 2792 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2793 2794 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2795 2796 if (pACB->ACBFlag & RESET_DEV) 2797 pACB->ACBFlag |= RESET_DONE; 2798 else { 2799 pACB->ACBFlag |= RESET_DETECT; 2800 trm_ResetDevParam(pACB); 2801 /* trm_DoingSRB_Done(pACB); ???? */ 2802 trm_RecoverSRB(pACB); 2803 pACB->pActiveDCB = NULL; 2804 pACB->ACBFlag = 0; 2805 trm_DoWaitingSRB(pACB); 2806 } 2807 splx(intflag); 2808 return; 2809} 2810 2811static void 2812trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2813{ 2814 union ccb *pccb; 2815 struct ccb_scsiio *pcsio; 2816 2817 pccb = pSRB->pccb; 2818 pcsio = &pccb->csio; 2819 2820 pSRB->SRBFlag |= AUTO_REQSENSE; 2821 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2822 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2823 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2824 pSRB->SRBSGCount); 2825 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2826 2827 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2828 pSRB->AdaptStatus = 0; 2829 pSRB->TargetStatus = 0; 2830 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2831 2832 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2833 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2834 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2835 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2836 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2837 pSRB->SRBSGCount = 1; 2838 pSRB->SRBSGIndex = 0; 2839 2840 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2841 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2842 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2843 pSRB->ScsiCmdLen = 6; 2844 2845 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2846 /* 2847 * If trm_StartSCSI return 1 : 2848 * current interrupt status is interrupt disreenable 2849 * It's said that SCSI processor has more one SRB need to do 2850 */ 2851 trm_RewaitSRB(pDCB, pSRB); 2852} 2853 2854static void 2855trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2856{ 2857 2858 pSRB->MsgCnt = 1; 2859 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2860} 2861 2862static void 2863trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2864{ 2865 2866 pSRB->MsgOutBuf[0] = MSG_ABORT; 2867 trm_EnableMsgOutAbort2(pACB, pSRB); 2868} 2869 2870static void 2871trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2872{ 2873 PNVRAMTYPE pEEpromBuf; 2874 u_int8_t bval,PeriodIndex; 2875 u_int target_id,target_lun; 2876 PDCB pTempDCB; 2877 int intflag; 2878 2879 target_id = i; 2880 target_lun = j; 2881 2882 /* 2883 * Using the lun 0 device to init other DCB first, if the device 2884 * has been initialized. 2885 * I don't want init sync arguments one by one, it is the same. 2886 */ 2887 if (target_lun != 0 && 2888 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2889 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2890 sizeof(TRM_DCB)); 2891 intflag = splcam(); 2892 if (pACB->pLinkDCB == 0) { 2893 pACB->pLinkDCB = pDCB; 2894 /* 2895 * RunRobin impersonate the role 2896 * that let each device had good proportion 2897 * about SCSI command proceeding 2898 */ 2899 pACB->pDCBRunRobin = pDCB; 2900 pDCB->pNextDCB = pDCB; 2901 } else { 2902 pTempDCB=pACB->pLinkDCB; 2903 /* search the last nod of DCB link */ 2904 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2905 pTempDCB = pTempDCB->pNextDCB; 2906 /* connect current DCB with last DCB tail */ 2907 pTempDCB->pNextDCB = pDCB; 2908 /* connect current DCB tail to this DCB Q head */ 2909 pDCB->pNextDCB=pACB->pLinkDCB; 2910 } 2911 splx(intflag); 2912 2913 pACB->DeviceCnt++; 2914 pDCB->TargetID = target_id; 2915 pDCB->TargetLUN = target_lun; 2916 pDCB->pWaitingSRB = NULL; 2917 pDCB->pGoingSRB = NULL; 2918 pDCB->GoingSRBCnt = 0; 2919 pDCB->pActiveSRB = NULL; 2920 pDCB->MaxActiveCommandCnt = 1; 2921 pDCB->DCBFlag = 0; 2922 pDCB->DCBstatus |= DS_IN_QUEUE; 2923 /* $$$$$$$ */ 2924 pEEpromBuf = &trm_eepromBuf[unit]; 2925 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2926 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2927 /* $$$$$$$ */ 2928 /* 2929 * disconnect enable ? 2930 */ 2931 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2932 bval = 0xC0; 2933 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2934 } else { 2935 bval = 0x80; 2936 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2937 } 2938 bval |= target_lun; 2939 pDCB->IdentifyMsg = bval; 2940 if (target_lun != 0 && 2941 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2942 return; 2943 /* $$$$$$$ */ 2944 /* 2945 * tag Qing enable ? 2946 */ 2947 if (pDCB->DevMode & TAG_QUEUING_) { 2948 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2949 } else 2950 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2951 /* $$$$$$$ */ 2952 /* 2953 * wide nego ,sync nego enable ? 2954 */ 2955 pDCB->SyncPeriod = 0; 2956 pDCB->SyncOffset = 0; 2957 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2958 if (pACB->AdaptType==1) {/* is U2? */ 2959 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2960 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2961 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2962 } else { 2963 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2964 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2965 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2966 } 2967 pDCB->SyncMode = 0; 2968 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2969 (pACB->Config & HCC_WIDE_CARD)) 2970 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2971 /* enable wide nego */ 2972 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2973 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2974 /* enable sync nego */ 2975 /* $$$$$$$ */ 2976 /* 2977 * Fill in tinfo structure. 2978 */ 2979 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2980 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2981 2982 pDCB->tinfo.current.period = 0; 2983 pDCB->tinfo.current.offset = 0; 2984 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2985} 2986 2987static void 2988trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2989{ 2990 PSRB pSRB; 2991 2992 pSRB=(PSRB) arg; 2993 pSRB->SRBSGPhyAddr=segs->ds_addr; 2994 return; 2995} 2996 2997static int 2998trm_initSRB(PACB pACB) 2999{ 3000 u_int16_t i; 3001 PSRB pSRB; 3002 3003 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 3004 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3005 3006 /* DMA tag for our S/G structures */ 3007 if (bus_dma_tag_create( 3008 /*parent_dmat*/pSRB->parent_dmat, 3009 /*alignment*/ 1, 3010 /*boundary*/ 0, 3011 /*lowaddr*/ BUS_SPACE_MAXADDR, 3012 /*highaddr*/ BUS_SPACE_MAXADDR, 3013 /*filter*/ NULL, 3014 /*filterarg*/ NULL, 3015 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3016 /*nsegments*/ 1, 3017 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3018 /*flags*/ 0, 3019 /*dmat*/ &pSRB->sg_dmat) != 0) { 3020 return ENXIO; 3021 } 3022 if (bus_dmamem_alloc(pSRB->sg_dmat, (void **)&pSRB->pSRBSGL, 3023 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3024 return ENXIO; 3025 } 3026 bus_dmamap_load(pSRB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3027 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3028 trm_srbmapSG, pSRB, /*flags*/0); 3029 if (i != TRM_MAX_SRB_CNT - 1) { 3030 /* 3031 * link all SRB 3032 */ 3033 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3034 } else { 3035 /* 3036 * load NULL to NextSRB of the last SRB 3037 */ 3038 pSRB->pNextSRB = NULL; 3039 } 3040 pSRB->TagNumber = i; 3041 } 3042 return (0); 3043} 3044 3045 3046 3047 3048static void 3049trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3050{ 3051 PNVRAMTYPE pEEpromBuf; 3052 3053 pEEpromBuf = &trm_eepromBuf[unit]; 3054 pACB->max_id = 15; 3055 3056 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3057 pACB->max_lun = 7; 3058 else 3059 pACB->max_lun = 0; 3060 3061 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3062 pACB->max_id, pACB->max_lun); 3063 pACB->pLinkDCB = NULL; 3064 pACB->pDCBRunRobin = NULL; 3065 pACB->pActiveDCB = NULL; 3066 pACB->AdapterUnit = (u_int8_t)unit; 3067 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3068 pACB->AdaptSCSILUN = 0; 3069 pACB->DeviceCnt = 0; 3070 pACB->AdaptType = adaptType; 3071 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3072 pACB->ACBFlag = 0; 3073 return; 3074} 3075 3076static void 3077NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3078{ 3079 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3080 u_int8_t bAddr; 3081 3082 /* Enable SEEPROM */ 3083 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3084 TRMREG_GEN_CONTROL); 3085 /* 3086 * Write enable 3087 */ 3088 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3089 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3090 NVRAM_trm_wait_30us(pACB); 3091 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3092 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3093 } 3094 /* 3095 * Write disable 3096 */ 3097 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3098 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3099 NVRAM_trm_wait_30us(pACB); 3100 /* Disable SEEPROM */ 3101 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3102 TRMREG_GEN_CONTROL); 3103 return; 3104} 3105 3106static void 3107NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3108{ 3109 int i; 3110 u_int8_t bSendData; 3111 /* 3112 * Send write command & address 3113 */ 3114 3115 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3116 /* 3117 * Write data 3118 */ 3119 for (i = 0; i < 8; i++, bData <<= 1) { 3120 bSendData = NVR_SELECT; 3121 if (bData & 0x80) 3122 /* Start from bit 7 */ 3123 bSendData |= NVR_BITOUT; 3124 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3125 NVRAM_trm_wait_30us(pACB); 3126 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3127 NVRAM_trm_wait_30us(pACB); 3128 } 3129 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3130 NVRAM_trm_wait_30us(pACB); 3131 /* 3132 * Disable chip select 3133 */ 3134 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3135 NVRAM_trm_wait_30us(pACB); 3136 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3137 NVRAM_trm_wait_30us(pACB); 3138 /* 3139 * Wait for write ready 3140 */ 3141 while (1) { 3142 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3143 NVRAM_trm_wait_30us(pACB); 3144 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3145 NVRAM_trm_wait_30us(pACB); 3146 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3147 break; 3148 } 3149 } 3150 /* 3151 * Disable chip select 3152 */ 3153 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3154 return; 3155} 3156 3157static void 3158NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3159{ 3160 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3161 u_int8_t bAddr; 3162 3163 /* 3164 * Enable SEEPROM 3165 */ 3166 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3167 TRMREG_GEN_CONTROL); 3168 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3169 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3170 /* 3171 * Disable SEEPROM 3172 */ 3173 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3174 TRMREG_GEN_CONTROL); 3175 return; 3176} 3177 3178static u_int8_t 3179NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3180{ 3181 int i; 3182 u_int8_t bReadData, bData = 0; 3183 /* 3184 * Send read command & address 3185 */ 3186 3187 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3188 3189 for (i = 0; i < 8; i++) { 3190 /* 3191 * Read data 3192 */ 3193 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3194 NVRAM_trm_wait_30us(pACB); 3195 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3196 /* 3197 * Get data bit while falling edge 3198 */ 3199 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3200 bData <<= 1; 3201 if (bReadData & NVR_BITIN) { 3202 bData |= 1; 3203 } 3204 NVRAM_trm_wait_30us(pACB); 3205 } 3206 /* 3207 * Disable chip select 3208 */ 3209 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3210 return (bData); 3211} 3212 3213static void 3214NVRAM_trm_wait_30us(PACB pACB) 3215{ 3216 3217 /* ScsiPortStallExecution(30); wait 30 us */ 3218 trm_reg_write8(5, TRMREG_GEN_TIMER); 3219 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3220 return; 3221} 3222 3223static void 3224NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3225{ 3226 int i; 3227 u_int8_t bSendData; 3228 3229 for (i = 0; i < 3; i++, bCmd <<= 1) { 3230 /* 3231 * Program SB+OP code 3232 */ 3233 bSendData = NVR_SELECT; 3234 if (bCmd & 0x04) 3235 bSendData |= NVR_BITOUT; 3236 /* start from bit 2 */ 3237 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3238 NVRAM_trm_wait_30us(pACB); 3239 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3240 NVRAM_trm_wait_30us(pACB); 3241 } 3242 for (i = 0; i < 7; i++, bAddr <<= 1) { 3243 /* 3244 * Program address 3245 */ 3246 bSendData = NVR_SELECT; 3247 if (bAddr & 0x40) 3248 /* Start from bit 6 */ 3249 bSendData |= NVR_BITOUT; 3250 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3251 NVRAM_trm_wait_30us(pACB); 3252 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3253 NVRAM_trm_wait_30us(pACB); 3254 } 3255 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3256 NVRAM_trm_wait_30us(pACB); 3257} 3258 3259static void 3260trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3261{ 3262 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3263 u_int16_t wAddr, wCheckSum; 3264 u_long dAddr, *dpEeprom; 3265 3266 NVRAM_trm_read_all(pEEpromBuf,pACB); 3267 wCheckSum = 0; 3268 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3269 wAddr < 64; wAddr++, wpEeprom++) { 3270 wCheckSum += *wpEeprom; 3271 } 3272 if (wCheckSum != 0x1234) { 3273 /* 3274 * Checksum error, load default 3275 */ 3276 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3277 pEEpromBuf->NvramSubVendorID[1] = 3278 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3279 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3280 pEEpromBuf->NvramSubSysID[1] = 3281 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3282 pEEpromBuf->NvramSubClass = 0x00; 3283 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3284 pEEpromBuf->NvramVendorID[1] = 3285 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3286 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3287 pEEpromBuf->NvramDeviceID[1] = 3288 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3289 pEEpromBuf->NvramReserved = 0x00; 3290 3291 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3292 dAddr < 16; dAddr++, dpEeprom++) { 3293 *dpEeprom = 0x00000077; 3294 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3295 } 3296 3297 *dpEeprom++ = 0x04000F07; 3298 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3299 *dpEeprom++ = 0x00000015; 3300 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3301 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3302 *dpEeprom = 0x00; 3303 pEEpromBuf->NvramCheckSum = 0x00; 3304 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3305 wAddr < 63; wAddr++, wpEeprom++) 3306 wCheckSum += *wpEeprom; 3307 *wpEeprom = 0x1234 - wCheckSum; 3308 NVRAM_trm_write_all(pEEpromBuf,pACB); 3309 } 3310 return; 3311} 3312static int 3313trm_initAdapter(PACB pACB, u_int16_t unit) 3314{ 3315 PNVRAMTYPE pEEpromBuf; 3316 u_int16_t wval; 3317 u_int8_t bval; 3318 3319 pEEpromBuf = &trm_eepromBuf[unit]; 3320 3321 /* 250ms selection timeout */ 3322 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3323 /* Mask all the interrupt */ 3324 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3325 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3326 /* Reset SCSI module */ 3327 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3328 /* program configuration 0 */ 3329 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3330 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3331 pACB->Config |= HCC_WIDE_CARD; 3332 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3333 pACB->Config |= HCC_SCSI_RESET; 3334 if (pACB->Config & HCC_PARITY) 3335 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3336 else 3337 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3338 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3339 /* program configuration 1 */ 3340 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3341 /* program Host ID */ 3342 bval = pEEpromBuf->NvramScsiId; 3343 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3344 /* set ansynchronous transfer */ 3345 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3346 /* Trun LED control off*/ 3347 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3348 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3349 /* DMA config */ 3350 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3351 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3352 /* Clear pending interrupt status */ 3353 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3354 /* Enable SCSI interrupt */ 3355 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3356 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3357 return (0); 3358} 3359 3360static void 3361trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3362{ 3363 PACB pACB; 3364 3365 pACB = (PACB)arg; 3366 pACB->srb_physbase = segs->ds_addr; 3367} 3368 3369static void 3370trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3371{ 3372 bus_addr_t *baddr; 3373 3374 baddr = (bus_addr_t *)arg; 3375 *baddr = segs->ds_addr; 3376} 3377 3378static PACB 3379trm_init(u_int16_t unit, device_t dev) 3380{ 3381 PACB pACB; 3382 int rid = PCIR_MAPS, i = 0, j = 0; 3383 u_int16_t adaptType = 0; 3384 3385 pACB = (PACB) device_get_softc(dev); 3386 if (!pACB) { 3387 printf("trm%d: cannot allocate ACB !\n", unit); 3388 return (NULL); 3389 } 3390 bzero (pACB, sizeof (struct _ACB)); 3391 pACB->iores = bus_alloc_resource(dev, SYS_RES_IOPORT, 3392 &rid, 0, ~0, 1, RF_ACTIVE); 3393 if (pACB->iores == NULL) { 3394 printf("trm_init: bus_alloc_resource failed!\n"); 3395 return (NULL); 3396 } 3397 switch (pci_get_devid(dev)) { 3398 case PCI_DEVICEID_TRMS1040: 3399 adaptType = 0; 3400 break; 3401 case PCI_DEVICEID_TRMS2080: 3402 adaptType = 1; 3403 break; 3404 default: 3405 printf("trm_init %d: unknown adapter type!\n", unit); 3406 goto bad; 3407 } 3408 pACB->dev = dev; 3409 pACB->tag = rman_get_bustag(pACB->iores); 3410 pACB->bsh = rman_get_bushandle(pACB->iores); 3411 if (bus_dma_tag_create(/*parent_dmat*/ pACB->parent_dmat, 3412 /*alignment*/ 1, 3413 /*boundary*/ 0, 3414 /*lowaddr*/ BUS_SPACE_MAXADDR, 3415 /*highaddr*/ BUS_SPACE_MAXADDR, 3416 /*filter*/ NULL, 3417 /*filterarg*/ NULL, 3418 /*maxsize*/ MAXBSIZE, 3419 /*nsegments*/ TRM_NSEG, 3420 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3421 /*flags*/ BUS_DMA_ALLOCNOW, 3422 &pACB->buffer_dmat) != 0) 3423 goto bad; 3424 /* DMA tag for our ccb structures */ 3425 if (bus_dma_tag_create( 3426 /*parent_dmat*/pACB->parent_dmat, 3427 /*alignment*/ 1, 3428 /*boundary*/ 0, 3429 /*lowaddr*/ BUS_SPACE_MAXADDR, 3430 /*highaddr*/ BUS_SPACE_MAXADDR, 3431 /*filter*/ NULL, 3432 /*filterarg*/ NULL, 3433 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3434 /*nsegments*/ 1, 3435 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3436 /*flags*/ 0, 3437 /*dmat*/ &pACB->srb_dmat) != 0) { 3438 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3439 goto bad; 3440 } 3441 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3442 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3443 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3444 goto bad; 3445 } 3446 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3447 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3448 /* flags */0); 3449 /* Create, allocate, and map DMA buffers for autosense data */ 3450 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3451 /*boundary*/0, 3452 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3453 /*highaddr*/BUS_SPACE_MAXADDR, 3454 /*filter*/NULL, /*filterarg*/NULL, 3455 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3456 /*nsegments*/1, 3457 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3458 /*flags*/0, &pACB->sense_dmat) != 0) { 3459 if (bootverbose) 3460 device_printf(dev, "cannot create sense buffer dmat\n"); 3461 goto bad; 3462 } 3463 3464 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3465 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3466 goto bad; 3467 3468 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3469 pACB->sense_buffers, 3470 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3471 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3472 3473 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3474 trm_initACB(pACB, adaptType, unit); 3475 for (i = 0; i < (pACB->max_id + 1); i++) { 3476 if (pACB->AdaptSCSIID == i) 3477 continue; 3478 for(j = 0; j < (pACB->max_lun + 1); j++) { 3479 pACB->scan_devices[i][j] = 1; 3480 /* we assume we need to scan all devices */ 3481 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3482 } 3483 } 3484 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3485 if (trm_initSRB(pACB)) { 3486 printf("trm_initSRB: error\n"); 3487 goto bad; 3488 } 3489 if (trm_initAdapter(pACB, unit)) { 3490 printf("trm_initAdapter: initial ERROR\n"); 3491 goto bad; 3492 } 3493 return (pACB); 3494bad: 3495 if (pACB->iores) 3496 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, 3497 pACB->iores); 3498 if (pACB->sense_dmamap) { 3499 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3500 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3501 pACB->sense_dmamap); 3502 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3503 } 3504 if (pACB->sense_dmat) 3505 bus_dma_tag_destroy(pACB->sense_dmat); 3506 if (pACB->srb_dmamap) { 3507 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3508 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3509 pACB->srb_dmamap); 3510 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3511 } 3512 if (pACB->srb_dmat) 3513 bus_dma_tag_destroy(pACB->srb_dmat); 3514 if (pACB->buffer_dmat) 3515 bus_dma_tag_destroy(pACB->buffer_dmat); 3516 return (NULL); 3517} 3518 3519static int 3520trm_attach(device_t dev) 3521{ 3522 struct cam_devq *device_Q; 3523 u_long device_id; 3524 PACB pACB = 0; 3525 int rid = 0; 3526 int unit = device_get_unit(dev); 3527 3528 device_id = pci_get_devid(dev); 3529 /* 3530 * These cards do not allow memory mapped accesses 3531 */ 3532 if ((pACB = trm_init((u_int16_t) unit, 3533 dev)) == NULL) { 3534 printf("trm%d: trm_init error!\n",unit); 3535 return (ENXIO); 3536 } 3537 /* After setting up the adapter, map our interrupt */ 3538 /* 3539 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3540 * start queue to reset to the idle loop. 3541 * Create device queue of SIM(s) 3542 * (MAX_START_JOB - 1) : max_sim_transactions 3543 */ 3544 pACB->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, 3545 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 3546 if (pACB->irq == NULL || 3547 bus_setup_intr(dev, pACB->irq, 3548 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3549 printf("trm%d: register Interrupt handler error!\n", unit); 3550 goto bad; 3551 } 3552 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3553 if (device_Q == NULL){ 3554 printf("trm%d: device_Q == NULL !\n",unit); 3555 goto bad; 3556 } 3557 /* 3558 * Now tell the generic SCSI layer 3559 * about our bus. 3560 * If this is the xpt layer creating a sim, then it's OK 3561 * to wait for an allocation. 3562 * XXX Should we pass in a flag to indicate that wait is OK? 3563 * 3564 * SIM allocation 3565 * 3566 * SCSI Interface Modules 3567 * The sim driver creates a sim for each controller. The sim device 3568 * queue is separately created in order to allow resource sharing betwee 3569 * sims. For instance, a driver may create one sim for each channel of 3570 * a multi-channel controller and use the same queue for each channel. 3571 * In this way, the queue resources are shared across all the channels 3572 * of the multi-channel controller. 3573 * trm_action : sim_action_func 3574 * trm_poll : sim_poll_func 3575 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3576 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3577 * pACB->unit : unit 3578 * 1 : max_dev_transactions 3579 * MAX_TAGS : max_tagged_dev_transactions 3580 * 3581 * *******Construct our first channel SIM entry 3582 */ 3583 pACB->psim = cam_sim_alloc(trm_action, 3584 trm_poll, 3585 "trm", 3586 pACB, 3587 unit, 3588 1, 3589 TRM_MAX_TAGS_CMD_QUEUE, 3590 device_Q); 3591 if (pACB->psim == NULL) { 3592 printf("trm%d: SIM allocate fault !\n",unit); 3593 cam_simq_free(device_Q); /* SIM allocate fault*/ 3594 goto bad; 3595 } 3596 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3597 printf("trm%d: xpt_bus_register fault !\n",unit); 3598 goto bad; 3599 } 3600 if (xpt_create_path(&pACB->ppath, 3601 NULL, 3602 cam_sim_path(pACB->psim), 3603 CAM_TARGET_WILDCARD, 3604 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3605 printf("trm%d: xpt_create_path fault !\n",unit); 3606 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3607 goto bad; 3608 } 3609 return (0); 3610bad: 3611 if (pACB->iores) 3612 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, 3613 pACB->iores); 3614 if (pACB->srb_dmamap) { 3615 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3616 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3617 pACB->srb_dmamap); 3618 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3619 } 3620 if (pACB->srb_dmat) 3621 bus_dma_tag_destroy(pACB->srb_dmat); 3622 if (pACB->sense_dmamap) { 3623 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3624 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3625 pACB->sense_dmamap); 3626 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3627 } 3628 if (pACB->sense_dmat) 3629 bus_dma_tag_destroy(pACB->sense_dmat); 3630 if (pACB->buffer_dmat) 3631 bus_dma_tag_destroy(pACB->buffer_dmat); 3632 if (pACB->ih) 3633 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3634 if (pACB->irq) 3635 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3636 if (pACB->psim) 3637 cam_sim_free(pACB->psim, TRUE); 3638 3639 return (ENXIO); 3640 3641} 3642 3643/* 3644* pci_device 3645* trm_probe (device_t tag, pcidi_t type) 3646* 3647*/ 3648static int 3649trm_probe(device_t dev) 3650{ 3651 switch (pci_get_devid(dev)) { 3652 case PCI_DEVICEID_TRMS1040: 3653 device_set_desc(dev, 3654 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3655 return (0); 3656 case PCI_DEVICEID_TRMS2080: 3657 device_set_desc(dev, 3658 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3659 return 0; 3660 default: 3661 return (ENXIO); 3662 } 3663} 3664 3665static int 3666trm_detach(device_t dev) 3667{ 3668 PACB pACB = device_get_softc(dev); 3669 3670 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, pACB->iores); 3671 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3672 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3673 pACB->srb_dmamap); 3674 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3675 bus_dma_tag_destroy(pACB->srb_dmat); 3676 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3677 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3678 pACB->sense_dmamap); 3679 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3680 bus_dma_tag_destroy(pACB->sense_dmat); 3681 bus_dma_tag_destroy(pACB->buffer_dmat); 3682 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3683 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3684 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3685 xpt_free_path(pACB->ppath); 3686 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3687 cam_sim_free(pACB->psim, TRUE); 3688 return (0); 3689} 3690static device_method_t trm_methods[] = { 3691 /* Device interface */ 3692 DEVMETHOD(device_probe, trm_probe), 3693 DEVMETHOD(device_attach, trm_attach), 3694 DEVMETHOD(device_detach, trm_detach), 3695 { 0, 0 } 3696}; 3697 3698static driver_t trm_driver = { 3699 "trm", trm_methods, sizeof(struct _ACB) 3700}; 3701 3702static devclass_t trm_devclass; 3703DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3704