trm.c revision 116351
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 *(C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 12 */ 13 14/* 15 * HISTORY: 16 * 17 * REV# DATE NAME DESCRIPTION 18 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 19 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 20 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 21 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 22 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 23 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 24 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 25 */ 26 27/* 28 * 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 */ 53 54/* 55 * Imported into FreeBSD source repository, and updated to compile under 56 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 57 */ 58 59/* 60 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 61 * <doginou@ci0.org>, 2002-03-04 62 */ 63 64#include <sys/cdefs.h> 65__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 116351 2003-06-14 22:17:41Z njl $"); 66 67#include <sys/param.h> 68 69#include <sys/systm.h> 70#include <sys/malloc.h> 71#include <sys/queue.h> 72#if __FreeBSD_version >= 500000 73#include <sys/bio.h> 74#endif 75#include <sys/buf.h> 76#include <sys/bus.h> 77#include <sys/kernel.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <pci/pcivar.h> 83#include <pci/pcireg.h> 84#include <machine/resource.h> 85#include <machine/bus_pio.h> 86#include <machine/bus.h> 87#include <machine/clock.h> 88#include <sys/rman.h> 89 90#include <cam/cam.h> 91#include <cam/cam_ccb.h> 92#include <cam/cam_sim.h> 93#include <cam/cam_xpt_sim.h> 94#include <cam/cam_debug.h> 95 96#include <cam/scsi/scsi_all.h> 97#include <cam/scsi/scsi_message.h> 98 99#include <dev/trm/trm.h> 100 101#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 102#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 103#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 104#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 105 reg, value) 106#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 107 reg, value) 108#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 109 reg, value) 110 111#define PCI_Vendor_ID_TEKRAM 0x1DE1 112#define PCI_Device_ID_TRM_S1040 0x0391 113#define PCI_DEVICEID_TRMS1040 0x03911DE1 114#define PCI_DEVICEID_TRMS2080 0x03921DE1 115 116#ifdef trm_DEBUG1 117#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 118#else 119#define TRM_DPRINTF(fmt, arg...) {} 120#endif /* TRM_DEBUG */ 121 122static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 123static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 125static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 126static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 127static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 128static void NVRAM_trm_wait_30us(PACB pACB); 129 130static void trm_Interrupt(void *vpACB); 131static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 154 u_int16_t * pscsi_status); 155static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 156static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 157static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 158static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 159static void trm_Disconnect(PACB pACB); 160static void trm_Reselect(PACB pACB); 161static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 162static void trm_DoingSRB_Done(PACB pACB); 163static void trm_ScsiRstDetect(PACB pACB); 164static void trm_ResetSCSIBus(PACB pACB); 165static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 166static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 167static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 168static void trm_SendSRB(PACB pACB, PSRB pSRB); 169static int trm_probe(device_t tag); 170static int trm_attach(device_t tag); 171static void trm_reset(PACB pACB); 172 173static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 174 175static int trm_initAdapter(PACB pACB, u_int16_t unit); 176static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 177 u_int32_t i, u_int32_t j); 178static int trm_initSRB(PACB pACB); 179static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 180/* CAM SIM entry points */ 181#define ccb_trmsrb_ptr spriv_ptr0 182#define ccb_trmacb_ptr spriv_ptr1 183static void trm_action(struct cam_sim *psim, union ccb *pccb); 184static void trm_poll(struct cam_sim *psim); 185 186 187static void * trm_SCSI_phase0[] = { 188 trm_DataOutPhase0, /* phase:0 */ 189 trm_DataInPhase0, /* phase:1 */ 190 trm_CommandPhase0, /* phase:2 */ 191 trm_StatusPhase0, /* phase:3 */ 192 trm_Nop0, /* phase:4 */ 193 trm_Nop1, /* phase:5 */ 194 trm_MsgOutPhase0, /* phase:6 */ 195 trm_MsgInPhase0, /* phase:7 */ 196}; 197 198/* 199 * 200 * stateV = (void *) trm_SCSI_phase1[phase] 201 * 202 */ 203static void * trm_SCSI_phase1[] = { 204 trm_DataOutPhase1, /* phase:0 */ 205 trm_DataInPhase1, /* phase:1 */ 206 trm_CommandPhase1, /* phase:2 */ 207 trm_StatusPhase1, /* phase:3 */ 208 trm_Nop0, /* phase:4 */ 209 trm_Nop1, /* phase:5 */ 210 trm_MsgOutPhase1, /* phase:6 */ 211 trm_MsgInPhase1, /* phase:7 */ 212}; 213 214 215NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 216/* 217 *Fast20: 000 50ns, 20.0 Mbytes/s 218 * 001 75ns, 13.3 Mbytes/s 219 * 010 100ns, 10.0 Mbytes/s 220 * 011 125ns, 8.0 Mbytes/s 221 * 100 150ns, 6.6 Mbytes/s 222 * 101 175ns, 5.7 Mbytes/s 223 * 110 200ns, 5.0 Mbytes/s 224 * 111 250ns, 4.0 Mbytes/s 225 * 226 *Fast40: 000 25ns, 40.0 Mbytes/s 227 * 001 50ns, 20.0 Mbytes/s 228 * 010 75ns, 13.3 Mbytes/s 229 * 011 100ns, 10.0 Mbytes/s 230 * 100 125ns, 8.0 Mbytes/s 231 * 101 150ns, 6.6 Mbytes/s 232 * 110 175ns, 5.7 Mbytes/s 233 * 111 200ns, 5.0 Mbytes/s 234 */ 235 /* real period: */ 236u_int8_t dc395x_clock_period[] = { 237 12,/* 48 ns 20 MB/sec */ 238 18,/* 72 ns 13.3 MB/sec */ 239 25,/* 100 ns 10.0 MB/sec */ 240 31,/* 124 ns 8.0 MB/sec */ 241 37,/* 148 ns 6.6 MB/sec */ 242 43,/* 172 ns 5.7 MB/sec */ 243 50,/* 200 ns 5.0 MB/sec */ 244 62 /* 248 ns 4.0 MB/sec */ 245}; 246 247u_int8_t dc395u2x_clock_period[]={ 248 10,/* 25 ns 40.0 MB/sec */ 249 12,/* 48 ns 20.0 MB/sec */ 250 18,/* 72 ns 13.3 MB/sec */ 251 25,/* 100 ns 10.0 MB/sec */ 252 31,/* 124 ns 8.0 MB/sec */ 253 37,/* 148 ns 6.6 MB/sec */ 254 43,/* 172 ns 5.7 MB/sec */ 255 50,/* 200 ns 5.0 MB/sec */ 256}; 257 258#define dc395x_tinfo_period dc395x_clock_period 259#define dc395u2x_tinfo_period dc395u2x_clock_period 260 261static PSRB 262trm_GetSRB(PACB pACB) 263{ 264 int intflag; 265 PSRB pSRB; 266 267 intflag = splcam(); 268 pSRB = pACB->pFreeSRB; 269 if (pSRB) { 270 pACB->pFreeSRB = pSRB->pNextSRB; 271 pSRB->pNextSRB = NULL; 272 } 273 splx(intflag); 274 return (pSRB); 275} 276 277static void 278trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 279{ 280 PSRB psrb1; 281 int intflag; 282 283 intflag = splcam(); 284 if ((psrb1 = pDCB->pWaitingSRB)) { 285 pSRB->pNextSRB = psrb1; 286 pDCB->pWaitingSRB = pSRB; 287 } else { 288 pSRB->pNextSRB = NULL; 289 pDCB->pWaitingSRB = pSRB; 290 pDCB->pWaitingLastSRB = pSRB; 291 } 292 splx(intflag); 293} 294 295static void 296trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 297{ 298 PSRB psrb1; 299 int intflag; 300 301 intflag = splcam(); 302 pDCB->GoingSRBCnt--; 303 psrb1 = pDCB->pGoingSRB; 304 if (pSRB == psrb1) 305 /* 306 * if this SRB is GoingSRB 307 * remove this SRB from GoingSRB Q 308 */ 309 pDCB->pGoingSRB = psrb1->pNextSRB; 310 else { 311 /* 312 * if this SRB is not current GoingSRB 313 * remove this SRB from GoingSRB Q 314 */ 315 while (pSRB != psrb1->pNextSRB) 316 psrb1 = psrb1->pNextSRB; 317 psrb1->pNextSRB = pSRB->pNextSRB; 318 if (pSRB == pDCB->pGoingLastSRB) 319 pDCB->pGoingLastSRB = psrb1; 320 } 321 if ((psrb1 = pDCB->pWaitingSRB)) { 322 /* 323 * if WaitingSRB Q is not NULL 324 * Q back this SRB into WaitingSRB 325 */ 326 327 pSRB->pNextSRB = psrb1; 328 pDCB->pWaitingSRB = pSRB; 329 } else { 330 pSRB->pNextSRB = NULL; 331 pDCB->pWaitingSRB = pSRB; 332 pDCB->pWaitingLastSRB = pSRB; 333 } 334 splx(intflag); 335} 336 337static void 338trm_DoWaitingSRB(PACB pACB) 339{ 340 int intflag; 341 PDCB ptr, ptr1; 342 PSRB pSRB; 343 344 intflag = splcam(); 345 if (!(pACB->pActiveDCB) && 346 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 347 ptr = pACB->pDCBRunRobin; 348 if (!ptr) { 349 ptr = pACB->pLinkDCB; 350 pACB->pDCBRunRobin = ptr; 351 } 352 ptr1 = ptr; 353 for (;ptr1 ;) { 354 pACB->pDCBRunRobin = ptr1->pNextDCB; 355 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 356 || !(pSRB = ptr1->pWaitingSRB)) { 357 if (pACB->pDCBRunRobin == ptr) 358 break; 359 ptr1 = ptr1->pNextDCB; 360 } else { 361 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 362 /* 363 * If trm_StartSCSI return 0 : 364 * current interrupt status is interrupt enable 365 * It's said that SCSI processor is unoccupied 366 */ 367 ptr1->GoingSRBCnt++; 368 if (ptr1->pWaitingLastSRB == pSRB) { 369 ptr1->pWaitingSRB = NULL; 370 ptr1->pWaitingLastSRB = NULL; 371 } else 372 ptr1->pWaitingSRB = pSRB->pNextSRB; 373 pSRB->pNextSRB = NULL; 374 if (ptr1->pGoingSRB) 375 ptr1->pGoingLastSRB->pNextSRB = pSRB; 376 else 377 ptr1->pGoingSRB = pSRB; 378 ptr1->pGoingLastSRB = pSRB; 379 } 380 break; 381 } 382 } 383 } 384 splx(intflag); 385 return; 386} 387 388static void 389trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 390{ 391 392 if (pDCB->pWaitingSRB) { 393 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 394 pDCB->pWaitingLastSRB = pSRB; 395 pSRB->pNextSRB = NULL; 396 } else { 397 pDCB->pWaitingSRB = pSRB; 398 pDCB->pWaitingLastSRB = pSRB; 399 } 400} 401 402static u_int32_t 403trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 404{ 405 int offset; 406 407 offset = pSRB->TagNumber; 408 return (pACB->sense_busaddr + 409 (offset * sizeof(struct scsi_sense_data))); 410} 411 412static struct scsi_sense_data * 413trm_get_sense_buf(PACB pACB, PSRB pSRB) 414{ 415 int offset; 416 417 offset = pSRB->TagNumber; 418 return (&pACB->sense_buffers[offset]); 419} 420static void 421trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 422{ 423 int flags; 424 PACB pACB; 425 PSRB pSRB; 426 union ccb *ccb; 427 u_long totalxferlen=0; 428 429 flags = splcam(); 430 pSRB = (PSRB)arg; 431 ccb = pSRB->pccb; 432 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 433 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 434 if (nseg != 0) { 435 PSEG psg; 436 bus_dma_segment_t *end_seg; 437 int op; 438 439 /* Copy the segments into our SG list */ 440 end_seg = dm_segs + nseg; 441 psg = pSRB->pSRBSGL; 442 while (dm_segs < end_seg) { 443 psg->address = dm_segs->ds_addr; 444 psg->length = (u_long)dm_segs->ds_len; 445 totalxferlen += dm_segs->ds_len; 446 psg++; 447 dm_segs++; 448 } 449 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 450 op = BUS_DMASYNC_PREREAD; 451 } else { 452 op = BUS_DMASYNC_PREWRITE; 453 } 454 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 455 } 456 pSRB->RetryCnt = 0; 457 pSRB->SRBTotalXferLength = totalxferlen; 458 pSRB->SRBSGCount = nseg; 459 pSRB->SRBSGIndex = 0; 460 pSRB->AdaptStatus = 0; 461 pSRB->TargetStatus = 0; 462 pSRB->MsgCnt = 0; 463 pSRB->SRBStatus = 0; 464 pSRB->SRBFlag = 0; 465 pSRB->SRBState = 0; 466 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 467 468 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 469 if (nseg != 0) 470 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 471 pSRB->pNextSRB = pACB->pFreeSRB; 472 pACB->pFreeSRB = pSRB; 473 xpt_done(ccb); 474 splx(flags); 475 return; 476 } 477 ccb->ccb_h.status |= CAM_SIM_QUEUED; 478#if 0 479 /* XXX Need a timeout handler */ 480 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 481#endif 482 trm_SendSRB(pACB, pSRB); 483 splx(flags); 484 return; 485} 486 487static void 488trm_SendSRB(PACB pACB, PSRB pSRB) 489{ 490 PDCB pDCB; 491 492 pDCB = pSRB->pSRBDCB; 493 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 494 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 495 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 496 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 497 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 498 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 499 trm_SRBwaiting(pDCB, pSRB); 500 goto SND_EXIT; 501 } 502 503 if (pDCB->pWaitingSRB) { 504 trm_SRBwaiting(pDCB, pSRB); 505 pSRB = pDCB->pWaitingSRB; 506 pDCB->pWaitingSRB = pSRB->pNextSRB; 507 pSRB->pNextSRB = NULL; 508 } 509 510 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 511 /* 512 * If trm_StartSCSI return 0 : 513 * current interrupt status is interrupt enable 514 * It's said that SCSI processor is unoccupied 515 */ 516 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 517 if (pDCB->pGoingSRB) { 518 pDCB->pGoingLastSRB->pNextSRB = pSRB; 519 pDCB->pGoingLastSRB = pSRB; 520 } else { 521 pDCB->pGoingSRB = pSRB; 522 pDCB->pGoingLastSRB = pSRB; 523 } 524 } else { 525 /* 526 * If trm_StartSCSI return 1 : 527 * current interrupt status is interrupt disreenable 528 * It's said that SCSI processor has more one SRB need to do 529 */ 530 trm_RewaitSRB0(pDCB, pSRB); 531 } 532SND_EXIT: 533 return; 534} 535 536 537static void 538trm_action(struct cam_sim *psim, union ccb *pccb) 539{ 540 PACB pACB; 541 int actionflags; 542 u_int target_id,target_lun; 543 544 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 545 546 actionflags = splcam(); 547 pACB = (PACB) cam_sim_softc(psim); 548 target_id = pccb->ccb_h.target_id; 549 target_lun = pccb->ccb_h.target_lun; 550 551 switch (pccb->ccb_h.func_code) { 552 case XPT_NOOP: 553 TRM_DPRINTF(" XPT_NOOP \n"); 554 pccb->ccb_h.status = CAM_REQ_INVALID; 555 xpt_done(pccb); 556 break; 557 /* 558 * Execute the requested I/O operation 559 */ 560 case XPT_SCSI_IO: { 561 PDCB pDCB = NULL; 562 PSRB pSRB; 563 struct ccb_scsiio *pcsio; 564 565 pcsio = &pccb->csio; 566 TRM_DPRINTF(" XPT_SCSI_IO \n"); 567 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 568 ,target_id, target_lun); 569 TRM_DPRINTF( 570 "pACB->scan_devices[target_id][target_lun]= %d \n" 571 ,pACB->scan_devices[target_id][target_lun]); 572 if((pccb->ccb_h.status & CAM_STATUS_MASK) !=CAM_REQ_INPROG) { 573 xpt_done(pccb); 574 splx(actionflags); 575 return; 576 } 577 pDCB = &pACB->DCBarray[target_id][target_lun]; 578 if(!(pDCB->DCBstatus & DS_IN_QUEUE)) { 579 pACB->scan_devices[target_id][target_lun] = 1; 580 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 581 target_id, target_lun); 582 } 583 /* 584 * Assign an SRB and connect it with this ccb. 585 */ 586 pSRB = trm_GetSRB(pACB); 587 if (!pSRB) { 588 /* Freeze SIMQ */ 589 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 590 xpt_done(pccb); 591 splx(actionflags); 592 return; 593 } 594 pSRB->pSRBDCB = pDCB; 595 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 596 pccb->ccb_h.ccb_trmacb_ptr = pACB; 597 pSRB->pccb = pccb; 598 pSRB->ScsiCmdLen = pcsio->cdb_len; 599 /* 600 * move layer of CAM command block to layer of SCSI 601 * Request Block for SCSI processor command doing 602 */ 603 if((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 604 if((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 605 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 606 ,pcsio->cdb_len); 607 } else { 608 pccb->ccb_h.status = CAM_REQ_INVALID; 609 pSRB->pNextSRB = pACB->pFreeSRB; 610 pACB->pFreeSRB= pSRB; 611 xpt_done(pccb); 612 splx(actionflags); 613 return; 614 } 615 } else 616 bcopy(pcsio->cdb_io.cdb_bytes, 617 pSRB->CmdBlock, pcsio->cdb_len); 618 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 619 != CAM_DIR_NONE) { 620 if ((pccb->ccb_h.flags & 621 CAM_SCATTER_VALID) == 0) { 622 if ((pccb->ccb_h.flags 623 & CAM_DATA_PHYS) == 0) { 624 int vmflags; 625 int error; 626 627 vmflags = splsoftvm(); 628 error = bus_dmamap_load( 629 pACB->buffer_dmat, 630 pSRB->dmamap, 631 pcsio->data_ptr, 632 pcsio->dxfer_len, 633 trm_ExecuteSRB, 634 pSRB, 635 0); 636 if (error == EINPROGRESS) { 637 xpt_freeze_simq( 638 pACB->psim, 639 1); 640 pccb->ccb_h.status |= 641 CAM_RELEASE_SIMQ; 642 } 643 splx(vmflags); 644 } else { 645 struct bus_dma_segment seg; 646 647 /* Pointer to physical buffer */ 648 seg.ds_addr = 649 (bus_addr_t)pcsio->data_ptr; 650 seg.ds_len = pcsio->dxfer_len; 651 trm_ExecuteSRB(pSRB, &seg, 1, 652 0); 653 } 654 } else { 655 /* CAM_SCATTER_VALID */ 656 struct bus_dma_segment *segs; 657 658 if ((pccb->ccb_h.flags & 659 CAM_SG_LIST_PHYS) == 0 || 660 (pccb->ccb_h.flags 661 & CAM_DATA_PHYS) != 0) { 662 pSRB->pNextSRB = pACB->pFreeSRB; 663 pACB->pFreeSRB = pSRB; 664 pccb->ccb_h.status = 665 CAM_PROVIDE_FAIL; 666 xpt_done(pccb); 667 splx(actionflags); 668 return; 669 } 670 671 /* cam SG list is physical, 672 * cam data is virtual 673 */ 674 segs = (struct bus_dma_segment *) 675 pcsio->data_ptr; 676 trm_ExecuteSRB(pSRB, segs, 677 pcsio->sglist_cnt, 1); 678 } /* CAM_SCATTER_VALID */ 679 } else 680 trm_ExecuteSRB(pSRB, NULL, 0, 0); 681 } 682 break; 683 case XPT_GDEV_TYPE: 684 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 685 pccb->ccb_h.status = CAM_REQ_INVALID; 686 xpt_done(pccb); 687 break; 688 case XPT_GDEVLIST: 689 TRM_DPRINTF(" XPT_GDEVLIST \n"); 690 pccb->ccb_h.status = CAM_REQ_INVALID; 691 xpt_done(pccb); 692 break; 693 /* 694 * Path routing inquiry 695 * Path Inquiry CCB 696 */ 697 case XPT_PATH_INQ: { 698 struct ccb_pathinq *cpi = &pccb->cpi; 699 700 TRM_DPRINTF(" XPT_PATH_INQ \n"); 701 cpi->version_num = 1; 702 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 703 cpi->target_sprt = 0; 704 cpi->hba_misc = 0; 705 cpi->hba_eng_cnt = 0; 706 cpi->max_target = 15 ; 707 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 708 cpi->initiator_id = pACB->AdaptSCSIID; 709 cpi->bus_id = cam_sim_bus(psim); 710 cpi->base_transfer_speed = 3300; 711 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 712 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 713 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 714 cpi->unit_number = cam_sim_unit(psim); 715 cpi->ccb_h.status = CAM_REQ_CMP; 716 xpt_done(pccb); 717 } 718 break; 719 /* 720 * Release a frozen SIM queue 721 * Release SIM Queue 722 */ 723 case XPT_REL_SIMQ: 724 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 725 pccb->ccb_h.status = CAM_REQ_INVALID; 726 xpt_done(pccb); 727 break; 728 /* 729 * Set Asynchronous Callback Parameters 730 * Set Asynchronous Callback CCB 731 */ 732 case XPT_SASYNC_CB: 733 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 734 pccb->ccb_h.status = CAM_REQ_INVALID; 735 xpt_done(pccb); 736 break; 737 /* 738 * Set device type information 739 * Set Device Type CCB 740 */ 741 case XPT_SDEV_TYPE: 742 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 743 pccb->ccb_h.status = CAM_REQ_INVALID; 744 xpt_done(pccb); 745 break; 746 /* 747 * (Re)Scan the SCSI Bus 748 * Rescan the given bus, or bus/target/lun 749 */ 750 case XPT_SCAN_BUS: 751 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 752 pccb->ccb_h.status = CAM_REQ_INVALID; 753 xpt_done(pccb); 754 break; 755 /* 756 * Get EDT entries matching the given pattern 757 */ 758 case XPT_DEV_MATCH: 759 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 760 pccb->ccb_h.status = CAM_REQ_INVALID; 761 xpt_done(pccb); 762 break; 763 /* 764 * Turn on debugging for a bus, target or lun 765 */ 766 case XPT_DEBUG: 767 TRM_DPRINTF(" XPT_DEBUG \n"); 768 pccb->ccb_h.status = CAM_REQ_INVALID; 769 xpt_done(pccb); 770 break; 771 /* 772 * XPT_ABORT = 0x10, Abort the specified CCB 773 * Abort XPT request CCB 774 */ 775 case XPT_ABORT: 776 TRM_DPRINTF(" XPT_ABORT \n"); 777 pccb->ccb_h.status = CAM_REQ_INVALID; 778 xpt_done(pccb); 779 break; 780 /* 781 * Reset the specified SCSI bus 782 * Reset SCSI Bus CCB 783 */ 784 case XPT_RESET_BUS: { 785 int i; 786 787 TRM_DPRINTF(" XPT_RESET_BUS \n"); 788 trm_reset(pACB); 789 pACB->ACBFlag=0; 790 for (i=0; i<500; i++) 791 DELAY(1000); 792 pccb->ccb_h.status = CAM_REQ_CMP; 793 xpt_done(pccb); 794 } 795 break; 796 /* 797 * Bus Device Reset the specified SCSI device 798 * Reset SCSI Device CCB 799 */ 800 case XPT_RESET_DEV: 801 /* 802 * Don't (yet?) support vendor 803 * specific commands. 804 */ 805 TRM_DPRINTF(" XPT_RESET_DEV \n"); 806 pccb->ccb_h.status = CAM_REQ_INVALID; 807 xpt_done(pccb); 808 break; 809 /* 810 * Terminate the I/O process 811 * Terminate I/O Process Request CCB 812 */ 813 case XPT_TERM_IO: 814 TRM_DPRINTF(" XPT_TERM_IO \n"); 815 pccb->ccb_h.status = CAM_REQ_INVALID; 816 xpt_done(pccb); 817 break; 818 /* 819 * Scan Logical Unit 820 */ 821 case XPT_SCAN_LUN: 822 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 823 pccb->ccb_h.status = CAM_REQ_INVALID; 824 xpt_done(pccb); 825 break; 826 827 /* 828 * Get/Set transfer rate/width/disconnection/tag queueing 829 * settings 830 * (GET) default/user transfer settings for the target 831 */ 832 case XPT_GET_TRAN_SETTINGS: { 833 struct ccb_trans_settings *cts; 834 int intflag; 835 struct trm_transinfo *tinfo; 836 PDCB pDCB; 837 838 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 839 cts = &pccb->cts; 840 pDCB = &pACB->DCBarray[target_id][target_lun]; 841 intflag = splcam(); 842 /* 843 * disable interrupt 844 */ 845 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 846 /* current transfer settings */ 847 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 848 cts->flags = CCB_TRANS_DISC_ENB; 849 else 850 cts->flags = 0;/* no tag & disconnect */ 851 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 852 cts->flags |= CCB_TRANS_TAG_ENB; 853 tinfo = &pDCB->tinfo.current; 854 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 855 cts->flags); 856 } else { 857 /* default(user) transfer settings */ 858 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 859 cts->flags = CCB_TRANS_DISC_ENB; 860 else 861 cts->flags = 0; 862 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 863 cts->flags |= CCB_TRANS_TAG_ENB; 864 tinfo = &pDCB->tinfo.user; 865 TRM_DPRINTF("USER: cts->flags= %2x \n", 866 cts->flags); 867 } 868 cts->sync_period = tinfo->period; 869 cts->sync_offset = tinfo->offset; 870 cts->bus_width = tinfo->width; 871 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 872 pDCB->SyncPeriod); 873 TRM_DPRINTF("period: %d \n", tinfo->period); 874 TRM_DPRINTF("offset: %d \n", tinfo->offset); 875 TRM_DPRINTF("width: %d \n", tinfo->width); 876 877 splx(intflag); 878 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 879 CCB_TRANS_SYNC_OFFSET_VALID | 880 CCB_TRANS_BUS_WIDTH_VALID | 881 CCB_TRANS_DISC_VALID | 882 CCB_TRANS_TQ_VALID; 883 pccb->ccb_h.status = CAM_REQ_CMP; 884 xpt_done(pccb); 885 } 886 break; 887 /* 888 * Get/Set transfer rate/width/disconnection/tag queueing 889 * settings 890 * (Set) transfer rate/width negotiation settings 891 */ 892 case XPT_SET_TRAN_SETTINGS: { 893 struct ccb_trans_settings *cts; 894 u_int update_type; 895 int intflag; 896 PDCB pDCB; 897 898 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 899 cts = &pccb->cts; 900 update_type = 0; 901 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 902 update_type |= TRM_TRANS_GOAL; 903 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 904 update_type |= TRM_TRANS_USER; 905 intflag = splcam(); 906 pDCB = &pACB->DCBarray[target_id][target_lun]; 907 908 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 909 /*ccb disc enables */ 910 if (update_type & TRM_TRANS_GOAL) { 911 if ((cts->flags & CCB_TRANS_DISC_ENB) 912 != 0) 913 pDCB->tinfo.disc_tag 914 |= TRM_CUR_DISCENB; 915 else 916 pDCB->tinfo.disc_tag &= 917 ~TRM_CUR_DISCENB; 918 } 919 if (update_type & TRM_TRANS_USER) { 920 if ((cts->flags & CCB_TRANS_DISC_ENB) 921 != 0) 922 pDCB->tinfo.disc_tag 923 |= TRM_USR_DISCENB; 924 else 925 pDCB->tinfo.disc_tag &= 926 ~TRM_USR_DISCENB; 927 } 928 } 929 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 930 /* if ccb tag q active */ 931 if (update_type & TRM_TRANS_GOAL) { 932 if ((cts->flags & CCB_TRANS_TAG_ENB) 933 != 0) 934 pDCB->tinfo.disc_tag |= 935 TRM_CUR_TAGENB; 936 else 937 pDCB->tinfo.disc_tag &= 938 ~TRM_CUR_TAGENB; 939 } 940 if (update_type & TRM_TRANS_USER) { 941 if ((cts->flags & CCB_TRANS_TAG_ENB) 942 != 0) 943 pDCB->tinfo.disc_tag |= 944 TRM_USR_TAGENB; 945 else 946 pDCB->tinfo.disc_tag &= 947 ~TRM_USR_TAGENB; 948 } 949 } 950 /* Minimum sync period factor */ 951 952 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 953 /* if ccb sync active */ 954 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 955 if ((cts->sync_period != 0) && 956 (cts->sync_period < 125)) 957 cts->sync_period = 125; 958 /* 1/(125*4) minsync 2 MByte/sec */ 959 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 960 != 0) { 961 if (cts->sync_offset == 0) 962 cts->sync_period = 0; 963 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 964 if (cts->sync_offset > 15) 965 cts->sync_offset = 15; 966 } 967 } 968 if ((update_type & TRM_TRANS_USER) != 0) { 969 pDCB->tinfo.user.period = cts->sync_period; 970 pDCB->tinfo.user.offset = cts->sync_offset; 971 pDCB->tinfo.user.width = cts->bus_width; 972 } 973 if ((update_type & TRM_TRANS_GOAL) != 0) { 974 pDCB->tinfo.goal.period = cts->sync_period; 975 pDCB->tinfo.goal.offset = cts->sync_offset; 976 pDCB->tinfo.goal.width = cts->bus_width; 977 } 978 splx(intflag); 979 pccb->ccb_h.status = CAM_REQ_CMP; 980 xpt_done(pccb); 981 break; 982 } 983 /* 984 * Calculate the geometry parameters for a device give 985 * the sector size and volume size. 986 */ 987 case XPT_CALC_GEOMETRY: 988 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 989 cam_calc_geometry(&pccb->ccg, /*extended*/1); 990 xpt_done(pccb); 991 break; 992 case XPT_ENG_INQ: 993 TRM_DPRINTF(" XPT_ENG_INQ \n"); 994 pccb->ccb_h.status = CAM_REQ_INVALID; 995 xpt_done(pccb); 996 break; 997 /* 998 * HBA execute engine request 999 * This structure must match SCSIIO size 1000 */ 1001 case XPT_ENG_EXEC: 1002 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1003 pccb->ccb_h.status = CAM_REQ_INVALID; 1004 xpt_done(pccb); 1005 break; 1006 /* 1007 * XPT_EN_LUN = 0x30, Enable LUN as a target 1008 * Target mode structures. 1009 */ 1010 case XPT_EN_LUN: 1011 /* 1012 * Don't (yet?) support vendor 1013 * specific commands. 1014 */ 1015 TRM_DPRINTF(" XPT_EN_LUN \n"); 1016 pccb->ccb_h.status = CAM_REQ_INVALID; 1017 xpt_done(pccb); 1018 break; 1019 /* 1020 * Execute target I/O request 1021 */ 1022 case XPT_TARGET_IO: 1023 /* 1024 * Don't (yet?) support vendor 1025 * specific commands. 1026 */ 1027 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1028 pccb->ccb_h.status = CAM_REQ_INVALID; 1029 xpt_done(pccb); 1030 break; 1031 /* 1032 * Accept Host Target Mode CDB 1033 */ 1034 case XPT_ACCEPT_TARGET_IO: 1035 /* 1036 * Don't (yet?) support vendor 1037 * specific commands. 1038 */ 1039 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1040 pccb->ccb_h.status = CAM_REQ_INVALID; 1041 xpt_done(pccb); 1042 break; 1043 /* 1044 * Continue Host Target I/O Connection 1045 */ 1046 case XPT_CONT_TARGET_IO: 1047 /* 1048 * Don't (yet?) support vendor 1049 * specific commands. 1050 */ 1051 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1052 pccb->ccb_h.status = CAM_REQ_INVALID; 1053 xpt_done(pccb); 1054 break; 1055 /* 1056 * Notify Host Target driver of event 1057 */ 1058 case XPT_IMMED_NOTIFY: 1059 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1060 pccb->ccb_h.status = CAM_REQ_INVALID; 1061 xpt_done(pccb); 1062 break; 1063 /* 1064 * Acknowledgement of event 1065 */ 1066 case XPT_NOTIFY_ACK: 1067 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1068 pccb->ccb_h.status = CAM_REQ_INVALID; 1069 xpt_done(pccb); 1070 break; 1071 /* 1072 * XPT_VUNIQUE = 0x80 1073 */ 1074 case XPT_VUNIQUE: 1075 pccb->ccb_h.status = CAM_REQ_INVALID; 1076 xpt_done(pccb); 1077 break; 1078 default: 1079 pccb->ccb_h.status = CAM_REQ_INVALID; 1080 xpt_done(pccb); 1081 break; 1082 } 1083 splx(actionflags); 1084} 1085 1086static void 1087trm_poll(struct cam_sim *psim) 1088{ 1089 1090} 1091 1092static void 1093trm_ResetDevParam(PACB pACB) 1094{ 1095 PDCB pDCB, pdcb; 1096 PNVRAMTYPE pEEpromBuf; 1097 u_int8_t PeriodIndex; 1098 1099 pDCB = pACB->pLinkDCB; 1100 if (pDCB == NULL) 1101 return; 1102 pdcb = pDCB; 1103 do { 1104 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1105 pDCB->SyncPeriod = 0; 1106 pDCB->SyncOffset = 0; 1107 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1108 pDCB->DevMode = 1109 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1110 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1111 PeriodIndex = 1112 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1113 if (pACB->AdaptType == 1) /* is U2? */ 1114 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1115 else 1116 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1117 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1118 (pACB->Config & HCC_WIDE_CARD)) 1119 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1120 pDCB = pDCB->pNextDCB; 1121 } 1122 while (pdcb != pDCB); 1123} 1124 1125static void 1126trm_RecoverSRB(PACB pACB) 1127{ 1128 PDCB pDCB, pdcb; 1129 PSRB psrb, psrb2; 1130 u_int16_t cnt, i; 1131 1132 pDCB = pACB->pLinkDCB; 1133 if (pDCB == NULL) 1134 return; 1135 pdcb = pDCB; 1136 do { 1137 cnt = pdcb->GoingSRBCnt; 1138 psrb = pdcb->pGoingSRB; 1139 for (i = 0; i < cnt; i++) { 1140 psrb2 = psrb; 1141 psrb = psrb->pNextSRB; 1142 if (pdcb->pWaitingSRB) { 1143 psrb2->pNextSRB = pdcb->pWaitingSRB; 1144 pdcb->pWaitingSRB = psrb2; 1145 } else { 1146 pdcb->pWaitingSRB = psrb2; 1147 pdcb->pWaitingLastSRB = psrb2; 1148 psrb2->pNextSRB = NULL; 1149 } 1150 } 1151 pdcb->GoingSRBCnt = 0; 1152 pdcb->pGoingSRB = NULL; 1153 pdcb = pdcb->pNextDCB; 1154 } 1155 while (pdcb != pDCB); 1156} 1157 1158static void 1159trm_reset(PACB pACB) 1160{ 1161 int intflag; 1162 u_int16_t i; 1163 1164 TRM_DPRINTF("trm: RESET"); 1165 intflag = splcam(); 1166 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1167 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1168 1169 trm_ResetSCSIBus(pACB); 1170 for (i = 0; i < 500; i++) 1171 DELAY(1000); 1172 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1173 /* Enable DMA interrupt */ 1174 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1175 /* Clear DMA FIFO */ 1176 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1177 /* Clear SCSI FIFO */ 1178 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1179 trm_ResetDevParam(pACB); 1180 trm_DoingSRB_Done(pACB); 1181 pACB->pActiveDCB = NULL; 1182 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1183 trm_DoWaitingSRB(pACB); 1184 /* Tell the XPT layer that a bus reset occured */ 1185 if (pACB->ppath != NULL) 1186 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1187 splx(intflag); 1188 return; 1189} 1190 1191static u_int16_t 1192trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1193{ 1194 u_int16_t return_code; 1195 u_int8_t scsicommand, i,command,identify_message; 1196 u_int8_t * ptr; 1197 union ccb *pccb; 1198 struct ccb_scsiio *pcsio; 1199 1200 pccb = pSRB->pccb; 1201 pcsio = &pccb->csio; 1202 1203 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1204 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1205 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1206 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1207 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1208 /* Flush FIFO */ 1209 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1210 1211 identify_message = pDCB->IdentifyMsg; 1212 1213 if ((pSRB->CmdBlock[0] == INQUIRY) || 1214 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1215 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1216 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1217 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1218 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1219 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1220 if (!(pDCB->IdentifyMsg & 7) || 1221 (pSRB->CmdBlock[0] != INQUIRY)) { 1222 scsicommand = SCMD_SEL_ATNSTOP; 1223 pSRB->SRBState = SRB_MSGOUT; 1224 goto polling; 1225 } 1226 } 1227 /* 1228 * Send identify message 1229 */ 1230 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1231 scsicommand = SCMD_SEL_ATN; 1232 pSRB->SRBState = SRB_START_; 1233 } else { 1234 /* not inquiry,request sense,auto request sense */ 1235 /* 1236 * Send identify message 1237 */ 1238 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1239 scsicommand = SCMD_SEL_ATN; 1240 pSRB->SRBState = SRB_START_; 1241 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1242 /* Send Tag message */ 1243 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1244 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1245 scsicommand = SCMD_SEL_ATN3; 1246 } 1247 } 1248polling: 1249 /* 1250 * Send CDB ..command block ......... 1251 */ 1252 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1253 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1254 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1255 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1256 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1257 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1258 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1259 } else { 1260 ptr = (u_int8_t *) pSRB->CmdBlock; 1261 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1262 command = *ptr++; 1263 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1264 } 1265 } 1266 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1267 /* 1268 * If trm_StartSCSI return 1 : 1269 * current interrupt status is interrupt disreenable 1270 * It's said that SCSI processor has more one SRB need to do, 1271 * SCSI processor has been occupied by one SRB. 1272 */ 1273 pSRB->SRBState = SRB_READY; 1274 return_code = 1; 1275 } else { 1276 /* 1277 * If trm_StartSCSI return 0 : 1278 * current interrupt status is interrupt enable 1279 * It's said that SCSI processor is unoccupied 1280 */ 1281 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1282 pACB->pActiveDCB = pDCB; 1283 pDCB->pActiveSRB = pSRB; 1284 return_code = 0; 1285 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1286 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1287 /* 1288 * SCSI cammand 1289 */ 1290 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1291 } 1292 return (return_code); 1293} 1294 1295static void 1296trm_Interrupt(vpACB) 1297void *vpACB; 1298{ 1299 PACB pACB; 1300 PDCB pDCB; 1301 PSRB pSRB; 1302 u_int16_t phase; 1303 void (*stateV)(PACB, PSRB, u_int16_t *); 1304 u_int16_t scsi_status=0; 1305 u_int8_t scsi_intstatus; 1306 1307 pACB = vpACB; 1308 1309 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1310 if (!(scsi_status & SCSIINTERRUPT)) { 1311 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1312 return; 1313 } 1314 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1315 1316 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1317 1318 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1319 1320 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1321 trm_Disconnect(pACB); 1322 return; 1323 } 1324 1325 if (scsi_intstatus & INT_RESELECTED) { 1326 trm_Reselect(pACB); 1327 return; 1328 } 1329 if (scsi_intstatus & INT_SCSIRESET) { 1330 trm_ScsiRstDetect(pACB); 1331 return; 1332 } 1333 1334 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1335 pDCB = pACB->pActiveDCB; 1336 pSRB = pDCB->pActiveSRB; 1337 if (pDCB) { 1338 if (pDCB->DCBFlag & ABORT_DEV_) 1339 trm_EnableMsgOutAbort1(pACB, pSRB); 1340 } 1341 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1342 stateV = (void *) trm_SCSI_phase0[phase]; 1343 stateV(pACB, pSRB, &scsi_status); 1344 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1345 /* phase:0,1,2,3,4,5,6,7 */ 1346 phase = (u_int16_t) scsi_status & PHASEMASK; 1347 stateV = (void *) trm_SCSI_phase1[phase]; 1348 stateV(pACB, pSRB, &scsi_status); 1349 } 1350} 1351 1352static void 1353trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1354{ 1355 1356 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1357 *pscsi_status = PH_BUS_FREE; 1358 /*.. initial phase*/ 1359} 1360 1361static void 1362trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1363{ 1364 u_int8_t bval; 1365 u_int16_t i, cnt; 1366 u_int8_t * ptr; 1367 PDCB pDCB; 1368 1369 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1370 pDCB = pACB->pActiveDCB; 1371 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1372 cnt = pSRB->MsgCnt; 1373 if (cnt) { 1374 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1375 for (i = 0; i < cnt; i++) { 1376 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1377 ptr++; 1378 } 1379 pSRB->MsgCnt = 0; 1380 if ((pDCB->DCBFlag & ABORT_DEV_) && 1381 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1382 pSRB->SRBState = SRB_ABORT_SENT; 1383 } 1384 } else { 1385 bval = MSG_ABORT; 1386 if ((pSRB->CmdBlock[0] == INQUIRY) || 1387 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1388 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1389 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1390 goto mop1; 1391 } 1392 } 1393 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1394 } 1395 } else { 1396mop1: /* message out phase */ 1397 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1398 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1399 /* 1400 * WIDE DATA TRANSFER REQUEST code (03h) 1401 */ 1402 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1403 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1404 TRMREG_SCSI_FIFO); 1405 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1406 /* (01h) */ 1407 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1408 /* Message length (02h) */ 1409 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1410 /* wide data xfer (03h) */ 1411 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1412 /* width:0(8bit),1(16bit),2(32bit) */ 1413 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1414 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1415 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1416 /* 1417 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1418 */ 1419 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1420 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1421 TRMREG_SCSI_FIFO); 1422 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1423 /* (01h) */ 1424 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1425 /* Message length (03h) */ 1426 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1427 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1428 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1429 /* Transfer peeriod factor */ 1430 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1431 TRMREG_SCSI_FIFO); 1432 /* REQ/ACK offset */ 1433 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1434 } 1435 } 1436 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1437 /* it's important for atn stop */ 1438 /* 1439 * SCSI cammand 1440 */ 1441 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1442} 1443 1444static void 1445trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1446{ 1447 1448} 1449 1450static void 1451trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1452{ 1453 PDCB pDCB; 1454 u_int8_t * ptr; 1455 u_int16_t i, cnt; 1456 union ccb *pccb; 1457 struct ccb_scsiio *pcsio; 1458 1459 pccb = pSRB->pccb; 1460 pcsio = &pccb->csio; 1461 1462 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1463 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1464 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1465 ptr = (u_int8_t *) pSRB->CmdBlock; 1466 for (i = 0; i < cnt; i++) { 1467 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1468 ptr++; 1469 } 1470 } else { 1471 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1472 pDCB = pACB->pActiveDCB; 1473 /* target id */ 1474 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1475 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1476 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1477 /* sizeof(struct scsi_sense_data) */ 1478 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1479 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1480 } 1481 pSRB->SRBState = SRB_COMMAND; 1482 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1483 /* it's important for atn stop*/ 1484 /* 1485 * SCSI cammand 1486 */ 1487 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1488} 1489 1490static void 1491trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1492{ 1493 PDCB pDCB; 1494 u_int8_t TempDMAstatus,SGIndexTemp; 1495 u_int16_t scsi_status; 1496 PSEG pseg; 1497 u_long TempSRBXferredLength,dLeftCounter=0; 1498 1499 pDCB = pSRB->pSRBDCB; 1500 scsi_status = *pscsi_status; 1501 1502 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1503 if (scsi_status & PARITYERROR) 1504 pSRB->SRBStatus |= PARITY_ERROR; 1505 if (!(scsi_status & SCSIXFERDONE)) { 1506 /* 1507 * when data transfer from DMA FIFO to SCSI FIFO 1508 * if there was some data left in SCSI FIFO 1509 */ 1510 dLeftCounter = (u_long) 1511 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1512 if (pDCB->SyncPeriod & WIDE_SYNC) { 1513 /* 1514 * if WIDE scsi SCSI FIFOCNT unit is word 1515 * so need to * 2 1516 */ 1517 dLeftCounter <<= 1; 1518 } 1519 } 1520 /* 1521 * caculate all the residue data that not yet tranfered 1522 * SCSI transfer counter + left in SCSI FIFO data 1523 * 1524 * .....TRM_SCSI_COUNTER (24bits) 1525 * The counter always decrement by one for every SCSI byte 1526 *transfer. 1527 * .....TRM_SCSI_FIFOCNT (5bits) 1528 * The counter is SCSI FIFO offset counter 1529 */ 1530 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1531 if (dLeftCounter == 1) { 1532 dLeftCounter = 0; 1533 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1534 } 1535 if ((dLeftCounter == 0) || 1536 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1537 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1538 while (!(TempDMAstatus & DMAXFERCOMP)) { 1539 TempDMAstatus = 1540 trm_reg_read8(TRMREG_DMA_STATUS); 1541 } 1542 pSRB->SRBTotalXferLength = 0; 1543 } else { 1544 /* Update SG list */ 1545 /* 1546 * if transfer not yet complete 1547 * there were some data residue in SCSI FIFO or 1548 * SCSI transfer counter not empty 1549 */ 1550 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1551 /* 1552 * data that had transferred length 1553 */ 1554 TempSRBXferredLength = 1555 pSRB->SRBTotalXferLength - dLeftCounter; 1556 /* 1557 * next time to be transferred length 1558 */ 1559 pSRB->SRBTotalXferLength = dLeftCounter; 1560 /* 1561 * parsing from last time disconnect SRBSGIndex 1562 */ 1563 pseg = 1564 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1565 for (SGIndexTemp = pSRB->SRBSGIndex; 1566 SGIndexTemp < pSRB->SRBSGCount; 1567 SGIndexTemp++) { 1568 /* 1569 * find last time which SG transfer be 1570 * disconnect 1571 */ 1572 if (TempSRBXferredLength >= 1573 pseg->length) 1574 TempSRBXferredLength -= 1575 pseg->length; 1576 else { 1577 /* 1578 * update last time disconnected SG 1579 * list 1580 */ 1581 pseg->length -= 1582 TempSRBXferredLength; 1583 /* residue data length */ 1584 pseg->address += 1585 TempSRBXferredLength; 1586 /* residue data pointer */ 1587 pSRB->SRBSGIndex = SGIndexTemp; 1588 break; 1589 } 1590 pseg++; 1591 } 1592 } 1593 } 1594 } 1595 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1596} 1597 1598 1599static void 1600trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1601{ 1602 u_int16_t ioDir; 1603 /* 1604 * do prepare befor transfer when data out phase 1605 */ 1606 1607 ioDir = XFERDATAOUT; 1608 trm_DataIO_transfer(pACB, pSRB, ioDir); 1609} 1610 1611static void 1612trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1613{ 1614 u_int8_t TempDMAstatus, SGIndexTemp; 1615 u_int16_t scsi_status; 1616 PSEG pseg; 1617 u_long TempSRBXferredLength,dLeftCounter = 0; 1618 1619 scsi_status = *pscsi_status; 1620 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1621 if (scsi_status & PARITYERROR) 1622 pSRB->SRBStatus |= PARITY_ERROR; 1623 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1624 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1625 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1626 while (!(TempDMAstatus & DMAXFERCOMP)) 1627 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1628 pSRB->SRBTotalXferLength = 0; 1629 } else { 1630 /* 1631 * parsing the case: 1632 * when a transfer not yet complete 1633 * but be disconnected by uper layer 1634 * if transfer not yet complete 1635 * there were some data residue in SCSI FIFO or 1636 * SCSI transfer counter not empty 1637 */ 1638 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1639 /* 1640 * data that had transferred length 1641 */ 1642 TempSRBXferredLength = 1643 pSRB->SRBTotalXferLength - dLeftCounter; 1644 /* 1645 * next time to be transferred length 1646 */ 1647 pSRB->SRBTotalXferLength = dLeftCounter; 1648 /* 1649 * parsing from last time disconnect SRBSGIndex 1650 */ 1651 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1652 for (SGIndexTemp = pSRB->SRBSGIndex; 1653 SGIndexTemp < pSRB->SRBSGCount; 1654 SGIndexTemp++) { 1655 /* 1656 * find last time which SG transfer be disconnect 1657 */ 1658 if (TempSRBXferredLength >= pseg->length) 1659 TempSRBXferredLength -= pseg->length; 1660 else { 1661 /* 1662 * update last time disconnected SG list 1663 */ 1664 pseg->length -= TempSRBXferredLength; 1665 /* residue data length */ 1666 pseg->address += TempSRBXferredLength; 1667 /* residue data pointer */ 1668 pSRB->SRBSGIndex = SGIndexTemp; 1669 break; 1670 } 1671 pseg++; 1672 } 1673 } 1674 } 1675 } 1676} 1677 1678static void 1679trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1680{ 1681 u_int16_t ioDir; 1682 /* 1683 * do prepare befor transfer when data in phase 1684 */ 1685 1686 ioDir = XFERDATAIN; 1687 trm_DataIO_transfer(pACB, pSRB, ioDir); 1688} 1689 1690static void 1691trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1692{ 1693 u_int8_t bval; 1694 PDCB pDCB; 1695 1696 pDCB = pSRB->pSRBDCB; 1697 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1698 if (pSRB->SRBTotalXferLength != 0) { 1699 /* 1700 * load what physical address of Scatter/Gather list 1701 table want to be transfer 1702 */ 1703 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1704 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1705 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1706 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1707 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1708 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1709 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1710 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1711 1712 pSRB->SRBState = SRB_DATA_XFER; 1713 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1714 trm_reg_write32( 1715 (pSRB->SRBSGPhyAddr + 1716 ((u_long)pSRB->SRBSGIndex << 3)), 1717 TRMREG_DMA_XLOWADDR); 1718 /* 1719 * load how many bytes in the Scatter/Gather 1720 * list table 1721 */ 1722 trm_reg_write32( 1723 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1724 TRMREG_DMA_XCNT); 1725 /* 1726 * load total transfer length (24bits) max value 1727 * 16Mbyte 1728 */ 1729 trm_reg_write32(pSRB->SRBTotalXferLength, 1730 TRMREG_SCSI_COUNTER); 1731 /* Start DMA transfer */ 1732 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1733 /* Start SCSI transfer */ 1734 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1735 /* it's important for atn stop */ 1736 /* 1737 * SCSI cammand 1738 */ 1739 bval = (ioDir == XFERDATAOUT) ? 1740 SCMD_DMA_OUT : SCMD_DMA_IN; 1741 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1742 } else { 1743 /* xfer pad */ 1744 if (pSRB->SRBSGCount) { 1745 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1746 pSRB->SRBStatus |= OVER_RUN; 1747 } 1748 if (pDCB->SyncPeriod & WIDE_SYNC) 1749 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1750 else 1751 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1752 if (ioDir == XFERDATAOUT) 1753 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1754 else 1755 trm_reg_read16(TRMREG_SCSI_FIFO); 1756 pSRB->SRBState |= SRB_XFERPAD; 1757 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1758 /* it's important for atn stop */ 1759 /* 1760 * SCSI cammand 1761 */ 1762 bval = (ioDir == XFERDATAOUT) ? 1763 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1764 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1765 } 1766 } 1767} 1768 1769static void 1770trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1771{ 1772 1773 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1774 pSRB->SRBState = SRB_COMPLETED; 1775 *pscsi_status = PH_BUS_FREE; 1776 /*.. initial phase*/ 1777 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1778 /* it's important for atn stop */ 1779 /* 1780 * SCSI cammand 1781 */ 1782 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1783} 1784 1785 1786 1787static void 1788trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1789{ 1790 1791 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1792 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1793 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1794 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1795 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1796 } else { 1797 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1798 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1799 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1800 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1801 } 1802 pSRB->SRBState = SRB_STATUS; 1803 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1804 /* it's important for atn stop */ 1805 /* 1806 * SCSI cammand 1807 */ 1808 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1809} 1810 1811/* 1812 *scsiiom 1813 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1814 * stateV = (void *) trm_SCSI_phase0[phase] 1815 * if phase =7 1816 * extended message codes: 1817 * 1818 * code description 1819 * 1820 * 02h Reserved 1821 * 00h MODIFY DATA POINTER 1822 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1823 * 03h WIDE DATA TRANSFER REQUEST 1824 * 04h - 7Fh Reserved 1825 * 80h - FFh Vendor specific 1826 * 1827 */ 1828 1829static void 1830trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1831{ 1832 u_int8_t message_in_code,bIndex,message_in_tag_id; 1833 PDCB pDCB; 1834 PSRB pSRBTemp; 1835 1836 pDCB = pACB->pActiveDCB; 1837 1838 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1839 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1840 if (message_in_code == MSG_DISCONNECT) { 1841 pSRB->SRBState = SRB_DISCONNECT; 1842 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1843 /* it's important for atn stop */ 1844 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1845 /* 1846 * SCSI command 1847 */ 1848 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1849 return; 1850 } else if (message_in_code == MSG_SAVE_PTR) { 1851 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1852 /* it's important for atn stop */ 1853 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1854 /* 1855 * SCSI command 1856 */ 1857 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1858 return; 1859 } else if ((message_in_code == MSG_EXTENDED) || 1860 ((message_in_code >= MSG_SIMPLE_QTAG) && 1861 (message_in_code <= MSG_ORDER_QTAG))) { 1862 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1863 pSRB->MsgInBuf[0] = message_in_code; 1864 /* extended message (01h) */ 1865 pSRB->MsgCnt = 1; 1866 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1867 /* extended message length (n) */ 1868 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1869 /* it's important for atn stop */ 1870 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1871 /* 1872 * SCSI command 1873 */ 1874 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1875 return; 1876 } else if (message_in_code == MSG_REJECT_) { 1877 /* Reject message */ 1878 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1879 /* do wide nego reject */ 1880 pDCB = pSRB->pSRBDCB; 1881 pDCB->SyncMode |= WIDE_NEGO_DONE; 1882 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1883 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1884 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1885 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1886 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1887 /* Set ATN, in case ATN was clear */ 1888 pSRB->SRBState |= SRB_MSGOUT; 1889 trm_reg_write16( 1890 DO_SETATN, 1891 TRMREG_SCSI_CONTROL); 1892 } else { 1893 /* Clear ATN */ 1894 trm_reg_write16( 1895 DO_CLRATN, 1896 TRMREG_SCSI_CONTROL); 1897 } 1898 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1899 /* do sync nego reject */ 1900 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1901 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1902 pDCB = pSRB->pSRBDCB; 1903 pDCB->SyncMode &= 1904 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1905 pDCB->SyncPeriod = 0; 1906 pDCB->SyncOffset = 0; 1907 /* 1908 * 1909 * program SCSI control register 1910 * 1911 */ 1912 trm_reg_write8(pDCB->SyncPeriod, 1913 TRMREG_SCSI_SYNC); 1914 trm_reg_write8(pDCB->SyncOffset, 1915 TRMREG_SCSI_OFFSET); 1916 trm_SetXferRate(pACB,pSRB,pDCB); 1917 } 1918 } 1919 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1920 /* it's important for atn stop */ 1921 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1922 /* 1923 * SCSI command 1924 */ 1925 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1926 return; 1927 } else if (message_in_code == MSG_IGNOREWIDE) { 1928 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1929 trm_reg_read8(TRMREG_SCSI_FIFO); 1930 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1931 /* it's important for atn stop */ 1932 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1933 /* 1934 * SCSI command 1935 */ 1936 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1937 return; 1938 } else { 1939 /* Restore data pointer message */ 1940 /* Save data pointer message */ 1941 /* Completion message */ 1942 /* NOP message */ 1943 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1944 /* it's important for atn stop */ 1945 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1946 /* 1947 * SCSI command 1948 */ 1949 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1950 return; 1951 } 1952 } else { 1953 /* 1954 * Parsing incomming extented messages 1955 */ 1956 *pSRB->pMsgPtr = message_in_code; 1957 pSRB->MsgCnt++; 1958 pSRB->pMsgPtr++; 1959 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1960 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1961 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1962 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1963 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1964 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1965 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1966 /* 1967 * is QUEUE tag message : 1968 * 1969 * byte 0: 1970 * HEAD QUEUE TAG (20h) 1971 * ORDERED QUEUE TAG (21h) 1972 * SIMPLE QUEUE TAG (22h) 1973 * byte 1: 1974 * Queue tag (00h - FFh) 1975 */ 1976 if (pSRB->MsgCnt == 2) { 1977 pSRB->SRBState = 0; 1978 message_in_tag_id = pSRB->MsgInBuf[1]; 1979 pSRB = pDCB->pGoingSRB; 1980 pSRBTemp = pDCB->pGoingLastSRB; 1981 if (pSRB) { 1982 for (;;) { 1983 if (pSRB->TagNumber != 1984 message_in_tag_id) { 1985 if (pSRB == pSRBTemp) { 1986 goto mingx0; 1987 } 1988 pSRB = pSRB->pNextSRB; 1989 } else 1990 break; 1991 } 1992 if (pDCB->DCBFlag & ABORT_DEV_) { 1993 pSRB->SRBState = SRB_ABORT_SENT; 1994 trm_EnableMsgOutAbort1( 1995 pACB, pSRB); 1996 } 1997 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1998 TRM_DPRINTF("SRB not yet disconnect........ \n "); 1999 goto mingx0; 2000 } 2001 pDCB->pActiveSRB = pSRB; 2002 pSRB->SRBState = SRB_DATA_XFER; 2003 } else { 2004mingx0: 2005 pSRB = &pACB->TmpSRB; 2006 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2007 pDCB->pActiveSRB = pSRB; 2008 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2009 trm_EnableMsgOutAbort2( 2010 pACB, 2011 pSRB); 2012 } 2013 } 2014 *pscsi_status = PH_BUS_FREE; 2015 /* .. initial phase */ 2016 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2017 /* it's important for atn stop */ 2018 /* 2019 * SCSI command 2020 */ 2021 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2022 return; 2023 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2024 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2025 /* 2026 * is Wide data xfer Extended message : 2027 * ====================================== 2028 * WIDE DATA TRANSFER REQUEST 2029 * ====================================== 2030 * byte 0 : Extended message (01h) 2031 * byte 1 : Extended message length (02h) 2032 * byte 2 : WIDE DATA TRANSFER code (03h) 2033 * byte 3 : Transfer width exponent 2034 */ 2035 pDCB = pSRB->pSRBDCB; 2036 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2037 if ((pSRB->MsgInBuf[1] != 2)) { 2038 /* Length is wrong, reject it */ 2039 pDCB->SyncMode &= 2040 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2041 pSRB->MsgCnt = 1; 2042 pSRB->MsgInBuf[0] = MSG_REJECT_; 2043 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2044 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2045 /* it's important for atn stop */ 2046 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2047 /* 2048 * SCSI command 2049 */ 2050 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2051 return; 2052 } 2053 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2054 /* Do wide negoniation */ 2055 if (pSRB->MsgInBuf[3] > 2) { 2056 /* > 32 bit */ 2057 /* reject_msg: */ 2058 pDCB->SyncMode &= 2059 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2060 pSRB->MsgCnt = 1; 2061 pSRB->MsgInBuf[0] = MSG_REJECT_; 2062 trm_reg_write16(DO_SETATN, 2063 TRMREG_SCSI_CONTROL); 2064 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2065 /* it's important for atn stop */ 2066 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2067 /* 2068 * SCSI command 2069 */ 2070 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2071 return; 2072 } 2073 if (pSRB->MsgInBuf[3] == 2) { 2074 pSRB->MsgInBuf[3] = 1; 2075 /* do 16 bits */ 2076 } else { 2077 if (!(pDCB->SyncMode 2078 & WIDE_NEGO_DONE)) { 2079 pSRB->SRBState &= 2080 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2081 pDCB->SyncMode |= 2082 WIDE_NEGO_DONE; 2083 pDCB->SyncMode &= 2084 ~(SYNC_NEGO_DONE | 2085 EN_ATN_STOP | 2086 WIDE_NEGO_ENABLE); 2087 if (pSRB->MsgInBuf[3] != 0) { 2088 /* is Wide data xfer */ 2089 pDCB->SyncPeriod |= 2090 WIDE_SYNC; 2091 pDCB->tinfo.current.width 2092 = MSG_EXT_WDTR_BUS_16_BIT; 2093 pDCB->tinfo.goal.width 2094 = MSG_EXT_WDTR_BUS_16_BIT; 2095 } 2096 } 2097 } 2098 } else 2099 pSRB->MsgInBuf[3] = 0; 2100 pSRB->SRBState |= SRB_MSGOUT; 2101 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2102 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2103 /* it's important for atn stop */ 2104 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2105 /* 2106 * SCSI command 2107 */ 2108 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2109 return; 2110 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2111 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2112 /* 2113 * is 8bit transfer Extended message : 2114 * ================================= 2115 * SYNCHRONOUS DATA TRANSFER REQUEST 2116 * ================================= 2117 * byte 0 : Extended message (01h) 2118 * byte 1 : Extended message length (03) 2119 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2120 * byte 3 : Transfer period factor 2121 * byte 4 : REQ/ACK offset 2122 */ 2123 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2124 if ((pSRB->MsgInBuf[1] != 3) || 2125 (pSRB->MsgInBuf[2] != 1)) { 2126 /* reject_msg: */ 2127 pSRB->MsgCnt = 1; 2128 pSRB->MsgInBuf[0] = MSG_REJECT_; 2129 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2130 *pscsi_status = PH_BUS_FREE; 2131 /* .. initial phase */ 2132 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2133 /* it's important for atn stop */ 2134 /* 2135 * SCSI cammand 2136 */ 2137 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2138 return; 2139 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2140 /* set async */ 2141 pDCB = pSRB->pSRBDCB; 2142 /* disable sync & sync nego */ 2143 pDCB->SyncMode &= 2144 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2145 pDCB->SyncPeriod = 0; 2146 pDCB->SyncOffset = 0; 2147 pDCB->tinfo.goal.period = 0; 2148 pDCB->tinfo.goal.offset = 0; 2149 pDCB->tinfo.current.period = 0; 2150 pDCB->tinfo.current.offset = 0; 2151 pDCB->tinfo.current.width = 2152 MSG_EXT_WDTR_BUS_8_BIT; 2153 /* 2154 * 2155 * program SCSI control register 2156 * 2157 */ 2158 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2159 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2160 trm_SetXferRate(pACB,pSRB,pDCB); 2161 *pscsi_status = PH_BUS_FREE; 2162 /* .. initial phase */ 2163 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2164 /* it's important for atn stop */ 2165 /* 2166 * SCSI cammand 2167 */ 2168 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2169 return; 2170 } else { 2171 /* set sync */ 2172 pDCB = pSRB->pSRBDCB; 2173 pDCB->SyncMode |= 2174 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2175 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2176 /* Transfer period factor */ 2177 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2178 /* REQ/ACK offset */ 2179 if(pACB->AdaptType == 1) { 2180 for(bIndex = 0; bIndex < 7; bIndex++) { 2181 if(pSRB->MsgInBuf[3] <= 2182 dc395u2x_clock_period[bIndex]) { 2183 pDCB->tinfo.goal.period = 2184 dc395u2x_tinfo_period[bIndex]; 2185 pDCB->tinfo.current.period = 2186 dc395u2x_tinfo_period[bIndex]; 2187 pDCB->tinfo.goal.offset = 2188 pDCB->SyncOffset; 2189 pDCB->tinfo.current.offset = 2190 pDCB->SyncOffset; 2191 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2192 break; 2193 } 2194 } 2195 } else { 2196 for(bIndex = 0; bIndex < 7; bIndex++) { 2197 if(pSRB->MsgInBuf[3] <= 2198 dc395x_clock_period[bIndex]) { 2199 pDCB->tinfo.goal.period = 2200 dc395x_tinfo_period[bIndex]; 2201 pDCB->tinfo.current.period = 2202 dc395x_tinfo_period[bIndex]; 2203 pDCB->tinfo.goal.offset = 2204 pDCB->SyncOffset; 2205 pDCB->tinfo.current.offset = 2206 pDCB->SyncOffset; 2207 pDCB->SyncPeriod |= 2208 (bIndex|ALT_SYNC); 2209 break; 2210 } 2211 } 2212 } 2213 /* 2214 * 2215 * program SCSI control register 2216 * 2217 */ 2218 trm_reg_write8(pDCB->SyncPeriod, 2219 TRMREG_SCSI_SYNC); 2220 trm_reg_write8(pDCB->SyncOffset, 2221 TRMREG_SCSI_OFFSET); 2222 trm_SetXferRate(pACB,pSRB,pDCB); 2223 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2224 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2225 /* 2226 ** SCSI command 2227 */ 2228 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2229 return; 2230 } 2231 } 2232 *pscsi_status = PH_BUS_FREE; 2233 /* .. initial phase */ 2234 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2235 /* it's important for atn stop */ 2236 /* 2237 * SCSI cammand 2238 */ 2239 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2240 } 2241} 2242 2243static void 2244trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2245{ 2246 2247 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2248 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2249 if (!(pSRB->SRBState & SRB_MSGIN)) { 2250 pSRB->SRBState &= SRB_DISCONNECT; 2251 pSRB->SRBState |= SRB_MSGIN; 2252 } 2253 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2254 /* it's important for atn stop*/ 2255 /* 2256 * SCSI cammand 2257 */ 2258 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2259} 2260 2261static void 2262trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2263{ 2264 2265} 2266 2267static void 2268trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2269{ 2270 2271} 2272 2273static void 2274trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2275{ 2276 union ccb *pccb; 2277 struct ccb_trans_settings neg; 2278 u_int16_t cnt, i; 2279 u_int8_t bval; 2280 PDCB pDCBTemp; 2281 2282 /* 2283 * set all lun device's period , offset 2284 */ 2285 TRM_DPRINTF("trm_SetXferRate\n"); 2286 pccb = pSRB->pccb; 2287 neg.sync_period = pDCB->tinfo.goal.period; 2288 neg.sync_offset = pDCB->tinfo.goal.offset; 2289 neg.valid = CCB_TRANS_SYNC_RATE_VALID | CCB_TRANS_SYNC_OFFSET_VALID; 2290 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2291 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2292 if (!(pDCB->IdentifyMsg & 0x07)) { 2293 pDCBTemp = pACB->pLinkDCB; 2294 cnt = pACB->DeviceCnt; 2295 bval = pDCB->TargetID; 2296 for (i = 0; i < cnt; i++) { 2297 if (pDCBTemp->TargetID == bval) { 2298 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2299 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2300 pDCBTemp->SyncMode = pDCB->SyncMode; 2301 } 2302 pDCBTemp = pDCBTemp->pNextDCB; 2303 } 2304 } 2305 return; 2306} 2307 2308/* 2309 * scsiiom 2310 * trm_Interrupt 2311 * 2312 * 2313 * ---SCSI bus phase 2314 * 2315 * PH_DATA_OUT 0x00 Data out phase 2316 * PH_DATA_IN 0x01 Data in phase 2317 * PH_COMMAND 0x02 Command phase 2318 * PH_STATUS 0x03 Status phase 2319 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2320 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2321 * PH_MSG_OUT 0x06 Message out phase 2322 * PH_MSG_IN 0x07 Message in phase 2323 * 2324 */ 2325static void 2326trm_Disconnect(PACB pACB) 2327{ 2328 PDCB pDCB; 2329 PSRB pSRB, psrb; 2330 u_int16_t i,j, cnt; 2331 u_int target_id,target_lun; 2332 2333 TRM_DPRINTF("trm_Disconnect...............\n "); 2334 2335 pDCB = pACB->pActiveDCB; 2336 if (!pDCB) { 2337 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2338 j = 400; 2339 while (--j) 2340 DELAY(1); 2341 /* 1 msec */ 2342 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2343 TRMREG_SCSI_CONTROL); 2344 return; 2345 } 2346 pSRB = pDCB->pActiveSRB; 2347 /* bug pSRB=0 */ 2348 target_id = pSRB->pccb->ccb_h.target_id; 2349 target_lun = pSRB->pccb->ccb_h.target_lun; 2350 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2351 pACB->pActiveDCB = 0; 2352 pSRB->ScsiPhase = PH_BUS_FREE; 2353 /* SCSI bus free Phase */ 2354 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2355 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2356 pSRB->SRBState = 0; 2357 trm_DoWaitingSRB(pACB); 2358 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2359 pDCB->DCBFlag = 0; 2360 cnt = pDCB->GoingSRBCnt; 2361 pDCB->GoingSRBCnt = 0; 2362 pSRB = pDCB->pGoingSRB; 2363 for (i = 0; i < cnt; i++) { 2364 psrb = pSRB->pNextSRB; 2365 pSRB->pNextSRB = pACB->pFreeSRB; 2366 pACB->pFreeSRB = pSRB; 2367 pSRB = psrb; 2368 } 2369 pDCB->pGoingSRB = 0; 2370 trm_DoWaitingSRB(pACB); 2371 } else { 2372 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2373 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2374 /* Selection time out */ 2375 if (!(pACB->scan_devices[target_id][target_lun]) && 2376 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2377 pSRB->CmdBlock[0] != INQUIRY) { 2378 pSRB->SRBState = SRB_READY; 2379 trm_RewaitSRB(pDCB, pSRB); 2380 } else { 2381 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2382 goto disc1; 2383 } 2384 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2385 /* 2386 * SRB_DISCONNECT 2387 */ 2388 trm_DoWaitingSRB(pACB); 2389 } else if (pSRB->SRBState & SRB_COMPLETED) { 2390disc1: 2391 /* 2392 * SRB_COMPLETED 2393 */ 2394 pDCB->pActiveSRB = 0; 2395 pSRB->SRBState = SRB_FREE; 2396 trm_SRBdone(pACB, pDCB, pSRB); 2397 } 2398 } 2399 return; 2400} 2401 2402static void 2403trm_Reselect(PACB pACB) 2404{ 2405 PDCB pDCB; 2406 PSRB pSRB; 2407 u_int16_t RselTarLunId; 2408 2409 TRM_DPRINTF("trm_Reselect................. \n"); 2410 pDCB = pACB->pActiveDCB; 2411 if (pDCB) { 2412 /* Arbitration lost but Reselection win */ 2413 pSRB = pDCB->pActiveSRB; 2414 pSRB->SRBState = SRB_READY; 2415 trm_RewaitSRB(pDCB, pSRB); 2416 } 2417 /* Read Reselected Target Id and LUN */ 2418 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2419 pDCB = pACB->pLinkDCB; 2420 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2421 /* get pDCB of the reselect id */ 2422 pDCB = pDCB->pNextDCB; 2423 } 2424 2425 pACB->pActiveDCB = pDCB; 2426 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2427 pSRB = &pACB->TmpSRB; 2428 pDCB->pActiveSRB = pSRB; 2429 } else { 2430 pSRB = pDCB->pActiveSRB; 2431 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2432 /* 2433 * abort command 2434 */ 2435 pSRB = &pACB->TmpSRB; 2436 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2437 pDCB->pActiveSRB = pSRB; 2438 trm_EnableMsgOutAbort1(pACB, pSRB); 2439 } else { 2440 if (pDCB->DCBFlag & ABORT_DEV_) { 2441 pSRB->SRBState = SRB_ABORT_SENT; 2442 trm_EnableMsgOutAbort1(pACB, pSRB); 2443 } else 2444 pSRB->SRBState = SRB_DATA_XFER; 2445 } 2446 } 2447 pSRB->ScsiPhase = PH_BUS_FREE; 2448 /* SCSI bus free Phase */ 2449 /* 2450 * Program HA ID, target ID, period and offset 2451 */ 2452 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2453 /* target ID */ 2454 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2455 /* host ID */ 2456 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2457 /* period */ 2458 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2459 /* offset */ 2460 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2461 /* it's important for atn stop*/ 2462 /* 2463 * SCSI cammand 2464 */ 2465 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2466 /* to rls the /ACK signal */ 2467} 2468 2469static void 2470trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2471{ 2472 PSRB psrb; 2473 u_int8_t bval, bval1,status; 2474 union ccb *pccb; 2475 struct ccb_scsiio *pcsio; 2476 PSCSI_INQDATA ptr; 2477 int intflag; 2478 u_int target_id,target_lun; 2479 PDCB pTempDCB; 2480 2481 pccb = pSRB->pccb; 2482 if (pccb == NULL) 2483 return; 2484 pcsio = &pccb->csio; 2485 target_id = pSRB->pccb->ccb_h.target_id; 2486 target_lun = pSRB->pccb->ccb_h.target_lun; 2487 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2488 bus_dmasync_op_t op; 2489 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2490 op = BUS_DMASYNC_POSTREAD; 2491 else 2492 op = BUS_DMASYNC_POSTWRITE; 2493 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2494 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2495 } 2496 /* 2497 * 2498 * target status 2499 * 2500 */ 2501 status = pSRB->TargetStatus; 2502 pcsio->scsi_status=SCSI_STAT_GOOD; 2503 pccb->ccb_h.status = CAM_REQ_CMP; 2504 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2505 /* 2506 * status of auto request sense 2507 */ 2508 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2509 pSRB->AdaptStatus = 0; 2510 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2511 2512 if (status == SCSI_STATUS_CHECK_COND) { 2513 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2514 goto ckc_e; 2515 } 2516 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2517 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2518 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2519 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2520 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2521 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2522 bzero(&pcsio->sense_data, pcsio->sense_len); 2523 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2524 pcsio->sense_len); 2525 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2526 | CAM_AUTOSNS_VALID; 2527 goto ckc_e; 2528 } 2529 /* 2530 * target status 2531 */ 2532 if (status) { 2533 if (status == SCSI_STATUS_CHECK_COND) { 2534 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2535 TRM_DPRINTF("trm_RequestSense..................\n"); 2536 trm_RequestSense(pACB, pDCB, pSRB); 2537 return; 2538 } 2539 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2540 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2541 goto ckc_e; 2542 } else if (status == SCSI_STAT_QUEUEFULL) { 2543 bval = (u_int8_t) pDCB->GoingSRBCnt; 2544 bval--; 2545 pDCB->MaxActiveCommandCnt = bval; 2546 trm_RewaitSRB(pDCB, pSRB); 2547 pSRB->AdaptStatus = 0; 2548 pSRB->TargetStatus = 0; 2549 return; 2550 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2551 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2552 pSRB->TargetStatus = 0; 2553 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2554 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2555 } else if (status == SCSI_STAT_BUSY) { 2556 TRM_DPRINTF("trm: target busy at %s %d\n", 2557 __FILE__, __LINE__); 2558 pcsio->scsi_status = SCSI_STAT_BUSY; 2559 pccb->ccb_h.status = CAM_SCSI_BUSY; 2560 return; 2561 /* The device busy, try again later? */ 2562 } else if (status == SCSI_STAT_RESCONFLICT) { 2563 TRM_DPRINTF("trm: target reserved at %s %d\n", 2564 __FILE__, __LINE__); 2565 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2566 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2567 return; 2568 } else { 2569 pSRB->AdaptStatus = 0; 2570 if (pSRB->RetryCnt) { 2571 pSRB->RetryCnt--; 2572 pSRB->TargetStatus = 0; 2573 pSRB->SRBSGIndex = 0; 2574 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2575 /* 2576 * If trm_StartSCSI return 1 : 2577 * current interrupt status is interrupt 2578 * disreenable 2579 * It's said that SCSI processor has more 2580 * one SRB need to do 2581 */ 2582 trm_RewaitSRB(pDCB, pSRB); 2583 } 2584 return; 2585 } else { 2586 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2587 __FILE__, __LINE__); 2588 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2589 } 2590 } 2591 } else { 2592 /* 2593 * process initiator status.......................... 2594 * Adapter (initiator) status 2595 */ 2596 status = pSRB->AdaptStatus; 2597 if (status & H_OVER_UNDER_RUN) { 2598 pSRB->TargetStatus = 0; 2599 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2600 /* Illegal length (over/under run) */ 2601 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2602 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2603 __FILE__, __LINE__); 2604 pDCB->tinfo.goal.period = 0; 2605 pDCB->tinfo.goal.offset = 0; 2606 /* Driver failed to perform operation */ 2607 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2608 } else { 2609 /* no error */ 2610 pSRB->AdaptStatus = 0; 2611 pSRB->TargetStatus = 0; 2612 pccb->ccb_h.status = CAM_REQ_CMP; 2613 /* there is no error, (sense is invalid) */ 2614 } 2615 } 2616ckc_e: 2617 if (pACB->scan_devices[target_id][target_lun]) { 2618 /* 2619 * if SCSI command in "scan devices" duty 2620 */ 2621 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2622 pACB->scan_devices[target_id][target_lun] = 0; 2623 /* SCSI command phase :test unit ready */ 2624 else if (pSRB->CmdBlock[0] == INQUIRY) { 2625 /* 2626 * SCSI command phase :inquiry scsi device data 2627 * (type,capacity,manufacture.... 2628 */ 2629 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2630 goto NO_DEV; 2631 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2632 /* page fault */ 2633 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2634 ptr->DevType); 2635 bval1 = ptr->DevType & SCSI_DEVTYPE; 2636 if (bval1 == SCSI_NODEV) { 2637NO_DEV: 2638 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2639 target_id, 2640 target_lun); 2641 intflag = splcam(); 2642 pACB->scan_devices[target_id][target_lun] = 0; 2643 /* no device set scan device flag =0*/ 2644 /* pDCB Q link */ 2645 /* move the head of DCB to tempDCB*/ 2646 pTempDCB=pACB->pLinkDCB; 2647 /* search current DCB for pass link */ 2648 while (pTempDCB->pNextDCB != pDCB) { 2649 pTempDCB = pTempDCB->pNextDCB; 2650 } 2651 /* 2652 * when the current DCB found than connect 2653 * current DCB tail 2654 */ 2655 /* to the DCB tail that before current DCB */ 2656 pTempDCB->pNextDCB = pDCB->pNextDCB; 2657 /* 2658 * if there was only one DCB ,connect his tail 2659 * to his head 2660 */ 2661 if (pACB->pLinkDCB == pDCB) 2662 pACB->pLinkDCB = pTempDCB->pNextDCB; 2663 if (pACB->pDCBRunRobin == pDCB) 2664 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2665 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2666 pACB->DeviceCnt--; 2667 if (pACB->DeviceCnt == 0) { 2668 pACB->pLinkDCB = NULL; 2669 pACB->pDCBRunRobin = NULL; 2670 } 2671 splx(intflag); 2672 } else { 2673#ifdef trm_DEBUG1 2674 int j; 2675 for (j = 0; j < 28; j++) { 2676 TRM_DPRINTF("ptr=%2x ", 2677 ((u_int8_t *)ptr)[j]); 2678 } 2679#endif 2680 pDCB->DevType = bval1; 2681 if (bval1 == SCSI_DASD || 2682 bval1 == SCSI_OPTICAL) { 2683 if ((((ptr->Vers & 0x07) >= 2) || 2684 ((ptr->RDF & 0x0F) == 2)) && 2685 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2686 (pDCB->DevMode & TAG_QUEUING_) && 2687 (pDCB->DevMode & EN_DISCONNECT_)) { 2688 if (pDCB->DevMode & 2689 TAG_QUEUING_) { 2690 pDCB-> 2691 MaxActiveCommandCnt = 2692 pACB->TagMaxNum; 2693 pDCB->SyncMode |= 2694 EN_TAG_QUEUING; 2695 pDCB->tinfo.disc_tag |= 2696 TRM_CUR_TAGENB; 2697 } else { 2698 pDCB->SyncMode |= 2699 EN_ATN_STOP; 2700 pDCB->tinfo.disc_tag &= 2701 ~TRM_CUR_TAGENB; 2702 } 2703 } 2704 } 2705 } 2706 /* pSRB->CmdBlock[0] == INQUIRY */ 2707 } 2708 /* pACB->scan_devices[target_id][target_lun] */ 2709 } 2710 intflag = splcam(); 2711 /* ReleaseSRB(pDCB, pSRB); */ 2712 if (pSRB == pDCB->pGoingSRB) 2713 pDCB->pGoingSRB = pSRB->pNextSRB; 2714 else { 2715 psrb = pDCB->pGoingSRB; 2716 while (psrb->pNextSRB != pSRB) { 2717 psrb = psrb->pNextSRB; 2718 } 2719 psrb->pNextSRB = pSRB->pNextSRB; 2720 if (pSRB == pDCB->pGoingLastSRB) { 2721 pDCB->pGoingLastSRB = psrb; 2722 } 2723 } 2724 pSRB->pNextSRB = pACB->pFreeSRB; 2725 pACB->pFreeSRB = pSRB; 2726 pDCB->GoingSRBCnt--; 2727 trm_DoWaitingSRB(pACB); 2728 2729 splx(intflag); 2730 /* Notify cmd done */ 2731 xpt_done (pccb); 2732} 2733 2734static void 2735trm_DoingSRB_Done(PACB pACB) 2736{ 2737 PDCB pDCB, pdcb; 2738 PSRB psrb, psrb2; 2739 u_int16_t cnt, i; 2740 union ccb *pccb; 2741 2742 pDCB = pACB->pLinkDCB; 2743 if (pDCB == NULL) 2744 return; 2745 pdcb = pDCB; 2746 do { 2747 cnt = pdcb->GoingSRBCnt; 2748 psrb = pdcb->pGoingSRB; 2749 for (i = 0; i < cnt; i++) { 2750 psrb2 = psrb->pNextSRB; 2751 pccb = psrb->pccb; 2752 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2753 /* ReleaseSRB(pDCB, pSRB); */ 2754 psrb->pNextSRB = pACB->pFreeSRB; 2755 pACB->pFreeSRB = psrb; 2756 xpt_done(pccb); 2757 psrb = psrb2; 2758 } 2759 pdcb->GoingSRBCnt = 0;; 2760 pdcb->pGoingSRB = NULL; 2761 pdcb = pdcb->pNextDCB; 2762 } 2763 while (pdcb != pDCB); 2764} 2765 2766static void 2767trm_ResetSCSIBus(PACB pACB) 2768{ 2769 int intflag; 2770 2771 intflag = splcam(); 2772 pACB->ACBFlag |= RESET_DEV; 2773 2774 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2775 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2776 splx(intflag); 2777 return; 2778} 2779 2780static void 2781trm_ScsiRstDetect(PACB pACB) 2782{ 2783 int intflag; 2784 u_long wlval; 2785 2786 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2787 wlval = 1000; 2788 while (--wlval) 2789 DELAY(1000); 2790 intflag = splcam(); 2791 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2792 2793 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2794 2795 if (pACB->ACBFlag & RESET_DEV) 2796 pACB->ACBFlag |= RESET_DONE; 2797 else { 2798 pACB->ACBFlag |= RESET_DETECT; 2799 trm_ResetDevParam(pACB); 2800 /* trm_DoingSRB_Done(pACB); ???? */ 2801 trm_RecoverSRB(pACB); 2802 pACB->pActiveDCB = NULL; 2803 pACB->ACBFlag = 0; 2804 trm_DoWaitingSRB(pACB); 2805 } 2806 splx(intflag); 2807 return; 2808} 2809 2810static void 2811trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2812{ 2813 union ccb *pccb; 2814 struct ccb_scsiio *pcsio; 2815 2816 pccb = pSRB->pccb; 2817 pcsio = &pccb->csio; 2818 2819 pSRB->SRBFlag |= AUTO_REQSENSE; 2820 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2821 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2822 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2823 pSRB->SRBSGCount); 2824 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2825 2826 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2827 pSRB->AdaptStatus = 0; 2828 pSRB->TargetStatus = 0; 2829 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2830 2831 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2832 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2833 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2834 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2835 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2836 pSRB->SRBSGCount = 1; 2837 pSRB->SRBSGIndex = 0; 2838 2839 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2840 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2841 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2842 pSRB->ScsiCmdLen = 6; 2843 2844 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2845 /* 2846 * If trm_StartSCSI return 1 : 2847 * current interrupt status is interrupt disreenable 2848 * It's said that SCSI processor has more one SRB need to do 2849 */ 2850 trm_RewaitSRB(pDCB, pSRB); 2851} 2852 2853static void 2854trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2855{ 2856 2857 pSRB->MsgCnt = 1; 2858 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2859} 2860 2861static void 2862trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2863{ 2864 2865 pSRB->MsgOutBuf[0] = MSG_ABORT; 2866 trm_EnableMsgOutAbort2(pACB, pSRB); 2867} 2868 2869static void 2870trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2871{ 2872 PNVRAMTYPE pEEpromBuf; 2873 u_int8_t bval,PeriodIndex; 2874 u_int target_id,target_lun; 2875 PDCB pTempDCB; 2876 int intflag; 2877 2878 target_id = i; 2879 target_lun = j; 2880 2881 /* 2882 * Using the lun 0 device to init other DCB first, if the device 2883 * has been initialized. 2884 * I don't want init sync arguments one by one, it is the same. 2885 */ 2886 if (target_lun != 0 && 2887 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2888 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2889 sizeof(TRM_DCB)); 2890 intflag = splcam(); 2891 if (pACB->pLinkDCB == 0) { 2892 pACB->pLinkDCB = pDCB; 2893 /* 2894 * RunRobin impersonate the role 2895 * that let each device had good proportion 2896 * about SCSI command proceeding 2897 */ 2898 pACB->pDCBRunRobin = pDCB; 2899 pDCB->pNextDCB = pDCB; 2900 } else { 2901 pTempDCB=pACB->pLinkDCB; 2902 /* search the last nod of DCB link */ 2903 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2904 pTempDCB = pTempDCB->pNextDCB; 2905 /* connect current DCB with last DCB tail */ 2906 pTempDCB->pNextDCB = pDCB; 2907 /* connect current DCB tail to this DCB Q head */ 2908 pDCB->pNextDCB=pACB->pLinkDCB; 2909 } 2910 splx(intflag); 2911 2912 pACB->DeviceCnt++; 2913 pDCB->TargetID = target_id; 2914 pDCB->TargetLUN = target_lun; 2915 pDCB->pWaitingSRB = NULL; 2916 pDCB->pGoingSRB = NULL; 2917 pDCB->GoingSRBCnt = 0; 2918 pDCB->pActiveSRB = NULL; 2919 pDCB->MaxActiveCommandCnt = 1; 2920 pDCB->DCBFlag = 0; 2921 pDCB->DCBstatus |= DS_IN_QUEUE; 2922 /* $$$$$$$ */ 2923 pEEpromBuf = &trm_eepromBuf[unit]; 2924 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2925 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2926 /* $$$$$$$ */ 2927 /* 2928 * disconnect enable ? 2929 */ 2930 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2931 bval = 0xC0; 2932 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2933 } else { 2934 bval = 0x80; 2935 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2936 } 2937 bval |= target_lun; 2938 pDCB->IdentifyMsg = bval; 2939 if (target_lun != 0 && 2940 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2941 return; 2942 /* $$$$$$$ */ 2943 /* 2944 * tag Qing enable ? 2945 */ 2946 if (pDCB->DevMode & TAG_QUEUING_) { 2947 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2948 } else 2949 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2950 /* $$$$$$$ */ 2951 /* 2952 * wide nego ,sync nego enable ? 2953 */ 2954 pDCB->SyncPeriod = 0; 2955 pDCB->SyncOffset = 0; 2956 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2957 if(pACB->AdaptType==1) {/* is U2? */ 2958 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2959 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2960 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2961 } else { 2962 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2963 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2964 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2965 } 2966 pDCB->SyncMode = 0; 2967 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2968 (pACB->Config & HCC_WIDE_CARD)) 2969 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2970 /* enable wide nego */ 2971 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2972 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2973 /* enable sync nego */ 2974 /* $$$$$$$ */ 2975 /* 2976 * Fill in tinfo structure. 2977 */ 2978 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2979 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2980 2981 pDCB->tinfo.current.period = 0; 2982 pDCB->tinfo.current.offset = 0; 2983 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2984} 2985 2986static void 2987trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2988{ 2989 PSRB pSRB; 2990 2991 pSRB=(PSRB) arg; 2992 pSRB->SRBSGPhyAddr=segs->ds_addr; 2993 return; 2994} 2995 2996static int 2997trm_initSRB(PACB pACB) 2998{ 2999 u_int16_t i; 3000 PSRB pSRB; 3001 3002 for(i = 0; i < TRM_MAX_SRB_CNT; i++) { 3003 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3004 3005 /* DMA tag for our S/G structures */ 3006 if(bus_dma_tag_create( 3007 /*parent_dmat*/pSRB->parent_dmat, 3008 /*alignment*/ 1, 3009 /*boundary*/ 0, 3010 /*lowaddr*/ BUS_SPACE_MAXADDR, 3011 /*highaddr*/ BUS_SPACE_MAXADDR, 3012 /*filter*/ NULL, 3013 /*filterarg*/ NULL, 3014 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3015 /*nsegments*/ 1, 3016 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3017 /*flags*/ 0, 3018 /*dmat*/ &pSRB->sg_dmat) != 0) { 3019 return ENXIO; 3020 } 3021 if(bus_dmamem_alloc(pSRB->sg_dmat, (void **)&pSRB->pSRBSGL, 3022 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3023 return ENXIO; 3024 } 3025 bus_dmamap_load(pSRB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3026 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3027 trm_srbmapSG, pSRB, /*flags*/0); 3028 if(i != TRM_MAX_SRB_CNT - 1) { 3029 /* 3030 ** link all SRB 3031 */ 3032 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3033 } else { 3034 /* 3035 ** load NULL to NextSRB of the last SRB 3036 */ 3037 pSRB->pNextSRB = NULL; 3038 } 3039 pSRB->TagNumber = i; 3040 } 3041 return (0); 3042} 3043 3044 3045 3046 3047static void 3048trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3049{ 3050 PNVRAMTYPE pEEpromBuf; 3051 3052 pEEpromBuf = &trm_eepromBuf[unit]; 3053 pACB->max_id = 15; 3054 3055 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3056 pACB->max_lun = 7; 3057 else 3058 pACB->max_lun = 0; 3059 3060 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3061 pACB->max_id, pACB->max_lun); 3062 pACB->pLinkDCB = NULL; 3063 pACB->pDCBRunRobin = NULL; 3064 pACB->pActiveDCB = NULL; 3065 pACB->AdapterUnit = (u_int8_t)unit; 3066 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3067 pACB->AdaptSCSILUN = 0; 3068 pACB->DeviceCnt = 0; 3069 pACB->AdaptType = adaptType; 3070 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3071 pACB->ACBFlag = 0; 3072 return; 3073} 3074 3075static void 3076NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3077{ 3078 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3079 u_int8_t bAddr; 3080 3081 /* Enable SEEPROM */ 3082 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3083 TRMREG_GEN_CONTROL); 3084 /* 3085 * Write enable 3086 */ 3087 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3088 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3089 NVRAM_trm_wait_30us(pACB); 3090 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3091 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3092 } 3093 /* 3094 * Write disable 3095 */ 3096 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3097 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3098 NVRAM_trm_wait_30us(pACB); 3099 /* Disable SEEPROM */ 3100 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3101 TRMREG_GEN_CONTROL); 3102 return; 3103} 3104 3105static void 3106NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3107{ 3108 int i; 3109 u_int8_t bSendData; 3110 /* 3111 * Send write command & address 3112 */ 3113 3114 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3115 /* 3116 * Write data 3117 */ 3118 for (i = 0; i < 8; i++, bData <<= 1) { 3119 bSendData = NVR_SELECT; 3120 if (bData & 0x80) 3121 /* Start from bit 7 */ 3122 bSendData |= NVR_BITOUT; 3123 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3124 NVRAM_trm_wait_30us(pACB); 3125 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3126 NVRAM_trm_wait_30us(pACB); 3127 } 3128 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3129 NVRAM_trm_wait_30us(pACB); 3130 /* 3131 * Disable chip select 3132 */ 3133 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3134 NVRAM_trm_wait_30us(pACB); 3135 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3136 NVRAM_trm_wait_30us(pACB); 3137 /* 3138 * Wait for write ready 3139 */ 3140 while (1) { 3141 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3142 NVRAM_trm_wait_30us(pACB); 3143 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3144 NVRAM_trm_wait_30us(pACB); 3145 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3146 break; 3147 } 3148 } 3149 /* 3150 * Disable chip select 3151 */ 3152 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3153 return; 3154} 3155 3156static void 3157NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3158{ 3159 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3160 u_int8_t bAddr; 3161 3162 /* 3163 * Enable SEEPROM 3164 */ 3165 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3166 TRMREG_GEN_CONTROL); 3167 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3168 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3169 /* 3170 * Disable SEEPROM 3171 */ 3172 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3173 TRMREG_GEN_CONTROL); 3174 return; 3175} 3176 3177static u_int8_t 3178NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3179{ 3180 int i; 3181 u_int8_t bReadData, bData = 0; 3182 /* 3183 * Send read command & address 3184 */ 3185 3186 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3187 3188 for (i = 0; i < 8; i++) { 3189 /* 3190 * Read data 3191 */ 3192 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3193 NVRAM_trm_wait_30us(pACB); 3194 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3195 /* 3196 * Get data bit while falling edge 3197 */ 3198 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3199 bData <<= 1; 3200 if (bReadData & NVR_BITIN) { 3201 bData |= 1; 3202 } 3203 NVRAM_trm_wait_30us(pACB); 3204 } 3205 /* 3206 * Disable chip select 3207 */ 3208 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3209 return (bData); 3210} 3211 3212static void 3213NVRAM_trm_wait_30us(PACB pACB) 3214{ 3215 3216 /* ScsiPortStallExecution(30); wait 30 us */ 3217 trm_reg_write8(5, TRMREG_GEN_TIMER); 3218 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3219 return; 3220} 3221 3222static void 3223NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3224{ 3225 int i; 3226 u_int8_t bSendData; 3227 3228 for (i = 0; i < 3; i++, bCmd <<= 1) { 3229 /* 3230 * Program SB+OP code 3231 */ 3232 bSendData = NVR_SELECT; 3233 if (bCmd & 0x04) 3234 bSendData |= NVR_BITOUT; 3235 /* start from bit 2 */ 3236 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3237 NVRAM_trm_wait_30us(pACB); 3238 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3239 NVRAM_trm_wait_30us(pACB); 3240 } 3241 for (i = 0; i < 7; i++, bAddr <<= 1) { 3242 /* 3243 * Program address 3244 */ 3245 bSendData = NVR_SELECT; 3246 if (bAddr & 0x40) 3247 /* Start from bit 6 */ 3248 bSendData |= NVR_BITOUT; 3249 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3250 NVRAM_trm_wait_30us(pACB); 3251 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3252 NVRAM_trm_wait_30us(pACB); 3253 } 3254 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3255 NVRAM_trm_wait_30us(pACB); 3256} 3257 3258static void 3259trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3260{ 3261 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3262 u_int16_t wAddr, wCheckSum; 3263 u_long dAddr, *dpEeprom; 3264 3265 NVRAM_trm_read_all(pEEpromBuf,pACB); 3266 wCheckSum = 0; 3267 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3268 wAddr < 64; wAddr++, wpEeprom++) { 3269 wCheckSum += *wpEeprom; 3270 } 3271 if (wCheckSum != 0x1234) { 3272 /* 3273 * Checksum error, load default 3274 */ 3275 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3276 pEEpromBuf->NvramSubVendorID[1] = 3277 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3278 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3279 pEEpromBuf->NvramSubSysID[1] = 3280 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3281 pEEpromBuf->NvramSubClass = 0x00; 3282 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3283 pEEpromBuf->NvramVendorID[1] = 3284 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3285 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3286 pEEpromBuf->NvramDeviceID[1] = 3287 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3288 pEEpromBuf->NvramReserved = 0x00; 3289 3290 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3291 dAddr < 16; dAddr++, dpEeprom++) { 3292 *dpEeprom = 0x00000077; 3293 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3294 } 3295 3296 *dpEeprom++ = 0x04000F07; 3297 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3298 *dpEeprom++ = 0x00000015; 3299 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3300 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3301 *dpEeprom = 0x00; 3302 pEEpromBuf->NvramCheckSum = 0x00; 3303 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3304 wAddr < 63; wAddr++, wpEeprom++) 3305 wCheckSum += *wpEeprom; 3306 *wpEeprom = 0x1234 - wCheckSum; 3307 NVRAM_trm_write_all(pEEpromBuf,pACB); 3308 } 3309 return; 3310} 3311static int 3312trm_initAdapter(PACB pACB, u_int16_t unit) 3313{ 3314 PNVRAMTYPE pEEpromBuf; 3315 u_int16_t wval; 3316 u_int8_t bval; 3317 3318 pEEpromBuf = &trm_eepromBuf[unit]; 3319 3320 /* 250ms selection timeout */ 3321 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3322 /* Mask all the interrupt */ 3323 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3324 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3325 /* Reset SCSI module */ 3326 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3327 /* program configuration 0 */ 3328 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3329 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3330 pACB->Config |= HCC_WIDE_CARD; 3331 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3332 pACB->Config |= HCC_SCSI_RESET; 3333 if (pACB->Config & HCC_PARITY) 3334 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3335 else 3336 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3337 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3338 /* program configuration 1 */ 3339 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3340 /* program Host ID */ 3341 bval = pEEpromBuf->NvramScsiId; 3342 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3343 /* set ansynchronous transfer */ 3344 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3345 /* Trun LED control off*/ 3346 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3347 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3348 /* DMA config */ 3349 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3350 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3351 /* Clear pending interrupt status */ 3352 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3353 /* Enable SCSI interrupt */ 3354 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3355 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3356 return (0); 3357} 3358 3359static void 3360trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3361{ 3362 PACB pACB; 3363 3364 pACB = (PACB)arg; 3365 pACB->srb_physbase = segs->ds_addr; 3366} 3367 3368static void 3369trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3370{ 3371 bus_addr_t *baddr; 3372 3373 baddr = (bus_addr_t *)arg; 3374 *baddr = segs->ds_addr; 3375} 3376 3377static PACB 3378trm_init(u_int16_t unit, device_t dev) 3379{ 3380 PACB pACB; 3381 int rid = PCIR_MAPS, i = 0, j = 0; 3382 u_int16_t adaptType = 0; 3383 3384 pACB = (PACB) device_get_softc(dev); 3385 if (!pACB) { 3386 printf("trm%d: cannot allocate ACB !\n", unit); 3387 return (NULL); 3388 } 3389 bzero (pACB, sizeof (struct _ACB)); 3390 pACB->iores = bus_alloc_resource(dev, SYS_RES_IOPORT, 3391 &rid, 0, ~0, 1, RF_ACTIVE); 3392 if (pACB->iores == NULL) { 3393 printf("trm_init: bus_alloc_resource failed!\n"); 3394 return (NULL); 3395 } 3396 switch (pci_get_devid(dev)) { 3397 case PCI_DEVICEID_TRMS1040: 3398 adaptType = 0; 3399 break; 3400 case PCI_DEVICEID_TRMS2080: 3401 adaptType = 1; 3402 break; 3403 default: 3404 printf("trm_init %d: unknown adapter type!\n", unit); 3405 goto bad; 3406 } 3407 pACB->dev = dev; 3408 pACB->tag = rman_get_bustag(pACB->iores); 3409 pACB->bsh = rman_get_bushandle(pACB->iores); 3410 if (bus_dma_tag_create(/*parent_dmat*/ pACB->parent_dmat, 3411 /*alignment*/ 1, 3412 /*boundary*/ 0, 3413 /*lowaddr*/ BUS_SPACE_MAXADDR, 3414 /*highaddr*/ BUS_SPACE_MAXADDR, 3415 /*filter*/ NULL, 3416 /*filterarg*/ NULL, 3417 /*maxsize*/ MAXBSIZE, 3418 /*nsegments*/ TRM_NSEG, 3419 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3420 /*flags*/ BUS_DMA_ALLOCNOW, 3421 &pACB->buffer_dmat) != 0) 3422 goto bad; 3423 /* DMA tag for our ccb structures */ 3424 if(bus_dma_tag_create( 3425 /*parent_dmat*/pACB->parent_dmat, 3426 /*alignment*/ 1, 3427 /*boundary*/ 0, 3428 /*lowaddr*/ BUS_SPACE_MAXADDR, 3429 /*highaddr*/ BUS_SPACE_MAXADDR, 3430 /*filter*/ NULL, 3431 /*filterarg*/ NULL, 3432 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3433 /*nsegments*/ 1, 3434 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3435 /*flags*/ 0, 3436 /*dmat*/ &pACB->srb_dmat) != 0) { 3437 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3438 goto bad; 3439 } 3440 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3441 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3442 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3443 goto bad; 3444 } 3445 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3446 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3447 /* flags */0); 3448 /* Create, allocate, and map DMA buffers for autosense data */ 3449 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3450 /*boundary*/0, 3451 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3452 /*highaddr*/BUS_SPACE_MAXADDR, 3453 /*filter*/NULL, /*filterarg*/NULL, 3454 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3455 /*nsegments*/1, 3456 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3457 /*flags*/0, &pACB->sense_dmat) != 0) { 3458 if (bootverbose) 3459 device_printf(dev, "cannot create sense buffer dmat\n"); 3460 goto bad; 3461 } 3462 3463 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3464 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3465 goto bad; 3466 3467 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3468 pACB->sense_buffers, 3469 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3470 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3471 3472 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3473 trm_initACB(pACB, adaptType, unit); 3474 for (i = 0; i < (pACB->max_id + 1); i++) { 3475 if (pACB->AdaptSCSIID == i) 3476 continue; 3477 for(j = 0; j < (pACB->max_lun + 1); j++) { 3478 pACB->scan_devices[i][j] = 1; 3479 /* we assume we need to scan all devices */ 3480 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3481 } 3482 } 3483 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3484 if (trm_initSRB(pACB)) { 3485 printf("trm_initSRB: error\n"); 3486 goto bad; 3487 } 3488 if (trm_initAdapter(pACB, unit)) { 3489 printf("trm_initAdapter: initial ERROR\n"); 3490 goto bad; 3491 } 3492 return (pACB); 3493bad: 3494 if (pACB->iores) 3495 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, 3496 pACB->iores); 3497 if (pACB->sense_dmamap) { 3498 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3499 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3500 pACB->sense_dmamap); 3501 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3502 } 3503 if (pACB->sense_dmat) 3504 bus_dma_tag_destroy(pACB->sense_dmat); 3505 if (pACB->srb_dmamap) { 3506 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3507 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3508 pACB->srb_dmamap); 3509 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3510 } 3511 if (pACB->srb_dmat) 3512 bus_dma_tag_destroy(pACB->srb_dmat); 3513 if (pACB->buffer_dmat) 3514 bus_dma_tag_destroy(pACB->buffer_dmat); 3515 return (NULL); 3516} 3517 3518static int 3519trm_attach(device_t dev) 3520{ 3521 struct cam_devq *device_Q; 3522 u_long device_id; 3523 PACB pACB = 0; 3524 int rid = 0; 3525 int unit = device_get_unit(dev); 3526 3527 device_id = pci_get_devid(dev); 3528 /* 3529 * These cards do not allow memory mapped accesses 3530 */ 3531 if ((pACB = trm_init((u_int16_t) unit, 3532 dev)) == NULL) { 3533 printf("trm%d: trm_init error!\n",unit); 3534 return (ENXIO); 3535 } 3536 /* After setting up the adapter, map our interrupt */ 3537 /* 3538 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3539 * start queue to reset to the idle loop. 3540 * Create device queue of SIM(s) 3541 * (MAX_START_JOB - 1) : max_sim_transactions 3542 */ 3543 pACB->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, 3544 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 3545 if (pACB->irq == NULL || 3546 bus_setup_intr(dev, pACB->irq, 3547 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3548 printf("trm%d: register Interrupt handler error!\n", unit); 3549 goto bad; 3550 } 3551 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3552 if (device_Q == NULL){ 3553 printf("trm%d: device_Q == NULL !\n",unit); 3554 goto bad; 3555 } 3556 /* 3557 * Now tell the generic SCSI layer 3558 * about our bus. 3559 * If this is the xpt layer creating a sim, then it's OK 3560 * to wait for an allocation. 3561 * XXX Should we pass in a flag to indicate that wait is OK? 3562 * 3563 * SIM allocation 3564 * 3565 * SCSI Interface Modules 3566 * The sim driver creates a sim for each controller. The sim device 3567 * queue is separately created in order to allow resource sharing betwee 3568 * sims. For instance, a driver may create one sim for each channel of 3569 * a multi-channel controller and use the same queue for each channel. 3570 * In this way, the queue resources are shared across all the channels 3571 * of the multi-channel controller. 3572 * trm_action : sim_action_func 3573 * trm_poll : sim_poll_func 3574 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3575 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3576 * pACB->unit : unit 3577 * 1 : max_dev_transactions 3578 * MAX_TAGS : max_tagged_dev_transactions 3579 * 3580 * *******Construct our first channel SIM entry 3581 */ 3582 pACB->psim = cam_sim_alloc(trm_action, 3583 trm_poll, 3584 "trm", 3585 pACB, 3586 unit, 3587 1, 3588 TRM_MAX_TAGS_CMD_QUEUE, 3589 device_Q); 3590 if (pACB->psim == NULL) { 3591 printf("trm%d: SIM allocate fault !\n",unit); 3592 cam_simq_free(device_Q); /* SIM allocate fault*/ 3593 goto bad; 3594 } 3595 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3596 printf("trm%d: xpt_bus_register fault !\n",unit); 3597 goto bad; 3598 } 3599 if (xpt_create_path(&pACB->ppath, 3600 NULL, 3601 cam_sim_path(pACB->psim), 3602 CAM_TARGET_WILDCARD, 3603 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3604 printf("trm%d: xpt_create_path fault !\n",unit); 3605 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3606 goto bad; 3607 } 3608 return (0); 3609bad: 3610 if (pACB->iores) 3611 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, 3612 pACB->iores); 3613 if (pACB->srb_dmamap) { 3614 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3615 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3616 pACB->srb_dmamap); 3617 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3618 } 3619 if (pACB->srb_dmat) 3620 bus_dma_tag_destroy(pACB->srb_dmat); 3621 if (pACB->sense_dmamap) { 3622 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3623 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3624 pACB->sense_dmamap); 3625 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3626 } 3627 if (pACB->sense_dmat) 3628 bus_dma_tag_destroy(pACB->sense_dmat); 3629 if (pACB->buffer_dmat) 3630 bus_dma_tag_destroy(pACB->buffer_dmat); 3631 if (pACB->ih) 3632 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3633 if (pACB->irq) 3634 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3635 if (pACB->psim) 3636 cam_sim_free(pACB->psim, TRUE); 3637 3638 return (ENXIO); 3639 3640} 3641 3642/* 3643* pci_device 3644* trm_probe (device_t tag, pcidi_t type) 3645* 3646*/ 3647static int 3648trm_probe(device_t dev) 3649{ 3650 switch (pci_get_devid(dev)) { 3651 case PCI_DEVICEID_TRMS1040: 3652 device_set_desc(dev, 3653 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3654 return (0); 3655 case PCI_DEVICEID_TRMS2080: 3656 device_set_desc(dev, 3657 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3658 return 0; 3659 default: 3660 return (ENXIO); 3661 } 3662} 3663 3664static int 3665trm_detach(device_t dev) 3666{ 3667 PACB pACB = device_get_softc(dev); 3668 3669 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, pACB->iores); 3670 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3671 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3672 pACB->srb_dmamap); 3673 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3674 bus_dma_tag_destroy(pACB->srb_dmat); 3675 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3676 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3677 pACB->sense_dmamap); 3678 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3679 bus_dma_tag_destroy(pACB->sense_dmat); 3680 bus_dma_tag_destroy(pACB->buffer_dmat); 3681 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3682 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3683 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3684 xpt_free_path(pACB->ppath); 3685 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3686 cam_sim_free(pACB->psim, TRUE); 3687 return (0); 3688} 3689static device_method_t trm_methods[] = { 3690 /* Device interface */ 3691 DEVMETHOD(device_probe, trm_probe), 3692 DEVMETHOD(device_attach, trm_attach), 3693 DEVMETHOD(device_detach, trm_detach), 3694 { 0, 0 } 3695}; 3696 3697static driver_t trm_driver = { 3698 "trm", trm_methods, sizeof(struct _ACB) 3699}; 3700 3701static devclass_t trm_devclass; 3702DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3703