trm.c revision 113350
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 *(C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 12 */ 13 14/* 15 * HISTORY: 16 * 17 * REV# DATE NAME DESCRIPTION 18 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 19 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 20 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 21 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 22 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 23 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 24 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 25 */ 26 27/* 28 * 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 */ 53 54/* 55 * Imported into FreeBSD source repository, and updated to compile under 56 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 57 */ 58 59/* 60 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 61 * <doginou@ci0.org>, 2002-03-04 62 */ 63 64#include <sys/cdefs.h> 65__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 113350 2003-04-10 23:50:06Z mux $"); 66 67#include <sys/param.h> 68 69#include <sys/systm.h> 70#include <sys/malloc.h> 71#include <sys/queue.h> 72#if __FreeBSD_version >= 500000 73#include <sys/bio.h> 74#endif 75#include <sys/buf.h> 76#include <sys/bus.h> 77#include <sys/kernel.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <pci/pcivar.h> 83#include <pci/pcireg.h> 84#include <machine/resource.h> 85#include <machine/bus_pio.h> 86#include <machine/bus.h> 87#include <machine/clock.h> 88#include <sys/rman.h> 89 90#include <cam/cam.h> 91#include <cam/cam_ccb.h> 92#include <cam/cam_sim.h> 93#include <cam/cam_xpt_sim.h> 94#include <cam/cam_debug.h> 95 96#include <cam/scsi/scsi_all.h> 97#include <cam/scsi/scsi_message.h> 98 99#include <dev/trm/trm.h> 100 101#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 102#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 103#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 104#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 105 reg, value) 106#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 107 reg, value) 108#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 109 reg, value) 110 111#define PCI_Vendor_ID_TEKRAM 0x1DE1 112#define PCI_Device_ID_TRM_S1040 0x0391 113#define PCI_DEVICEID_TRMS1040 0x03911DE1 114#define PCI_DEVICEID_TRMS2080 0x03921DE1 115 116#ifdef trm_DEBUG1 117#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 118#else 119#define TRM_DPRINTF(fmt, arg...) {} 120#endif /* TRM_DEBUG */ 121 122static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 123static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 125static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 126static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 127static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 128static void NVRAM_trm_wait_30us(PACB pACB); 129 130static void trm_Interrupt(void *vpACB); 131static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 154 u_int16_t * pscsi_status); 155static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 156static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 157static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 158static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 159static void trm_Disconnect(PACB pACB); 160static void trm_Reselect(PACB pACB); 161static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 162static void trm_DoingSRB_Done(PACB pACB); 163static void trm_ScsiRstDetect(PACB pACB); 164static void trm_ResetSCSIBus(PACB pACB); 165static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 166static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 167static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 168static void trm_SendSRB(PACB pACB, PSRB pSRB); 169static int trm_probe(device_t tag); 170static int trm_attach(device_t tag); 171static void trm_reset(PACB pACB); 172 173static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 174 175static int trm_initAdapter(PACB pACB, u_int16_t unit); 176static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 177 u_int32_t i, u_int32_t j); 178static int trm_initSRB(PACB pACB); 179static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 180/* CAM SIM entry points */ 181#define ccb_trmsrb_ptr spriv_ptr0 182#define ccb_trmacb_ptr spriv_ptr1 183static void trm_action(struct cam_sim *psim, union ccb *pccb); 184static void trm_poll(struct cam_sim *psim); 185 186 187static void * trm_SCSI_phase0[] = { 188 trm_DataOutPhase0, /* phase:0 */ 189 trm_DataInPhase0, /* phase:1 */ 190 trm_CommandPhase0, /* phase:2 */ 191 trm_StatusPhase0, /* phase:3 */ 192 trm_Nop0, /* phase:4 */ 193 trm_Nop1, /* phase:5 */ 194 trm_MsgOutPhase0, /* phase:6 */ 195 trm_MsgInPhase0, /* phase:7 */ 196}; 197 198/* 199 * 200 * stateV = (void *) trm_SCSI_phase1[phase] 201 * 202 */ 203static void * trm_SCSI_phase1[] = { 204 trm_DataOutPhase1, /* phase:0 */ 205 trm_DataInPhase1, /* phase:1 */ 206 trm_CommandPhase1, /* phase:2 */ 207 trm_StatusPhase1, /* phase:3 */ 208 trm_Nop0, /* phase:4 */ 209 trm_Nop1, /* phase:5 */ 210 trm_MsgOutPhase1, /* phase:6 */ 211 trm_MsgInPhase1, /* phase:7 */ 212}; 213 214 215NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 216/* 217 *Fast20: 000 50ns, 20.0 Mbytes/s 218 * 001 75ns, 13.3 Mbytes/s 219 * 010 100ns, 10.0 Mbytes/s 220 * 011 125ns, 8.0 Mbytes/s 221 * 100 150ns, 6.6 Mbytes/s 222 * 101 175ns, 5.7 Mbytes/s 223 * 110 200ns, 5.0 Mbytes/s 224 * 111 250ns, 4.0 Mbytes/s 225 * 226 *Fast40: 000 25ns, 40.0 Mbytes/s 227 * 001 50ns, 20.0 Mbytes/s 228 * 010 75ns, 13.3 Mbytes/s 229 * 011 100ns, 10.0 Mbytes/s 230 * 100 125ns, 8.0 Mbytes/s 231 * 101 150ns, 6.6 Mbytes/s 232 * 110 175ns, 5.7 Mbytes/s 233 * 111 200ns, 5.0 Mbytes/s 234 */ 235 /* real period: */ 236u_int8_t dc395x_clock_period[] = { 237 12,/* 48 ns 20 MB/sec */ 238 18,/* 72 ns 13.3 MB/sec */ 239 25,/* 100 ns 10.0 MB/sec */ 240 31,/* 124 ns 8.0 MB/sec */ 241 37,/* 148 ns 6.6 MB/sec */ 242 43,/* 172 ns 5.7 MB/sec */ 243 50,/* 200 ns 5.0 MB/sec */ 244 62 /* 248 ns 4.0 MB/sec */ 245}; 246 247u_int8_t dc395u2x_clock_period[]={ 248 10,/* 25 ns 40.0 MB/sec */ 249 12,/* 48 ns 20.0 MB/sec */ 250 18,/* 72 ns 13.3 MB/sec */ 251 25,/* 100 ns 10.0 MB/sec */ 252 31,/* 124 ns 8.0 MB/sec */ 253 37,/* 148 ns 6.6 MB/sec */ 254 43,/* 172 ns 5.7 MB/sec */ 255 50,/* 200 ns 5.0 MB/sec */ 256}; 257 258#define dc395x_tinfo_period dc395x_clock_period 259#define dc395u2x_tinfo_period dc395u2x_clock_period 260 261static PSRB 262trm_GetSRB(PACB pACB) 263{ 264 int intflag; 265 PSRB pSRB; 266 267 intflag = splcam(); 268 pSRB = pACB->pFreeSRB; 269 if (pSRB) { 270 pACB->pFreeSRB = pSRB->pNextSRB; 271 pSRB->pNextSRB = NULL; 272 } 273 splx(intflag); 274 return (pSRB); 275} 276 277static void 278trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 279{ 280 PSRB psrb1; 281 int intflag; 282 283 intflag = splcam(); 284 if ((psrb1 = pDCB->pWaitingSRB)) { 285 pSRB->pNextSRB = psrb1; 286 pDCB->pWaitingSRB = pSRB; 287 } else { 288 pSRB->pNextSRB = NULL; 289 pDCB->pWaitingSRB = pSRB; 290 pDCB->pWaitingLastSRB = pSRB; 291 } 292 splx(intflag); 293} 294 295static void 296trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 297{ 298 PSRB psrb1; 299 int intflag; 300 301 intflag = splcam(); 302 pDCB->GoingSRBCnt--; 303 psrb1 = pDCB->pGoingSRB; 304 if (pSRB == psrb1) 305 /* 306 * if this SRB is GoingSRB 307 * remove this SRB from GoingSRB Q 308 */ 309 pDCB->pGoingSRB = psrb1->pNextSRB; 310 else { 311 /* 312 * if this SRB is not current GoingSRB 313 * remove this SRB from GoingSRB Q 314 */ 315 while (pSRB != psrb1->pNextSRB) 316 psrb1 = psrb1->pNextSRB; 317 psrb1->pNextSRB = pSRB->pNextSRB; 318 if (pSRB == pDCB->pGoingLastSRB) 319 pDCB->pGoingLastSRB = psrb1; 320 } 321 if ((psrb1 = pDCB->pWaitingSRB)) { 322 /* 323 * if WaitingSRB Q is not NULL 324 * Q back this SRB into WaitingSRB 325 */ 326 327 pSRB->pNextSRB = psrb1; 328 pDCB->pWaitingSRB = pSRB; 329 } else { 330 pSRB->pNextSRB = NULL; 331 pDCB->pWaitingSRB = pSRB; 332 pDCB->pWaitingLastSRB = pSRB; 333 } 334 splx(intflag); 335} 336 337static void 338trm_DoWaitingSRB(PACB pACB) 339{ 340 int intflag; 341 PDCB ptr, ptr1; 342 PSRB pSRB; 343 344 intflag = splcam(); 345 if (!(pACB->pActiveDCB) && 346 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 347 ptr = pACB->pDCBRunRobin; 348 if (!ptr) { 349 ptr = pACB->pLinkDCB; 350 pACB->pDCBRunRobin = ptr; 351 } 352 ptr1 = ptr; 353 for (;ptr1 ;) { 354 pACB->pDCBRunRobin = ptr1->pNextDCB; 355 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 356 || !(pSRB = ptr1->pWaitingSRB)) { 357 if (pACB->pDCBRunRobin == ptr) 358 break; 359 ptr1 = ptr1->pNextDCB; 360 } else { 361 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 362 /* 363 * If trm_StartSCSI return 0 : 364 * current interrupt status is interrupt enable 365 * It's said that SCSI processor is unoccupied 366 */ 367 ptr1->GoingSRBCnt++; 368 if (ptr1->pWaitingLastSRB == pSRB) { 369 ptr1->pWaitingSRB = NULL; 370 ptr1->pWaitingLastSRB = NULL; 371 } else 372 ptr1->pWaitingSRB = pSRB->pNextSRB; 373 pSRB->pNextSRB = NULL; 374 if (ptr1->pGoingSRB) 375 ptr1->pGoingLastSRB->pNextSRB = pSRB; 376 else 377 ptr1->pGoingSRB = pSRB; 378 ptr1->pGoingLastSRB = pSRB; 379 } 380 break; 381 } 382 } 383 } 384 splx(intflag); 385 return; 386} 387 388static void 389trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 390{ 391 392 if (pDCB->pWaitingSRB) { 393 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 394 pDCB->pWaitingLastSRB = pSRB; 395 pSRB->pNextSRB = NULL; 396 } else { 397 pDCB->pWaitingSRB = pSRB; 398 pDCB->pWaitingLastSRB = pSRB; 399 } 400} 401 402static u_int32_t 403trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 404{ 405 int offset; 406 407 offset = pSRB->TagNumber; 408 return (pACB->sense_busaddr + 409 (offset * sizeof(struct scsi_sense_data))); 410} 411 412static struct scsi_sense_data * 413trm_get_sense_buf(PACB pACB, PSRB pSRB) 414{ 415 int offset; 416 417 offset = pSRB->TagNumber; 418 return (&pACB->sense_buffers[offset]); 419} 420static void 421trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 422{ 423 int flags; 424 PACB pACB; 425 PSRB pSRB; 426 union ccb *ccb; 427 u_long totalxferlen=0; 428 429 flags = splcam(); 430 pSRB = (PSRB)arg; 431 ccb = pSRB->pccb; 432 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 433 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 434 if (nseg != 0) { 435 PSEG psg; 436 bus_dma_segment_t *end_seg; 437 int op; 438 439 /* Copy the segments into our SG list */ 440 end_seg = dm_segs + nseg; 441 psg = pSRB->pSRBSGL; 442 while (dm_segs < end_seg) { 443 psg->address = dm_segs->ds_addr; 444 psg->length = (u_long)dm_segs->ds_len; 445 totalxferlen += dm_segs->ds_len; 446 psg++; 447 dm_segs++; 448 } 449 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 450 op = BUS_DMASYNC_PREREAD; 451 } else { 452 op = BUS_DMASYNC_PREWRITE; 453 } 454 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 455 } 456 pSRB->RetryCnt = 0; 457 pSRB->SRBTotalXferLength = totalxferlen; 458 pSRB->SRBSGCount = nseg; 459 pSRB->SRBSGIndex = 0; 460 pSRB->AdaptStatus = 0; 461 pSRB->TargetStatus = 0; 462 pSRB->MsgCnt = 0; 463 pSRB->SRBStatus = 0; 464 pSRB->SRBFlag = 0; 465 pSRB->SRBState = 0; 466 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 467 468 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 469 if (nseg != 0) 470 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 471 pSRB->pNextSRB = pACB->pFreeSRB; 472 pACB->pFreeSRB = pSRB; 473 xpt_done(ccb); 474 splx(flags); 475 return; 476 } 477 ccb->ccb_h.status |= CAM_SIM_QUEUED; 478#if 0 479 /* XXX Need a timeout handler */ 480 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 481#endif 482 trm_SendSRB(pACB, pSRB); 483 splx(flags); 484 return; 485} 486 487static void 488trm_SendSRB(PACB pACB, PSRB pSRB) 489{ 490 PDCB pDCB; 491 492 pDCB = pSRB->pSRBDCB; 493 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 494 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 495 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 496 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 497 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 498 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 499 trm_SRBwaiting(pDCB, pSRB); 500 goto SND_EXIT; 501 } 502 503 if (pDCB->pWaitingSRB) { 504 trm_SRBwaiting(pDCB, pSRB); 505 pSRB = pDCB->pWaitingSRB; 506 pDCB->pWaitingSRB = pSRB->pNextSRB; 507 pSRB->pNextSRB = NULL; 508 } 509 510 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 511 /* 512 * If trm_StartSCSI return 0 : 513 * current interrupt status is interrupt enable 514 * It's said that SCSI processor is unoccupied 515 */ 516 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 517 if (pDCB->pGoingSRB) { 518 pDCB->pGoingLastSRB->pNextSRB = pSRB; 519 pDCB->pGoingLastSRB = pSRB; 520 } else { 521 pDCB->pGoingSRB = pSRB; 522 pDCB->pGoingLastSRB = pSRB; 523 } 524 } else { 525 /* 526 * If trm_StartSCSI return 1 : 527 * current interrupt status is interrupt disreenable 528 * It's said that SCSI processor has more one SRB need to do 529 */ 530 trm_RewaitSRB0(pDCB, pSRB); 531 } 532SND_EXIT: 533 return; 534} 535 536 537static void 538trm_action(struct cam_sim *psim, union ccb *pccb) 539{ 540 PACB pACB; 541 int actionflags; 542 u_int target_id,target_lun; 543 544 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 545 546 actionflags = splcam(); 547 pACB = (PACB) cam_sim_softc(psim); 548 target_id = pccb->ccb_h.target_id; 549 target_lun = pccb->ccb_h.target_lun; 550 551 switch (pccb->ccb_h.func_code) { 552 case XPT_NOOP: 553 TRM_DPRINTF(" XPT_NOOP \n"); 554 pccb->ccb_h.status = CAM_REQ_INVALID; 555 xpt_done(pccb); 556 break; 557 /* 558 * Execute the requested I/O operation 559 */ 560 case XPT_SCSI_IO: { 561 PDCB pDCB = NULL; 562 PSRB pSRB; 563 struct ccb_scsiio *pcsio; 564 565 pcsio = &pccb->csio; 566 TRM_DPRINTF(" XPT_SCSI_IO \n"); 567 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 568 ,target_id, target_lun); 569 TRM_DPRINTF( 570 "pACB->scan_devices[target_id][target_lun]= %d \n" 571 ,pACB->scan_devices[target_id][target_lun]); 572 if((pccb->ccb_h.status & CAM_STATUS_MASK) !=CAM_REQ_INPROG) { 573 xpt_done(pccb); 574 splx(actionflags); 575 return; 576 } 577 pDCB = &pACB->DCBarray[target_id][target_lun]; 578 if(!(pDCB->DCBstatus & DS_IN_QUEUE)) { 579 pACB->scan_devices[target_id][target_lun] = 1; 580 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 581 target_id, target_lun); 582 } 583 /* 584 * Assign an SRB and connect it with this ccb. 585 */ 586 pSRB = trm_GetSRB(pACB); 587 if (!pSRB) { 588 /* Freeze SIMQ */ 589 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 590 xpt_done(pccb); 591 splx(actionflags); 592 return; 593 } 594 pSRB->pSRBDCB = pDCB; 595 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 596 pccb->ccb_h.ccb_trmacb_ptr = pACB; 597 pSRB->pccb = pccb; 598 pSRB->ScsiCmdLen = pcsio->cdb_len; 599 /* 600 * move layer of CAM command block to layer of SCSI 601 * Request Block for SCSI processor command doing 602 */ 603 if((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 604 if((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 605 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 606 ,pcsio->cdb_len); 607 } else { 608 pccb->ccb_h.status = CAM_REQ_INVALID; 609 pSRB->pNextSRB = pACB->pFreeSRB; 610 pACB->pFreeSRB= pSRB; 611 xpt_done(pccb); 612 splx(actionflags); 613 return; 614 } 615 } else 616 bcopy(pcsio->cdb_io.cdb_bytes, 617 pSRB->CmdBlock, pcsio->cdb_len); 618 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 619 != CAM_DIR_NONE) { 620 if ((pccb->ccb_h.flags & 621 CAM_SCATTER_VALID) == 0) { 622 if ((pccb->ccb_h.flags 623 & CAM_DATA_PHYS) == 0) { 624 int vmflags; 625 int error; 626 627 vmflags = splsoftvm(); 628 error = bus_dmamap_load( 629 pACB->buffer_dmat, 630 pSRB->dmamap, 631 pcsio->data_ptr, 632 pcsio->dxfer_len, 633 trm_ExecuteSRB, 634 pSRB, 635 0); 636 if (error == EINPROGRESS) { 637 xpt_freeze_simq( 638 pACB->psim, 639 1); 640 pccb->ccb_h.status |= 641 CAM_RELEASE_SIMQ; 642 } 643 splx(vmflags); 644 } else { 645 struct bus_dma_segment seg; 646 647 /* Pointer to physical buffer */ 648 seg.ds_addr = 649 (bus_addr_t)pcsio->data_ptr; 650 seg.ds_len = pcsio->dxfer_len; 651 trm_ExecuteSRB(pSRB, &seg, 1, 652 0); 653 } 654 } else { 655 /* CAM_SCATTER_VALID */ 656 struct bus_dma_segment *segs; 657 658 if ((pccb->ccb_h.flags & 659 CAM_SG_LIST_PHYS) == 0 || 660 (pccb->ccb_h.flags 661 & CAM_DATA_PHYS) != 0) { 662 pSRB->pNextSRB = pACB->pFreeSRB; 663 pACB->pFreeSRB = pSRB; 664 pccb->ccb_h.status = 665 CAM_PROVIDE_FAIL; 666 xpt_done(pccb); 667 splx(actionflags); 668 return; 669 } 670 671 /* cam SG list is physical, 672 * cam data is virtual 673 */ 674 segs = (struct bus_dma_segment *) 675 pcsio->data_ptr; 676 trm_ExecuteSRB(pSRB, segs, 677 pcsio->sglist_cnt, 1); 678 } /* CAM_SCATTER_VALID */ 679 } else 680 trm_ExecuteSRB(pSRB, NULL, 0, 0); 681 } 682 break; 683 case XPT_GDEV_TYPE: 684 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 685 pccb->ccb_h.status = CAM_REQ_INVALID; 686 xpt_done(pccb); 687 break; 688 case XPT_GDEVLIST: 689 TRM_DPRINTF(" XPT_GDEVLIST \n"); 690 pccb->ccb_h.status = CAM_REQ_INVALID; 691 xpt_done(pccb); 692 break; 693 /* 694 * Path routing inquiry 695 * Path Inquiry CCB 696 */ 697 case XPT_PATH_INQ: { 698 struct ccb_pathinq *cpi = &pccb->cpi; 699 700 TRM_DPRINTF(" XPT_PATH_INQ \n"); 701 cpi->version_num = 1; 702 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 703 cpi->target_sprt = 0; 704 cpi->hba_misc = 0; 705 cpi->hba_eng_cnt = 0; 706 cpi->max_target = 15 ; 707 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 708 cpi->initiator_id = pACB->AdaptSCSIID; 709 cpi->bus_id = cam_sim_bus(psim); 710 cpi->base_transfer_speed = 3300; 711 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 712 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 713 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 714 cpi->unit_number = cam_sim_unit(psim); 715 cpi->ccb_h.status = CAM_REQ_CMP; 716 xpt_done(pccb); 717 } 718 break; 719 /* 720 * Release a frozen SIM queue 721 * Release SIM Queue 722 */ 723 case XPT_REL_SIMQ: 724 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 725 pccb->ccb_h.status = CAM_REQ_INVALID; 726 xpt_done(pccb); 727 break; 728 /* 729 * Set Asynchronous Callback Parameters 730 * Set Asynchronous Callback CCB 731 */ 732 case XPT_SASYNC_CB: 733 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 734 pccb->ccb_h.status = CAM_REQ_INVALID; 735 xpt_done(pccb); 736 break; 737 /* 738 * Set device type information 739 * Set Device Type CCB 740 */ 741 case XPT_SDEV_TYPE: 742 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 743 pccb->ccb_h.status = CAM_REQ_INVALID; 744 xpt_done(pccb); 745 break; 746 /* 747 * (Re)Scan the SCSI Bus 748 * Rescan the given bus, or bus/target/lun 749 */ 750 case XPT_SCAN_BUS: 751 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 752 pccb->ccb_h.status = CAM_REQ_INVALID; 753 xpt_done(pccb); 754 break; 755 /* 756 * Get EDT entries matching the given pattern 757 */ 758 case XPT_DEV_MATCH: 759 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 760 pccb->ccb_h.status = CAM_REQ_INVALID; 761 xpt_done(pccb); 762 break; 763 /* 764 * Turn on debugging for a bus, target or lun 765 */ 766 case XPT_DEBUG: 767 TRM_DPRINTF(" XPT_DEBUG \n"); 768 pccb->ccb_h.status = CAM_REQ_INVALID; 769 xpt_done(pccb); 770 break; 771 /* 772 * XPT_ABORT = 0x10, Abort the specified CCB 773 * Abort XPT request CCB 774 */ 775 case XPT_ABORT: 776 TRM_DPRINTF(" XPT_ABORT \n"); 777 pccb->ccb_h.status = CAM_REQ_INVALID; 778 xpt_done(pccb); 779 break; 780 /* 781 * Reset the specified SCSI bus 782 * Reset SCSI Bus CCB 783 */ 784 case XPT_RESET_BUS: { 785 int i; 786 787 TRM_DPRINTF(" XPT_RESET_BUS \n"); 788 trm_reset(pACB); 789 pACB->ACBFlag=0; 790 for (i=0; i<500; i++) 791 DELAY(1000); 792 pccb->ccb_h.status = CAM_REQ_CMP; 793 xpt_done(pccb); 794 } 795 break; 796 /* 797 * Bus Device Reset the specified SCSI device 798 * Reset SCSI Device CCB 799 */ 800 case XPT_RESET_DEV: 801 /* 802 * Don't (yet?) support vendor 803 * specific commands. 804 */ 805 TRM_DPRINTF(" XPT_RESET_DEV \n"); 806 pccb->ccb_h.status = CAM_REQ_INVALID; 807 xpt_done(pccb); 808 break; 809 /* 810 * Terminate the I/O process 811 * Terminate I/O Process Request CCB 812 */ 813 case XPT_TERM_IO: 814 TRM_DPRINTF(" XPT_TERM_IO \n"); 815 pccb->ccb_h.status = CAM_REQ_INVALID; 816 xpt_done(pccb); 817 break; 818 /* 819 * Scan Logical Unit 820 */ 821 case XPT_SCAN_LUN: 822 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 823 pccb->ccb_h.status = CAM_REQ_INVALID; 824 xpt_done(pccb); 825 break; 826 827 /* 828 * Get/Set transfer rate/width/disconnection/tag queueing 829 * settings 830 * (GET) default/user transfer settings for the target 831 */ 832 case XPT_GET_TRAN_SETTINGS: { 833 struct ccb_trans_settings *cts; 834 int intflag; 835 struct trm_transinfo *tinfo; 836 PDCB pDCB; 837 838 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 839 cts = &pccb->cts; 840 pDCB = &pACB->DCBarray[target_id][target_lun]; 841 intflag = splcam(); 842 /* 843 * disable interrupt 844 */ 845 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 846 /* current transfer settings */ 847 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 848 cts->flags = CCB_TRANS_DISC_ENB; 849 else 850 cts->flags = 0;/* no tag & disconnect */ 851 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 852 cts->flags |= CCB_TRANS_TAG_ENB; 853 tinfo = &pDCB->tinfo.current; 854 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 855 cts->flags); 856 } else { 857 /* default(user) transfer settings */ 858 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 859 cts->flags = CCB_TRANS_DISC_ENB; 860 else 861 cts->flags = 0; 862 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 863 cts->flags |= CCB_TRANS_TAG_ENB; 864 tinfo = &pDCB->tinfo.user; 865 TRM_DPRINTF("USER: cts->flags= %2x \n", 866 cts->flags); 867 } 868 cts->sync_period = tinfo->period; 869 cts->sync_offset = tinfo->offset; 870 cts->bus_width = tinfo->width; 871 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 872 pDCB->SyncPeriod); 873 TRM_DPRINTF("period: %d \n", tinfo->period); 874 TRM_DPRINTF("offset: %d \n", tinfo->offset); 875 TRM_DPRINTF("width: %d \n", tinfo->width); 876 877 splx(intflag); 878 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 879 CCB_TRANS_SYNC_OFFSET_VALID | 880 CCB_TRANS_BUS_WIDTH_VALID | 881 CCB_TRANS_DISC_VALID | 882 CCB_TRANS_TQ_VALID; 883 pccb->ccb_h.status = CAM_REQ_CMP; 884 xpt_done(pccb); 885 } 886 break; 887 /* 888 * Get/Set transfer rate/width/disconnection/tag queueing 889 * settings 890 * (Set) transfer rate/width negotiation settings 891 */ 892 case XPT_SET_TRAN_SETTINGS: { 893 struct ccb_trans_settings *cts; 894 u_int update_type; 895 int intflag; 896 PDCB pDCB; 897 898 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 899 cts = &pccb->cts; 900 update_type = 0; 901 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 902 update_type |= TRM_TRANS_GOAL; 903 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 904 update_type |= TRM_TRANS_USER; 905 intflag = splcam(); 906 pDCB = &pACB->DCBarray[target_id][target_lun]; 907 908 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 909 /*ccb disc enables */ 910 if (update_type & TRM_TRANS_GOAL) { 911 if ((cts->flags & CCB_TRANS_DISC_ENB) 912 != 0) 913 pDCB->tinfo.disc_tag 914 |= TRM_CUR_DISCENB; 915 else 916 pDCB->tinfo.disc_tag &= 917 ~TRM_CUR_DISCENB; 918 } 919 if (update_type & TRM_TRANS_USER) { 920 if ((cts->flags & CCB_TRANS_DISC_ENB) 921 != 0) 922 pDCB->tinfo.disc_tag 923 |= TRM_USR_DISCENB; 924 else 925 pDCB->tinfo.disc_tag &= 926 ~TRM_USR_DISCENB; 927 } 928 } 929 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 930 /* if ccb tag q active */ 931 if (update_type & TRM_TRANS_GOAL) { 932 if ((cts->flags & CCB_TRANS_TAG_ENB) 933 != 0) 934 pDCB->tinfo.disc_tag |= 935 TRM_CUR_TAGENB; 936 else 937 pDCB->tinfo.disc_tag &= 938 ~TRM_CUR_TAGENB; 939 } 940 if (update_type & TRM_TRANS_USER) { 941 if ((cts->flags & CCB_TRANS_TAG_ENB) 942 != 0) 943 pDCB->tinfo.disc_tag |= 944 TRM_USR_TAGENB; 945 else 946 pDCB->tinfo.disc_tag &= 947 ~TRM_USR_TAGENB; 948 } 949 } 950 /* Minimum sync period factor */ 951 952 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 953 /* if ccb sync active */ 954 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 955 if ((cts->sync_period != 0) && 956 (cts->sync_period < 125)) 957 cts->sync_period = 125; 958 /* 1/(125*4) minsync 2 MByte/sec */ 959 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 960 != 0) { 961 if (cts->sync_offset == 0) 962 cts->sync_period = 0; 963 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 964 if (cts->sync_offset > 15) 965 cts->sync_offset = 15; 966 } 967 } 968 if ((update_type & TRM_TRANS_USER) != 0) { 969 pDCB->tinfo.user.period = cts->sync_period; 970 pDCB->tinfo.user.offset = cts->sync_offset; 971 pDCB->tinfo.user.width = cts->bus_width; 972 } 973 if ((update_type & TRM_TRANS_GOAL) != 0) { 974 pDCB->tinfo.goal.period = cts->sync_period; 975 pDCB->tinfo.goal.offset = cts->sync_offset; 976 pDCB->tinfo.goal.width = cts->bus_width; 977 } 978 splx(intflag); 979 pccb->ccb_h.status = CAM_REQ_CMP; 980 xpt_done(pccb); 981 break; 982 } 983 /* 984 * Calculate the geometry parameters for a device give 985 * the sector size and volume size. 986 */ 987 case XPT_CALC_GEOMETRY: { 988 struct ccb_calc_geometry *ccg; 989 u_int32_t size_mb; 990 u_int32_t secs_per_cylinder; 991 int extended; 992 993 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 994 ccg = &pccb->ccg; 995 size_mb = ccg->volume_size / 996 ((1024L * 1024L) / ccg->block_size); 997 extended = 1; 998 if (size_mb > 1024 && extended) { 999 ccg->heads = 255; 1000 ccg->secs_per_track = 63; 1001 } else { 1002 ccg->heads = 64; 1003 ccg->secs_per_track = 32; 1004 } 1005 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 1006 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 1007 pccb->ccb_h.status = CAM_REQ_CMP; 1008 xpt_done(pccb); 1009 } 1010 break; 1011 case XPT_ENG_INQ: 1012 TRM_DPRINTF(" XPT_ENG_INQ \n"); 1013 pccb->ccb_h.status = CAM_REQ_INVALID; 1014 xpt_done(pccb); 1015 break; 1016 /* 1017 * HBA execute engine request 1018 * This structure must match SCSIIO size 1019 */ 1020 case XPT_ENG_EXEC: 1021 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1022 pccb->ccb_h.status = CAM_REQ_INVALID; 1023 xpt_done(pccb); 1024 break; 1025 /* 1026 * XPT_EN_LUN = 0x30, Enable LUN as a target 1027 * Target mode structures. 1028 */ 1029 case XPT_EN_LUN: 1030 /* 1031 * Don't (yet?) support vendor 1032 * specific commands. 1033 */ 1034 TRM_DPRINTF(" XPT_EN_LUN \n"); 1035 pccb->ccb_h.status = CAM_REQ_INVALID; 1036 xpt_done(pccb); 1037 break; 1038 /* 1039 * Execute target I/O request 1040 */ 1041 case XPT_TARGET_IO: 1042 /* 1043 * Don't (yet?) support vendor 1044 * specific commands. 1045 */ 1046 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1047 pccb->ccb_h.status = CAM_REQ_INVALID; 1048 xpt_done(pccb); 1049 break; 1050 /* 1051 * Accept Host Target Mode CDB 1052 */ 1053 case XPT_ACCEPT_TARGET_IO: 1054 /* 1055 * Don't (yet?) support vendor 1056 * specific commands. 1057 */ 1058 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1059 pccb->ccb_h.status = CAM_REQ_INVALID; 1060 xpt_done(pccb); 1061 break; 1062 /* 1063 * Continue Host Target I/O Connection 1064 */ 1065 case XPT_CONT_TARGET_IO: 1066 /* 1067 * Don't (yet?) support vendor 1068 * specific commands. 1069 */ 1070 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1071 pccb->ccb_h.status = CAM_REQ_INVALID; 1072 xpt_done(pccb); 1073 break; 1074 /* 1075 * Notify Host Target driver of event 1076 */ 1077 case XPT_IMMED_NOTIFY: 1078 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1079 pccb->ccb_h.status = CAM_REQ_INVALID; 1080 xpt_done(pccb); 1081 break; 1082 /* 1083 * Acknowledgement of event 1084 */ 1085 case XPT_NOTIFY_ACK: 1086 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1087 pccb->ccb_h.status = CAM_REQ_INVALID; 1088 xpt_done(pccb); 1089 break; 1090 /* 1091 * XPT_VUNIQUE = 0x80 1092 */ 1093 case XPT_VUNIQUE: 1094 pccb->ccb_h.status = CAM_REQ_INVALID; 1095 xpt_done(pccb); 1096 break; 1097 default: 1098 pccb->ccb_h.status = CAM_REQ_INVALID; 1099 xpt_done(pccb); 1100 break; 1101 } 1102 splx(actionflags); 1103} 1104 1105static void 1106trm_poll(struct cam_sim *psim) 1107{ 1108 1109} 1110 1111static void 1112trm_ResetDevParam(PACB pACB) 1113{ 1114 PDCB pDCB, pdcb; 1115 PNVRAMTYPE pEEpromBuf; 1116 u_int8_t PeriodIndex; 1117 1118 pDCB = pACB->pLinkDCB; 1119 if (pDCB == NULL) 1120 return; 1121 pdcb = pDCB; 1122 do { 1123 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1124 pDCB->SyncPeriod = 0; 1125 pDCB->SyncOffset = 0; 1126 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1127 pDCB->DevMode = 1128 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1129 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1130 PeriodIndex = 1131 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1132 if (pACB->AdaptType == 1) /* is U2? */ 1133 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1134 else 1135 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1136 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1137 (pACB->Config & HCC_WIDE_CARD)) 1138 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1139 pDCB = pDCB->pNextDCB; 1140 } 1141 while (pdcb != pDCB); 1142} 1143 1144static void 1145trm_RecoverSRB(PACB pACB) 1146{ 1147 PDCB pDCB, pdcb; 1148 PSRB psrb, psrb2; 1149 u_int16_t cnt, i; 1150 1151 pDCB = pACB->pLinkDCB; 1152 if (pDCB == NULL) 1153 return; 1154 pdcb = pDCB; 1155 do { 1156 cnt = pdcb->GoingSRBCnt; 1157 psrb = pdcb->pGoingSRB; 1158 for (i = 0; i < cnt; i++) { 1159 psrb2 = psrb; 1160 psrb = psrb->pNextSRB; 1161 if (pdcb->pWaitingSRB) { 1162 psrb2->pNextSRB = pdcb->pWaitingSRB; 1163 pdcb->pWaitingSRB = psrb2; 1164 } else { 1165 pdcb->pWaitingSRB = psrb2; 1166 pdcb->pWaitingLastSRB = psrb2; 1167 psrb2->pNextSRB = NULL; 1168 } 1169 } 1170 pdcb->GoingSRBCnt = 0; 1171 pdcb->pGoingSRB = NULL; 1172 pdcb = pdcb->pNextDCB; 1173 } 1174 while (pdcb != pDCB); 1175} 1176 1177static void 1178trm_reset(PACB pACB) 1179{ 1180 int intflag; 1181 u_int16_t i; 1182 1183 TRM_DPRINTF("trm: RESET"); 1184 intflag = splcam(); 1185 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1186 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1187 1188 trm_ResetSCSIBus(pACB); 1189 for (i = 0; i < 500; i++) 1190 DELAY(1000); 1191 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1192 /* Enable DMA interrupt */ 1193 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1194 /* Clear DMA FIFO */ 1195 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1196 /* Clear SCSI FIFO */ 1197 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1198 trm_ResetDevParam(pACB); 1199 trm_DoingSRB_Done(pACB); 1200 pACB->pActiveDCB = NULL; 1201 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1202 trm_DoWaitingSRB(pACB); 1203 /* Tell the XPT layer that a bus reset occured */ 1204 if (pACB->ppath != NULL) 1205 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1206 splx(intflag); 1207 return; 1208} 1209 1210static u_int16_t 1211trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1212{ 1213 u_int16_t return_code; 1214 u_int8_t scsicommand, i,command,identify_message; 1215 u_int8_t * ptr; 1216 union ccb *pccb; 1217 struct ccb_scsiio *pcsio; 1218 1219 pccb = pSRB->pccb; 1220 pcsio = &pccb->csio; 1221 1222 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1223 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1224 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1225 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1226 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1227 /* Flush FIFO */ 1228 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1229 1230 identify_message = pDCB->IdentifyMsg; 1231 1232 if ((pSRB->CmdBlock[0] == INQUIRY) || 1233 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1234 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1235 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1236 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1237 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1238 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1239 if (!(pDCB->IdentifyMsg & 7) || 1240 (pSRB->CmdBlock[0] != INQUIRY)) { 1241 scsicommand = SCMD_SEL_ATNSTOP; 1242 pSRB->SRBState = SRB_MSGOUT; 1243 goto polling; 1244 } 1245 } 1246 /* 1247 * Send identify message 1248 */ 1249 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1250 scsicommand = SCMD_SEL_ATN; 1251 pSRB->SRBState = SRB_START_; 1252 } else { 1253 /* not inquiry,request sense,auto request sense */ 1254 /* 1255 * Send identify message 1256 */ 1257 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1258 scsicommand = SCMD_SEL_ATN; 1259 pSRB->SRBState = SRB_START_; 1260 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1261 /* Send Tag message */ 1262 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1263 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1264 scsicommand = SCMD_SEL_ATN3; 1265 } 1266 } 1267polling: 1268 /* 1269 * Send CDB ..command block ......... 1270 */ 1271 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1272 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1273 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1274 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1275 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1276 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1277 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1278 } else { 1279 ptr = (u_int8_t *) pSRB->CmdBlock; 1280 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1281 command = *ptr++; 1282 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1283 } 1284 } 1285 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1286 /* 1287 * If trm_StartSCSI return 1 : 1288 * current interrupt status is interrupt disreenable 1289 * It's said that SCSI processor has more one SRB need to do, 1290 * SCSI processor has been occupied by one SRB. 1291 */ 1292 pSRB->SRBState = SRB_READY; 1293 return_code = 1; 1294 } else { 1295 /* 1296 * If trm_StartSCSI return 0 : 1297 * current interrupt status is interrupt enable 1298 * It's said that SCSI processor is unoccupied 1299 */ 1300 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1301 pACB->pActiveDCB = pDCB; 1302 pDCB->pActiveSRB = pSRB; 1303 return_code = 0; 1304 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1305 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1306 /* 1307 * SCSI cammand 1308 */ 1309 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1310 } 1311 return (return_code); 1312} 1313 1314static void 1315trm_Interrupt(vpACB) 1316void *vpACB; 1317{ 1318 PACB pACB; 1319 PDCB pDCB; 1320 PSRB pSRB; 1321 u_int16_t phase; 1322 void (*stateV)(PACB, PSRB, u_int16_t *); 1323 u_int16_t scsi_status=0; 1324 u_int8_t scsi_intstatus; 1325 1326 pACB = vpACB; 1327 1328 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1329 if (!(scsi_status & SCSIINTERRUPT)) { 1330 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1331 return; 1332 } 1333 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1334 1335 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1336 1337 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1338 1339 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1340 trm_Disconnect(pACB); 1341 return; 1342 } 1343 1344 if (scsi_intstatus & INT_RESELECTED) { 1345 trm_Reselect(pACB); 1346 return; 1347 } 1348 if (scsi_intstatus & INT_SCSIRESET) { 1349 trm_ScsiRstDetect(pACB); 1350 return; 1351 } 1352 1353 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1354 pDCB = pACB->pActiveDCB; 1355 pSRB = pDCB->pActiveSRB; 1356 if (pDCB) { 1357 if (pDCB->DCBFlag & ABORT_DEV_) 1358 trm_EnableMsgOutAbort1(pACB, pSRB); 1359 } 1360 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1361 stateV = (void *) trm_SCSI_phase0[phase]; 1362 stateV(pACB, pSRB, &scsi_status); 1363 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1364 /* phase:0,1,2,3,4,5,6,7 */ 1365 phase = (u_int16_t) scsi_status & PHASEMASK; 1366 stateV = (void *) trm_SCSI_phase1[phase]; 1367 stateV(pACB, pSRB, &scsi_status); 1368 } 1369} 1370 1371static void 1372trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1373{ 1374 1375 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1376 *pscsi_status = PH_BUS_FREE; 1377 /*.. initial phase*/ 1378} 1379 1380static void 1381trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1382{ 1383 u_int8_t bval; 1384 u_int16_t i, cnt; 1385 u_int8_t * ptr; 1386 PDCB pDCB; 1387 1388 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1389 pDCB = pACB->pActiveDCB; 1390 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1391 cnt = pSRB->MsgCnt; 1392 if (cnt) { 1393 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1394 for (i = 0; i < cnt; i++) { 1395 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1396 ptr++; 1397 } 1398 pSRB->MsgCnt = 0; 1399 if ((pDCB->DCBFlag & ABORT_DEV_) && 1400 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1401 pSRB->SRBState = SRB_ABORT_SENT; 1402 } 1403 } else { 1404 bval = MSG_ABORT; 1405 if ((pSRB->CmdBlock[0] == INQUIRY) || 1406 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1407 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1408 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1409 goto mop1; 1410 } 1411 } 1412 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1413 } 1414 } else { 1415mop1: /* message out phase */ 1416 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1417 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1418 /* 1419 * WIDE DATA TRANSFER REQUEST code (03h) 1420 */ 1421 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1422 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1423 TRMREG_SCSI_FIFO); 1424 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1425 /* (01h) */ 1426 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1427 /* Message length (02h) */ 1428 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1429 /* wide data xfer (03h) */ 1430 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1431 /* width:0(8bit),1(16bit),2(32bit) */ 1432 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1433 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1434 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1435 /* 1436 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1437 */ 1438 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1439 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1440 TRMREG_SCSI_FIFO); 1441 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1442 /* (01h) */ 1443 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1444 /* Message length (03h) */ 1445 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1446 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1447 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1448 /* Transfer peeriod factor */ 1449 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1450 TRMREG_SCSI_FIFO); 1451 /* REQ/ACK offset */ 1452 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1453 } 1454 } 1455 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1456 /* it's important for atn stop */ 1457 /* 1458 * SCSI cammand 1459 */ 1460 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1461} 1462 1463static void 1464trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1465{ 1466 1467} 1468 1469static void 1470trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1471{ 1472 PDCB pDCB; 1473 u_int8_t * ptr; 1474 u_int16_t i, cnt; 1475 union ccb *pccb; 1476 struct ccb_scsiio *pcsio; 1477 1478 pccb = pSRB->pccb; 1479 pcsio = &pccb->csio; 1480 1481 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1482 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1483 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1484 ptr = (u_int8_t *) pSRB->CmdBlock; 1485 for (i = 0; i < cnt; i++) { 1486 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1487 ptr++; 1488 } 1489 } else { 1490 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1491 pDCB = pACB->pActiveDCB; 1492 /* target id */ 1493 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1494 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1495 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1496 /* sizeof(struct scsi_sense_data) */ 1497 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1498 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1499 } 1500 pSRB->SRBState = SRB_COMMAND; 1501 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1502 /* it's important for atn stop*/ 1503 /* 1504 * SCSI cammand 1505 */ 1506 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1507} 1508 1509static void 1510trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1511{ 1512 PDCB pDCB; 1513 u_int8_t TempDMAstatus,SGIndexTemp; 1514 u_int16_t scsi_status; 1515 PSEG pseg; 1516 u_long TempSRBXferredLength,dLeftCounter=0; 1517 1518 pDCB = pSRB->pSRBDCB; 1519 scsi_status = *pscsi_status; 1520 1521 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1522 if (scsi_status & PARITYERROR) 1523 pSRB->SRBStatus |= PARITY_ERROR; 1524 if (!(scsi_status & SCSIXFERDONE)) { 1525 /* 1526 * when data transfer from DMA FIFO to SCSI FIFO 1527 * if there was some data left in SCSI FIFO 1528 */ 1529 dLeftCounter = (u_long) 1530 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1531 if (pDCB->SyncPeriod & WIDE_SYNC) { 1532 /* 1533 * if WIDE scsi SCSI FIFOCNT unit is word 1534 * so need to * 2 1535 */ 1536 dLeftCounter <<= 1; 1537 } 1538 } 1539 /* 1540 * caculate all the residue data that not yet tranfered 1541 * SCSI transfer counter + left in SCSI FIFO data 1542 * 1543 * .....TRM_SCSI_COUNTER (24bits) 1544 * The counter always decrement by one for every SCSI byte 1545 *transfer. 1546 * .....TRM_SCSI_FIFOCNT (5bits) 1547 * The counter is SCSI FIFO offset counter 1548 */ 1549 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1550 if (dLeftCounter == 1) { 1551 dLeftCounter = 0; 1552 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1553 } 1554 if ((dLeftCounter == 0) || 1555 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1556 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1557 while (!(TempDMAstatus & DMAXFERCOMP)) { 1558 TempDMAstatus = 1559 trm_reg_read8(TRMREG_DMA_STATUS); 1560 } 1561 pSRB->SRBTotalXferLength = 0; 1562 } else { 1563 /* Update SG list */ 1564 /* 1565 * if transfer not yet complete 1566 * there were some data residue in SCSI FIFO or 1567 * SCSI transfer counter not empty 1568 */ 1569 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1570 /* 1571 * data that had transferred length 1572 */ 1573 TempSRBXferredLength = 1574 pSRB->SRBTotalXferLength - dLeftCounter; 1575 /* 1576 * next time to be transferred length 1577 */ 1578 pSRB->SRBTotalXferLength = dLeftCounter; 1579 /* 1580 * parsing from last time disconnect SRBSGIndex 1581 */ 1582 pseg = 1583 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1584 for (SGIndexTemp = pSRB->SRBSGIndex; 1585 SGIndexTemp < pSRB->SRBSGCount; 1586 SGIndexTemp++) { 1587 /* 1588 * find last time which SG transfer be 1589 * disconnect 1590 */ 1591 if (TempSRBXferredLength >= 1592 pseg->length) 1593 TempSRBXferredLength -= 1594 pseg->length; 1595 else { 1596 /* 1597 * update last time disconnected SG 1598 * list 1599 */ 1600 pseg->length -= 1601 TempSRBXferredLength; 1602 /* residue data length */ 1603 pseg->address += 1604 TempSRBXferredLength; 1605 /* residue data pointer */ 1606 pSRB->SRBSGIndex = SGIndexTemp; 1607 break; 1608 } 1609 pseg++; 1610 } 1611 } 1612 } 1613 } 1614 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1615} 1616 1617 1618static void 1619trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1620{ 1621 u_int16_t ioDir; 1622 /* 1623 * do prepare befor transfer when data out phase 1624 */ 1625 1626 ioDir = XFERDATAOUT; 1627 trm_DataIO_transfer(pACB, pSRB, ioDir); 1628} 1629 1630static void 1631trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1632{ 1633 u_int8_t TempDMAstatus, SGIndexTemp; 1634 u_int16_t scsi_status; 1635 PSEG pseg; 1636 u_long TempSRBXferredLength,dLeftCounter = 0; 1637 1638 scsi_status = *pscsi_status; 1639 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1640 if (scsi_status & PARITYERROR) 1641 pSRB->SRBStatus |= PARITY_ERROR; 1642 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1643 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1644 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1645 while (!(TempDMAstatus & DMAXFERCOMP)) 1646 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1647 pSRB->SRBTotalXferLength = 0; 1648 } else { 1649 /* 1650 * parsing the case: 1651 * when a transfer not yet complete 1652 * but be disconnected by uper layer 1653 * if transfer not yet complete 1654 * there were some data residue in SCSI FIFO or 1655 * SCSI transfer counter not empty 1656 */ 1657 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1658 /* 1659 * data that had transferred length 1660 */ 1661 TempSRBXferredLength = 1662 pSRB->SRBTotalXferLength - dLeftCounter; 1663 /* 1664 * next time to be transferred length 1665 */ 1666 pSRB->SRBTotalXferLength = dLeftCounter; 1667 /* 1668 * parsing from last time disconnect SRBSGIndex 1669 */ 1670 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1671 for (SGIndexTemp = pSRB->SRBSGIndex; 1672 SGIndexTemp < pSRB->SRBSGCount; 1673 SGIndexTemp++) { 1674 /* 1675 * find last time which SG transfer be disconnect 1676 */ 1677 if (TempSRBXferredLength >= pseg->length) 1678 TempSRBXferredLength -= pseg->length; 1679 else { 1680 /* 1681 * update last time disconnected SG list 1682 */ 1683 pseg->length -= TempSRBXferredLength; 1684 /* residue data length */ 1685 pseg->address += TempSRBXferredLength; 1686 /* residue data pointer */ 1687 pSRB->SRBSGIndex = SGIndexTemp; 1688 break; 1689 } 1690 pseg++; 1691 } 1692 } 1693 } 1694 } 1695} 1696 1697static void 1698trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1699{ 1700 u_int16_t ioDir; 1701 /* 1702 * do prepare befor transfer when data in phase 1703 */ 1704 1705 ioDir = XFERDATAIN; 1706 trm_DataIO_transfer(pACB, pSRB, ioDir); 1707} 1708 1709static void 1710trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1711{ 1712 u_int8_t bval; 1713 PDCB pDCB; 1714 1715 pDCB = pSRB->pSRBDCB; 1716 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1717 if (pSRB->SRBTotalXferLength != 0) { 1718 /* 1719 * load what physical address of Scatter/Gather list 1720 table want to be transfer 1721 */ 1722 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1723 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1724 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1725 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1726 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1727 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1728 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1729 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1730 1731 pSRB->SRBState = SRB_DATA_XFER; 1732 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1733 trm_reg_write32( 1734 (pSRB->SRBSGPhyAddr + 1735 ((u_long)pSRB->SRBSGIndex << 3)), 1736 TRMREG_DMA_XLOWADDR); 1737 /* 1738 * load how many bytes in the Scatter/Gather 1739 * list table 1740 */ 1741 trm_reg_write32( 1742 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1743 TRMREG_DMA_XCNT); 1744 /* 1745 * load total transfer length (24bits) max value 1746 * 16Mbyte 1747 */ 1748 trm_reg_write32(pSRB->SRBTotalXferLength, 1749 TRMREG_SCSI_COUNTER); 1750 /* Start DMA transfer */ 1751 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1752 /* Start SCSI transfer */ 1753 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1754 /* it's important for atn stop */ 1755 /* 1756 * SCSI cammand 1757 */ 1758 bval = (ioDir == XFERDATAOUT) ? 1759 SCMD_DMA_OUT : SCMD_DMA_IN; 1760 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1761 } else { 1762 /* xfer pad */ 1763 if (pSRB->SRBSGCount) { 1764 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1765 pSRB->SRBStatus |= OVER_RUN; 1766 } 1767 if (pDCB->SyncPeriod & WIDE_SYNC) 1768 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1769 else 1770 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1771 if (ioDir == XFERDATAOUT) 1772 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1773 else 1774 trm_reg_read16(TRMREG_SCSI_FIFO); 1775 pSRB->SRBState |= SRB_XFERPAD; 1776 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1777 /* it's important for atn stop */ 1778 /* 1779 * SCSI cammand 1780 */ 1781 bval = (ioDir == XFERDATAOUT) ? 1782 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1783 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1784 } 1785 } 1786} 1787 1788static void 1789trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1790{ 1791 1792 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1793 pSRB->SRBState = SRB_COMPLETED; 1794 *pscsi_status = PH_BUS_FREE; 1795 /*.. initial phase*/ 1796 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1797 /* it's important for atn stop */ 1798 /* 1799 * SCSI cammand 1800 */ 1801 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1802} 1803 1804 1805 1806static void 1807trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1808{ 1809 1810 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1811 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1812 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1813 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1814 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1815 } else { 1816 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1817 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1818 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1819 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1820 } 1821 pSRB->SRBState = SRB_STATUS; 1822 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1823 /* it's important for atn stop */ 1824 /* 1825 * SCSI cammand 1826 */ 1827 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1828} 1829 1830/* 1831 *scsiiom 1832 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1833 * stateV = (void *) trm_SCSI_phase0[phase] 1834 * if phase =7 1835 * extended message codes: 1836 * 1837 * code description 1838 * 1839 * 02h Reserved 1840 * 00h MODIFY DATA POINTER 1841 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1842 * 03h WIDE DATA TRANSFER REQUEST 1843 * 04h - 7Fh Reserved 1844 * 80h - FFh Vendor specific 1845 * 1846 */ 1847 1848static void 1849trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1850{ 1851 u_int8_t message_in_code,bIndex,message_in_tag_id; 1852 PDCB pDCB; 1853 PSRB pSRBTemp; 1854 1855 pDCB = pACB->pActiveDCB; 1856 1857 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1858 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1859 if (message_in_code == MSG_DISCONNECT) { 1860 pSRB->SRBState = SRB_DISCONNECT; 1861 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1862 /* it's important for atn stop */ 1863 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1864 /* 1865 * SCSI command 1866 */ 1867 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1868 return; 1869 } else if (message_in_code == MSG_SAVE_PTR) { 1870 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1871 /* it's important for atn stop */ 1872 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1873 /* 1874 * SCSI command 1875 */ 1876 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1877 return; 1878 } else if ((message_in_code == MSG_EXTENDED) || 1879 ((message_in_code >= MSG_SIMPLE_QTAG) && 1880 (message_in_code <= MSG_ORDER_QTAG))) { 1881 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1882 pSRB->MsgInBuf[0] = message_in_code; 1883 /* extended message (01h) */ 1884 pSRB->MsgCnt = 1; 1885 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1886 /* extended message length (n) */ 1887 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1888 /* it's important for atn stop */ 1889 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1890 /* 1891 * SCSI command 1892 */ 1893 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1894 return; 1895 } else if (message_in_code == MSG_REJECT_) { 1896 /* Reject message */ 1897 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1898 /* do wide nego reject */ 1899 pDCB = pSRB->pSRBDCB; 1900 pDCB->SyncMode |= WIDE_NEGO_DONE; 1901 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1902 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1903 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1904 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1905 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1906 /* Set ATN, in case ATN was clear */ 1907 pSRB->SRBState |= SRB_MSGOUT; 1908 trm_reg_write16( 1909 DO_SETATN, 1910 TRMREG_SCSI_CONTROL); 1911 } else { 1912 /* Clear ATN */ 1913 trm_reg_write16( 1914 DO_CLRATN, 1915 TRMREG_SCSI_CONTROL); 1916 } 1917 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1918 /* do sync nego reject */ 1919 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1920 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1921 pDCB = pSRB->pSRBDCB; 1922 pDCB->SyncMode &= 1923 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1924 pDCB->SyncPeriod = 0; 1925 pDCB->SyncOffset = 0; 1926 /* 1927 * 1928 * program SCSI control register 1929 * 1930 */ 1931 trm_reg_write8(pDCB->SyncPeriod, 1932 TRMREG_SCSI_SYNC); 1933 trm_reg_write8(pDCB->SyncOffset, 1934 TRMREG_SCSI_OFFSET); 1935 trm_SetXferRate(pACB,pSRB,pDCB); 1936 } 1937 } 1938 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1939 /* it's important for atn stop */ 1940 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1941 /* 1942 * SCSI command 1943 */ 1944 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1945 return; 1946 } else if (message_in_code == MSG_IGNOREWIDE) { 1947 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1948 trm_reg_read8(TRMREG_SCSI_FIFO); 1949 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1950 /* it's important for atn stop */ 1951 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1952 /* 1953 * SCSI command 1954 */ 1955 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1956 return; 1957 } else { 1958 /* Restore data pointer message */ 1959 /* Save data pointer message */ 1960 /* Completion message */ 1961 /* NOP message */ 1962 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1963 /* it's important for atn stop */ 1964 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1965 /* 1966 * SCSI command 1967 */ 1968 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1969 return; 1970 } 1971 } else { 1972 /* 1973 * Parsing incomming extented messages 1974 */ 1975 *pSRB->pMsgPtr = message_in_code; 1976 pSRB->MsgCnt++; 1977 pSRB->pMsgPtr++; 1978 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1979 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1980 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1981 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1982 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1983 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1984 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1985 /* 1986 * is QUEUE tag message : 1987 * 1988 * byte 0: 1989 * HEAD QUEUE TAG (20h) 1990 * ORDERED QUEUE TAG (21h) 1991 * SIMPLE QUEUE TAG (22h) 1992 * byte 1: 1993 * Queue tag (00h - FFh) 1994 */ 1995 if (pSRB->MsgCnt == 2) { 1996 pSRB->SRBState = 0; 1997 message_in_tag_id = pSRB->MsgInBuf[1]; 1998 pSRB = pDCB->pGoingSRB; 1999 pSRBTemp = pDCB->pGoingLastSRB; 2000 if (pSRB) { 2001 for (;;) { 2002 if (pSRB->TagNumber != 2003 message_in_tag_id) { 2004 if (pSRB == pSRBTemp) { 2005 goto mingx0; 2006 } 2007 pSRB = pSRB->pNextSRB; 2008 } else 2009 break; 2010 } 2011 if (pDCB->DCBFlag & ABORT_DEV_) { 2012 pSRB->SRBState = SRB_ABORT_SENT; 2013 trm_EnableMsgOutAbort1( 2014 pACB, pSRB); 2015 } 2016 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 2017 TRM_DPRINTF("SRB not yet disconnect........ \n "); 2018 goto mingx0; 2019 } 2020 pDCB->pActiveSRB = pSRB; 2021 pSRB->SRBState = SRB_DATA_XFER; 2022 } else { 2023mingx0: 2024 pSRB = &pACB->TmpSRB; 2025 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2026 pDCB->pActiveSRB = pSRB; 2027 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2028 trm_EnableMsgOutAbort2( 2029 pACB, 2030 pSRB); 2031 } 2032 } 2033 *pscsi_status = PH_BUS_FREE; 2034 /* .. initial phase */ 2035 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2036 /* it's important for atn stop */ 2037 /* 2038 * SCSI command 2039 */ 2040 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2041 return; 2042 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2043 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2044 /* 2045 * is Wide data xfer Extended message : 2046 * ====================================== 2047 * WIDE DATA TRANSFER REQUEST 2048 * ====================================== 2049 * byte 0 : Extended message (01h) 2050 * byte 1 : Extended message length (02h) 2051 * byte 2 : WIDE DATA TRANSFER code (03h) 2052 * byte 3 : Transfer width exponent 2053 */ 2054 pDCB = pSRB->pSRBDCB; 2055 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2056 if ((pSRB->MsgInBuf[1] != 2)) { 2057 /* Length is wrong, reject it */ 2058 pDCB->SyncMode &= 2059 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2060 pSRB->MsgCnt = 1; 2061 pSRB->MsgInBuf[0] = MSG_REJECT_; 2062 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2063 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2064 /* it's important for atn stop */ 2065 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2066 /* 2067 * SCSI command 2068 */ 2069 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2070 return; 2071 } 2072 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2073 /* Do wide negoniation */ 2074 if (pSRB->MsgInBuf[3] > 2) { 2075 /* > 32 bit */ 2076 /* reject_msg: */ 2077 pDCB->SyncMode &= 2078 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2079 pSRB->MsgCnt = 1; 2080 pSRB->MsgInBuf[0] = MSG_REJECT_; 2081 trm_reg_write16(DO_SETATN, 2082 TRMREG_SCSI_CONTROL); 2083 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2084 /* it's important for atn stop */ 2085 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2086 /* 2087 * SCSI command 2088 */ 2089 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2090 return; 2091 } 2092 if (pSRB->MsgInBuf[3] == 2) { 2093 pSRB->MsgInBuf[3] = 1; 2094 /* do 16 bits */ 2095 } else { 2096 if (!(pDCB->SyncMode 2097 & WIDE_NEGO_DONE)) { 2098 pSRB->SRBState &= 2099 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2100 pDCB->SyncMode |= 2101 WIDE_NEGO_DONE; 2102 pDCB->SyncMode &= 2103 ~(SYNC_NEGO_DONE | 2104 EN_ATN_STOP | 2105 WIDE_NEGO_ENABLE); 2106 if (pSRB->MsgInBuf[3] != 0) { 2107 /* is Wide data xfer */ 2108 pDCB->SyncPeriod |= 2109 WIDE_SYNC; 2110 pDCB->tinfo.current.width 2111 = MSG_EXT_WDTR_BUS_16_BIT; 2112 pDCB->tinfo.goal.width 2113 = MSG_EXT_WDTR_BUS_16_BIT; 2114 } 2115 } 2116 } 2117 } else 2118 pSRB->MsgInBuf[3] = 0; 2119 pSRB->SRBState |= SRB_MSGOUT; 2120 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2121 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2122 /* it's important for atn stop */ 2123 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2124 /* 2125 * SCSI command 2126 */ 2127 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2128 return; 2129 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2130 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2131 /* 2132 * is 8bit transfer Extended message : 2133 * ================================= 2134 * SYNCHRONOUS DATA TRANSFER REQUEST 2135 * ================================= 2136 * byte 0 : Extended message (01h) 2137 * byte 1 : Extended message length (03) 2138 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2139 * byte 3 : Transfer period factor 2140 * byte 4 : REQ/ACK offset 2141 */ 2142 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2143 if ((pSRB->MsgInBuf[1] != 3) || 2144 (pSRB->MsgInBuf[2] != 1)) { 2145 /* reject_msg: */ 2146 pSRB->MsgCnt = 1; 2147 pSRB->MsgInBuf[0] = MSG_REJECT_; 2148 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2149 *pscsi_status = PH_BUS_FREE; 2150 /* .. initial phase */ 2151 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2152 /* it's important for atn stop */ 2153 /* 2154 * SCSI cammand 2155 */ 2156 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2157 return; 2158 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2159 /* set async */ 2160 pDCB = pSRB->pSRBDCB; 2161 /* disable sync & sync nego */ 2162 pDCB->SyncMode &= 2163 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2164 pDCB->SyncPeriod = 0; 2165 pDCB->SyncOffset = 0; 2166 pDCB->tinfo.goal.period = 0; 2167 pDCB->tinfo.goal.offset = 0; 2168 pDCB->tinfo.current.period = 0; 2169 pDCB->tinfo.current.offset = 0; 2170 pDCB->tinfo.current.width = 2171 MSG_EXT_WDTR_BUS_8_BIT; 2172 /* 2173 * 2174 * program SCSI control register 2175 * 2176 */ 2177 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2178 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2179 trm_SetXferRate(pACB,pSRB,pDCB); 2180 *pscsi_status = PH_BUS_FREE; 2181 /* .. initial phase */ 2182 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2183 /* it's important for atn stop */ 2184 /* 2185 * SCSI cammand 2186 */ 2187 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2188 return; 2189 } else { 2190 /* set sync */ 2191 pDCB = pSRB->pSRBDCB; 2192 pDCB->SyncMode |= 2193 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2194 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2195 /* Transfer period factor */ 2196 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2197 /* REQ/ACK offset */ 2198 if(pACB->AdaptType == 1) { 2199 for(bIndex = 0; bIndex < 7; bIndex++) { 2200 if(pSRB->MsgInBuf[3] <= 2201 dc395u2x_clock_period[bIndex]) { 2202 pDCB->tinfo.goal.period = 2203 dc395u2x_tinfo_period[bIndex]; 2204 pDCB->tinfo.current.period = 2205 dc395u2x_tinfo_period[bIndex]; 2206 pDCB->tinfo.goal.offset = 2207 pDCB->SyncOffset; 2208 pDCB->tinfo.current.offset = 2209 pDCB->SyncOffset; 2210 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2211 break; 2212 } 2213 } 2214 } else { 2215 for(bIndex = 0; bIndex < 7; bIndex++) { 2216 if(pSRB->MsgInBuf[3] <= 2217 dc395x_clock_period[bIndex]) { 2218 pDCB->tinfo.goal.period = 2219 dc395x_tinfo_period[bIndex]; 2220 pDCB->tinfo.current.period = 2221 dc395x_tinfo_period[bIndex]; 2222 pDCB->tinfo.goal.offset = 2223 pDCB->SyncOffset; 2224 pDCB->tinfo.current.offset = 2225 pDCB->SyncOffset; 2226 pDCB->SyncPeriod |= 2227 (bIndex|ALT_SYNC); 2228 break; 2229 } 2230 } 2231 } 2232 /* 2233 * 2234 * program SCSI control register 2235 * 2236 */ 2237 trm_reg_write8(pDCB->SyncPeriod, 2238 TRMREG_SCSI_SYNC); 2239 trm_reg_write8(pDCB->SyncOffset, 2240 TRMREG_SCSI_OFFSET); 2241 trm_SetXferRate(pACB,pSRB,pDCB); 2242 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2243 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2244 /* 2245 ** SCSI command 2246 */ 2247 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2248 return; 2249 } 2250 } 2251 *pscsi_status = PH_BUS_FREE; 2252 /* .. initial phase */ 2253 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2254 /* it's important for atn stop */ 2255 /* 2256 * SCSI cammand 2257 */ 2258 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2259 } 2260} 2261 2262static void 2263trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2264{ 2265 2266 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2267 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2268 if (!(pSRB->SRBState & SRB_MSGIN)) { 2269 pSRB->SRBState &= SRB_DISCONNECT; 2270 pSRB->SRBState |= SRB_MSGIN; 2271 } 2272 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2273 /* it's important for atn stop*/ 2274 /* 2275 * SCSI cammand 2276 */ 2277 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2278} 2279 2280static void 2281trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2282{ 2283 2284} 2285 2286static void 2287trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2288{ 2289 2290} 2291 2292static void 2293trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2294{ 2295 union ccb *pccb; 2296 struct ccb_trans_settings neg; 2297 u_int16_t cnt, i; 2298 u_int8_t bval; 2299 PDCB pDCBTemp; 2300 2301 /* 2302 * set all lun device's period , offset 2303 */ 2304 TRM_DPRINTF("trm_SetXferRate\n"); 2305 pccb = pSRB->pccb; 2306 neg.sync_period = pDCB->tinfo.goal.period; 2307 neg.sync_offset = pDCB->tinfo.goal.offset; 2308 neg.valid = CCB_TRANS_SYNC_RATE_VALID | CCB_TRANS_SYNC_OFFSET_VALID; 2309 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2310 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2311 if (!(pDCB->IdentifyMsg & 0x07)) { 2312 pDCBTemp = pACB->pLinkDCB; 2313 cnt = pACB->DeviceCnt; 2314 bval = pDCB->TargetID; 2315 for (i = 0; i < cnt; i++) { 2316 if (pDCBTemp->TargetID == bval) { 2317 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2318 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2319 pDCBTemp->SyncMode = pDCB->SyncMode; 2320 } 2321 pDCBTemp = pDCBTemp->pNextDCB; 2322 } 2323 } 2324 return; 2325} 2326 2327/* 2328 * scsiiom 2329 * trm_Interrupt 2330 * 2331 * 2332 * ---SCSI bus phase 2333 * 2334 * PH_DATA_OUT 0x00 Data out phase 2335 * PH_DATA_IN 0x01 Data in phase 2336 * PH_COMMAND 0x02 Command phase 2337 * PH_STATUS 0x03 Status phase 2338 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2339 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2340 * PH_MSG_OUT 0x06 Message out phase 2341 * PH_MSG_IN 0x07 Message in phase 2342 * 2343 */ 2344static void 2345trm_Disconnect(PACB pACB) 2346{ 2347 PDCB pDCB; 2348 PSRB pSRB, psrb; 2349 u_int16_t i,j, cnt; 2350 u_int target_id,target_lun; 2351 2352 TRM_DPRINTF("trm_Disconnect...............\n "); 2353 2354 pDCB = pACB->pActiveDCB; 2355 if (!pDCB) { 2356 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2357 j = 400; 2358 while (--j) 2359 DELAY(1); 2360 /* 1 msec */ 2361 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2362 TRMREG_SCSI_CONTROL); 2363 return; 2364 } 2365 pSRB = pDCB->pActiveSRB; 2366 /* bug pSRB=0 */ 2367 target_id = pSRB->pccb->ccb_h.target_id; 2368 target_lun = pSRB->pccb->ccb_h.target_lun; 2369 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2370 pACB->pActiveDCB = 0; 2371 pSRB->ScsiPhase = PH_BUS_FREE; 2372 /* SCSI bus free Phase */ 2373 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2374 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2375 pSRB->SRBState = 0; 2376 trm_DoWaitingSRB(pACB); 2377 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2378 pDCB->DCBFlag = 0; 2379 cnt = pDCB->GoingSRBCnt; 2380 pDCB->GoingSRBCnt = 0; 2381 pSRB = pDCB->pGoingSRB; 2382 for (i = 0; i < cnt; i++) { 2383 psrb = pSRB->pNextSRB; 2384 pSRB->pNextSRB = pACB->pFreeSRB; 2385 pACB->pFreeSRB = pSRB; 2386 pSRB = psrb; 2387 } 2388 pDCB->pGoingSRB = 0; 2389 trm_DoWaitingSRB(pACB); 2390 } else { 2391 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2392 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2393 /* Selection time out */ 2394 if (!(pACB->scan_devices[target_id][target_lun]) && 2395 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2396 pSRB->CmdBlock[0] != INQUIRY) { 2397 pSRB->SRBState = SRB_READY; 2398 trm_RewaitSRB(pDCB, pSRB); 2399 } else { 2400 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2401 goto disc1; 2402 } 2403 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2404 /* 2405 * SRB_DISCONNECT 2406 */ 2407 trm_DoWaitingSRB(pACB); 2408 } else if (pSRB->SRBState & SRB_COMPLETED) { 2409disc1: 2410 /* 2411 * SRB_COMPLETED 2412 */ 2413 pDCB->pActiveSRB = 0; 2414 pSRB->SRBState = SRB_FREE; 2415 trm_SRBdone(pACB, pDCB, pSRB); 2416 } 2417 } 2418 return; 2419} 2420 2421static void 2422trm_Reselect(PACB pACB) 2423{ 2424 PDCB pDCB; 2425 PSRB pSRB; 2426 u_int16_t RselTarLunId; 2427 2428 TRM_DPRINTF("trm_Reselect................. \n"); 2429 pDCB = pACB->pActiveDCB; 2430 if (pDCB) { 2431 /* Arbitration lost but Reselection win */ 2432 pSRB = pDCB->pActiveSRB; 2433 pSRB->SRBState = SRB_READY; 2434 trm_RewaitSRB(pDCB, pSRB); 2435 } 2436 /* Read Reselected Target Id and LUN */ 2437 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2438 pDCB = pACB->pLinkDCB; 2439 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2440 /* get pDCB of the reselect id */ 2441 pDCB = pDCB->pNextDCB; 2442 } 2443 2444 pACB->pActiveDCB = pDCB; 2445 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2446 pSRB = &pACB->TmpSRB; 2447 pDCB->pActiveSRB = pSRB; 2448 } else { 2449 pSRB = pDCB->pActiveSRB; 2450 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2451 /* 2452 * abort command 2453 */ 2454 pSRB = &pACB->TmpSRB; 2455 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2456 pDCB->pActiveSRB = pSRB; 2457 trm_EnableMsgOutAbort1(pACB, pSRB); 2458 } else { 2459 if (pDCB->DCBFlag & ABORT_DEV_) { 2460 pSRB->SRBState = SRB_ABORT_SENT; 2461 trm_EnableMsgOutAbort1(pACB, pSRB); 2462 } else 2463 pSRB->SRBState = SRB_DATA_XFER; 2464 } 2465 } 2466 pSRB->ScsiPhase = PH_BUS_FREE; 2467 /* SCSI bus free Phase */ 2468 /* 2469 * Program HA ID, target ID, period and offset 2470 */ 2471 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2472 /* target ID */ 2473 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2474 /* host ID */ 2475 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2476 /* period */ 2477 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2478 /* offset */ 2479 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2480 /* it's important for atn stop*/ 2481 /* 2482 * SCSI cammand 2483 */ 2484 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2485 /* to rls the /ACK signal */ 2486} 2487 2488static void 2489trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2490{ 2491 PSRB psrb; 2492 u_int8_t bval, bval1,status; 2493 union ccb *pccb; 2494 struct ccb_scsiio *pcsio; 2495 PSCSI_INQDATA ptr; 2496 int intflag; 2497 u_int target_id,target_lun; 2498 PDCB pTempDCB; 2499 2500 pccb = pSRB->pccb; 2501 if (pccb == NULL) 2502 return; 2503 pcsio = &pccb->csio; 2504 target_id = pSRB->pccb->ccb_h.target_id; 2505 target_lun = pSRB->pccb->ccb_h.target_lun; 2506 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2507 int op; 2508 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2509 op = BUS_DMASYNC_POSTREAD; 2510 else 2511 op = BUS_DMASYNC_POSTWRITE; 2512 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2513 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2514 } 2515 /* 2516 * 2517 * target status 2518 * 2519 */ 2520 status = pSRB->TargetStatus; 2521 pcsio->scsi_status=SCSI_STAT_GOOD; 2522 pccb->ccb_h.status = CAM_REQ_CMP; 2523 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2524 /* 2525 * status of auto request sense 2526 */ 2527 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2528 pSRB->AdaptStatus = 0; 2529 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2530 2531 if (status == SCSI_STATUS_CHECK_COND) { 2532 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2533 goto ckc_e; 2534 } 2535 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2536 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2537 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2538 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2539 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2540 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2541 bzero(&pcsio->sense_data, pcsio->sense_len); 2542 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2543 pcsio->sense_len); 2544 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2545 | CAM_AUTOSNS_VALID; 2546 goto ckc_e; 2547 } 2548 /* 2549 * target status 2550 */ 2551 if (status) { 2552 if (status == SCSI_STATUS_CHECK_COND) { 2553 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2554 TRM_DPRINTF("trm_RequestSense..................\n"); 2555 trm_RequestSense(pACB, pDCB, pSRB); 2556 return; 2557 } 2558 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2559 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2560 goto ckc_e; 2561 } else if (status == SCSI_STAT_QUEUEFULL) { 2562 bval = (u_int8_t) pDCB->GoingSRBCnt; 2563 bval--; 2564 pDCB->MaxActiveCommandCnt = bval; 2565 trm_RewaitSRB(pDCB, pSRB); 2566 pSRB->AdaptStatus = 0; 2567 pSRB->TargetStatus = 0; 2568 return; 2569 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2570 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2571 pSRB->TargetStatus = 0; 2572 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2573 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2574 } else if (status == SCSI_STAT_BUSY) { 2575 TRM_DPRINTF("trm: target busy at %s %d\n", 2576 __FILE__, __LINE__); 2577 pcsio->scsi_status = SCSI_STAT_BUSY; 2578 pccb->ccb_h.status = CAM_SCSI_BUSY; 2579 return; 2580 /* The device busy, try again later? */ 2581 } else if (status == SCSI_STAT_RESCONFLICT) { 2582 TRM_DPRINTF("trm: target reserved at %s %d\n", 2583 __FILE__, __LINE__); 2584 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2585 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2586 return; 2587 } else { 2588 pSRB->AdaptStatus = 0; 2589 if (pSRB->RetryCnt) { 2590 pSRB->RetryCnt--; 2591 pSRB->TargetStatus = 0; 2592 pSRB->SRBSGIndex = 0; 2593 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2594 /* 2595 * If trm_StartSCSI return 1 : 2596 * current interrupt status is interrupt 2597 * disreenable 2598 * It's said that SCSI processor has more 2599 * one SRB need to do 2600 */ 2601 trm_RewaitSRB(pDCB, pSRB); 2602 } 2603 return; 2604 } else { 2605 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2606 __FILE__, __LINE__); 2607 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2608 } 2609 } 2610 } else { 2611 /* 2612 * process initiator status.......................... 2613 * Adapter (initiator) status 2614 */ 2615 status = pSRB->AdaptStatus; 2616 if (status & H_OVER_UNDER_RUN) { 2617 pSRB->TargetStatus = 0; 2618 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2619 /* Illegal length (over/under run) */ 2620 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2621 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2622 __FILE__, __LINE__); 2623 pDCB->tinfo.goal.period = 0; 2624 pDCB->tinfo.goal.offset = 0; 2625 /* Driver failed to perform operation */ 2626 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2627 } else { 2628 /* no error */ 2629 pSRB->AdaptStatus = 0; 2630 pSRB->TargetStatus = 0; 2631 pccb->ccb_h.status = CAM_REQ_CMP; 2632 /* there is no error, (sense is invalid) */ 2633 } 2634 } 2635ckc_e: 2636 if (pACB->scan_devices[target_id][target_lun]) { 2637 /* 2638 * if SCSI command in "scan devices" duty 2639 */ 2640 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2641 pACB->scan_devices[target_id][target_lun] = 0; 2642 /* SCSI command phase :test unit ready */ 2643 else if (pSRB->CmdBlock[0] == INQUIRY) { 2644 /* 2645 * SCSI command phase :inquiry scsi device data 2646 * (type,capacity,manufacture.... 2647 */ 2648 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2649 goto NO_DEV; 2650 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2651 /* page fault */ 2652 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2653 ptr->DevType); 2654 bval1 = ptr->DevType & SCSI_DEVTYPE; 2655 if (bval1 == SCSI_NODEV) { 2656NO_DEV: 2657 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2658 target_id, 2659 target_lun); 2660 intflag = splcam(); 2661 pACB->scan_devices[target_id][target_lun] = 0; 2662 /* no device set scan device flag =0*/ 2663 /* pDCB Q link */ 2664 /* move the head of DCB to tempDCB*/ 2665 pTempDCB=pACB->pLinkDCB; 2666 /* search current DCB for pass link */ 2667 while (pTempDCB->pNextDCB != pDCB) { 2668 pTempDCB = pTempDCB->pNextDCB; 2669 } 2670 /* 2671 * when the current DCB found than connect 2672 * current DCB tail 2673 */ 2674 /* to the DCB tail that before current DCB */ 2675 pTempDCB->pNextDCB = pDCB->pNextDCB; 2676 /* 2677 * if there was only one DCB ,connect his tail 2678 * to his head 2679 */ 2680 if (pACB->pLinkDCB == pDCB) 2681 pACB->pLinkDCB = pTempDCB->pNextDCB; 2682 if (pACB->pDCBRunRobin == pDCB) 2683 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2684 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2685 pACB->DeviceCnt--; 2686 if (pACB->DeviceCnt == 0) { 2687 pACB->pLinkDCB = NULL; 2688 pACB->pDCBRunRobin = NULL; 2689 } 2690 splx(intflag); 2691 } else { 2692#ifdef trm_DEBUG1 2693 int j; 2694 for (j = 0; j < 28; j++) { 2695 TRM_DPRINTF("ptr=%2x ", 2696 ((u_int8_t *)ptr)[j]); 2697 } 2698#endif 2699 pDCB->DevType = bval1; 2700 if (bval1 == SCSI_DASD || 2701 bval1 == SCSI_OPTICAL) { 2702 if ((((ptr->Vers & 0x07) >= 2) || 2703 ((ptr->RDF & 0x0F) == 2)) && 2704 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2705 (pDCB->DevMode & TAG_QUEUING_) && 2706 (pDCB->DevMode & EN_DISCONNECT_)) { 2707 if (pDCB->DevMode & 2708 TAG_QUEUING_) { 2709 pDCB-> 2710 MaxActiveCommandCnt = 2711 pACB->TagMaxNum; 2712 pDCB->SyncMode |= 2713 EN_TAG_QUEUING; 2714 pDCB->tinfo.disc_tag |= 2715 TRM_CUR_TAGENB; 2716 } else { 2717 pDCB->SyncMode |= 2718 EN_ATN_STOP; 2719 pDCB->tinfo.disc_tag &= 2720 ~TRM_CUR_TAGENB; 2721 } 2722 } 2723 } 2724 } 2725 /* pSRB->CmdBlock[0] == INQUIRY */ 2726 } 2727 /* pACB->scan_devices[target_id][target_lun] */ 2728 } 2729 intflag = splcam(); 2730 /* ReleaseSRB(pDCB, pSRB); */ 2731 if (pSRB == pDCB->pGoingSRB) 2732 pDCB->pGoingSRB = pSRB->pNextSRB; 2733 else { 2734 psrb = pDCB->pGoingSRB; 2735 while (psrb->pNextSRB != pSRB) { 2736 psrb = psrb->pNextSRB; 2737 } 2738 psrb->pNextSRB = pSRB->pNextSRB; 2739 if (pSRB == pDCB->pGoingLastSRB) { 2740 pDCB->pGoingLastSRB = psrb; 2741 } 2742 } 2743 pSRB->pNextSRB = pACB->pFreeSRB; 2744 pACB->pFreeSRB = pSRB; 2745 pDCB->GoingSRBCnt--; 2746 trm_DoWaitingSRB(pACB); 2747 2748 splx(intflag); 2749 /* Notify cmd done */ 2750 xpt_done (pccb); 2751} 2752 2753static void 2754trm_DoingSRB_Done(PACB pACB) 2755{ 2756 PDCB pDCB, pdcb; 2757 PSRB psrb, psrb2; 2758 u_int16_t cnt, i; 2759 union ccb *pccb; 2760 2761 pDCB = pACB->pLinkDCB; 2762 if (pDCB == NULL) 2763 return; 2764 pdcb = pDCB; 2765 do { 2766 cnt = pdcb->GoingSRBCnt; 2767 psrb = pdcb->pGoingSRB; 2768 for (i = 0; i < cnt; i++) { 2769 psrb2 = psrb->pNextSRB; 2770 pccb = psrb->pccb; 2771 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2772 /* ReleaseSRB(pDCB, pSRB); */ 2773 psrb->pNextSRB = pACB->pFreeSRB; 2774 pACB->pFreeSRB = psrb; 2775 xpt_done(pccb); 2776 psrb = psrb2; 2777 } 2778 pdcb->GoingSRBCnt = 0;; 2779 pdcb->pGoingSRB = NULL; 2780 pdcb = pdcb->pNextDCB; 2781 } 2782 while (pdcb != pDCB); 2783} 2784 2785static void 2786trm_ResetSCSIBus(PACB pACB) 2787{ 2788 int intflag; 2789 2790 intflag = splcam(); 2791 pACB->ACBFlag |= RESET_DEV; 2792 2793 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2794 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2795 splx(intflag); 2796 return; 2797} 2798 2799static void 2800trm_ScsiRstDetect(PACB pACB) 2801{ 2802 int intflag; 2803 u_long wlval; 2804 2805 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2806 wlval = 1000; 2807 while (--wlval) 2808 DELAY(1000); 2809 intflag = splcam(); 2810 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2811 2812 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2813 2814 if (pACB->ACBFlag & RESET_DEV) 2815 pACB->ACBFlag |= RESET_DONE; 2816 else { 2817 pACB->ACBFlag |= RESET_DETECT; 2818 trm_ResetDevParam(pACB); 2819 /* trm_DoingSRB_Done(pACB); ???? */ 2820 trm_RecoverSRB(pACB); 2821 pACB->pActiveDCB = NULL; 2822 pACB->ACBFlag = 0; 2823 trm_DoWaitingSRB(pACB); 2824 } 2825 splx(intflag); 2826 return; 2827} 2828 2829static void 2830trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2831{ 2832 union ccb *pccb; 2833 struct ccb_scsiio *pcsio; 2834 2835 pccb = pSRB->pccb; 2836 pcsio = &pccb->csio; 2837 2838 pSRB->SRBFlag |= AUTO_REQSENSE; 2839 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2840 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2841 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2842 pSRB->SRBSGCount); 2843 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2844 2845 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2846 pSRB->AdaptStatus = 0; 2847 pSRB->TargetStatus = 0; 2848 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2849 2850 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2851 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2852 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2853 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2854 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2855 pSRB->SRBSGCount = 1; 2856 pSRB->SRBSGIndex = 0; 2857 2858 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2859 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2860 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2861 pSRB->ScsiCmdLen = 6; 2862 2863 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2864 /* 2865 * If trm_StartSCSI return 1 : 2866 * current interrupt status is interrupt disreenable 2867 * It's said that SCSI processor has more one SRB need to do 2868 */ 2869 trm_RewaitSRB(pDCB, pSRB); 2870} 2871 2872static void 2873trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2874{ 2875 2876 pSRB->MsgCnt = 1; 2877 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2878} 2879 2880static void 2881trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2882{ 2883 2884 pSRB->MsgOutBuf[0] = MSG_ABORT; 2885 trm_EnableMsgOutAbort2(pACB, pSRB); 2886} 2887 2888static void 2889trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2890{ 2891 PNVRAMTYPE pEEpromBuf; 2892 u_int8_t bval,PeriodIndex; 2893 u_int target_id,target_lun; 2894 PDCB pTempDCB; 2895 int intflag; 2896 2897 target_id = i; 2898 target_lun = j; 2899 2900 /* 2901 * Using the lun 0 device to init other DCB first, if the device 2902 * has been initialized. 2903 * I don't want init sync arguments one by one, it is the same. 2904 */ 2905 if (target_lun != 0 && 2906 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2907 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2908 sizeof(TRM_DCB)); 2909 intflag = splcam(); 2910 if (pACB->pLinkDCB == 0) { 2911 pACB->pLinkDCB = pDCB; 2912 /* 2913 * RunRobin impersonate the role 2914 * that let each device had good proportion 2915 * about SCSI command proceeding 2916 */ 2917 pACB->pDCBRunRobin = pDCB; 2918 pDCB->pNextDCB = pDCB; 2919 } else { 2920 pTempDCB=pACB->pLinkDCB; 2921 /* search the last nod of DCB link */ 2922 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2923 pTempDCB = pTempDCB->pNextDCB; 2924 /* connect current DCB with last DCB tail */ 2925 pTempDCB->pNextDCB = pDCB; 2926 /* connect current DCB tail to this DCB Q head */ 2927 pDCB->pNextDCB=pACB->pLinkDCB; 2928 } 2929 splx(intflag); 2930 2931 pACB->DeviceCnt++; 2932 pDCB->TargetID = target_id; 2933 pDCB->TargetLUN = target_lun; 2934 pDCB->pWaitingSRB = NULL; 2935 pDCB->pGoingSRB = NULL; 2936 pDCB->GoingSRBCnt = 0; 2937 pDCB->pActiveSRB = NULL; 2938 pDCB->MaxActiveCommandCnt = 1; 2939 pDCB->DCBFlag = 0; 2940 pDCB->DCBstatus |= DS_IN_QUEUE; 2941 /* $$$$$$$ */ 2942 pEEpromBuf = &trm_eepromBuf[unit]; 2943 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2944 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2945 /* $$$$$$$ */ 2946 /* 2947 * disconnect enable ? 2948 */ 2949 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2950 bval = 0xC0; 2951 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2952 } else { 2953 bval = 0x80; 2954 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2955 } 2956 bval |= target_lun; 2957 pDCB->IdentifyMsg = bval; 2958 if (target_lun != 0 && 2959 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2960 return; 2961 /* $$$$$$$ */ 2962 /* 2963 * tag Qing enable ? 2964 */ 2965 if (pDCB->DevMode & TAG_QUEUING_) { 2966 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2967 } else 2968 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2969 /* $$$$$$$ */ 2970 /* 2971 * wide nego ,sync nego enable ? 2972 */ 2973 pDCB->SyncPeriod = 0; 2974 pDCB->SyncOffset = 0; 2975 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2976 if(pACB->AdaptType==1) {/* is U2? */ 2977 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2978 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2979 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2980 } else { 2981 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2982 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2983 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2984 } 2985 pDCB->SyncMode = 0; 2986 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2987 (pACB->Config & HCC_WIDE_CARD)) 2988 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2989 /* enable wide nego */ 2990 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2991 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2992 /* enable sync nego */ 2993 /* $$$$$$$ */ 2994 /* 2995 * Fill in tinfo structure. 2996 */ 2997 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2998 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2999 3000 pDCB->tinfo.current.period = 0; 3001 pDCB->tinfo.current.offset = 0; 3002 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 3003} 3004 3005static void 3006trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3007{ 3008 PSRB pSRB; 3009 3010 pSRB=(PSRB) arg; 3011 pSRB->SRBSGPhyAddr=segs->ds_addr; 3012 return; 3013} 3014 3015static int 3016trm_initSRB(PACB pACB) 3017{ 3018 u_int16_t i; 3019 PSRB pSRB; 3020 3021 for(i = 0; i < TRM_MAX_SRB_CNT; i++) { 3022 pSRB = (PSRB)&pACB->pFreeSRB[i]; 3023 3024 /* DMA tag for our S/G structures */ 3025 if(bus_dma_tag_create( 3026 /*parent_dmat*/pSRB->parent_dmat, 3027 /*alignment*/ 1, 3028 /*boundary*/ 0, 3029 /*lowaddr*/ BUS_SPACE_MAXADDR, 3030 /*highaddr*/ BUS_SPACE_MAXADDR, 3031 /*filter*/ NULL, 3032 /*filterarg*/ NULL, 3033 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3034 /*nsegments*/ 1, 3035 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3036 /*flags*/ 0, 3037 /*dmat*/ &pSRB->sg_dmat) != 0) { 3038 return ENXIO; 3039 } 3040 if(bus_dmamem_alloc(pSRB->sg_dmat, (void **)&pSRB->pSRBSGL, 3041 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 3042 return ENXIO; 3043 } 3044 bus_dmamap_load(pSRB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 3045 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3046 trm_srbmapSG, pSRB, /*flags*/0); 3047 if(i != TRM_MAX_SRB_CNT - 1) { 3048 /* 3049 ** link all SRB 3050 */ 3051 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 3052 } else { 3053 /* 3054 ** load NULL to NextSRB of the last SRB 3055 */ 3056 pSRB->pNextSRB = NULL; 3057 } 3058 pSRB->TagNumber = i; 3059 } 3060 return (0); 3061} 3062 3063 3064 3065 3066static void 3067trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3068{ 3069 PNVRAMTYPE pEEpromBuf; 3070 3071 pEEpromBuf = &trm_eepromBuf[unit]; 3072 pACB->max_id = 15; 3073 3074 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3075 pACB->max_lun = 7; 3076 else 3077 pACB->max_lun = 0; 3078 3079 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3080 pACB->max_id, pACB->max_lun); 3081 pACB->pLinkDCB = NULL; 3082 pACB->pDCBRunRobin = NULL; 3083 pACB->pActiveDCB = NULL; 3084 pACB->AdapterUnit = (u_int8_t)unit; 3085 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3086 pACB->AdaptSCSILUN = 0; 3087 pACB->DeviceCnt = 0; 3088 pACB->AdaptType = adaptType; 3089 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3090 pACB->ACBFlag = 0; 3091 return; 3092} 3093 3094static void 3095NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3096{ 3097 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3098 u_int8_t bAddr; 3099 3100 /* Enable SEEPROM */ 3101 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3102 TRMREG_GEN_CONTROL); 3103 /* 3104 * Write enable 3105 */ 3106 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3107 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3108 NVRAM_trm_wait_30us(pACB); 3109 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3110 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3111 } 3112 /* 3113 * Write disable 3114 */ 3115 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3116 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3117 NVRAM_trm_wait_30us(pACB); 3118 /* Disable SEEPROM */ 3119 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3120 TRMREG_GEN_CONTROL); 3121 return; 3122} 3123 3124static void 3125NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3126{ 3127 int i; 3128 u_int8_t bSendData; 3129 /* 3130 * Send write command & address 3131 */ 3132 3133 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3134 /* 3135 * Write data 3136 */ 3137 for (i = 0; i < 8; i++, bData <<= 1) { 3138 bSendData = NVR_SELECT; 3139 if (bData & 0x80) 3140 /* Start from bit 7 */ 3141 bSendData |= NVR_BITOUT; 3142 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3143 NVRAM_trm_wait_30us(pACB); 3144 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3145 NVRAM_trm_wait_30us(pACB); 3146 } 3147 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3148 NVRAM_trm_wait_30us(pACB); 3149 /* 3150 * Disable chip select 3151 */ 3152 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3153 NVRAM_trm_wait_30us(pACB); 3154 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3155 NVRAM_trm_wait_30us(pACB); 3156 /* 3157 * Wait for write ready 3158 */ 3159 while (1) { 3160 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3161 NVRAM_trm_wait_30us(pACB); 3162 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3163 NVRAM_trm_wait_30us(pACB); 3164 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3165 break; 3166 } 3167 } 3168 /* 3169 * Disable chip select 3170 */ 3171 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3172 return; 3173} 3174 3175static void 3176NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3177{ 3178 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3179 u_int8_t bAddr; 3180 3181 /* 3182 * Enable SEEPROM 3183 */ 3184 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3185 TRMREG_GEN_CONTROL); 3186 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3187 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3188 /* 3189 * Disable SEEPROM 3190 */ 3191 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3192 TRMREG_GEN_CONTROL); 3193 return; 3194} 3195 3196static u_int8_t 3197NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3198{ 3199 int i; 3200 u_int8_t bReadData, bData = 0; 3201 /* 3202 * Send read command & address 3203 */ 3204 3205 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3206 3207 for (i = 0; i < 8; i++) { 3208 /* 3209 * Read data 3210 */ 3211 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3212 NVRAM_trm_wait_30us(pACB); 3213 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3214 /* 3215 * Get data bit while falling edge 3216 */ 3217 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3218 bData <<= 1; 3219 if (bReadData & NVR_BITIN) { 3220 bData |= 1; 3221 } 3222 NVRAM_trm_wait_30us(pACB); 3223 } 3224 /* 3225 * Disable chip select 3226 */ 3227 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3228 return (bData); 3229} 3230 3231static void 3232NVRAM_trm_wait_30us(PACB pACB) 3233{ 3234 3235 /* ScsiPortStallExecution(30); wait 30 us */ 3236 trm_reg_write8(5, TRMREG_GEN_TIMER); 3237 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3238 return; 3239} 3240 3241static void 3242NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3243{ 3244 int i; 3245 u_int8_t bSendData; 3246 3247 for (i = 0; i < 3; i++, bCmd <<= 1) { 3248 /* 3249 * Program SB+OP code 3250 */ 3251 bSendData = NVR_SELECT; 3252 if (bCmd & 0x04) 3253 bSendData |= NVR_BITOUT; 3254 /* start from bit 2 */ 3255 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3256 NVRAM_trm_wait_30us(pACB); 3257 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3258 NVRAM_trm_wait_30us(pACB); 3259 } 3260 for (i = 0; i < 7; i++, bAddr <<= 1) { 3261 /* 3262 * Program address 3263 */ 3264 bSendData = NVR_SELECT; 3265 if (bAddr & 0x40) 3266 /* Start from bit 6 */ 3267 bSendData |= NVR_BITOUT; 3268 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3269 NVRAM_trm_wait_30us(pACB); 3270 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3271 NVRAM_trm_wait_30us(pACB); 3272 } 3273 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3274 NVRAM_trm_wait_30us(pACB); 3275} 3276 3277static void 3278trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3279{ 3280 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3281 u_int16_t wAddr, wCheckSum; 3282 u_long dAddr, *dpEeprom; 3283 3284 NVRAM_trm_read_all(pEEpromBuf,pACB); 3285 wCheckSum = 0; 3286 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3287 wAddr < 64; wAddr++, wpEeprom++) { 3288 wCheckSum += *wpEeprom; 3289 } 3290 if (wCheckSum != 0x1234) { 3291 /* 3292 * Checksum error, load default 3293 */ 3294 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3295 pEEpromBuf->NvramSubVendorID[1] = 3296 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3297 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3298 pEEpromBuf->NvramSubSysID[1] = 3299 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3300 pEEpromBuf->NvramSubClass = 0x00; 3301 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3302 pEEpromBuf->NvramVendorID[1] = 3303 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3304 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3305 pEEpromBuf->NvramDeviceID[1] = 3306 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3307 pEEpromBuf->NvramReserved = 0x00; 3308 3309 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3310 dAddr < 16; dAddr++, dpEeprom++) { 3311 *dpEeprom = 0x00000077; 3312 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3313 } 3314 3315 *dpEeprom++ = 0x04000F07; 3316 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3317 *dpEeprom++ = 0x00000015; 3318 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3319 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3320 *dpEeprom = 0x00; 3321 pEEpromBuf->NvramCheckSum = 0x00; 3322 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3323 wAddr < 63; wAddr++, wpEeprom++) 3324 wCheckSum += *wpEeprom; 3325 *wpEeprom = 0x1234 - wCheckSum; 3326 NVRAM_trm_write_all(pEEpromBuf,pACB); 3327 } 3328 return; 3329} 3330static int 3331trm_initAdapter(PACB pACB, u_int16_t unit) 3332{ 3333 PNVRAMTYPE pEEpromBuf; 3334 u_int16_t wval; 3335 u_int8_t bval; 3336 3337 pEEpromBuf = &trm_eepromBuf[unit]; 3338 3339 /* 250ms selection timeout */ 3340 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3341 /* Mask all the interrupt */ 3342 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3343 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3344 /* Reset SCSI module */ 3345 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3346 /* program configuration 0 */ 3347 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3348 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3349 pACB->Config |= HCC_WIDE_CARD; 3350 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3351 pACB->Config |= HCC_SCSI_RESET; 3352 if (pACB->Config & HCC_PARITY) 3353 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3354 else 3355 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3356 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3357 /* program configuration 1 */ 3358 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3359 /* program Host ID */ 3360 bval = pEEpromBuf->NvramScsiId; 3361 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3362 /* set ansynchronous transfer */ 3363 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3364 /* Trun LED control off*/ 3365 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3366 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3367 /* DMA config */ 3368 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3369 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3370 /* Clear pending interrupt status */ 3371 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3372 /* Enable SCSI interrupt */ 3373 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3374 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3375 return (0); 3376} 3377 3378static void 3379trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3380{ 3381 PACB pACB; 3382 3383 pACB = (PACB)arg; 3384 pACB->srb_physbase = segs->ds_addr; 3385} 3386 3387static void 3388trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3389{ 3390 bus_addr_t *baddr; 3391 3392 baddr = (bus_addr_t *)arg; 3393 *baddr = segs->ds_addr; 3394} 3395 3396static PACB 3397trm_init(u_int16_t unit, device_t dev) 3398{ 3399 PACB pACB; 3400 int rid = PCIR_MAPS, i = 0, j = 0; 3401 u_int16_t adaptType = 0; 3402 3403 pACB = (PACB) device_get_softc(dev); 3404 if (!pACB) { 3405 printf("trm%d: cannot allocate ACB !\n", unit); 3406 return (NULL); 3407 } 3408 bzero (pACB, sizeof (struct _ACB)); 3409 pACB->iores = bus_alloc_resource(dev, SYS_RES_IOPORT, 3410 &rid, 0, ~0, 1, RF_ACTIVE); 3411 if (pACB->iores == NULL) { 3412 printf("trm_init: bus_alloc_resource failed!\n"); 3413 return (NULL); 3414 } 3415 switch (pci_get_devid(dev)) { 3416 case PCI_DEVICEID_TRMS1040: 3417 adaptType = 0; 3418 break; 3419 case PCI_DEVICEID_TRMS2080: 3420 adaptType = 1; 3421 break; 3422 default: 3423 printf("trm_init %d: unknown adapter type!\n", unit); 3424 goto bad; 3425 } 3426 pACB->dev = dev; 3427 pACB->tag = rman_get_bustag(pACB->iores); 3428 pACB->bsh = rman_get_bushandle(pACB->iores); 3429 if (bus_dma_tag_create(/*parent_dmat*/ pACB->parent_dmat, 3430 /*alignment*/ 1, 3431 /*boundary*/ 0, 3432 /*lowaddr*/ BUS_SPACE_MAXADDR, 3433 /*highaddr*/ BUS_SPACE_MAXADDR, 3434 /*filter*/ NULL, 3435 /*filterarg*/ NULL, 3436 /*maxsize*/ MAXBSIZE, 3437 /*nsegments*/ TRM_NSEG, 3438 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3439 /*flags*/ BUS_DMA_ALLOCNOW, 3440 &pACB->buffer_dmat) != 0) 3441 goto bad; 3442 /* DMA tag for our ccb structures */ 3443 if(bus_dma_tag_create( 3444 /*parent_dmat*/pACB->parent_dmat, 3445 /*alignment*/ 1, 3446 /*boundary*/ 0, 3447 /*lowaddr*/ BUS_SPACE_MAXADDR, 3448 /*highaddr*/ BUS_SPACE_MAXADDR, 3449 /*filter*/ NULL, 3450 /*filterarg*/ NULL, 3451 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3452 /*nsegments*/ 1, 3453 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3454 /*flags*/ 0, 3455 /*dmat*/ &pACB->srb_dmat) != 0) { 3456 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3457 goto bad; 3458 } 3459 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3460 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3461 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3462 goto bad; 3463 } 3464 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3465 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3466 /* flags */0); 3467 /* Create, allocate, and map DMA buffers for autosense data */ 3468 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1, 3469 /*boundary*/0, 3470 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3471 /*highaddr*/BUS_SPACE_MAXADDR, 3472 /*filter*/NULL, /*filterarg*/NULL, 3473 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3474 /*nsegments*/1, 3475 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3476 /*flags*/0, &pACB->sense_dmat) != 0) { 3477 if (bootverbose) 3478 device_printf(dev, "cannot create sense buffer dmat\n"); 3479 goto bad; 3480 } 3481 3482 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3483 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3484 goto bad; 3485 3486 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3487 pACB->sense_buffers, 3488 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3489 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3490 3491 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3492 trm_initACB(pACB, adaptType, unit); 3493 for (i = 0; i < (pACB->max_id + 1); i++) { 3494 if (pACB->AdaptSCSIID == i) 3495 continue; 3496 for(j = 0; j < (pACB->max_lun + 1); j++) { 3497 pACB->scan_devices[i][j] = 1; 3498 /* we assume we need to scan all devices */ 3499 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3500 } 3501 } 3502 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3503 if (trm_initSRB(pACB)) { 3504 printf("trm_initSRB: error\n"); 3505 goto bad; 3506 } 3507 if (trm_initAdapter(pACB, unit)) { 3508 printf("trm_initAdapter: initial ERROR\n"); 3509 goto bad; 3510 } 3511 return (pACB); 3512bad: 3513 if (pACB->iores) 3514 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, 3515 pACB->iores); 3516 if (pACB->sense_dmamap) { 3517 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3518 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3519 pACB->sense_dmamap); 3520 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3521 } 3522 if (pACB->sense_dmat) 3523 bus_dma_tag_destroy(pACB->sense_dmat); 3524 if (pACB->srb_dmamap) { 3525 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3526 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3527 pACB->srb_dmamap); 3528 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3529 } 3530 if (pACB->srb_dmat) 3531 bus_dma_tag_destroy(pACB->srb_dmat); 3532 if (pACB->buffer_dmat) 3533 bus_dma_tag_destroy(pACB->buffer_dmat); 3534 return (NULL); 3535} 3536 3537static int 3538trm_attach(device_t dev) 3539{ 3540 struct cam_devq *device_Q; 3541 u_long device_id; 3542 PACB pACB = 0; 3543 int rid = 0; 3544 int unit = device_get_unit(dev); 3545 3546 device_id = pci_get_devid(dev); 3547 /* 3548 * These cards do not allow memory mapped accesses 3549 */ 3550 if ((pACB = trm_init((u_int16_t) unit, 3551 dev)) == NULL) { 3552 printf("trm%d: trm_init error!\n",unit); 3553 return (ENXIO); 3554 } 3555 /* After setting up the adapter, map our interrupt */ 3556 /* 3557 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3558 * start queue to reset to the idle loop. 3559 * Create device queue of SIM(s) 3560 * (MAX_START_JOB - 1) : max_sim_transactions 3561 */ 3562 pACB->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, 3563 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 3564 if (pACB->irq == NULL || 3565 bus_setup_intr(dev, pACB->irq, 3566 INTR_TYPE_CAM, trm_Interrupt, pACB, &pACB->ih)) { 3567 printf("trm%d: register Interrupt handler error!\n", unit); 3568 goto bad; 3569 } 3570 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3571 if (device_Q == NULL){ 3572 printf("trm%d: device_Q == NULL !\n",unit); 3573 goto bad; 3574 } 3575 /* 3576 * Now tell the generic SCSI layer 3577 * about our bus. 3578 * If this is the xpt layer creating a sim, then it's OK 3579 * to wait for an allocation. 3580 * XXX Should we pass in a flag to indicate that wait is OK? 3581 * 3582 * SIM allocation 3583 * 3584 * SCSI Interface Modules 3585 * The sim driver creates a sim for each controller. The sim device 3586 * queue is separately created in order to allow resource sharing betwee 3587 * sims. For instance, a driver may create one sim for each channel of 3588 * a multi-channel controller and use the same queue for each channel. 3589 * In this way, the queue resources are shared across all the channels 3590 * of the multi-channel controller. 3591 * trm_action : sim_action_func 3592 * trm_poll : sim_poll_func 3593 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3594 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3595 * pACB->unit : unit 3596 * 1 : max_dev_transactions 3597 * MAX_TAGS : max_tagged_dev_transactions 3598 * 3599 * *******Construct our first channel SIM entry 3600 */ 3601 pACB->psim = cam_sim_alloc(trm_action, 3602 trm_poll, 3603 "trm", 3604 pACB, 3605 unit, 3606 1, 3607 TRM_MAX_TAGS_CMD_QUEUE, 3608 device_Q); 3609 if (pACB->psim == NULL) { 3610 printf("trm%d: SIM allocate fault !\n",unit); 3611 cam_simq_free(device_Q); /* SIM allocate fault*/ 3612 goto bad; 3613 } 3614 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3615 printf("trm%d: xpt_bus_register fault !\n",unit); 3616 goto bad; 3617 } 3618 if (xpt_create_path(&pACB->ppath, 3619 NULL, 3620 cam_sim_path(pACB->psim), 3621 CAM_TARGET_WILDCARD, 3622 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3623 printf("trm%d: xpt_create_path fault !\n",unit); 3624 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3625 goto bad; 3626 } 3627 return (0); 3628bad: 3629 if (pACB->iores) 3630 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, 3631 pACB->iores); 3632 if (pACB->srb_dmamap) { 3633 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3634 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3635 pACB->srb_dmamap); 3636 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3637 } 3638 if (pACB->srb_dmat) 3639 bus_dma_tag_destroy(pACB->srb_dmat); 3640 if (pACB->sense_dmamap) { 3641 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3642 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3643 pACB->sense_dmamap); 3644 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3645 } 3646 if (pACB->sense_dmat) 3647 bus_dma_tag_destroy(pACB->sense_dmat); 3648 if (pACB->buffer_dmat) 3649 bus_dma_tag_destroy(pACB->buffer_dmat); 3650 if (pACB->ih) 3651 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3652 if (pACB->irq) 3653 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3654 if (pACB->psim) 3655 cam_sim_free(pACB->psim, TRUE); 3656 3657 return (ENXIO); 3658 3659} 3660 3661/* 3662* pci_device 3663* trm_probe (device_t tag, pcidi_t type) 3664* 3665*/ 3666static int 3667trm_probe(device_t dev) 3668{ 3669 switch (pci_get_devid(dev)) { 3670 case PCI_DEVICEID_TRMS1040: 3671 device_set_desc(dev, 3672 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3673 return (0); 3674 case PCI_DEVICEID_TRMS2080: 3675 device_set_desc(dev, 3676 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3677 return 0; 3678 default: 3679 return (ENXIO); 3680 } 3681} 3682 3683static int 3684trm_detach(device_t dev) 3685{ 3686 PACB pACB = device_get_softc(dev); 3687 3688 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, pACB->iores); 3689 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3690 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3691 pACB->srb_dmamap); 3692 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3693 bus_dma_tag_destroy(pACB->srb_dmat); 3694 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3695 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3696 pACB->sense_dmamap); 3697 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3698 bus_dma_tag_destroy(pACB->sense_dmat); 3699 bus_dma_tag_destroy(pACB->buffer_dmat); 3700 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3701 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3702 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3703 xpt_free_path(pACB->ppath); 3704 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3705 cam_sim_free(pACB->psim, TRUE); 3706 return (0); 3707} 3708static device_method_t trm_methods[] = { 3709 /* Device interface */ 3710 DEVMETHOD(device_probe, trm_probe), 3711 DEVMETHOD(device_attach, trm_attach), 3712 DEVMETHOD(device_detach, trm_detach), 3713 { 0, 0 } 3714}; 3715 3716static driver_t trm_driver = { 3717 "trm", trm_methods, sizeof(struct _ACB) 3718}; 3719 3720static devclass_t trm_devclass; 3721DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3722