trm.c revision 106922
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram DC395U/UW/F ,DC315/U 7 * PCI SCSI Bus Master Host Adapter 8 * (SCSI chip set used Tekram ASIC TRM-S1040) 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 */ 11 12/* 13 * HISTORY: 14 * 15 * REV# DATE NAME DESCRIPTION 16 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 17 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 18 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 19 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 20 */ 21 22/* 23 * 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. The name of the author may not be used to endorse or promote products 34 * derived from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 38 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 39 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 41 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 45 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 * 47 */ 48 49/* 50 * Imported into FreeBSD source repository, and updated to compile under 51 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 52 */ 53 54/* 55 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 56 * <doginou@ci0.org>, 2002-03-04 57 */ 58 59#include <sys/cdefs.h> 60__FBSDID("$FreeBSD: head/sys/dev/trm/trm.c 106922 2002-11-14 19:54:33Z cognet $"); 61 62#include <sys/param.h> 63 64#include <sys/systm.h> 65#include <sys/malloc.h> 66#include <sys/queue.h> 67#if __FreeBSD_version >= 500000 68#include <sys/bio.h> 69#endif 70#include <sys/buf.h> 71#include <sys/bus.h> 72#include <sys/kernel.h> 73 74#include <vm/vm.h> 75#include <vm/pmap.h> 76 77#include <pci/pcivar.h> 78#include <pci/pcireg.h> 79#include <machine/resource.h> 80#include <machine/bus_pio.h> 81#include <machine/bus.h> 82#include <machine/clock.h> 83#include <sys/rman.h> 84 85#include <cam/cam.h> 86#include <cam/cam_ccb.h> 87#include <cam/cam_sim.h> 88#include <cam/cam_xpt_sim.h> 89#include <cam/cam_debug.h> 90 91#include <cam/scsi/scsi_all.h> 92 93#include <dev/trm/trm.h> 94 95#define PCI_BASE_ADDR0 0x10 96#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 97#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 98#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 99#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 100 reg, value) 101#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 102 reg, value) 103#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 104 reg, value) 105 106#define PCI_Vendor_ID_TEKRAM 0x1DE1 107#define PCI_Device_ID_TRM_S1040 0x0391 108#define PCI_DEVICEID_TRMS1040 0x03911DE1 109 110#ifdef trm_DEBUG1 111#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 112#else 113#define TRM_DPRINTF(fmt, arg...) {} 114#endif /* TRM_DEBUG */ 115 116static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 117static void TRM_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 118static u_int8_t TRM_get_data(PACB pACB, u_int8_t bAddr); 119static void TRM_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 120static void TRM_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 121static void TRM_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 122static void TRM_wait_30us(PACB pACB); 123 124static void trm_Interrupt(void *vpACB); 125static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 126 u_int8_t * pscsi_status); 127static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 128 u_int8_t * pscsi_status); 129static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 130 u_int8_t * pscsi_status); 131static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 132 u_int8_t * pscsi_status); 133static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 134 u_int8_t * pscsi_status); 135static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 136 u_int8_t * pscsi_status); 137static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 138 u_int8_t * pscsi_status); 139static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 140 u_int8_t * pscsi_status); 141static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 142 u_int8_t * pscsi_status); 143static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 144 u_int8_t * pscsi_status); 145static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 146 u_int8_t * pscsi_status); 147static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 148 u_int8_t * pscsi_status); 149static void trm_Nop0(PACB pACB, PSRB pSRB, u_int8_t * pscsi_status); 150static void trm_Nop1(PACB pACB, PSRB pSRB, u_int8_t * pscsi_status); 151static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 152static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 153static void trm_Disconnect(PACB pACB); 154static void trm_Reselect(PACB pACB); 155static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 156static void trm_DoingSRB_Done(PACB pACB); 157static void trm_ScsiRstDetect(PACB pACB); 158static void trm_ResetSCSIBus(PACB pACB); 159static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 160static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 161static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 162static void trm_SendSRB(PACB pACB, PSRB pSRB); 163static int trm_probe(device_t tag); 164static int trm_attach(device_t tag); 165static void trm_reset(PACB pACB); 166 167static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 168 169static int trm_initAdapter(PACB pACB, u_int16_t unit, 170 device_t pci_config_id); 171static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 172 u_int32_t i, u_int32_t j); 173static void trm_initSRB(PSRB psrb); 174static void trm_linkSRB(PACB pACB); 175static void trm_initACB(PACB pACB, u_int16_t unit); 176/* CAM SIM entry points */ 177#define ccb_trmsrb_ptr spriv_ptr0 178#define ccb_trmacb_ptr spriv_ptr1 179static void trm_action(struct cam_sim *psim, union ccb *pccb); 180static void trm_poll(struct cam_sim *psim); 181 182 183static void * trm_SCSI_phase0[] = { 184 trm_DataOutPhase0, /* phase:0 */ 185 trm_DataInPhase0, /* phase:1 */ 186 trm_CommandPhase0, /* phase:2 */ 187 trm_StatusPhase0, /* phase:3 */ 188 trm_Nop0, /* phase:4 */ 189 trm_Nop1, /* phase:5 */ 190 trm_MsgOutPhase0, /* phase:6 */ 191 trm_MsgInPhase0, /* phase:7 */ 192}; 193 194/* 195 * 196 * stateV = (void *) trm_SCSI_phase1[phase] 197 * 198 */ 199static void * trm_SCSI_phase1[] = { 200 trm_DataOutPhase1, /* phase:0 */ 201 trm_DataInPhase1, /* phase:1 */ 202 trm_CommandPhase1, /* phase:2 */ 203 trm_StatusPhase1, /* phase:3 */ 204 trm_Nop0, /* phase:4 */ 205 trm_Nop1, /* phase:5 */ 206 trm_MsgOutPhase1, /* phase:6 */ 207 trm_MsgInPhase1, /* phase:7 */ 208}; 209 210 211NVRAMTYPE trm_eepromBuf[MAX_ADAPTER_NUM]; 212/* 213 *Fast20: 000 50ns, 20.0 Mbytes/s 214 * 001 75ns, 13.3 Mbytes/s 215 * 010 100ns, 10.0 Mbytes/s 216 * 011 125ns, 8.0 Mbytes/s 217 * 100 150ns, 6.6 Mbytes/s 218 * 101 175ns, 5.7 Mbytes/s 219 * 110 200ns, 5.0 Mbytes/s 220 * 111 250ns, 4.0 Mbytes/s 221 * 222 *Fast40: 000 25ns, 40.0 Mbytes/s 223 * 001 50ns, 20.0 Mbytes/s 224 * 010 75ns, 13.3 Mbytes/s 225 * 011 100ns, 10.0 Mbytes/s 226 * 100 125ns, 8.0 Mbytes/s 227 * 101 150ns, 6.6 Mbytes/s 228 * 110 175ns, 5.7 Mbytes/s 229 * 111 200ns, 5.0 Mbytes/s 230 */ 231 /* real period: */ 232u_int8_t dc395x_trm_clock_period[] = { 233 12,/* 48 ns 20 MB/sec */ 234 18,/* 72 ns 13.3 MB/sec */ 235 25,/* 100 ns 10.0 MB/sec */ 236 31,/* 124 ns 8.0 MB/sec */ 237 37,/* 148 ns 6.6 MB/sec */ 238 43,/* 172 ns 5.7 MB/sec */ 239 50,/* 200 ns 5.0 MB/sec */ 240 62 /* 248 ns 4.0 MB/sec */ 241}; 242 243u_int8_t dc395x_trm_tinfo_sync_period[] = { 244 12,/* 20.0 MB/sec */ 245 18,/* 13.3 MB/sec */ 246 25,/* 10.0 MB/sec */ 247 31,/* 8.0 MB/sec */ 248 37,/* 6.6 MB/sec */ 249 43,/* 5.7 MB/sec */ 250 50,/* 5.0 MB/sec */ 251 62,/* 4.0 MB/sec */ 252}; 253 254static PSRB 255trm_GetSRB(PACB pACB) 256{ 257 int intflag; 258 PSRB pSRB; 259 260 intflag = splcam(); 261 pSRB = pACB->pFreeSRB; 262 if (pSRB) { 263 pACB->pFreeSRB = pSRB->pNextSRB; 264 pSRB->pNextSRB = NULL; 265 } 266 splx(intflag); 267 return (pSRB); 268} 269 270static void 271trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 272{ 273 PSRB psrb1; 274 int intflag; 275 276 intflag = splcam(); 277 if ((psrb1 = pDCB->pWaitingSRB)) { 278 pSRB->pNextSRB = psrb1; 279 pDCB->pWaitingSRB = pSRB; 280 } else { 281 pSRB->pNextSRB = NULL; 282 pDCB->pWaitingSRB = pSRB; 283 pDCB->pWaitLastSRB = pSRB; 284 } 285 splx(intflag); 286} 287 288static void 289trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 290{ 291 PSRB psrb1; 292 int intflag; 293 u_int8_t bval; 294 295 intflag = splcam(); 296 pDCB->GoingSRBCnt--; 297 psrb1 = pDCB->pGoingSRB; 298 if (pSRB == psrb1) 299 pDCB->pGoingSRB = psrb1->pNextSRB; 300 else { 301 while (pSRB != psrb1->pNextSRB) 302 psrb1 = psrb1->pNextSRB; 303 psrb1->pNextSRB = pSRB->pNextSRB; 304 if (pSRB == pDCB->pGoingLastSRB) 305 pDCB->pGoingLastSRB = psrb1; 306 } 307 if ((psrb1 = pDCB->pWaitingSRB)) { 308 pSRB->pNextSRB = psrb1; 309 pDCB->pWaitingSRB = pSRB; 310 } else { 311 pSRB->pNextSRB = NULL; 312 pDCB->pWaitingSRB = pSRB; 313 pDCB->pWaitLastSRB = pSRB; 314 } 315 bval = pSRB->TagNumber; 316 pDCB->TagMask &= (~(1 << bval)); /* Free TAG number */ 317 splx(intflag); 318} 319 320static void 321trm_DoWaitingSRB(PACB pACB) 322{ 323 int intflag; 324 PDCB ptr, ptr1; 325 PSRB pSRB; 326 327 intflag = splcam(); 328 if (!(pACB->pActiveDCB) && 329 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 330 ptr = pACB->pDCBRunRobin; 331 if (!ptr) { 332 ptr = pACB->pLinkDCB; 333 pACB->pDCBRunRobin = ptr; 334 } 335 ptr1 = ptr; 336 for (;ptr1 ;) { 337 pACB->pDCBRunRobin = ptr1->pNextDCB; 338 if (!(ptr1->MaxCommand > ptr1->GoingSRBCnt) 339 || !(pSRB = ptr1->pWaitingSRB)) { 340 if (pACB->pDCBRunRobin == ptr) 341 break; 342 ptr1 = ptr1->pNextDCB; 343 } else { 344 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 345 /* 346 * If trm_StartSCSI return 0 : 347 * current interrupt status is interrupt enable 348 * It's said that SCSI processor is unoccupied 349 */ 350 ptr1->GoingSRBCnt++; 351 if (ptr1->pWaitLastSRB == pSRB) { 352 ptr1->pWaitingSRB = NULL; 353 ptr1->pWaitLastSRB = NULL; 354 } else 355 ptr1->pWaitingSRB = pSRB->pNextSRB; 356 pSRB->pNextSRB = NULL; 357 if (ptr1->pGoingSRB) 358 ptr1->pGoingLastSRB->pNextSRB = pSRB; 359 else 360 ptr1->pGoingSRB = pSRB; 361 ptr1->pGoingLastSRB = pSRB; 362 } 363 break; 364 } 365 } 366 } 367 splx(intflag); 368 return; 369} 370 371static void 372trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 373{ 374 375 if (pDCB->pWaitingSRB) { 376 pDCB->pWaitLastSRB->pNextSRB = pSRB; 377 pDCB->pWaitLastSRB = pSRB; 378 pSRB->pNextSRB = NULL; 379 } else { 380 pDCB->pWaitingSRB = pSRB; 381 pDCB->pWaitLastSRB = pSRB; 382 } 383} 384 385static void 386trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int vp) 387{ 388 int flags; 389 PACB pACB; 390 PSRB pSRB; 391 union ccb *ccb; 392 u_long totalxferlen=0; 393 394 pSRB = (PSRB)arg; 395 ccb = pSRB->pccb; 396 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 397 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 398 if (nseg != 0) { 399 PSEG psg; 400 bus_dma_segment_t *end_seg; 401 bus_dmasync_op_t op; 402 403 /* Copy the segments into our SG list */ 404 end_seg = dm_segs + nseg; 405 psg = (PSEG) &pSRB->SegmentX[0]; 406 pSRB->SRBSGListPointer= psg; 407 while (dm_segs < end_seg) { 408 psg->address = vp?(u_long)vtophys(dm_segs->ds_addr) 409 :(u_long)dm_segs->ds_addr; 410 psg->length = (u_long)dm_segs->ds_len; 411 totalxferlen += dm_segs->ds_len; 412 psg++; 413 dm_segs++; 414 } 415 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 416 op = BUS_DMASYNC_PREREAD; 417 } else { 418 op = BUS_DMASYNC_PREWRITE; 419 } 420 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 421 } 422 pSRB->RetryCnt = 0; 423 pSRB->SRBTotalXferLength=totalxferlen; 424 pSRB->SRBSGCount = nseg; 425 pSRB->SRBSGIndex = 0; 426 pSRB->AdaptStatus = 0; 427 pSRB->TargetStatus = 0; 428 pSRB->MsgCnt = 0; 429 pSRB->SRBStatus = 0; 430 pSRB->SRBFlag = 0; 431 pSRB->SRBState = 0; 432 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 433 434 flags = splcam(); 435 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 436 if (nseg != 0) 437 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 438 pSRB->pNextSRB = pACB->pFreeSRB; 439 pACB->pFreeSRB = pSRB; 440 xpt_done(ccb); 441 splx(flags); 442 return; 443 } 444 ccb->ccb_h.status |= CAM_SIM_QUEUED; 445#if 0 446 /* XXX Need a timeout handler */ 447 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 448#endif 449 trm_SendSRB(pACB, pSRB); 450 splx(flags); 451 return; 452} 453 454static void 455trm_SendSRB(PACB pACB, PSRB pSRB) 456{ 457 int intflag; 458 PDCB pDCB; 459 460 intflag = splcam(); 461 pDCB = pSRB->pSRBDCB; 462 if (!(pDCB->MaxCommand > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 463 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 464 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxCommand); 465 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 466 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 467 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 468 trm_SRBwaiting(pDCB, pSRB); 469 goto SND_EXIT; 470 } 471 472 if (pDCB->pWaitingSRB) { 473 trm_SRBwaiting(pDCB, pSRB); 474 pSRB = pDCB->pWaitingSRB; 475 pDCB->pWaitingSRB = pSRB->pNextSRB; 476 pSRB->pNextSRB = NULL; 477 } 478 479 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 480 /* 481 * If trm_StartSCSI return 0 : 482 * current interrupt status is interrupt enable 483 * It's said that SCSI processor is unoccupied 484 */ 485 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 486 if (pDCB->pGoingSRB) { 487 pDCB->pGoingLastSRB->pNextSRB = pSRB; 488 pDCB->pGoingLastSRB = pSRB; 489 } else { 490 pDCB->pGoingSRB = pSRB; 491 pDCB->pGoingLastSRB = pSRB; 492 } 493 } else { 494 /* 495 * If trm_StartSCSI return 1 : 496 * current interrupt status is interrupt disreenable 497 * It's said that SCSI processor has more one SRB need to do 498 */ 499 trm_RewaitSRB0(pDCB, pSRB); 500 } 501SND_EXIT: 502 splx(intflag); 503 /* 504 * enable interrupt 505 */ 506 return; 507} 508 509 510static void 511trm_action(struct cam_sim *psim, union ccb *pccb) 512{ 513 PACB pACB; 514 u_int target_id,target_lun; 515 516 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 517 518 pACB = (PACB) cam_sim_softc(psim); 519 target_id = pccb->ccb_h.target_id; 520 target_lun = pccb->ccb_h.target_lun; 521 522 switch (pccb->ccb_h.func_code) { 523 case XPT_NOOP: 524 TRM_DPRINTF(" XPT_NOOP \n"); 525 pccb->ccb_h.status = CAM_REQ_INVALID; 526 xpt_done(pccb); 527 break; 528 /* 529 * Execute the requested I/O operation 530 */ 531 case XPT_SCSI_IO: { 532 PDCB pDCB = NULL; 533 PSRB pSRB; 534 struct ccb_scsiio *pcsio; 535 536 pcsio = &pccb->csio; 537 TRM_DPRINTF(" XPT_SCSI_IO \n"); 538 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 539 ,target_id, target_lun); 540 TRM_DPRINTF( 541 "pACB->scan_devices[target_id][target_lun]= %d \n" 542 ,pACB->scan_devices[target_id][target_lun]); 543 pDCB = pACB->pDCB[target_id][target_lun]; 544 /* 545 * Assign an SRB and connect it with this ccb. 546 */ 547 pSRB = trm_GetSRB(pACB); 548 if (!pSRB) { 549 /* Freeze SIMQ */ 550 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 551 xpt_done(pccb); 552 return; 553 } 554 pSRB->pSRBDCB = pDCB; 555 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 556 pccb->ccb_h.ccb_trmacb_ptr = pACB; 557 pSRB->pccb = pccb; 558 pSRB->ScsiCmdLen = pcsio->cdb_len; 559 /* 560 * move layer of CAM command block to layer of SCSI 561 * Request Block for SCSI processor command doing 562 */ 563 bcopy(pcsio->cdb_io.cdb_bytes,pSRB->CmdBlock 564 ,pcsio->cdb_len); 565 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 566 != CAM_DIR_NONE) { 567 if ((pccb->ccb_h.flags & 568 CAM_SCATTER_VALID) == 0) { 569 if ((pccb->ccb_h.flags 570 & CAM_DATA_PHYS) == 0) { 571 int flags; 572 int error; 573 574 flags = splsoftvm(); 575 error = bus_dmamap_load( 576 pACB->buffer_dmat, 577 pSRB->dmamap, 578 pcsio->data_ptr, 579 pcsio->dxfer_len, 580 trm_ExecuteSRB, 581 pSRB, 582 0); 583 if (error == EINPROGRESS) { 584 xpt_freeze_simq( 585 pACB->psim, 586 1); 587 pccb->ccb_h.status |= 588 CAM_RELEASE_SIMQ; 589 } 590 splx(flags); 591 } else { 592 struct bus_dma_segment seg; 593 594 /* Pointer to physical buffer */ 595 seg.ds_addr = 596 (bus_addr_t)pcsio->data_ptr; 597 seg.ds_len = pcsio->dxfer_len; 598 trm_ExecuteSRB(pSRB, &seg, 1, 599 0); 600 } 601 } else { 602 /* CAM_SCATTER_VALID */ 603 struct bus_dma_segment *segs; 604 605 if ((pccb->ccb_h.flags & 606 CAM_SG_LIST_PHYS) == 0 || 607 (pccb->ccb_h.flags 608 & CAM_DATA_PHYS) != 0) { 609 pSRB->pNextSRB = pACB->pFreeSRB; 610 pACB->pFreeSRB = pSRB; 611 pccb->ccb_h.status = 612 CAM_PROVIDE_FAIL; 613 xpt_done(pccb); 614 return; 615 } 616 617 /* cam SG list is physical, 618 * cam data is virtual 619 */ 620 segs = (struct bus_dma_segment *) 621 pcsio->data_ptr; 622 trm_ExecuteSRB(pSRB, segs, 623 pcsio->sglist_cnt, 1); 624 } /* CAM_SCATTER_VALID */ 625 } else 626 trm_ExecuteSRB(pSRB, NULL, 0, 0); 627 } 628 break; 629 case XPT_GDEV_TYPE: 630 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 631 pccb->ccb_h.status = CAM_REQ_INVALID; 632 xpt_done(pccb); 633 break; 634 case XPT_GDEVLIST: 635 TRM_DPRINTF(" XPT_GDEVLIST \n"); 636 pccb->ccb_h.status = CAM_REQ_INVALID; 637 xpt_done(pccb); 638 break; 639 /* 640 * Path routing inquiry 641 * Path Inquiry CCB 642 */ 643 case XPT_PATH_INQ: { 644 struct ccb_pathinq *cpi = &pccb->cpi; 645 646 TRM_DPRINTF(" XPT_PATH_INQ \n"); 647 cpi->version_num = 1; 648 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 649 cpi->target_sprt = 0; 650 cpi->hba_misc = 0; 651 cpi->hba_eng_cnt = 0; 652 cpi->max_target = 15 ; 653 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 654 cpi->initiator_id = pACB->AdaptSCSIID; 655 cpi->bus_id = cam_sim_bus(psim); 656 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 657 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 658 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 659 cpi->unit_number = cam_sim_unit(psim); 660 cpi->ccb_h.status = CAM_REQ_CMP; 661 xpt_done(pccb); 662 } 663 break; 664 /* 665 * Release a frozen SIM queue 666 * Release SIM Queue 667 */ 668 case XPT_REL_SIMQ: 669 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 670 pccb->ccb_h.status = CAM_REQ_INVALID; 671 xpt_done(pccb); 672 break; 673 /* 674 * Set Asynchronous Callback Parameters 675 * Set Asynchronous Callback CCB 676 */ 677 case XPT_SASYNC_CB: 678 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 679 pccb->ccb_h.status = CAM_REQ_INVALID; 680 xpt_done(pccb); 681 break; 682 /* 683 * Set device type information 684 * Set Device Type CCB 685 */ 686 case XPT_SDEV_TYPE: 687 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 688 pccb->ccb_h.status = CAM_REQ_INVALID; 689 xpt_done(pccb); 690 break; 691 /* 692 * (Re)Scan the SCSI Bus 693 * Rescan the given bus, or bus/target/lun 694 */ 695 case XPT_SCAN_BUS: 696 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 697 pccb->ccb_h.status = CAM_REQ_INVALID; 698 xpt_done(pccb); 699 break; 700 /* 701 * Get EDT entries matching the given pattern 702 */ 703 case XPT_DEV_MATCH: 704 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 705 pccb->ccb_h.status = CAM_REQ_INVALID; 706 xpt_done(pccb); 707 break; 708 /* 709 * Turn on debugging for a bus, target or lun 710 */ 711 case XPT_DEBUG: 712 TRM_DPRINTF(" XPT_DEBUG \n"); 713 pccb->ccb_h.status = CAM_REQ_INVALID; 714 xpt_done(pccb); 715 break; 716 /* 717 * XPT_ABORT = 0x10, Abort the specified CCB 718 * Abort XPT request CCB 719 */ 720 case XPT_ABORT: 721 TRM_DPRINTF(" XPT_ABORT \n"); 722 pccb->ccb_h.status = CAM_REQ_INVALID; 723 xpt_done(pccb); 724 break; 725 /* 726 * Reset the specified SCSI bus 727 * Reset SCSI Bus CCB 728 */ 729 case XPT_RESET_BUS: { 730 int i; 731 732 TRM_DPRINTF(" XPT_RESET_BUS \n"); 733 trm_reset(pACB); 734 pACB->ACBFlag=0; 735 for (i=0; i<500; i++) 736 DELAY(1000); 737 pccb->ccb_h.status = CAM_REQ_CMP; 738 xpt_done(pccb); 739 } 740 break; 741 /* 742 * Bus Device Reset the specified SCSI device 743 * Reset SCSI Device CCB 744 */ 745 case XPT_RESET_DEV: 746 /* 747 * Don't (yet?) support vendor 748 * specific commands. 749 */ 750 TRM_DPRINTF(" XPT_RESET_DEV \n"); 751 pccb->ccb_h.status = CAM_REQ_INVALID; 752 xpt_done(pccb); 753 break; 754 /* 755 * Terminate the I/O process 756 * Terminate I/O Process Request CCB 757 */ 758 case XPT_TERM_IO: 759 TRM_DPRINTF(" XPT_TERM_IO \n"); 760 pccb->ccb_h.status = CAM_REQ_INVALID; 761 xpt_done(pccb); 762 break; 763 /* 764 * Scan Logical Unit 765 */ 766 case XPT_SCAN_LUN: 767 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 768 pccb->ccb_h.status = CAM_REQ_INVALID; 769 xpt_done(pccb); 770 break; 771 772 /* 773 * Get/Set transfer rate/width/disconnection/tag queueing 774 * settings 775 * (GET) default/user transfer settings for the target 776 */ 777 case XPT_GET_TRAN_SETTINGS: { 778 struct ccb_trans_settings *cts; 779 int intflag; 780 struct trm_transinfo *tinfo; 781 PDCB pDCB; 782 783 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 784 cts = &pccb->cts; 785 pDCB = pACB->pDCB[target_id][target_lun]; 786 intflag = splcam(); 787 /* 788 * disable interrupt 789 */ 790 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 791 /* current transfer settings */ 792 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 793 cts->flags = CCB_TRANS_DISC_ENB; 794 else 795 cts->flags = 0;/* no tag & disconnect */ 796 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 797 cts->flags |= CCB_TRANS_TAG_ENB; 798 tinfo = &pDCB->tinfo.current; 799 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 800 cts->flags); 801 } else { 802 /* default(user) transfer settings */ 803 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 804 cts->flags = CCB_TRANS_DISC_ENB; 805 else 806 cts->flags = 0; 807 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 808 cts->flags |= CCB_TRANS_TAG_ENB; 809 tinfo = &pDCB->tinfo.user; 810 TRM_DPRINTF("USER: cts->flags= %2x \n", 811 cts->flags); 812 } 813 cts->sync_period = tinfo->period; 814 cts->sync_offset = tinfo->offset; 815 cts->bus_width = tinfo->width; 816 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 817 pDCB->SyncPeriod); 818 TRM_DPRINTF("period: %d \n", tinfo->period); 819 TRM_DPRINTF("offset: %d \n", tinfo->offset); 820 TRM_DPRINTF("width: %d \n", tinfo->width); 821 822 splx(intflag); 823 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 824 CCB_TRANS_SYNC_OFFSET_VALID | 825 CCB_TRANS_BUS_WIDTH_VALID | 826 CCB_TRANS_DISC_VALID | 827 CCB_TRANS_TQ_VALID; 828 pccb->ccb_h.status = CAM_REQ_CMP; 829 xpt_done(pccb); 830 } 831 break; 832 /* 833 * Get/Set transfer rate/width/disconnection/tag queueing 834 * settings 835 * (Set) transfer rate/width negotiation settings 836 */ 837 case XPT_SET_TRAN_SETTINGS: { 838 struct ccb_trans_settings *cts; 839 u_int update_type; 840 int intflag; 841 PDCB pDCB; 842 843 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 844 cts = &pccb->cts; 845 update_type = 0; 846 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 847 update_type |= TRM_TRANS_GOAL; 848 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 849 update_type |= TRM_TRANS_USER; 850 intflag = splcam(); 851 pDCB = pACB->pDCB[target_id][target_lun]; 852 853 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 854 /*ccb disc enables */ 855 if (update_type & TRM_TRANS_GOAL) { 856 if ((cts->flags & CCB_TRANS_DISC_ENB) 857 != 0) 858 pDCB->tinfo.disc_tag 859 |= TRM_CUR_DISCENB; 860 else 861 pDCB->tinfo.disc_tag &= 862 ~TRM_CUR_DISCENB; 863 } 864 if (update_type & TRM_TRANS_USER) { 865 if ((cts->flags & CCB_TRANS_DISC_ENB) 866 != 0) 867 pDCB->tinfo.disc_tag 868 |= TRM_USR_DISCENB; 869 else 870 pDCB->tinfo.disc_tag &= 871 ~TRM_USR_DISCENB; 872 } 873 } 874 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 875 /* if ccb tag q active */ 876 if (update_type & TRM_TRANS_GOAL) { 877 if ((cts->flags & CCB_TRANS_TAG_ENB) 878 != 0) 879 pDCB->tinfo.disc_tag |= 880 TRM_CUR_TAGENB; 881 else 882 pDCB->tinfo.disc_tag &= 883 ~TRM_CUR_TAGENB; 884 } 885 if (update_type & TRM_TRANS_USER) { 886 if ((cts->flags & CCB_TRANS_TAG_ENB) 887 != 0) 888 pDCB->tinfo.disc_tag |= 889 TRM_USR_TAGENB; 890 else 891 pDCB->tinfo.disc_tag &= 892 ~TRM_USR_TAGENB; 893 } 894 } 895 /* Minimum sync period factor */ 896 897 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 898 /* if ccb sync active */ 899 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 900 if ((cts->sync_period != 0) && 901 (cts->sync_period < 125)) 902 cts->sync_period = 125; 903 /* 1/(125*4) minsync 2 MByte/sec */ 904 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 905 != 0) { 906 if (cts->sync_offset == 0) 907 cts->sync_period = 0; 908 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 909 if (cts->sync_offset > 15) 910 cts->sync_offset = 15; 911 } 912 } 913 if ((update_type & TRM_TRANS_USER) != 0) { 914 pDCB->tinfo.user.period = cts->sync_period; 915 pDCB->tinfo.user.offset = cts->sync_offset; 916 pDCB->tinfo.user.width = cts->bus_width; 917 } 918 if ((update_type & TRM_TRANS_GOAL) != 0) { 919 pDCB->tinfo.goal.period = cts->sync_period; 920 pDCB->tinfo.goal.offset = cts->sync_offset; 921 pDCB->tinfo.goal.width = cts->bus_width; 922 } 923 splx(intflag); 924 pccb->ccb_h.status = CAM_REQ_CMP; 925 xpt_done(pccb); 926 break; 927 } 928 /* 929 * Calculate the geometry parameters for a device give 930 * the sector size and volume size. 931 */ 932 case XPT_CALC_GEOMETRY: { 933 struct ccb_calc_geometry *ccg; 934 u_int32_t size_mb; 935 u_int32_t secs_per_cylinder; 936 int extended; 937 938 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 939 ccg = &pccb->ccg; 940 size_mb = ccg->volume_size / 941 ((1024L * 1024L) / ccg->block_size); 942 extended = 1; 943 if (size_mb > 1024 && extended) { 944 ccg->heads = 255; 945 ccg->secs_per_track = 63; 946 } else { 947 ccg->heads = 64; 948 ccg->secs_per_track = 32; 949 } 950 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 951 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 952 pccb->ccb_h.status = CAM_REQ_CMP; 953 xpt_done(pccb); 954 } 955 break; 956 case XPT_ENG_INQ: 957 TRM_DPRINTF(" XPT_ENG_INQ \n"); 958 pccb->ccb_h.status = CAM_REQ_INVALID; 959 xpt_done(pccb); 960 break; 961 /* 962 * HBA execute engine request 963 * This structure must match SCSIIO size 964 */ 965 case XPT_ENG_EXEC: 966 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 967 pccb->ccb_h.status = CAM_REQ_INVALID; 968 xpt_done(pccb); 969 break; 970 /* 971 * XPT_EN_LUN = 0x30, Enable LUN as a target 972 * Target mode structures. 973 */ 974 case XPT_EN_LUN: 975 /* 976 * Don't (yet?) support vendor 977 * specific commands. 978 */ 979 TRM_DPRINTF(" XPT_EN_LUN \n"); 980 pccb->ccb_h.status = CAM_REQ_INVALID; 981 xpt_done(pccb); 982 break; 983 /* 984 * Execute target I/O request 985 */ 986 case XPT_TARGET_IO: 987 /* 988 * Don't (yet?) support vendor 989 * specific commands. 990 */ 991 TRM_DPRINTF(" XPT_TARGET_IO \n"); 992 pccb->ccb_h.status = CAM_REQ_INVALID; 993 xpt_done(pccb); 994 break; 995 /* 996 * Accept Host Target Mode CDB 997 */ 998 case XPT_ACCEPT_TARGET_IO: 999 /* 1000 * Don't (yet?) support vendor 1001 * specific commands. 1002 */ 1003 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1004 pccb->ccb_h.status = CAM_REQ_INVALID; 1005 xpt_done(pccb); 1006 break; 1007 /* 1008 * Continue Host Target I/O Connection 1009 */ 1010 case XPT_CONT_TARGET_IO: 1011 /* 1012 * Don't (yet?) support vendor 1013 * specific commands. 1014 */ 1015 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1016 pccb->ccb_h.status = CAM_REQ_INVALID; 1017 xpt_done(pccb); 1018 break; 1019 /* 1020 * Notify Host Target driver of event 1021 */ 1022 case XPT_IMMED_NOTIFY: 1023 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1024 pccb->ccb_h.status = CAM_REQ_INVALID; 1025 xpt_done(pccb); 1026 break; 1027 /* 1028 * Acknowledgement of event 1029 */ 1030 case XPT_NOTIFY_ACK: 1031 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1032 pccb->ccb_h.status = CAM_REQ_INVALID; 1033 xpt_done(pccb); 1034 break; 1035 /* 1036 * XPT_VUNIQUE = 0x80 1037 */ 1038 case XPT_VUNIQUE: 1039 pccb->ccb_h.status = CAM_REQ_INVALID; 1040 xpt_done(pccb); 1041 break; 1042 default: 1043 pccb->ccb_h.status = CAM_REQ_INVALID; 1044 xpt_done(pccb); 1045 break; 1046 } 1047} 1048 1049static void 1050trm_poll(struct cam_sim *psim) 1051{ 1052 1053} 1054 1055static void 1056trm_ResetDevParam(PACB pACB) 1057{ 1058 PDCB pDCB, pdcb; 1059 PNVRAMTYPE pEEpromBuf; 1060 u_int8_t PeriodIndex; 1061 1062 pDCB = pACB->pLinkDCB; 1063 if (pDCB == NULL) 1064 return; 1065 pdcb = pDCB; 1066 do { 1067 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1068 pDCB->SyncPeriod = 0; 1069 pDCB->SyncOffset = 0; 1070 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1071 pDCB->DevMode = 1072 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1073 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1074 PeriodIndex = 1075 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1076 pDCB->MaxNegoPeriod = dc395x_trm_clock_period[PeriodIndex]; 1077 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1078 (pACB->Config & HCC_WIDE_CARD)) 1079 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1080 pDCB = pDCB->pNextDCB; 1081 } 1082 while (pdcb != pDCB); 1083} 1084 1085static void 1086trm_RecoverSRB(PACB pACB) 1087{ 1088 PDCB pDCB, pdcb; 1089 PSRB psrb, psrb2; 1090 u_int16_t cnt, i; 1091 1092 pDCB = pACB->pLinkDCB; 1093 if (pDCB == NULL) 1094 return; 1095 pdcb = pDCB; 1096 do { 1097 cnt = pdcb->GoingSRBCnt; 1098 psrb = pdcb->pGoingSRB; 1099 for (i = 0; i < cnt; i++) { 1100 psrb2 = psrb; 1101 psrb = psrb->pNextSRB; 1102 if (pdcb->pWaitingSRB) { 1103 psrb2->pNextSRB = pdcb->pWaitingSRB; 1104 pdcb->pWaitingSRB = psrb2; 1105 } else { 1106 pdcb->pWaitingSRB = psrb2; 1107 pdcb->pWaitLastSRB = psrb2; 1108 psrb2->pNextSRB = NULL; 1109 } 1110 } 1111 pdcb->GoingSRBCnt = 0; 1112 pdcb->pGoingSRB = NULL; 1113 pdcb->TagMask = 0; 1114 pdcb = pdcb->pNextDCB; 1115 } 1116 while (pdcb != pDCB); 1117} 1118 1119static void 1120trm_reset(PACB pACB) 1121{ 1122 int intflag; 1123 u_int16_t i; 1124 1125 TRM_DPRINTF("trm: RESET"); 1126 intflag = splcam(); 1127 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1128 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1129 1130 trm_ResetSCSIBus(pACB); 1131 for (i = 0; i < 500; i++) 1132 DELAY(1000); 1133 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1134 /* Enable DMA interrupt */ 1135 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1136 /* Clear DMA FIFO */ 1137 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1138 /* Clear SCSI FIFO */ 1139 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1140 trm_ResetDevParam(pACB); 1141 trm_DoingSRB_Done(pACB); 1142 pACB->pActiveDCB = NULL; 1143 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1144 trm_DoWaitingSRB(pACB); 1145 /* Tell the XPT layer that a bus reset occured */ 1146 if (pACB->ppath != NULL) 1147 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1148 splx(intflag); 1149 return; 1150} 1151 1152static u_int16_t 1153trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1154{ 1155 u_int16_t return_code; 1156 u_int8_t tag_number, scsicommand, i,command,identify_message; 1157 u_int8_t * ptr; 1158 u_long tag_mask; 1159 union ccb *pccb; 1160 struct ccb_scsiio *pcsio; 1161 1162 pccb = pSRB->pccb; 1163 pcsio = &pccb->csio; 1164 pSRB->TagNumber = 31; 1165 1166 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1167 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1168 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1169 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1170 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1171 /* Flush FIFO */ 1172 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1173 1174 identify_message = pDCB->IdentifyMsg; 1175 1176 if ((pSRB->CmdBlock[0] == INQUIRY) || 1177 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1178 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1179 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1180 !(pDCB->SyncMode & WIDE_NEGO_DONE)) \ 1181 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1182 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1183 if (!(pDCB->IdentifyMsg & 7) || 1184 (pSRB->CmdBlock[0] != INQUIRY)) { 1185 scsicommand = SCMD_SEL_ATNSTOP; 1186 pSRB->SRBState = SRB_MSGOUT; 1187 goto polling; 1188 } 1189 } 1190 /* 1191 * Send identify message 1192 */ 1193 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1194 scsicommand = SCMD_SEL_ATN; 1195 pSRB->SRBState = SRB_START_; 1196 } else { 1197 /* not inquiry,request sense,auto request sense */ 1198 /* 1199 * Send identify message 1200 */ 1201 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1202 scsicommand = SCMD_SEL_ATN; 1203 pSRB->SRBState = SRB_START_; 1204 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1205 /* Send Tag message */ 1206 /* 1207 * Get tag id 1208 */ 1209 tag_mask = 1; 1210 tag_number = 0; 1211 while (tag_mask & pDCB->TagMask) { 1212 tag_mask = tag_mask << 1; 1213 tag_number++; 1214 } 1215 /* 1216 * Send Tag id 1217 */ 1218 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1219 trm_reg_write8(tag_number, TRMREG_SCSI_FIFO); 1220 pDCB->TagMask |= tag_mask; 1221 pSRB->TagNumber = tag_number; 1222 scsicommand = SCMD_SEL_ATN3; 1223 pSRB->SRBState = SRB_START_; 1224 } 1225 } 1226polling: 1227 /* 1228 * Send CDB ..command block ......... 1229 */ 1230 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1231 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1232 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1233 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1234 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1235 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1236 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1237 } else { 1238 ptr = (u_int8_t *) pSRB->CmdBlock; 1239 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1240 command = *ptr++; 1241 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1242 } 1243 } 1244 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1245 /* 1246 * If trm_StartSCSI return 1 : 1247 * current interrupt status is interrupt disreenable 1248 * It's said that SCSI processor has more one SRB need to do, 1249 * SCSI processor has been occupied by one SRB. 1250 */ 1251 pSRB->SRBState = SRB_READY; 1252 pDCB->TagMask &= ~(1 << pSRB->TagNumber); 1253 return_code = 1; 1254 } else { 1255 /* 1256 * If trm_StartSCSI return 0 : 1257 * current interrupt status is interrupt enable 1258 * It's said that SCSI processor is unoccupied 1259 */ 1260 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1261 pACB->pActiveDCB = pDCB; 1262 pDCB->pActiveSRB = pSRB; 1263 return_code = 0; 1264 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1265 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1266 /* 1267 * SCSI cammand 1268 */ 1269 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1270 } 1271 return (return_code); 1272} 1273 1274static void 1275trm_Interrupt(vpACB) 1276void *vpACB; 1277{ 1278 PACB pACB; 1279 PDCB pDCB; 1280 PSRB pSRB; 1281 u_int16_t phase; 1282 void (*stateV)(PACB, PSRB, u_int8_t *); 1283 u_int8_t scsi_status=0, scsi_intstatus; 1284 1285 pACB = vpACB; 1286 1287 if (pACB == NULL) { 1288 TRM_DPRINTF("trm_Interrupt: pACB NULL return......"); 1289 return; 1290 } 1291 1292 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1293 if (!(scsi_status & SCSIINTERRUPT)) { 1294 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1295 return; 1296 } 1297 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1298 1299 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1300 1301 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1302 1303 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1304 trm_Disconnect(pACB); 1305 return; 1306 } 1307 1308 if (scsi_intstatus & INT_RESELECTED) { 1309 trm_Reselect(pACB); 1310 return; 1311 } 1312 if (scsi_intstatus & INT_SCSIRESET) { 1313 trm_ScsiRstDetect(pACB); 1314 return; 1315 } 1316 1317 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1318 pDCB = pACB->pActiveDCB; 1319 pSRB = pDCB->pActiveSRB; 1320 if (pDCB) { 1321 if (pDCB->DCBFlag & ABORT_DEV_) 1322 trm_EnableMsgOutAbort1(pACB, pSRB); 1323 } 1324 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1325 stateV = (void *) trm_SCSI_phase0[phase]; 1326 stateV(pACB, pSRB, &scsi_status); 1327 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1328 /* phase:0,1,2,3,4,5,6,7 */ 1329 phase = (u_int16_t) scsi_status & PHASEMASK; 1330 stateV = (void *) trm_SCSI_phase1[phase]; 1331 stateV(pACB, pSRB, &scsi_status); 1332 } 1333} 1334 1335static void 1336trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1337{ 1338 1339 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1340 *pscsi_status = PH_BUS_FREE; 1341 /*.. initial phase*/ 1342} 1343 1344static void 1345trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1346{ 1347 u_int8_t bval; 1348 u_int16_t i, cnt; 1349 u_int8_t * ptr; 1350 PDCB pDCB; 1351 1352 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1353 pDCB = pACB->pActiveDCB; 1354 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1355 cnt = pSRB->MsgCnt; 1356 if (cnt) { 1357 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1358 for (i = 0; i < cnt; i++) { 1359 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1360 ptr++; 1361 } 1362 pSRB->MsgCnt = 0; 1363 if ((pDCB->DCBFlag & ABORT_DEV_) && 1364 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1365 pSRB->SRBState = SRB_ABORT_SENT; 1366 } 1367 } else { 1368 bval = MSG_ABORT; 1369 if ((pSRB->CmdBlock[0] == INQUIRY) || 1370 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1371 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1372 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1373 goto mop1; 1374 } 1375 } 1376 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1377 } 1378 } else { 1379mop1: /* message out phase */ 1380 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1381 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1382 /* 1383 * WIDE DATA TRANSFER REQUEST code (03h) 1384 */ 1385 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1386 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1387 TRMREG_SCSI_FIFO); 1388 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1389 /* (01h) */ 1390 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1391 /* Message length (02h) */ 1392 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1393 /* wide data xfer (03h) */ 1394 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1395 /* width:0(8bit),1(16bit),2(32bit) */ 1396 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1397 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1398 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1399 /* 1400 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1401 */ 1402 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1403 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1404 TRMREG_SCSI_FIFO); 1405 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1406 /* (01h) */ 1407 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1408 /* Message length (03h) */ 1409 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1410 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1411 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1412 /* Transfer peeriod factor */ 1413 trm_reg_write8(SYNC_NEGO_OFFSET,TRMREG_SCSI_FIFO); 1414 /* REQ/ACK offset */ 1415 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1416 } 1417 } 1418 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1419 /* it's important for atn stop */ 1420 /* 1421 * SCSI cammand 1422 */ 1423 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1424} 1425 1426static void 1427trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1428{ 1429 1430} 1431 1432static void 1433trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1434{ 1435 PDCB pDCB; 1436 u_int8_t * ptr; 1437 u_int16_t i, cnt; 1438 union ccb *pccb; 1439 struct ccb_scsiio *pcsio; 1440 1441 pccb = pSRB->pccb; 1442 pcsio = &pccb->csio; 1443 1444 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1445 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1446 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1447 ptr = (u_int8_t *) pSRB->CmdBlock; 1448 for (i = 0; i < cnt; i++) { 1449 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1450 ptr++; 1451 } 1452 } else { 1453 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1454 pDCB = pACB->pActiveDCB; 1455 /* target id */ 1456 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1457 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1458 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1459 /* sizeof(struct scsi_sense_data) */ 1460 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1461 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1462 } 1463 pSRB->SRBState = SRB_COMMAND; 1464 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1465 /* it's important for atn stop*/ 1466 /* 1467 * SCSI cammand 1468 */ 1469 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1470} 1471 1472static void 1473trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1474{ 1475 PDCB pDCB; 1476 u_int8_t TempDMAstatus,SGIndexTemp; 1477 u_int16_t scsi_status; 1478 PSEG pseg; 1479 u_long TempSRBXferredLength,dLeftCounter=0; 1480 1481 pDCB = pSRB->pSRBDCB; 1482 scsi_status = *pscsi_status; 1483 1484 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1485 if (scsi_status & PARITYERROR) 1486 pSRB->SRBStatus |= PARITY_ERROR; 1487 if (!(scsi_status & SCSIXFERDONE)) { 1488 /* 1489 * when data transfer from DMA FIFO to SCSI FIFO 1490 * if there was some data left in SCSI FIFO 1491 */ 1492 dLeftCounter = (u_long) 1493 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x1F); 1494 if (pDCB->SyncPeriod & WIDE_SYNC) { 1495 /* 1496 * if WIDE scsi SCSI FIFOCNT unit is word 1497 * so need to * 2 1498 */ 1499 dLeftCounter <<= 1; 1500 } 1501 } 1502 /* 1503 * caculate all the residue data that not yet tranfered 1504 * SCSI transfer counter + left in SCSI FIFO data 1505 * 1506 * .....TRM_SCSI_COUNTER (24bits) 1507 * The counter always decrement by one for every SCSI byte 1508 *transfer. 1509 * .....TRM_SCSI_FIFOCNT (5bits) 1510 * The counter is SCSI FIFO offset counter 1511 */ 1512 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1513 if (dLeftCounter == 1) { 1514 dLeftCounter = 0; 1515 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1516 } 1517 if ((dLeftCounter == 0) || 1518 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1519 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1520 while (!(TempDMAstatus & DMAXFERCOMP)) { 1521 TempDMAstatus = 1522 trm_reg_read8(TRMREG_DMA_STATUS); 1523 } 1524 pSRB->SRBTotalXferLength = 0; 1525 } else { 1526 /* Update SG list */ 1527 /* 1528 * if transfer not yet complete 1529 * there were some data residue in SCSI FIFO or 1530 * SCSI transfer counter not empty 1531 */ 1532 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1533 /* 1534 * data that had transferred length 1535 */ 1536 TempSRBXferredLength = 1537 pSRB->SRBTotalXferLength - dLeftCounter; 1538 /* 1539 * next time to be transferred length 1540 */ 1541 pSRB->SRBTotalXferLength = dLeftCounter; 1542 /* 1543 * parsing from last time disconnect SRBSGIndex 1544 */ 1545 pseg = 1546 pSRB->SRBSGListPointer + pSRB->SRBSGIndex; 1547 for (SGIndexTemp = pSRB->SRBSGIndex; 1548 SGIndexTemp < pSRB->SRBSGCount; 1549 SGIndexTemp++) { 1550 /* 1551 * find last time which SG transfer be 1552 * disconnect 1553 */ 1554 if (TempSRBXferredLength >= 1555 pseg->length) 1556 TempSRBXferredLength -= 1557 pseg->length; 1558 else { 1559 /* 1560 * update last time disconnected SG 1561 * list 1562 */ 1563 pseg->length -= 1564 TempSRBXferredLength; 1565 /* residue data length */ 1566 pseg->address += 1567 TempSRBXferredLength; 1568 /* residue data pointer */ 1569 pSRB->SRBSGIndex = SGIndexTemp; 1570 break; 1571 } 1572 pseg++; 1573 } 1574 } 1575 } 1576 } 1577 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1578} 1579 1580 1581static void 1582trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1583{ 1584 u_int16_t ioDir; 1585 /* 1586 * do prepare befor transfer when data out phase 1587 */ 1588 1589 ioDir = XFERDATAOUT; 1590 trm_DataIO_transfer(pACB, pSRB, ioDir); 1591} 1592 1593static void 1594trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1595{ 1596 u_int8_t bval,SGIndexTemp; 1597 u_int16_t scsi_status; 1598 PSEG pseg; 1599 u_long TempSRBXferredLength,dLeftCounter = 0; 1600 1601 scsi_status = *pscsi_status; 1602 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1603 if (scsi_status & PARITYERROR) 1604 pSRB->SRBStatus |= PARITY_ERROR; 1605 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1606 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1607 bval = trm_reg_read8(TRMREG_DMA_STATUS); 1608 while (!(bval & DMAXFERCOMP)) 1609 bval = trm_reg_read8(TRMREG_DMA_STATUS); 1610 pSRB->SRBTotalXferLength = 0; 1611 } else { 1612 /* 1613 * parsing the case: 1614 * when a transfer not yet complete 1615 * but be disconnected by uper layer 1616 * if transfer not yet complete 1617 * there were some data residue in SCSI FIFO or 1618 * SCSI transfer counter not empty 1619 */ 1620 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1621 /* 1622 * data that had transferred length 1623 */ 1624 TempSRBXferredLength = 1625 pSRB->SRBTotalXferLength - dLeftCounter; 1626 /* 1627 * next time to be transferred length 1628 */ 1629 pSRB->SRBTotalXferLength = dLeftCounter; 1630 /* 1631 * parsing from last time disconnect SRBSGIndex 1632 */ 1633 pseg = pSRB->SRBSGListPointer + pSRB->SRBSGIndex; 1634 for (SGIndexTemp = pSRB->SRBSGIndex; 1635 SGIndexTemp < pSRB->SRBSGCount; 1636 SGIndexTemp++) { 1637 /* 1638 * find last time which SG transfer be disconnect 1639 */ 1640 if (TempSRBXferredLength >= pseg->length) 1641 TempSRBXferredLength -= pseg->length; 1642 else { 1643 /* 1644 * update last time disconnected SG list 1645 */ 1646 pseg->length -= TempSRBXferredLength; 1647 /* residue data length */ 1648 pseg->address += TempSRBXferredLength; 1649 /* residue data pointer */ 1650 pSRB->SRBSGIndex = SGIndexTemp; 1651 break; 1652 } 1653 pseg++; 1654 } 1655 } 1656 } 1657 } 1658} 1659 1660static void 1661trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1662{ 1663 u_int16_t ioDir; 1664 /* 1665 * do prepare befor transfer when data in phase 1666 */ 1667 1668 ioDir = XFERDATAIN; 1669 trm_DataIO_transfer(pACB, pSRB, ioDir); 1670} 1671 1672static void 1673trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1674{ 1675 u_int8_t bval; 1676 PDCB pDCB; 1677 1678 pDCB = pSRB->pSRBDCB; 1679 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1680 if (pSRB->SRBTotalXferLength != 0) { 1681 pSRB->SRBSGPhyAddr = vtophys(pSRB->SRBSGListPointer); 1682 /* 1683 * load what physical address of Scatter/Gather list 1684 table want to be transfer 1685 */ 1686 pSRB->SRBState = SRB_DATA_XFER; 1687 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1688 trm_reg_write32( 1689 (pSRB->SRBSGPhyAddr + 1690 ((u_long)pSRB->SRBSGIndex << 3)), 1691 TRMREG_DMA_XLOWADDR); 1692 /* 1693 * load how many bytes in the Scatter/Gather 1694 * list table 1695 */ 1696 trm_reg_write32( 1697 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1698 TRMREG_DMA_XCNT); 1699 /* 1700 * load total transfer length (24bits) max value 1701 * 16Mbyte 1702 */ 1703 trm_reg_write32(pSRB->SRBTotalXferLength, 1704 TRMREG_SCSI_COUNTER); 1705 /* Start DMA transfer */ 1706 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1707 /* Start SCSI transfer */ 1708 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1709 /* it's important for atn stop */ 1710 /* 1711 * SCSI cammand 1712 */ 1713 bval = (ioDir == XFERDATAOUT) ? 1714 SCMD_DMA_OUT : SCMD_DMA_IN; 1715 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1716 } else { 1717 /* xfer pad */ 1718 if (pSRB->SRBSGCount) { 1719 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1720 pSRB->SRBStatus |= OVER_RUN; 1721 } 1722 if (pDCB->SyncPeriod & WIDE_SYNC) 1723 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1724 else 1725 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1726 if (ioDir == XFERDATAOUT) 1727 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1728 else 1729 trm_reg_read16(TRMREG_SCSI_FIFO); 1730 pSRB->SRBState |= SRB_XFERPAD; 1731 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1732 /* it's important for atn stop */ 1733 /* 1734 * SCSI cammand 1735 */ 1736 bval = (ioDir == XFERDATAOUT) ? 1737 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1738 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1739 } 1740 } 1741} 1742 1743static void 1744trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1745{ 1746 1747 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1748 pSRB->SRBState = SRB_COMPLETED; 1749 *pscsi_status = PH_BUS_FREE; 1750 /*.. initial phase*/ 1751 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1752 /* it's important for atn stop */ 1753 /* 1754 * SCSI cammand 1755 */ 1756 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1757} 1758 1759 1760 1761static void 1762trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1763{ 1764 1765 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1766 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1767 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1768 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1769 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1770 } else { 1771 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1772 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1773 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1774 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1775 } 1776 pSRB->SRBState = SRB_STATUS; 1777 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1778 /* it's important for atn stop */ 1779 /* 1780 * SCSI cammand 1781 */ 1782 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1783} 1784 1785/* 1786 *scsiiom 1787 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1788 * stateV = (void *) trm_SCSI_phase0[phase] 1789 * if phase =7 1790 * extended message codes: 1791 * 1792 * code description 1793 * 1794 * 02h Reserved 1795 * 00h MODIFY DATA POINTER 1796 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1797 * 03h WIDE DATA TRANSFER REQUEST 1798 * 04h - 7Fh Reserved 1799 * 80h - FFh Vendor specific 1800 * 1801 */ 1802 1803static void 1804trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1805{ 1806 u_int8_t message_in_code,bIndex,message_in_tag_id; 1807 PDCB pDCB; 1808 PSRB pSRBTemp; 1809 1810 pDCB = pACB->pActiveDCB; 1811 1812 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1813 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1814 if (message_in_code == MSG_DISCONNECT) { 1815 pSRB->SRBState = SRB_DISCONNECT; 1816 goto min6; 1817 } else if (message_in_code == MSG_SAVE_PTR) { 1818 goto min6; 1819 } else if ((message_in_code == MSG_EXTENDED) || 1820 ((message_in_code >= MSG_SIMPLE_QTAG) && 1821 (message_in_code <= MSG_ORDER_QTAG))) { 1822 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1823 pSRB->MsgInBuf[0] = message_in_code; 1824 /* extended message (01h) */ 1825 pSRB->MsgCnt = 1; 1826 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1827 /* extended message length (n) */ 1828 goto min6; 1829 } else if (message_in_code == MSG_REJECT_) { 1830 /* Reject message */ 1831 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1832 /* do wide nego reject */ 1833 pDCB = pSRB->pSRBDCB; 1834 pDCB->SyncMode |= WIDE_NEGO_DONE; 1835 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1836 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1837 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1838 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1839 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1840 /* Set ATN, in case ATN was clear */ 1841 pSRB->SRBState |= SRB_MSGOUT; 1842 trm_reg_write16( 1843 DO_SETATN, 1844 TRMREG_SCSI_CONTROL); 1845 } else { 1846 /* Clear ATN */ 1847 trm_reg_write16( 1848 DO_CLRATN, 1849 TRMREG_SCSI_CONTROL); 1850 } 1851 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1852 /* do sync nego reject */ 1853 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1854 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1855 pDCB = pSRB->pSRBDCB; 1856 pDCB->SyncMode &= 1857 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1858 pDCB->SyncPeriod = 0; 1859 pDCB->SyncOffset = 0; 1860 goto re_prog; 1861 } 1862 } 1863 goto min6; 1864 } else if (message_in_code == MSG_IGNOREWIDE) { 1865 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1866 trm_reg_read8(TRMREG_SCSI_FIFO); 1867 goto min6; 1868 } else { 1869 /* Restore data pointer message */ 1870 /* Save data pointer message */ 1871 /* Completion message */ 1872 /* NOP message */ 1873 goto min6; 1874 } 1875 } else { 1876 /* 1877 * Parsing incomming extented messages 1878 */ 1879 *pSRB->pMsgPtr = message_in_code; 1880 pSRB->MsgCnt++; 1881 pSRB->pMsgPtr++; 1882 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1883 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1884 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1885 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1886 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1887 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1888 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1889 /* 1890 * is QUEUE tag message : 1891 * 1892 * byte 0: 1893 * HEAD QUEUE TAG (20h) 1894 * ORDERED QUEUE TAG (21h) 1895 * SIMPLE QUEUE TAG (22h) 1896 * byte 1: 1897 * Queue tag (00h - FFh) 1898 */ 1899 if (pSRB->MsgCnt == 2) { 1900 pSRB->SRBState = 0; 1901 message_in_tag_id = pSRB->MsgInBuf[1]; 1902 pSRB = pDCB->pGoingSRB; 1903 pSRBTemp = pDCB->pGoingLastSRB; 1904 if (pSRB) { 1905 for (;;) { 1906 if (pSRB->TagNumber != 1907 message_in_tag_id) { 1908 if (pSRB == pSRBTemp) { 1909 goto mingx0; 1910 } 1911 pSRB = pSRB->pNextSRB; 1912 } else 1913 break; 1914 } 1915 if (pDCB->DCBFlag & ABORT_DEV_) { 1916 pSRB->SRBState = SRB_ABORT_SENT; 1917 trm_EnableMsgOutAbort1( 1918 pACB, pSRB); 1919 } 1920 if (!(pSRB->SRBState & SRB_DISCONNECT)) 1921 goto mingx0; 1922 pDCB->pActiveSRB = pSRB; 1923 pSRB->SRBState = SRB_DATA_XFER; 1924 } else { 1925mingx0: 1926 pSRB = pACB->pTmpSRB; 1927 pSRB->SRBState = SRB_UNEXPECT_RESEL; 1928 pDCB->pActiveSRB = pSRB; 1929 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 1930 trm_EnableMsgOutAbort2( 1931 pACB, 1932 pSRB); 1933 } 1934 } 1935 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1936 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 1937 /* 1938 * is Wide data xfer Extended message : 1939 * ====================================== 1940 * WIDE DATA TRANSFER REQUEST 1941 * ====================================== 1942 * byte 0 : Extended message (01h) 1943 * byte 1 : Extended message length (02h) 1944 * byte 2 : WIDE DATA TRANSFER code (03h) 1945 * byte 3 : Transfer width exponent 1946 */ 1947 pDCB = pSRB->pSRBDCB; 1948 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 1949 if ((pSRB->MsgInBuf[1] != 2)) { 1950 /* Length is wrong, reject it */ 1951 pDCB->SyncMode &= 1952 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1953 pSRB->MsgCnt = 1; 1954 pSRB->MsgInBuf[0] = MSG_REJECT_; 1955 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 1956 goto min6; 1957 } 1958 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1959 /* Do wide negoniation */ 1960 if (pSRB->MsgInBuf[3] > 2) { 1961 /* > 32 bit */ 1962 /* reject_msg: */ 1963 pDCB->SyncMode &= 1964 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1965 pSRB->MsgCnt = 1; 1966 pSRB->MsgInBuf[0] = MSG_REJECT_; 1967 trm_reg_write16(DO_SETATN, 1968 TRMREG_SCSI_CONTROL); 1969 goto min6; 1970 } 1971 if (pSRB->MsgInBuf[3] == 2) { 1972 pSRB->MsgInBuf[3] = 1; 1973 /* do 16 bits */ 1974 } else { 1975 if (!(pDCB->SyncMode 1976 & WIDE_NEGO_DONE)) { 1977 pSRB->SRBState &= 1978 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1979 pDCB->SyncMode |= 1980 WIDE_NEGO_DONE; 1981 pDCB->SyncMode &= 1982 ~(SYNC_NEGO_DONE | 1983 EN_ATN_STOP | 1984 WIDE_NEGO_ENABLE); 1985 if (pSRB->MsgInBuf[3] != 0) { 1986 /* is Wide data xfer */ 1987 pDCB->SyncPeriod |= 1988 WIDE_SYNC; 1989 pDCB->tinfo.current.width 1990 = MSG_EXT_WDTR_BUS_16_BIT; 1991 pDCB->tinfo.goal.width 1992 = MSG_EXT_WDTR_BUS_16_BIT; 1993 } 1994 } 1995 } 1996 } else 1997 pSRB->MsgInBuf[3] = 0; 1998 pSRB->SRBState |= SRB_MSGOUT; 1999 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2000 goto min6; 2001 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2002 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2003 /* 2004 * is 8bit transfer Extended message : 2005 * ================================= 2006 * SYNCHRONOUS DATA TRANSFER REQUEST 2007 * ================================= 2008 * byte 0 : Extended message (01h) 2009 * byte 1 : Extended message length (03) 2010 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2011 * byte 3 : Transfer period factor 2012 * byte 4 : REQ/ACK offset 2013 */ 2014 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2015 if ((pSRB->MsgInBuf[1] != 3) || 2016 (pSRB->MsgInBuf[2] != 1)) { 2017 /* reject_msg: */ 2018 pSRB->MsgCnt = 1; 2019 pSRB->MsgInBuf[0] = MSG_REJECT_; 2020 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2021 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2022 /* set async */ 2023 pDCB = pSRB->pSRBDCB; 2024 /* disable sync & sync nego */ 2025 pDCB->SyncMode &= 2026 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2027 pDCB->SyncPeriod = 0; 2028 pDCB->SyncOffset = 0; 2029 pDCB->tinfo.goal.period = 0; 2030 pDCB->tinfo.goal.offset = 0; 2031 pDCB->tinfo.current.period = 0; 2032 pDCB->tinfo.current.offset = 0; 2033 pDCB->tinfo.current.width = 2034 MSG_EXT_WDTR_BUS_8_BIT; 2035 goto re_prog; 2036 } else { 2037 /* set sync */ 2038 pDCB = pSRB->pSRBDCB; 2039 pDCB->SyncMode |= 2040 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2041 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2042 /* Transfer period factor */ 2043 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2044 /* REQ/ACK offset */ 2045 for (bIndex = 0; bIndex < 7; bIndex++) { 2046 if (pSRB->MsgInBuf[3] <= 2047 dc395x_trm_clock_period[bIndex]) { 2048 break; 2049 } 2050 } 2051 pDCB->tinfo.goal.period = 2052 dc395x_trm_tinfo_sync_period[bIndex]; 2053 pDCB->tinfo.current.period = 2054 dc395x_trm_tinfo_sync_period[bIndex]; 2055 pDCB->tinfo.goal.offset = pDCB->SyncOffset; 2056 pDCB->tinfo.current.offset = pDCB->SyncOffset; 2057 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 2058re_prog: 2059 /* 2060 * 2061 * program SCSI control register 2062 * 2063 */ 2064 trm_reg_write8(pDCB->SyncPeriod, 2065 TRMREG_SCSI_SYNC); 2066 trm_reg_write8(pDCB->SyncOffset, 2067 TRMREG_SCSI_OFFSET); 2068 trm_SetXferRate(pACB,pSRB,pDCB); 2069 } 2070 } 2071 } 2072min6: 2073 *pscsi_status = PH_BUS_FREE; 2074 /* .. initial phase */ 2075 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2076 /* it's important for atn stop */ 2077 /* 2078 * SCSI cammand 2079 */ 2080 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2081} 2082 2083static void 2084trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2085{ 2086 2087 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2088 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2089 if (!(pSRB->SRBState & SRB_MSGIN)) { 2090 pSRB->SRBState &= SRB_DISCONNECT; 2091 pSRB->SRBState |= SRB_MSGIN; 2092 } 2093 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2094 /* it's important for atn stop*/ 2095 /* 2096 * SCSI cammand 2097 */ 2098 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2099} 2100 2101static void 2102trm_Nop0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2103{ 2104 2105} 2106 2107static void 2108trm_Nop1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2109{ 2110 2111} 2112 2113static void 2114trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2115{ 2116 u_int16_t cnt, i; 2117 u_int8_t bval; 2118 PDCB pDCBTemp; 2119 u_int target_id,target_lun; 2120 2121 /* 2122 * set all lun device's period , offset 2123 */ 2124 target_id = pSRB->pccb->ccb_h.target_id; 2125 target_lun = pSRB->pccb->ccb_h.target_lun; 2126 TRM_DPRINTF("trm_SetXferRate:target_id= %d ,target_lun= %d \n" 2127 ,target_id,target_lun); 2128 if (!(pDCB->IdentifyMsg & 0x07)) { 2129 if (!pACB->scan_devices[target_id][target_lun]) { 2130 pDCBTemp = pACB->pLinkDCB; 2131 cnt = pACB->DeviceCnt; 2132 bval = pDCB->TargetID; 2133 for (i = 0; i < cnt; i++) { 2134 if (pDCBTemp->TargetID == bval) { 2135 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2136 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2137 pDCBTemp->SyncMode = pDCB->SyncMode; 2138 } 2139 pDCBTemp = pDCBTemp->pNextDCB; 2140 } 2141 } 2142 } 2143 return; 2144} 2145 2146/* 2147 * scsiiom 2148 * trm_Interrupt 2149 * 2150 * 2151 * ---SCSI bus phase 2152 * 2153 * PH_DATA_OUT 0x00 Data out phase 2154 * PH_DATA_IN 0x01 Data in phase 2155 * PH_COMMAND 0x02 Command phase 2156 * PH_STATUS 0x03 Status phase 2157 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2158 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2159 * PH_MSG_OUT 0x06 Message out phase 2160 * PH_MSG_IN 0x07 Message in phase 2161 * 2162 */ 2163static void 2164trm_Disconnect(PACB pACB) 2165{ 2166 PDCB pDCB; 2167 PSRB pSRB, psrb; 2168 int intflag; 2169 u_int16_t i,j, cnt; 2170 u_int8_t bval; 2171 u_int target_id,target_lun; 2172 2173 TRM_DPRINTF("trm_Disconnect...............\n "); 2174 2175 intflag = splcam(); 2176 pDCB = pACB->pActiveDCB; 2177 if (!pDCB) { 2178 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2179 j = 400; 2180 while (--j) 2181 DELAY(1); 2182 /* 1 msec */ 2183 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2184 TRMREG_SCSI_CONTROL); 2185 return; 2186 } 2187 pSRB = pDCB->pActiveSRB; 2188 /* bug pSRB=0 */ 2189 target_id = pSRB->pccb->ccb_h.target_id; 2190 target_lun = pSRB->pccb->ccb_h.target_lun; 2191 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2192 pACB->pActiveDCB = 0; 2193 pSRB->ScsiPhase = PH_BUS_FREE; 2194 /* SCSI bus free Phase */ 2195 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2196 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2197 pSRB->SRBState = 0; 2198 trm_DoWaitingSRB(pACB); 2199 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2200 pDCB->TagMask = 0; 2201 pDCB->DCBFlag = 0; 2202 cnt = pDCB->GoingSRBCnt; 2203 pDCB->GoingSRBCnt = 0; 2204 pSRB = pDCB->pGoingSRB; 2205 for (i = 0; i < cnt; i++) { 2206 psrb = pSRB->pNextSRB; 2207 pSRB->pNextSRB = pACB->pFreeSRB; 2208 pACB->pFreeSRB = pSRB; 2209 pSRB = psrb; 2210 } 2211 pDCB->pGoingSRB = 0; 2212 trm_DoWaitingSRB(pACB); 2213 } else { 2214 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2215 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2216 /* Selection time out */ 2217 if (!(pACB->scan_devices[target_id][target_lun])) { 2218 pSRB->SRBState = SRB_READY; 2219 trm_RewaitSRB(pDCB, pSRB); 2220 } else { 2221 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2222 goto disc1; 2223 } 2224 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2225 /* 2226 * SRB_DISCONNECT 2227 */ 2228 trm_DoWaitingSRB(pACB); 2229 } else if (pSRB->SRBState & SRB_COMPLETED) { 2230disc1: 2231 /* 2232 * SRB_COMPLETED 2233 */ 2234 if (pDCB->MaxCommand > 1) { 2235 bval = pSRB->TagNumber; 2236 pDCB->TagMask &= (~(1 << bval)); 2237 /* free tag mask */ 2238 } 2239 pDCB->pActiveSRB = 0; 2240 pSRB->SRBState = SRB_FREE; 2241 trm_SRBdone(pACB, pDCB, pSRB); 2242 } 2243 } 2244 splx(intflag); 2245 return; 2246} 2247 2248static void 2249trm_Reselect(PACB pACB) 2250{ 2251 PDCB pDCB; 2252 PSRB pSRB; 2253 u_int16_t RselTarLunId; 2254 2255 TRM_DPRINTF("trm_Reselect................. \n"); 2256 pDCB = pACB->pActiveDCB; 2257 if (pDCB) { 2258 /* Arbitration lost but Reselection win */ 2259 pSRB = pDCB->pActiveSRB; 2260 pSRB->SRBState = SRB_READY; 2261 trm_RewaitSRB(pDCB, pSRB); 2262 } 2263 /* Read Reselected Target Id and LUN */ 2264 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2265 pDCB = pACB->pLinkDCB; 2266 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2267 /* get pDCB of the reselect id */ 2268 pDCB = pDCB->pNextDCB; 2269 } 2270 2271 pACB->pActiveDCB = pDCB; 2272 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2273 pSRB = pACB->pTmpSRB; 2274 pDCB->pActiveSRB = pSRB; 2275 } else { 2276 pSRB = pDCB->pActiveSRB; 2277 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2278 /* 2279 * abort command 2280 */ 2281 pSRB = pACB->pTmpSRB; 2282 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2283 pDCB->pActiveSRB = pSRB; 2284 trm_EnableMsgOutAbort1(pACB, pSRB); 2285 } else { 2286 if (pDCB->DCBFlag & ABORT_DEV_) { 2287 pSRB->SRBState = SRB_ABORT_SENT; 2288 trm_EnableMsgOutAbort1(pACB, pSRB); 2289 } else 2290 pSRB->SRBState = SRB_DATA_XFER; 2291 } 2292 } 2293 pSRB->ScsiPhase = PH_BUS_FREE; 2294 /* SCSI bus free Phase */ 2295 /* 2296 * Program HA ID, target ID, period and offset 2297 */ 2298 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2299 /* target ID */ 2300 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2301 /* host ID */ 2302 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2303 /* period */ 2304 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2305 /* offset */ 2306 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2307 /* it's important for atn stop*/ 2308 /* 2309 * SCSI cammand 2310 */ 2311 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2312 /* to rls the /ACK signal */ 2313} 2314 2315static void 2316trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2317{ 2318 PSRB psrb; 2319 u_int8_t bval, bval1,status; 2320 union ccb *pccb; 2321 struct ccb_scsiio *pcsio; 2322 PSCSI_INQDATA ptr; 2323 int intflag; 2324 u_int target_id,target_lun; 2325 PDCB pTempDCB; 2326 2327 pccb = pSRB->pccb; 2328 if (pccb == NULL) 2329 return; 2330 pcsio = &pccb->csio; 2331 target_id = pSRB->pccb->ccb_h.target_id; 2332 target_lun = pSRB->pccb->ccb_h.target_lun; 2333 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2334 bus_dmasync_op_t op; 2335 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2336 op = BUS_DMASYNC_POSTREAD; 2337 else 2338 op = BUS_DMASYNC_POSTWRITE; 2339 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2340 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2341 } 2342 /* 2343 * 2344 * target status 2345 * 2346 */ 2347 status = pSRB->TargetStatus; 2348 pcsio->scsi_status=SCSI_STAT_GOOD; 2349 pccb->ccb_h.status = CAM_REQ_CMP; 2350 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2351 /* 2352 * status of auto request sense 2353 */ 2354 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2355 pSRB->AdaptStatus = 0; 2356 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2357 2358 if (status == SCSI_STATUS_CHECK_COND) { 2359 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2360 goto ckc_e; 2361 } 2362 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2363 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2364 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2365 pSRB->SegmentX[0].address = pSRB->SgSenseTemp.address; 2366 pSRB->SegmentX[0].length = pSRB->SgSenseTemp.length; 2367 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2368 pccb->ccb_h.status = CAM_AUTOSNS_VALID; 2369 goto ckc_e; 2370 } 2371 /* 2372 * target status 2373 */ 2374 if (status) { 2375 if (status == SCSI_STATUS_CHECK_COND) { 2376 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2377 TRM_DPRINTF("trm_RequestSense..................\n"); 2378 trm_RequestSense(pACB, pDCB, pSRB); 2379 return; 2380 } 2381 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2382 pccb->ccb_h.status = CAM_AUTOSNS_VALID | 2383 CAM_SCSI_STATUS_ERROR; 2384 goto ckc_e; 2385 } else if (status == SCSI_STAT_QUEUEFULL) { 2386 bval = (u_int8_t) pDCB->GoingSRBCnt; 2387 bval--; 2388 pDCB->MaxCommand = bval; 2389 trm_RewaitSRB(pDCB, pSRB); 2390 pSRB->AdaptStatus = 0; 2391 pSRB->TargetStatus = 0; 2392 pcsio->scsi_status = SCSI_STAT_QUEUEFULL; 2393 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2394 goto ckc_e; 2395 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2396 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2397 pSRB->TargetStatus = 0; 2398 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2399 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2400 } else if (status == SCSI_STAT_BUSY) { 2401 TRM_DPRINTF("trm: target busy at %s %d\n", 2402 __FILE__, __LINE__); 2403 pcsio->scsi_status = SCSI_STAT_BUSY; 2404 pccb->ccb_h.status = CAM_SCSI_BUSY; 2405 /* The device busy, try again later? */ 2406 } else if (status == SCSI_STAT_RESCONFLICT) { 2407 TRM_DPRINTF("trm: target reserved at %s %d\n", 2408 __FILE__, __LINE__); 2409 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2410 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2411 } else { 2412 pSRB->AdaptStatus = 0; 2413 if (pSRB->RetryCnt) { 2414 pSRB->RetryCnt--; 2415 pSRB->TargetStatus = 0; 2416 pSRB->SRBSGIndex = 0; 2417 pSRB->SRBSGListPointer = (PSEG) 2418 &pSRB->SegmentX[0]; 2419 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2420 /* 2421 * If trm_StartSCSI return 1 : 2422 * current interrupt status is interrupt 2423 * disreenable 2424 * It's said that SCSI processor has more 2425 * one SRB need to do 2426 */ 2427 trm_RewaitSRB(pDCB, pSRB); 2428 } 2429 return; 2430 } else { 2431 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2432 __FILE__, __LINE__); 2433 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2434 } 2435 } 2436 } else { 2437 /* 2438 * process initiator status.......................... 2439 * Adapter (initiator) status 2440 */ 2441 status = pSRB->AdaptStatus; 2442 if (status & H_OVER_UNDER_RUN) { 2443 pSRB->TargetStatus = 0; 2444 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2445 /* Illegal length (over/under run) */ 2446 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2447 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2448 __FILE__, __LINE__); 2449 pDCB->tinfo.goal.period = 0; 2450 pDCB->tinfo.goal.offset = 0; 2451 /* Driver failed to perform operation */ 2452 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2453 } else { 2454 /* no error */ 2455 pSRB->AdaptStatus = 0; 2456 pSRB->TargetStatus = 0; 2457 pccb->ccb_h.status = CAM_REQ_CMP; 2458 /* there is no error, (sense is invalid) */ 2459 } 2460 } 2461ckc_e: 2462 if (pACB->scan_devices[target_id][target_lun]) { 2463 /* 2464 * if SCSI command in "scan devices" duty 2465 */ 2466 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2467 pACB->scan_devices[target_id][target_lun] = 0; 2468 /* SCSI command phase :test unit ready */ 2469 else if (pSRB->CmdBlock[0] == INQUIRY) { 2470 /* 2471 * SCSI command phase :inquiry scsi device data 2472 * (type,capacity,manufacture.... 2473 */ 2474 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2475 goto NO_DEV; 2476 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2477 /* page fault */ 2478 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2479 ptr->DevType); 2480 bval1 = ptr->DevType & SCSI_DEVTYPE; 2481 if (bval1 == SCSI_NODEV) { 2482NO_DEV: 2483 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2484 target_id, 2485 target_lun); 2486 intflag = splcam(); 2487 pACB->scan_devices[target_id][target_lun] = 0; 2488 /* no device set scan device flag =0*/ 2489 /* pDCB Q link */ 2490 /* move the head of DCB to tempDCB*/ 2491 pTempDCB=pACB->pLinkDCB; 2492 /* search current DCB for pass link */ 2493 while (pTempDCB->pNextDCB != pDCB) { 2494 pTempDCB = pTempDCB->pNextDCB; 2495 } 2496 /* 2497 * when the current DCB found than connect 2498 * current DCB tail 2499 */ 2500 /* to the DCB tail that before current DCB */ 2501 pTempDCB->pNextDCB = pDCB->pNextDCB; 2502 /* 2503 * if there was only one DCB ,connect his tail 2504 * to his head 2505 */ 2506 if (pACB->pLinkDCB == pDCB) 2507 pACB->pLinkDCB = pTempDCB->pNextDCB; 2508 if (pACB->pDCBRunRobin == pDCB) 2509 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2510 pACB->DeviceCnt--; 2511 if (pACB->DeviceCnt == 0) { 2512 pACB->pLinkDCB = NULL; 2513 pACB->pDCBRunRobin = NULL; 2514 } 2515 splx(intflag); 2516 } else { 2517#ifdef trm_DEBUG1 2518 int j; 2519 for (j = 0; j < 28; j++) { 2520 TRM_DPRINTF("ptr=%2x ", 2521 ((u_int8_t *)ptr)[j]); 2522 } 2523#endif 2524 pDCB->DevType = bval1; 2525 if (bval1 == SCSI_DASD || 2526 bval1 == SCSI_OPTICAL) { 2527 if ((((ptr->Vers & 0x07) >= 2) || 2528 ((ptr->RDF & 0x0F) == 2)) && 2529 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2530 (pDCB->DevMode & TAG_QUEUING_) && 2531 (pDCB->DevMode & EN_DISCONNECT_)) { 2532 if (pDCB->DevMode & 2533 TAG_QUEUING_) { 2534 pDCB->MaxCommand = 2535 pACB->TagMaxNum; 2536 pDCB->SyncMode |= 2537 EN_TAG_QUEUING; 2538 pDCB->TagMask = 0; 2539 pDCB->tinfo.disc_tag |= 2540 TRM_CUR_TAGENB; 2541 } else { 2542 pDCB->SyncMode |= 2543 EN_ATN_STOP; 2544 pDCB->tinfo.disc_tag &= 2545 ~TRM_CUR_TAGENB; 2546 } 2547 } 2548 } 2549 } 2550 /* pSRB->CmdBlock[0] == INQUIRY */ 2551 } 2552 /* pACB->scan_devices[target_id][target_lun] */ 2553 } 2554 intflag = splcam(); 2555 /* ReleaseSRB(pDCB, pSRB); */ 2556 if (pSRB == pDCB->pGoingSRB) 2557 pDCB->pGoingSRB = pSRB->pNextSRB; 2558 else { 2559 psrb = pDCB->pGoingSRB; 2560 while (psrb->pNextSRB != pSRB) { 2561 psrb = psrb->pNextSRB; 2562 } 2563 psrb->pNextSRB = pSRB->pNextSRB; 2564 if (pSRB == pDCB->pGoingLastSRB) { 2565 pDCB->pGoingLastSRB = psrb; 2566 } 2567 } 2568 pSRB->pNextSRB = pACB->pFreeSRB; 2569 pACB->pFreeSRB = pSRB; 2570 pDCB->GoingSRBCnt--; 2571 trm_DoWaitingSRB(pACB); 2572 2573 splx(intflag); 2574 /* Notify cmd done */ 2575 xpt_done (pccb); 2576} 2577 2578static void 2579trm_DoingSRB_Done(PACB pACB) 2580{ 2581 PDCB pDCB, pdcb; 2582 PSRB psrb, psrb2; 2583 u_int16_t cnt, i; 2584 union ccb *pccb; 2585 2586 pDCB = pACB->pLinkDCB; 2587 if (pDCB == NULL) 2588 return; 2589 pdcb = pDCB; 2590 do { 2591 cnt = pdcb->GoingSRBCnt; 2592 psrb = pdcb->pGoingSRB; 2593 for (i = 0; i < cnt; i++) { 2594 psrb2 = psrb->pNextSRB; 2595 pccb = psrb->pccb; 2596 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2597 /* ReleaseSRB(pDCB, pSRB); */ 2598 psrb->pNextSRB = pACB->pFreeSRB; 2599 pACB->pFreeSRB = psrb; 2600 xpt_done(pccb); 2601 psrb = psrb2; 2602 } 2603 pdcb->GoingSRBCnt = 0;; 2604 pdcb->pGoingSRB = NULL; 2605 pdcb->TagMask = 0; 2606 pdcb = pdcb->pNextDCB; 2607 } 2608 while (pdcb != pDCB); 2609} 2610 2611static void 2612trm_ResetSCSIBus(PACB pACB) 2613{ 2614 int intflag; 2615 2616 intflag = splcam(); 2617 pACB->ACBFlag |= RESET_DEV; 2618 2619 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2620 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2621 splx(intflag); 2622 return; 2623} 2624 2625static void 2626trm_ScsiRstDetect(PACB pACB) 2627{ 2628 int intflag; 2629 u_long wlval; 2630 2631 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2632 wlval = 1000; 2633 while (--wlval) 2634 DELAY(1000); 2635 intflag = splcam(); 2636 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2637 2638 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2639 2640 if (pACB->ACBFlag & RESET_DEV) 2641 pACB->ACBFlag |= RESET_DONE; 2642 else { 2643 pACB->ACBFlag |= RESET_DETECT; 2644 trm_ResetDevParam(pACB); 2645 /* trm_DoingSRB_Done(pACB); ???? */ 2646 trm_RecoverSRB(pACB); 2647 pACB->pActiveDCB = NULL; 2648 pACB->ACBFlag = 0; 2649 trm_DoWaitingSRB(pACB); 2650 } 2651 splx(intflag); 2652 return; 2653} 2654 2655static void 2656trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2657{ 2658 union ccb *pccb; 2659 struct ccb_scsiio *pcsio; 2660 2661 pccb = pSRB->pccb; 2662 pcsio = &pccb->csio; 2663 2664 pSRB->SRBFlag |= AUTO_REQSENSE; 2665 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2666 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2667 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2668 pSRB->SRBSGCount); 2669 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2670 2671 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2672 pSRB->AdaptStatus = 0; 2673 pSRB->TargetStatus = 0; 2674 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2675 2676 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2677 pSRB->SgSenseTemp.address = pSRB->SegmentX[0].address; 2678 pSRB->SgSenseTemp.length = pSRB->SegmentX[0].length; 2679 pSRB->SegmentX[0].address = (u_long) vtophys(&pcsio->sense_data); 2680 pSRB->SegmentX[0].length = (u_long) pcsio->sense_len; 2681 pSRB->SRBSGListPointer = &pSRB->SegmentX[0]; 2682 pSRB->SRBSGCount = 1; 2683 pSRB->SRBSGIndex = 0; 2684 2685 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2686 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2687 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2688 pSRB->ScsiCmdLen = 6; 2689 2690 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2691 /* 2692 * If trm_StartSCSI return 1 : 2693 * current interrupt status is interrupt disreenable 2694 * It's said that SCSI processor has more one SRB need to do 2695 */ 2696 trm_RewaitSRB(pDCB, pSRB); 2697} 2698 2699static void 2700trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2701{ 2702 2703 pSRB->MsgCnt = 1; 2704 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2705} 2706 2707static void 2708trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2709{ 2710 2711 pSRB->MsgOutBuf[0] = MSG_ABORT; 2712 trm_EnableMsgOutAbort2(pACB, pSRB); 2713} 2714 2715static void 2716trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2717{ 2718 PNVRAMTYPE pEEpromBuf; 2719 u_int8_t bval,PeriodIndex; 2720 u_int target_id,target_lun; 2721 PDCB pTempDCB; 2722 int intflag; 2723 2724 target_id = i; 2725 target_lun = j; 2726 2727 intflag = splcam(); 2728 if (pACB->pLinkDCB == 0) { 2729 pACB->pLinkDCB = pDCB; 2730 /* 2731 * RunRobin impersonate the role 2732 * that let each device had good proportion 2733 * about SCSI command proceeding 2734 */ 2735 pACB->pDCBRunRobin = pDCB; 2736 pDCB->pNextDCB = pDCB; 2737 } else { 2738 pTempDCB=pACB->pLinkDCB; 2739 /* search the last nod of DCB link */ 2740 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2741 pTempDCB = pTempDCB->pNextDCB; 2742 /* connect current DCB with last DCB tail */ 2743 pTempDCB->pNextDCB = pDCB; 2744 /* connect current DCB tail to this DCB Q head */ 2745 pDCB->pNextDCB=pACB->pLinkDCB; 2746 } 2747 splx(intflag); 2748 2749 pACB->DeviceCnt++; 2750 pDCB->pDCBACB = pACB; 2751 pDCB->TargetID = target_id; 2752 pDCB->TargetLUN = target_lun; 2753 pDCB->pWaitingSRB = NULL; 2754 pDCB->pGoingSRB = NULL; 2755 pDCB->GoingSRBCnt = 0; 2756 pDCB->pActiveSRB = NULL; 2757 pDCB->TagMask = 0; 2758 pDCB->MaxCommand = 1; 2759 pDCB->DCBFlag = 0; 2760 /* $$$$$$$ */ 2761 pEEpromBuf = &trm_eepromBuf[unit]; 2762 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2763 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2764 /* $$$$$$$ */ 2765 /* 2766 * disconnect enable ? 2767 */ 2768 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2769 bval = 0xC0; 2770 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2771 } else { 2772 bval = 0x80; 2773 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2774 } 2775 bval |= target_lun; 2776 pDCB->IdentifyMsg = bval; 2777 /* $$$$$$$ */ 2778 /* 2779 * tag Qing enable ? 2780 */ 2781 if (pDCB->DevMode & TAG_QUEUING_) { 2782 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2783 } else 2784 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2785 /* $$$$$$$ */ 2786 /* 2787 * wide nego ,sync nego enable ? 2788 */ 2789 pDCB->SyncPeriod = 0; 2790 pDCB->SyncOffset = 0; 2791 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2792 pDCB->MaxNegoPeriod = dc395x_trm_clock_period[ PeriodIndex ] ; 2793 pDCB->SyncMode = 0; 2794 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2795 (pACB->Config & HCC_WIDE_CARD)) 2796 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2797 /* enable wide nego */ 2798 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2799 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2800 /* enable sync nego */ 2801 /* $$$$$$$ */ 2802 /* 2803 * Fill in tinfo structure. 2804 */ 2805 pDCB->tinfo.user.period = pDCB->MaxNegoPeriod; 2806 pDCB->tinfo.user.offset = (pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2807 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2808 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2809 2810 pDCB->tinfo.current.period = 0; 2811 pDCB->tinfo.current.offset = 0; 2812 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2813} 2814 2815static void 2816trm_initSRB(PSRB psrb) 2817{ 2818 2819 psrb->PhysSRB = vtophys(psrb); 2820} 2821 2822static void 2823trm_linkSRB(PACB pACB) 2824{ 2825 u_int16_t i; 2826 2827 for (i = 0; i < MAX_SRB_CNT; i++) { 2828 if (i != MAX_SRB_CNT - 1) 2829 /* 2830 * link all SRB 2831 */ 2832 pACB->SRB_array[i].pNextSRB = &pACB->SRB_array[i+1]; 2833 else 2834 /* 2835 * load NULL to NextSRB of the last SRB 2836 */ 2837 pACB->SRB_array[i].pNextSRB = NULL; 2838 /* 2839 * convert and save physical address of SRB to pSRB->PhysSRB 2840 */ 2841 trm_initSRB((PSRB) &pACB->SRB_array[i]); 2842 } 2843} 2844 2845 2846static void 2847trm_initACB(PACB pACB, u_int16_t unit) 2848{ 2849 PNVRAMTYPE pEEpromBuf; 2850 u_int16_t i,j; 2851 2852 pEEpromBuf = &trm_eepromBuf[unit]; 2853 pACB->max_id = 15; 2854 2855 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 2856 pACB->max_lun = 7; 2857 else 2858 pACB->max_lun = 0; 2859 2860 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 2861 pACB->max_id, pACB->max_lun); 2862 2863 pACB->pLinkDCB = NULL; 2864 pACB->pDCBRunRobin = NULL; 2865 pACB->pActiveDCB = NULL; 2866 pACB->pFreeSRB = pACB->SRB_array; 2867 pACB->AdapterUnit = unit; 2868 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 2869 pACB->AdaptSCSILUN = 0; 2870 pACB->DeviceCnt = 0; 2871 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag ; 2872 pACB->ACBFlag = 0; 2873 /* 2874 * link all device's SRB Q of this adapter 2875 */ 2876 trm_linkSRB(pACB); 2877 /* 2878 * temp SRB for Q tag used or abord command used 2879 */ 2880 pACB->pTmpSRB = &pACB->TmpSRB; 2881 /* 2882 * convert and save physical address of SRB to pSRB->PhysSRB 2883 */ 2884 trm_initSRB(pACB->pTmpSRB); 2885 /* allocate DCB array for scan device */ 2886 for (i = 0; i < (pACB->max_id +1); i++) { 2887 if (pACB->AdaptSCSIID != i) { 2888 for (j = 0; j < (pACB->max_lun +1); j++) { 2889 pACB->scan_devices[i][j] = 1; 2890 pACB->pDCB[i][j]= (PDCB) malloc ( 2891 sizeof (struct _DCB), M_DEVBUF, M_WAITOK); 2892 trm_initDCB(pACB, 2893 pACB->pDCB[i][j], unit, i, j); 2894 TRM_DPRINTF("pDCB= %8x \n", 2895 (u_int)pACB->pDCB[i][j]); 2896 } 2897 } 2898 } 2899 TRM_DPRINTF("sizeof(struct _DCB)= %8x \n",sizeof(struct _DCB)); 2900 TRM_DPRINTF("sizeof(struct _ACB)= %8x \n",sizeof(struct _ACB)); 2901 TRM_DPRINTF("sizeof(struct _SRB)= %8x \n",sizeof(struct _SRB)); 2902} 2903 2904static void 2905TRM_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 2906{ 2907 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 2908 u_int8_t bAddr; 2909 2910 /* Enable SEEPROM */ 2911 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 2912 TRMREG_GEN_CONTROL); 2913 /* 2914 * Write enable 2915 */ 2916 TRM_write_cmd(pACB, 0x04, 0xFF); 2917 trm_reg_write8(0, TRMREG_GEN_NVRAM); 2918 TRM_wait_30us(pACB); 2919 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 2920 TRM_set_data(pACB, bAddr, *bpEeprom); 2921 } 2922 /* 2923 * Write disable 2924 */ 2925 TRM_write_cmd(pACB, 0x04, 0x00); 2926 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 2927 TRM_wait_30us(pACB); 2928 /* Disable SEEPROM */ 2929 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 2930 TRMREG_GEN_CONTROL); 2931 return; 2932} 2933 2934static void 2935TRM_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 2936{ 2937 int i; 2938 u_int8_t bSendData; 2939 /* 2940 * Send write command & address 2941 */ 2942 2943 TRM_write_cmd(pACB, 0x05, bAddr); 2944 /* 2945 * Write data 2946 */ 2947 for (i = 0; i < 8; i++, bData <<= 1) { 2948 bSendData = NVR_SELECT; 2949 if (bData & 0x80) 2950 /* Start from bit 7 */ 2951 bSendData |= NVR_BITOUT; 2952 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 2953 TRM_wait_30us(pACB); 2954 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 2955 TRM_wait_30us(pACB); 2956 } 2957 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 2958 TRM_wait_30us(pACB); 2959 /* 2960 * Disable chip select 2961 */ 2962 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 2963 TRM_wait_30us(pACB); 2964 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 2965 TRM_wait_30us(pACB); 2966 /* 2967 * Wait for write ready 2968 */ 2969 while (1) { 2970 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 2971 TRM_wait_30us(pACB); 2972 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 2973 TRM_wait_30us(pACB); 2974 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 2975 break; 2976 } 2977 } 2978 /* 2979 * Disable chip select 2980 */ 2981 trm_reg_write8(0, TRMREG_GEN_NVRAM); 2982 return; 2983} 2984 2985static void 2986TRM_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 2987{ 2988 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 2989 u_int8_t bAddr; 2990 2991 /* 2992 * Enable SEEPROM 2993 */ 2994 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 2995 TRMREG_GEN_CONTROL); 2996 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2997 *bpEeprom = TRM_get_data(pACB, bAddr); 2998 /* 2999 * Disable SEEPROM 3000 */ 3001 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3002 TRMREG_GEN_CONTROL); 3003 return; 3004} 3005 3006static u_int8_t 3007TRM_get_data(PACB pACB, u_int8_t bAddr) 3008{ 3009 int i; 3010 u_int8_t bReadData, bData = 0; 3011 /* 3012 * Send read command & address 3013 */ 3014 3015 TRM_write_cmd(pACB, 0x06, bAddr); 3016 3017 for (i = 0; i < 8; i++) { 3018 /* 3019 * Read data 3020 */ 3021 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3022 TRM_wait_30us(pACB); 3023 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3024 /* 3025 * Get data bit while falling edge 3026 */ 3027 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3028 bData <<= 1; 3029 if (bReadData & NVR_BITIN) { 3030 bData |= 1; 3031 } 3032 TRM_wait_30us(pACB); 3033 } 3034 /* 3035 * Disable chip select 3036 */ 3037 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3038 return (bData); 3039} 3040 3041static void 3042TRM_wait_30us(PACB pACB) 3043{ 3044 3045 /* ScsiPortStallExecution(30); wait 30 us */ 3046 trm_reg_write8(5, TRMREG_GEN_TIMER); 3047 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3048 return; 3049} 3050 3051static void 3052TRM_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3053{ 3054 int i; 3055 u_int8_t bSendData; 3056 3057 for (i = 0; i < 3; i++, bCmd <<= 1) { 3058 /* 3059 * Program SB+OP code 3060 */ 3061 bSendData = NVR_SELECT; 3062 if (bCmd & 0x04) 3063 bSendData |= NVR_BITOUT; 3064 /* start from bit 2 */ 3065 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3066 TRM_wait_30us(pACB); 3067 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3068 TRM_wait_30us(pACB); 3069 } 3070 for (i = 0; i < 7; i++, bAddr <<= 1) { 3071 /* 3072 * Program address 3073 */ 3074 bSendData = NVR_SELECT; 3075 if (bAddr & 0x40) 3076 /* Start from bit 6 */ 3077 bSendData |= NVR_BITOUT; 3078 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3079 TRM_wait_30us(pACB); 3080 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3081 TRM_wait_30us(pACB); 3082 } 3083 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3084 TRM_wait_30us(pACB); 3085} 3086 3087static void 3088trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3089{ 3090 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3091 u_int16_t wAddr, wCheckSum; 3092 u_long dAddr, *dpEeprom; 3093 3094 TRM_read_all(pEEpromBuf,pACB); 3095 wCheckSum = 0; 3096 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3097 wAddr < 64; wAddr++, wpEeprom++) { 3098 wCheckSum += *wpEeprom; 3099 } 3100 if (wCheckSum != 0x1234) { 3101 /* 3102 * Checksum error, load default 3103 */ 3104 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3105 pEEpromBuf->NvramSubVendorID[1] = 3106 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3107 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3108 pEEpromBuf->NvramSubSysID[1] = 3109 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3110 pEEpromBuf->NvramSubClass = 0x00; 3111 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3112 pEEpromBuf->NvramVendorID[1] = 3113 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3114 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3115 pEEpromBuf->NvramDeviceID[1] = 3116 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3117 pEEpromBuf->NvramReserved = 0x00; 3118 3119 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3120 dAddr < 16; dAddr++, dpEeprom++) { 3121 *dpEeprom = 0x00000077; 3122 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3123 } 3124 3125 *dpEeprom++ = 0x04000F07; 3126 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3127 *dpEeprom++ = 0x00000015; 3128 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3129 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3130 *dpEeprom = 0x00; 3131 pEEpromBuf->NvramCheckSum = 0x00; 3132 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3133 wAddr < 63; wAddr++, wpEeprom++) 3134 wCheckSum += *wpEeprom; 3135 *wpEeprom = 0x1234 - wCheckSum; 3136 TRM_write_all(pEEpromBuf,pACB); 3137 } 3138 return; 3139} 3140static int 3141trm_initAdapter(PACB pACB, u_int16_t unit, device_t pci_config_id) 3142{ 3143 PNVRAMTYPE pEEpromBuf; 3144 u_int16_t wval; 3145 u_int8_t bval; 3146 3147 pEEpromBuf = &trm_eepromBuf[unit]; 3148 3149 /* 250ms selection timeout */ 3150 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3151 /* Mask all the interrupt */ 3152 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3153 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3154 /* Reset SCSI module */ 3155 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3156 /* program configuration 0 */ 3157 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3158 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3159 pACB->Config |= HCC_WIDE_CARD; 3160 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3161 pACB->Config |= HCC_SCSI_RESET; 3162 if (pACB->Config & HCC_PARITY) 3163 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3164 else 3165 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3166 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3167 /* program configuration 1 */ 3168 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3169 /* program Host ID */ 3170 bval = pEEpromBuf->NvramScsiId; 3171 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3172 /* set ansynchronous transfer */ 3173 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3174 /* Trun LED control off*/ 3175 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3176 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3177 /* DMA config */ 3178 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3179 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3180 /* Clear pending interrupt status */ 3181 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3182 /* Enable SCSI interrupt */ 3183 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3184 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3185 return (0); 3186} 3187 3188static PACB 3189trm_init(u_int16_t unit, device_t pci_config_id) 3190{ 3191 PACB pACB; 3192 int rid = PCI_BASE_ADDR0; 3193 struct resource *iores; 3194 3195 pACB = (PACB) device_get_softc(pci_config_id); 3196 if (!pACB) { 3197 printf("trm%d: cannot allocate ACB !\n", unit); 3198 return (NULL); 3199 } 3200 bzero (pACB, sizeof (struct _ACB)); 3201 iores = bus_alloc_resource(pci_config_id, SYS_RES_IOPORT 3202 , &rid, 0, ~0, 1, RF_ACTIVE); 3203 if (iores == NULL) { 3204 printf("trm_init: bus_alloc_resource failed!\n"); 3205 return (NULL); 3206 } 3207 pACB->tag = rman_get_bustag(iores); 3208 pACB->bsh = rman_get_bushandle(iores); 3209 if (bus_dma_tag_create(/*parent_dmat*/ NULL, 3210 /*alignment*/ 1, 3211 /*boundary*/ 0, 3212 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3213 /*highaddr*/ BUS_SPACE_MAXADDR, 3214 /*filter*/ NULL, 3215 /*filterarg*/ NULL, 3216 /*maxsize*/ MAXBSIZE, 3217 /*nsegments*/ TRM_NSEG, 3218 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3219 /*flags*/ BUS_DMA_ALLOCNOW, 3220 &pACB->buffer_dmat) != 0) 3221 return (NULL); 3222 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3223 trm_initACB(pACB, unit); 3224 if (trm_initAdapter(pACB, unit, pci_config_id)) { 3225 printf("trm_initAdapter: initial ERROR\n"); 3226 return (NULL); 3227 } 3228 return (pACB); 3229} 3230 3231static int 3232trm_attach(device_t pci_config_id) 3233{ 3234 struct cam_devq *device_Q; 3235 u_long device_id; 3236 PACB pACB = 0; 3237 int rid = 0; 3238 void *ih; 3239 struct resource *irqres; 3240 int unit = device_get_unit(pci_config_id); 3241 3242 device_id = pci_get_devid(pci_config_id); 3243 /* 3244 * These cards do not allow memory mapped accesses 3245 */ 3246 if (device_id == PCI_DEVICEID_TRMS1040) { 3247 if ((pACB=trm_init((u_int16_t) unit, 3248 pci_config_id)) == NULL) { 3249 printf("trm%d: trm_init error!\n",unit); 3250 return (ENXIO); 3251 } 3252 } else 3253 return (ENXIO); 3254 /* After setting up the adapter, map our interrupt */ 3255 /* 3256 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3257 * start queue to reset to the idle loop. 3258 * Create device queue of SIM(s) 3259 * (MAX_START_JOB - 1) : max_sim_transactions 3260 */ 3261 irqres = bus_alloc_resource(pci_config_id, SYS_RES_IRQ, &rid, 0, ~0, 1, 3262 RF_SHAREABLE | RF_ACTIVE); 3263 if (irqres == NULL || 3264 bus_setup_intr(pci_config_id, irqres, 3265 INTR_TYPE_CAM, trm_Interrupt, pACB, &ih)) { 3266 printf("trm%d: register Interrupt handler error!\n", unit); 3267 return (ENXIO); 3268 } 3269 device_Q = cam_simq_alloc(MAX_START_JOB); 3270 if (device_Q == NULL){ 3271 printf("trm%d: device_Q == NULL !\n",unit); 3272 return (ENXIO); 3273 } 3274 /* 3275 * Now tell the generic SCSI layer 3276 * about our bus. 3277 * If this is the xpt layer creating a sim, then it's OK 3278 * to wait for an allocation. 3279 * XXX Should we pass in a flag to indicate that wait is OK? 3280 * 3281 * SIM allocation 3282 * 3283 * SCSI Interface Modules 3284 * The sim driver creates a sim for each controller. The sim device 3285 * queue is separately created in order to allow resource sharing betwee 3286 * sims. For instance, a driver may create one sim for each channel of 3287 * a multi-channel controller and use the same queue for each channel. 3288 * In this way, the queue resources are shared across all the channels 3289 * of the multi-channel controller. 3290 * trm_action : sim_action_func 3291 * trm_poll : sim_poll_func 3292 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3293 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3294 * pACB->unit : unit 3295 * 1 : max_dev_transactions 3296 * MAX_TAGS : max_tagged_dev_transactions 3297 * 3298 * *******Construct our first channel SIM entry 3299 */ 3300 pACB->psim = cam_sim_alloc(trm_action, 3301 trm_poll, 3302 "trm", 3303 pACB, 3304 unit, 3305 1, 3306 MAX_TAGS_CMD_QUEUE, 3307 device_Q); 3308 if (pACB->psim == NULL) { 3309 printf("trm%d: SIM allocate fault !\n",unit); 3310 cam_simq_free(device_Q); /* SIM allocate fault*/ 3311 return (ENXIO); 3312 } 3313 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3314 printf("trm%d: xpt_bus_register fault !\n",unit); 3315 cam_sim_free(pACB->psim, TRUE); 3316 /* 3317 * cam_sim_free(pACB->psim, TRUE); free_devq 3318 * pACB->psim = NULL; 3319 */ 3320 return (ENXIO); 3321 } 3322 if (xpt_create_path(&pACB->ppath, 3323 NULL, 3324 cam_sim_path(pACB->psim), 3325 CAM_TARGET_WILDCARD, 3326 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3327 printf("trm%d: xpt_create_path fault !\n",unit); 3328 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3329 cam_sim_free(pACB->psim, /*free_simq*/TRUE); 3330 /* 3331 * cam_sim_free(pACB->psim, TRUE); free_devq 3332 * pACB->psim = NULL; 3333 */ 3334 return (ENXIO); 3335 } 3336 return (0); 3337} 3338 3339/* 3340* pci_device 3341* trm_probe (device_t tag, pcidi_t type) 3342* 3343*/ 3344static int 3345trm_probe(device_t tag) 3346{ 3347 3348 if (pci_get_devid(tag) == PCI_DEVICEID_TRMS1040) { 3349 device_set_desc(tag, 3350 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3351 return (0); 3352 } else 3353 return (ENXIO); 3354} 3355 3356static int 3357trm_detach(PACB pACB) 3358{ 3359 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3360 xpt_free_path(pACB->ppath); 3361 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3362 cam_sim_free(pACB->psim, TRUE); 3363 return (0); 3364} 3365static device_method_t trm_methods[] = { 3366 /* Device interface */ 3367 DEVMETHOD(device_probe, trm_probe), 3368 DEVMETHOD(device_attach, trm_attach), 3369 DEVMETHOD(device_detach, trm_detach), 3370 { 0, 0 } 3371}; 3372 3373static driver_t trm_driver = { 3374 "trm", trm_methods, sizeof(struct _ACB) 3375}; 3376 3377static devclass_t trm_devclass; 3378DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3379