if_tireg.h revision 76033
1193326Sed/* 2193326Sed * Copyright (c) 1997, 1998, 1999 3193326Sed * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4193326Sed * 5193326Sed * Redistribution and use in source and binary forms, with or without 6193326Sed * modification, are permitted provided that the following conditions 7193326Sed * are met: 8193326Sed * 1. Redistributions of source code must retain the above copyright 9193326Sed * notice, this list of conditions and the following disclaimer. 10193326Sed * 2. Redistributions in binary form must reproduce the above copyright 11193326Sed * notice, this list of conditions and the following disclaimer in the 12193326Sed * documentation and/or other materials provided with the distribution. 13249423Sdim * 3. All advertising materials mentioning features or use of this software 14249423Sdim * must display the following acknowledgement: 15193326Sed * This product includes software developed by Bill Paul. 16193326Sed * 4. Neither the name of the author nor the names of any co-contributors 17193326Sed * may be used to endorse or promote products derived from this software 18193326Sed * without specific prior written permission. 19263508Sdim * 20263508Sdim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21193326Sed * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22193326Sed * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23193326Sed * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24193326Sed * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25193326Sed * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26198092Srdivacky * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27198092Srdivacky * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28198092Srdivacky * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29208600Srdivacky * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30193326Sed * THE POSSIBILITY OF SUCH DAMAGE. 31234353Sdim * 32234353Sdim * $FreeBSD: head/sys/dev/ti/if_tireg.h 76033 2001-04-26 16:40:45Z wpaul $ 33234353Sdim */ 34234353Sdim 35234353Sdim/* 36234353Sdim * Tigon register offsets. These are memory mapped registers 37234353Sdim * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38234353Sdim * Each register must be accessed using 32 bit operations. 39234353Sdim * 40234353Sdim * All reegisters are accessed through a 16K shared memory block. 41234353Sdim * The first group of registers are actually copies of the PCI 42234353Sdim * configuration space registers. 43234353Sdim */ 44234353Sdim 45234353Sdim#define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46234353Sdim#define TI_PCI_CMDSTAT 0x004 47234353Sdim#define TI_PCI_CLASSCODE 0x008 48234353Sdim#define TI_PCI_BIST 0x00C 49234353Sdim#define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50234353Sdim#define TI_PCI_SUBSYS 0x02C 51234353Sdim#define TI_PCI_ROMBASE 0x030 52234353Sdim#define TI_PCI_INT 0x03C 53263508Sdim 54263508Sdim#ifndef PCIM_CMD_MWIEN 55263508Sdim#define PCIM_CMD_MWIEN 0x0010 56234353Sdim#endif 57234353Sdim 58234353Sdim/* 59234353Sdim * Alteon AceNIC PCI vendor/device ID. 60263508Sdim */ 61263508Sdim#define ALT_VENDORID 0x12AE 62263508Sdim#define ALT_DEVICEID_ACENIC 0x0001 63263508Sdim#define ALT_DEVICEID_ACENIC_COPPER 0x0002 64263508Sdim 65234353Sdim/* 66234353Sdim * 3Com 3c985 PCI vendor/device ID. 67234353Sdim */ 68234353Sdim#define TC_VENDORID 0x10B7 69234353Sdim#define TC_DEVICEID_3C985 0x0001 70234353Sdim 71234353Sdim/* 72234353Sdim * Netgear GA620 PCI vendor/device ID. 73234353Sdim */ 74234353Sdim#define NG_VENDORID 0x1385 75234353Sdim#define NG_DEVICEID_GA620 0x620A 76234353Sdim#define NG_DEVICEID_GA620T 0x630A 77234353Sdim 78234353Sdim/* 79263508Sdim * SGI device/vendor ID. 80234353Sdim */ 81234353Sdim#define SGI_VENDORID 0x10A9 82234353Sdim#define SGI_DEVICEID_TIGON 0x0009 83234353Sdim 84263508Sdim/* 85234353Sdim * DEC vendor ID, Farallon device ID. Apparently, Farallon used 86263508Sdim * the DEC vendor ID in their cards by mistake. 87234353Sdim */ 88234353Sdim#define DEC_VENDORID 0x1011 89234353Sdim#define DEC_DEVICEID_FARALLON_PN9000SX 0x001a 90263508Sdim 91263508Sdim/* 92263508Sdim * Tigon configuration and control registers. 93263508Sdim */ 94234353Sdim#define TI_MISC_HOST_CTL 0x040 95263508Sdim#define TI_MISC_LOCAL_CTL 0x044 96263508Sdim#define TI_SEM_AB 0x048 /* Tigon 2 only */ 97234353Sdim#define TI_MISC_CONF 0x050 /* Tigon 2 only */ 98234353Sdim#define TI_TIMER_BITS 0x054 99234353Sdim#define TI_TIMERREF 0x058 100234353Sdim#define TI_PCI_STATE 0x05C 101234353Sdim#define TI_MAIN_EVENT_A 0x060 102234353Sdim#define TI_MAILBOX_EVENT_A 0x064 103234353Sdim#define TI_WINBASE 0x068 104234353Sdim#define TI_WINDATA 0x06C 105234353Sdim#define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 106234353Sdim#define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 107263508Sdim#define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 108263508Sdim#define TI_SERIAL 0x07C 109263508Sdim 110234353Sdim/* 111234353Sdim * Misc host control bits. 112234353Sdim */ 113234353Sdim#define TI_MHC_INTSTATE 0x00000001 114263508Sdim#define TI_MHC_CLEARINT 0x00000002 115263508Sdim#define TI_MHC_RESET 0x00000008 116263508Sdim#define TI_MHC_BYTE_SWAP_ENB 0x00000010 117263508Sdim#define TI_MHC_WORD_SWAP_ENB 0x00000020 118263508Sdim#define TI_MHC_MASK_INTS 0x00000040 119263508Sdim#define TI_MHC_CHIP_REV_MASK 0xF0000000 120263508Sdim 121263508Sdim#define TI_MHC_BIGENDIAN_INIT \ 122263508Sdim (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 123263508Sdim 124263508Sdim#define TI_MHC_LITTLEENDIAN_INIT \ 125263508Sdim (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 126263508Sdim 127263508Sdim/* 128234353Sdim * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 129239462Sdim * Rev 5 is also the Tigon 2, but is a broken version which was never 130234353Sdim * used in any actual hardware, so we ignore it. 131263508Sdim */ 132263508Sdim#define TI_REV_TIGON_I 0x40000000 133263508Sdim#define TI_REV_TIGON_II 0x60000000 134234353Sdim 135263508Sdim/* 136263508Sdim * Firmware revision that we want. 137263508Sdim */ 138263508Sdim#define TI_FIRMWARE_MAJOR 0xc 139263508Sdim#define TI_FIRMWARE_MINOR 0x4 140263508Sdim#define TI_FIRMWARE_FIX 0xd 141263508Sdim 142234353Sdim/* 143234353Sdim * Miscelaneous Local Control register. 144263508Sdim */ 145234353Sdim#define TI_MLC_EE_WRITE_ENB 0x00000010 146234353Sdim#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147263508Sdim#define TI_MLC_LOCALADDR_21 0x00004000 148263508Sdim#define TI_MLC_LOCALADDR_22 0x00008000 149263508Sdim#define TI_MLC_SBUS_WRITEERR 0x00080000 150263508Sdim#define TI_MLC_EE_CLK 0x00100000 151263508Sdim#define TI_MLC_EE_TXEN 0x00200000 152234353Sdim#define TI_MLC_EE_DOUT 0x00400000 153234353Sdim#define TI_MLC_EE_DIN 0x00800000 154234353Sdim 155234353Sdim/* Possible memory sizes. */ 156193326Sed#define TI_MLC_SRAM_BANK_DISA 0x00000000 157263508Sdim#define TI_MLC_SRAM_BANK_1024K 0x00000100 158263508Sdim#define TI_MLC_SRAM_BANK_512K 0x00000200 159193326Sed#define TI_MLC_SRAM_BANK_256K 0x00000300 160193326Sed 161263508Sdim/* 162263508Sdim * Offset of MAC address inside EEPROM. 163193326Sed */ 164243830Sdim#define TI_EE_MAC_OFFSET 0x8c 165251662Sdim 166243830Sdim#define TI_DMA_ASSIST 0x11C 167266715Sdim#define TI_CPU_STATE 0x140 168266715Sdim#define TI_CPU_PROGRAM_COUNTER 0x144 169234353Sdim#define TI_SRAM_ADDR 0x154 170234353Sdim#define TI_SRAM_DATA 0x158 171249423Sdim#define TI_GEN_0 0x180 172249423Sdim#define TI_GEN_X 0x1FC 173249423Sdim#define TI_MAC_TX_STATE 0x200 174249423Sdim#define TI_MAC_RX_STATE 0x220 175234353Sdim#define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 176234353Sdim#define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 177234353Sdim#define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 178234353Sdim#define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 179234353Sdim#define TI_GEN_B_0 0x280 /* Tigon 2 only */ 180234353Sdim#define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 181234353Sdim 182234353Sdim/* 183234353Sdim * Misc config register. 184234353Sdim */ 185193326Sed#define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 186249423Sdim 187249423Sdim/* 188249423Sdim * PCI state register. 189249423Sdim */ 190234353Sdim#define TI_PCISTATE_FORCE_RESET 0x00000001 191234353Sdim#define TI_PCISTATE_PROVIDE_LEN 0x00000002 192234353Sdim#define TI_PCISTATE_READ_MAXDMA 0x0000001C 193208600Srdivacky#define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 194212904Sdim#define TI_PCISTATE_MINDMA 0x0000FF00 195212904Sdim#define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 196212904Sdim#define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 197212904Sdim#define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 198249423Sdim#define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 199249423Sdim#define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 200249423Sdim#define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 201249423Sdim#define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 202249423Sdim#define TI_PCISTATE_READ_CMD 0x0F000000 203212904Sdim#define TI_PCISTATE_WRITE_CMD 0xF0000000 204249423Sdim 205249423Sdim#define TI_PCI_READMAX_4 0x04 206249423Sdim#define TI_PCI_READMAX_16 0x08 207193326Sed#define TI_PCI_READMAX_32 0x0C 208203955Srdivacky#define TI_PCI_READMAX_64 0x10 209198092Srdivacky#define TI_PCI_READMAX_128 0x14 210203955Srdivacky#define TI_PCI_READMAX_256 0x18 211203955Srdivacky#define TI_PCI_READMAX_1024 0x1C 212203955Srdivacky 213203955Srdivacky#define TI_PCI_WRITEMAX_4 0x20 214193326Sed#define TI_PCI_WRITEMAX_16 0x40 215221345Sdim#define TI_PCI_WRITEMAX_32 0x60 216203955Srdivacky#define TI_PCI_WRITEMAX_64 0x80 217208600Srdivacky#define TI_PCI_WRITEMAX_128 0xA0 218221345Sdim#define TI_PCI_WRITEMAX_256 0xC0 219221345Sdim#define TI_PCI_WRITEMAX_1024 0xE0 220221345Sdim 221221345Sdim#define TI_PCI_READ_CMD 0x06000000 222234353Sdim#define TI_PCI_WRITE_CMD 0x70000000 223203955Srdivacky 224239462Sdim/* 225193326Sed * DMA state register. 226193326Sed */ 227203955Srdivacky#define TI_DMASTATE_ENABLE 0x00000001 228193326Sed#define TI_DMASTATE_PAUSE 0x00000002 229239462Sdim 230239462Sdim/* 231239462Sdim * CPU state register. 232224145Sdim */ 233212904Sdim#define TI_CPUSTATE_RESET 0x00000001 234263508Sdim#define TI_CPUSTATE_STEP 0x00000002 235212904Sdim#define TI_CPUSTATE_ROMFAIL 0x00000010 236193326Sed#define TI_CPUSTATE_HALT 0x00010000 237263508Sdim/* 238263508Sdim * MAC TX state register 239198092Srdivacky */ 240193326Sed#define TI_TXSTATE_RESET 0x00000001 241263508Sdim#define TI_TXSTATE_ENB 0x00000002 242226633Sdim#define TI_TXSTATE_STOP 0x00000004 243212904Sdim 244198092Srdivacky/* 245198092Srdivacky * MAC RX state register 246198092Srdivacky */ 247203955Srdivacky#define TI_RXSTATE_RESET 0x00000001 248203955Srdivacky#define TI_RXSTATE_ENB 0x00000002 249221345Sdim#define TI_RXSTATE_STOP 0x00000004 250221345Sdim 251221345Sdim/* 252221345Sdim * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 253203955Srdivacky * split into 64 bit registers. Only the lower 32 bits of each mailbox 254203955Srdivacky * are used. 255221345Sdim */ 256221345Sdim#define TI_MB_HOSTINTR_HI 0x500 257234353Sdim#define TI_MB_HOSTINTR_LO 0x504 258203955Srdivacky#define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 259203955Srdivacky#define TI_MB_CMDPROD_IDX_HI 0x508 260203955Srdivacky#define TI_MB_CMDPROD_IDX_LO 0x50C 261203955Srdivacky#define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 262221345Sdim#define TI_MB_SENDPROD_IDX_HI 0x510 263221345Sdim#define TI_MB_SENDPROD_IDX_LO 0x514 264234353Sdim#define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 265193326Sed#define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 266193326Sed#define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 267203955Srdivacky#define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 268203955Srdivacky#define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 269203955Srdivacky#define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 270193326Sed#define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 271193326Sed#define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 272221345Sdim#define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 273221345Sdim#define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 274221345Sdim#define TI_MB_RSVD 0x530 275221345Sdim 276221345Sdim/* 277234353Sdim * Tigon 2 general communication registers. These are 64 and 32 bit 278243830Sdim * registers which are only valid after the firmware has been 279234353Sdim * loaded and started. They actually exist in NIC memory but are 280234353Sdim * mapped into the host memory via the shared memory region. 281205408Srdivacky * 282205408Srdivacky * The NIC internally maps these registers starting at address 0, 283234353Sdim * so to determine the NIC address of any of these registers, we 284203955Srdivacky * subtract 0x600 (the address of the first register). 285234353Sdim */ 286203955Srdivacky 287203955Srdivacky#define TI_GCR_BASE 0x600 288202879Srdivacky#define TI_GCR_MACADDR 0x600 289202879Srdivacky#define TI_GCR_PAR0 0x600 290202879Srdivacky#define TI_GCR_PAR1 0x604 291263508Sdim#define TI_GCR_GENINFO_HI 0x608 292202879Srdivacky#define TI_GCR_GENINFO_LO 0x60C 293203955Srdivacky#define TI_GCR_MCASTADDR 0x610 /* obsolete */ 294203955Srdivacky#define TI_GCR_MAR0 0x610 /* obsolete */ 295234353Sdim#define TI_GCR_MAR1 0x614 /* obsolete */ 296198092Srdivacky#define TI_GCR_OPMODE 0x618 297198092Srdivacky#define TI_GCR_DMA_READCFG 0x61C 298203955Srdivacky#define TI_GCR_DMA_WRITECFG 0x620 299203955Srdivacky#define TI_GCR_TX_BUFFER_RATIO 0x624 300234353Sdim#define TI_GCR_EVENTCONS_IDX 0x628 301193326Sed#define TI_GCR_CMDCONS_IDX 0x62C 302193326Sed#define TI_GCR_TUNEPARMS 0x630 303224145Sdim#define TI_GCR_RX_COAL_TICKS 0x630 304263508Sdim#define TI_GCR_TX_COAL_TICKS 0x634 305263508Sdim#define TI_GCR_STAT_TICKS 0x638 306263508Sdim#define TI_GCR_TX_MAX_COAL_BD 0x63C 307198092Srdivacky#define TI_GCR_RX_MAX_COAL_BD 0x640 308198092Srdivacky#define TI_GCR_NIC_TRACING 0x644 309263508Sdim#define TI_GCR_GLINK 0x648 310263508Sdim#define TI_GCR_LINK 0x64C 311263508Sdim#define TI_GCR_NICTRACE_PTR 0x650 312263508Sdim#define TI_GCR_NICTRACE_START 0x654 313198092Srdivacky#define TI_GCR_NICTRACE_LEN 0x658 314198092Srdivacky#define TI_GCR_IFINDEX 0x65C 315198092Srdivacky#define TI_GCR_IFMTU 0x660 316198092Srdivacky#define TI_GCR_MASK_INTRS 0x664 317212904Sdim#define TI_GCR_GLINK_STAT 0x668 318212904Sdim#define TI_GCR_LINK_STAT 0x66C 319218893Sdim#define TI_GCR_RXRETURNCONS_IDX 0x680 320218893Sdim#define TI_GCR_CMDRING 0x700 321239462Sdim 322226633Sdim#define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE); 323224145Sdim 324263508Sdim/* 325263508Sdim * Local memory window. The local memory window is a 2K shared 326263508Sdim * memory region which can be used to access the NIC's internal 327198092Srdivacky * SRAM. The window can be mapped to a given 2K region using 328199482Srdivacky * the TI_WINDOW_BASE register. 329212904Sdim */ 330212904Sdim#define TI_WINDOW 0x800 331212904Sdim#define TI_WINLEN 0x800 332199482Srdivacky 333208600Srdivacky#define TI_TICKS_PER_SEC 1000000 334234353Sdim 335234353Sdim/* 336208600Srdivacky * Operation mode register. 337239462Sdim */ 338239462Sdim#define TI_OPMODE_BYTESWAP_BD 0x00000002 339239462Sdim#define TI_OPMODE_WORDSWAP_BD 0x00000004 340239462Sdim#define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */ 341239462Sdim#define TI_OPMODE_BYTESWAP_DATA 0x00000010 342243830Sdim#define TI_OPMODE_1_DMA_ACTIVE 0x00000040 343243830Sdim#define TI_OPMODE_SBUS 0x00000100 344243830Sdim#define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 345243830Sdim#define TI_OPMODE_INCLUDE_CRC 0x00000400 346199482Srdivacky#define TI_OPMODE_RX_BADFRAMES 0x00000800 347207619Srdivacky#define TI_OPMODE_NO_EVENT_INTRS 0x00001000 348207619Srdivacky#define TI_OPMODE_NO_TX_INTRS 0x00002000 349199482Srdivacky#define TI_OPMODE_NO_RX_INTRS 0x00004000 350207619Srdivacky#define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ 351207619Srdivacky 352207619Srdivacky/* 353207619Srdivacky * DMA configuration thresholds. 354207619Srdivacky */ 355207619Srdivacky#define TI_DMA_STATE_THRESH_16W 0x00000100 356207619Srdivacky#define TI_DMA_STATE_THRESH_8W 0x00000080 357193326Sed#define TI_DMA_STATE_THRESH_4W 0x00000040 358226633Sdim#define TI_DMA_STATE_THRESH_2W 0x00000020 359226633Sdim#define TI_DMA_STATE_THRESH_1W 0x00000010 360226633Sdim 361234353Sdim#define TI_DMA_STATE_FORCE_32_BIT 0x00000008 362226633Sdim 363226633Sdim/* 364199482Srdivacky * Gigabit link status bits. 365234353Sdim */ 366234353Sdim#define TI_GLNK_SENSE_NO_BEG 0x00002000 367234353Sdim#define TI_GLNK_LOOPBACK 0x00004000 368243830Sdim#define TI_GLNK_PREF 0x00008000 369251662Sdim#define TI_GLNK_1000MB 0x00040000 370243830Sdim#define TI_GLNK_FULL_DUPLEX 0x00080000 371198092Srdivacky#define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 372221345Sdim#define TI_GLNK_RX_FLOWCTL_Y 0x00800000 373221345Sdim#define TI_GLNK_AUTONEGENB 0x20000000 374207619Srdivacky#define TI_GLNK_ENB 0x40000000 375207619Srdivacky 376243830Sdim/* 377234353Sdim * Link status bits. 378201361Srdivacky */ 379201361Srdivacky#define TI_LNK_LOOPBACK 0x00004000 380203955Srdivacky#define TI_LNK_PREF 0x00008000 381203955Srdivacky#define TI_LNK_10MB 0x00010000 382198092Srdivacky#define TI_LNK_100MB 0x00020000 383193326Sed#define TI_LNK_1000MB 0x00040000 384193326Sed#define TI_LNK_FULL_DUPLEX 0x00080000 385198092Srdivacky#define TI_LNK_HALF_DUPLEX 0x00100000 386208600Srdivacky#define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 387193326Sed#define TI_LNK_RX_FLOWCTL_Y 0x00800000 388263508Sdim#define TI_LNK_AUTONEGENB 0x20000000 389263508Sdim#define TI_LNK_ENB 0x40000000 390198092Srdivacky 391198092Srdivacky/* 392198092Srdivacky * Ring size constants. 393198092Srdivacky */ 394263508Sdim#define TI_EVENT_RING_CNT 256 395263508Sdim#define TI_CMD_RING_CNT 64 396263508Sdim#define TI_STD_RX_RING_CNT 512 397263508Sdim#define TI_JUMBO_RX_RING_CNT 256 398249423Sdim#define TI_MINI_RX_RING_CNT 1024 399249423Sdim#define TI_RETURN_RING_CNT 2048 400249423Sdim 401263508Sdim/* 402263508Sdim * Possible TX ring sizes. 403218893Sdim */ 404263508Sdim#define TI_TX_RING_CNT_128 128 405263508Sdim#define TI_TX_RING_BASE_128 0x3800 406218893Sdim 407263508Sdim#define TI_TX_RING_CNT_256 256 408263508Sdim#define TI_TX_RING_BASE_256 0x3000 409198092Srdivacky 410198092Srdivacky#define TI_TX_RING_CNT_512 512 411198092Srdivacky#define TI_TX_RING_BASE_512 0x2000 412198092Srdivacky 413208600Srdivacky#define TI_TX_RING_CNT TI_TX_RING_CNT_512 414198092Srdivacky#define TI_TX_RING_BASE TI_TX_RING_BASE_512 415263508Sdim 416263508Sdim/* 417263508Sdim * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 418193326Sed * is limited to 2MB total, and in general I think most adapters have 419263508Sdim * around 1MB. We use this value for zeroing the NIC's SRAM, so to 420226633Sdim * be safe we use the largest possible value (zeroing memory that 421212904Sdim * isn't there doesn't hurt anything). 422249423Sdim */ 423193326Sed#define TI_MEM_MAX 0x7FFFFF 424193326Sed 425218893Sdim/* 426234353Sdim * Even on the alpha, pci addresses are 32-bit quantities 427234353Sdim */ 428263508Sdim 429263508Sdim#ifdef __64_bit_pci_addressing__ 430263508Sdimtypedef struct { 431218893Sdim u_int64_t ti_addr; 432218893Sdim} ti_hostaddr; 433218893Sdim#define TI_HOSTADDR(x) x.ti_addr 434249423Sdim#else 435249423Sdimtypedef struct { 436218893Sdim u_int32_t ti_addr_hi; 437218893Sdim u_int32_t ti_addr_lo; 438218893Sdim} ti_hostaddr; 439218893Sdim#define TI_HOSTADDR(x) x.ti_addr_lo 440208600Srdivacky#endif 441198092Srdivacky 442263508Sdim/* 443263508Sdim * Ring control block structure. The rules for the max_len field 444198092Srdivacky * are as follows: 445249423Sdim * 446249423Sdim * For the send ring, max_len indicates the number of entries in the 447249423Sdim * ring (128, 256 or 512). 448198092Srdivacky * 449198092Srdivacky * For the standard receive ring, max_len indicates the threshold 450234353Sdim * used to decide when a frame should be put in the jumbo receive ring 451234353Sdim * instead of the standard one. 452263508Sdim * 453263508Sdim * For the mini ring, max_len indicates the size of the buffers in the 454234353Sdim * ring. This is the value used to decide when a frame is small enough 455249423Sdim * to be placed in the mini ring. 456249423Sdim * 457249423Sdim * For the return receive ring, max_len indicates the number of entries 458249423Sdim * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 459234353Sdim * 2048 for backwards compatibility). The value 1024 can only be used 460234353Sdim * if the mini ring is disabled. 461234353Sdim */ 462234353Sdimstruct ti_rcb { 463218893Sdim ti_hostaddr ti_hostaddr; 464195341Sed#if BYTE_ORDER == BIG_ENDIAN 465263508Sdim u_int16_t ti_max_len; 466263508Sdim u_int16_t ti_flags; 467195341Sed#else 468239462Sdim u_int16_t ti_flags; 469234353Sdim u_int16_t ti_max_len; 470263508Sdim#endif 471234353Sdim u_int32_t ti_unused; 472263508Sdim}; 473263508Sdim 474263508Sdim#define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 475263508Sdim#define TI_RCB_FLAG_IP_CKSUM 0x00000002 476249423Sdim#define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 477249423Sdim#define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 478249423Sdim#define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 479195341Sed#define TI_RCB_FLAG_HOST_RING 0x00000040 480195341Sed#define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 481239462Sdim#define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 482239462Sdim#define TI_RCB_FLAG_RING_DISABLED 0x00000200 483263508Sdim 484263508Sdimstruct ti_producer { 485239462Sdim u_int32_t ti_idx; 486239462Sdim u_int32_t ti_unused; 487239462Sdim}; 488239462Sdim 489239462Sdim/* 490263508Sdim * Tigon statistics counters. 491263508Sdim */ 492263508Sdimstruct ti_stats { 493263508Sdim /* 494263508Sdim * MAC stats, taken from RFC 1643, ethernet-like MIB 495239462Sdim */ 496239462Sdim volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 497239462Sdim volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 498249423Sdim volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 499249423Sdim volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 500249423Sdim volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 501249423Sdim volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 502239462Sdim volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 503239462Sdim volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 504218893Sdim volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 505193326Sed volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 506263508Sdim volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 507263508Sdim volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 508263508Sdim /* 509193326Sed * interface stats, taken from RFC 1213, MIB-II, interfaces group 510239462Sdim */ 511234353Sdim volatile u_int32_t ifIndex; /* 12 */ 512234353Sdim volatile u_int32_t ifType; /* 13 */ 513263508Sdim volatile u_int32_t ifMtu; /* 14 */ 514263508Sdim volatile u_int32_t ifSpeed; /* 15 */ 515263508Sdim volatile u_int32_t ifAdminStatus; /* 16 */ 516263508Sdim#define IF_ADMIN_STATUS_UP 1 517263508Sdim#define IF_ADMIN_STATUS_DOWN 2 518263508Sdim#define IF_ADMIN_STATUS_TESTING 3 519263508Sdim volatile u_int32_t ifOperStatus; /* 17 */ 520263508Sdim#define IF_OPER_STATUS_UP 1 521263508Sdim#define IF_OPER_STATUS_DOWN 2 522263508Sdim#define IF_OPER_STATUS_TESTING 3 523255321Stheraven#define IF_OPER_STATUS_UNKNOWN 4 524244640Sandrew#define IF_OPER_STATUS_DORMANT 5 525249423Sdim volatile u_int32_t ifLastChange; /* 18 */ 526249423Sdim volatile u_int32_t ifInDiscards; /* 19 */ 527249423Sdim volatile u_int32_t ifInErrors; /* 20 */ 528193326Sed volatile u_int32_t ifInUnknownProtos; /* 21 */ 529193326Sed volatile u_int32_t ifOutDiscards; /* 22 */ 530218893Sdim volatile u_int32_t ifOutErrors; /* 23 */ 531218893Sdim volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 532263508Sdim volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 533263508Sdim volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 534218893Sdim u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 535239462Sdim /* 536234353Sdim * more interface stats, taken from RFC 1573, MIB-IIupdate, 537234353Sdim * interfaces group 538263508Sdim */ 539251662Sdim volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 540263508Sdim volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 541263508Sdim volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 542263508Sdim volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 543263508Sdim volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 544263508Sdim volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 545263508Sdim volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 546263508Sdim volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 547263508Sdim volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 548263508Sdim volatile u_int32_t ifHighSpeed; /* 53 */ 549263508Sdim volatile u_int32_t ifPromiscuousMode; /* 54 */ 550263508Sdim volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 551251662Sdim /* 552249423Sdim * Host Commands 553249423Sdim */ 554249423Sdim volatile u_int32_t nicCmdsHostState; /* 56 */ 555218893Sdim volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 556218893Sdim volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 557234353Sdim volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 558210299Sed volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 559263508Sdim volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 560263508Sdim volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 561210299Sed volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 562249423Sdim volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 563249423Sdim volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 564249423Sdim volatile u_int32_t nicCmdsClearProfile; /* 66 */ 565210299Sed volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 566210299Sed volatile u_int32_t nicCmdsClearStats; /* 68 */ 567218893Sdim volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 568193326Sed volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 569263508Sdim volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 570263508Sdim volatile u_int32_t nicCmdsUnknown; /* 72 */ 571193326Sed /* 572239462Sdim * NIC Events 573239462Sdim */ 574249423Sdim volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 575249423Sdim volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 576249423Sdim volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 577193326Sed volatile u_int32_t nicEventsError; /* 76 */ 578193326Sed volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 579218893Sdim volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 580193326Sed /* 581263508Sdim * Ring manipulation 582263508Sdim */ 583212904Sdim volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 584218893Sdim volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 585218893Sdim volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 586263508Sdim /* 587263508Sdim * Interrupts 588263508Sdim */ 589263508Sdim volatile u_int32_t nicInterrupts; /* 82 */ 590263508Sdim volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 591263508Sdim /* 592251662Sdim * BD Coalessing Thresholds 593228379Sdim */ 594218893Sdim volatile u_int32_t nicEventThresholdHit; /* 84 */ 595218893Sdim volatile u_int32_t nicSendThresholdHit; /* 85 */ 596234353Sdim volatile u_int32_t nicRecvThresholdHit; /* 86 */ 597249423Sdim /* 598249423Sdim * DMA Attentions 599249423Sdim */ 600249423Sdim volatile u_int32_t nicDmaRdOverrun; /* 87 */ 601234353Sdim volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 602249423Sdim volatile u_int32_t nicDmaWrOverrun; /* 89 */ 603249423Sdim volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 604263508Sdim volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 605263508Sdim volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 606263508Sdim /* 607263508Sdim * NIC Resources 608234353Sdim */ 609263508Sdim volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 610263508Sdim volatile u_int32_t nicDmaReadRingFull; /* 94 */ 611251662Sdim volatile u_int32_t nicEventRingFull; /* 95 */ 612263508Sdim volatile u_int32_t nicEventProducerRingFull; /* 96 */ 613193326Sed volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 614193326Sed volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 615249423Sdim volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 616249423Sdim volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 617249423Sdim volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 618249423Sdim volatile u_int32_t nicSendBDs; /* current count 102 */ 619249423Sdim volatile u_int32_t nicRecvBDs; /* current count 103 */ 620193326Sed volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 621249423Sdim volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 622249423Sdim volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 623263508Sdim volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 624249423Sdim volatile u_int32_t nicJumboSpillOver; /* 108 */ 625249423Sdim volatile u_int32_t nicSbusHangCleared; /* 109 */ 626263508Sdim volatile u_int32_t nicEnqEventDelayed; /* 110 */ 627263508Sdim /* 628263508Sdim * Stats from MAC rx completion 629263508Sdim */ 630263508Sdim volatile u_int32_t nicMacRxLateColls; /* 111 */ 631263508Sdim volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 632263508Sdim volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 633249423Sdim volatile u_int32_t nicMacRxMacAbort; /* 114 */ 634249423Sdim volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 635249423Sdim /* 636249423Sdim * Stats from the mac_stats area 637249423Sdim */ 638263508Sdim volatile u_int32_t nicMacRxDropUla; /* 116 */ 639249423Sdim volatile u_int32_t nicMacRxDropMcast; /* 117 */ 640249423Sdim volatile u_int32_t nicMacRxFlowControl; /* 118 */ 641204793Srdivacky volatile u_int32_t nicMacRxDropSpace; /* 119 */ 642204793Srdivacky volatile u_int32_t nicMacRxColls; /* 120 */ 643208600Srdivacky /* 644204793Srdivacky * MAC RX Attentions 645263508Sdim */ 646263508Sdim volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 647204793Srdivacky volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 648204793Srdivacky volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 649204793Srdivacky volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 650243830Sdim volatile u_int32_t nicMacReset; /* 125 */ 651251662Sdim volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 652243830Sdim volatile u_int32_t nicMacRxBufAttns; /* 127 */ 653204793Srdivacky volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 654204793Srdivacky volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 655212904Sdim volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 656212904Sdim volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 657263508Sdim volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 658263508Sdim /* 659212904Sdim * Stats from the mac_stats area 660212904Sdim */ 661212904Sdim volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 662243830Sdim /* 663251662Sdim * MAC TX Attentions 664243830Sdim */ 665228379Sdim volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 666263508Sdim /* 667263508Sdim * NIC Profile 668263508Sdim */ 669263508Sdim volatile u_int32_t nicProfile[32]; /* 135 */ 670263508Sdim /* 671263508Sdim * Pat to 1024 bytes. 672263508Sdim */ 673249423Sdim u_int32_t pad[75]; 674249423Sdim}; 675249423Sdim/* 676212904Sdim * Tigon general information block. This resides in host memory 677212904Sdim * and contains the status counters, ring control blocks and 678263508Sdim * producer pointers. 679263508Sdim */ 680263508Sdim 681263508Sdimstruct ti_gib { 682263508Sdim struct ti_stats ti_stats; 683263508Sdim struct ti_rcb ti_ev_rcb; 684263508Sdim struct ti_rcb ti_cmd_rcb; 685263508Sdim struct ti_rcb ti_tx_rcb; 686263508Sdim struct ti_rcb ti_std_rx_rcb; 687263508Sdim struct ti_rcb ti_jumbo_rx_rcb; 688263508Sdim struct ti_rcb ti_mini_rx_rcb; 689263508Sdim struct ti_rcb ti_return_rcb; 690263508Sdim ti_hostaddr ti_ev_prodidx_ptr; 691263508Sdim ti_hostaddr ti_return_prodidx_ptr; 692263508Sdim ti_hostaddr ti_tx_considx_ptr; 693263508Sdim ti_hostaddr ti_refresh_stats_ptr; 694263508Sdim}; 695263508Sdim 696263508Sdim/* 697263508Sdim * Buffer descriptor structures. There are basically three types 698263508Sdim * of structures: normal receive descriptors, extended receive 699263508Sdim * descriptors and transmit descriptors. The extended receive 700263508Sdim * descriptors are optionally used only for the jumbo receive ring. 701263508Sdim */ 702193326Sed 703193326Sedstruct ti_rx_desc { 704193326Sed ti_hostaddr ti_addr; 705193326Sed#if BYTE_ORDER == BIG_ENDIAN 706193326Sed u_int16_t ti_idx; 707 u_int16_t ti_len; 708#else 709 u_int16_t ti_len; 710 u_int16_t ti_idx; 711#endif 712#if BYTE_ORDER == BIG_ENDIAN 713 u_int16_t ti_type; 714 u_int16_t ti_flags; 715#else 716 u_int16_t ti_flags; 717 u_int16_t ti_type; 718#endif 719#if BYTE_ORDER == BIG_ENDIAN 720 u_int16_t ti_ip_cksum; 721 u_int16_t ti_tcp_udp_cksum; 722#else 723 u_int16_t ti_tcp_udp_cksum; 724 u_int16_t ti_ip_cksum; 725#endif 726#if BYTE_ORDER == BIG_ENDIAN 727 u_int16_t ti_error_flags; 728 u_int16_t ti_vlan_tag; 729#else 730 u_int16_t ti_vlan_tag; 731 u_int16_t ti_error_flags; 732#endif 733 u_int32_t ti_rsvd; 734 u_int32_t ti_opaque; 735}; 736 737struct ti_rx_desc_ext { 738 ti_hostaddr ti_addr1; 739 ti_hostaddr ti_addr2; 740 ti_hostaddr ti_addr3; 741#if BYTE_ORDER == BIG_ENDIAN 742 u_int16_t ti_len1; 743 u_int16_t ti_len2; 744#else 745 u_int16_t ti_len2; 746 u_int16_t ti_len1; 747#endif 748#if BYTE_ORDER == BIG_ENDIAN 749 u_int16_t ti_len3; 750 u_int16_t ti_rsvd0; 751#else 752 u_int16_t ti_rsvd0; 753 u_int16_t ti_len3; 754#endif 755 ti_hostaddr ti_addr0; 756#if BYTE_ORDER == BIG_ENDIAN 757 u_int16_t ti_idx; 758 u_int16_t ti_len0; 759#else 760 u_int16_t ti_len0; 761 u_int16_t ti_idx; 762#endif 763#if BYTE_ORDER == BIG_ENDIAN 764 u_int16_t ti_type; 765 u_int16_t ti_flags; 766#else 767 u_int16_t ti_flags; 768 u_int16_t ti_type; 769#endif 770#if BYTE_ORDER == BIG_ENDIAN 771 u_int16_t ti_ip_cksum; 772 u_int16_t ti_tcp_udp_cksum; 773#else 774 u_int16_t ti_tcp_udp_cksum; 775 u_int16_t ti_ip_cksum; 776#endif 777#if BYTE_ORDER == BIG_ENDIAN 778 u_int16_t ti_error_flags; 779 u_int16_t ti_vlan_tag; 780#else 781 u_int16_t ti_vlan_tag; 782 u_int16_t ti_error_flags; 783#endif 784 u_int32_t ti_rsvd1; 785 u_int32_t ti_opaque; 786}; 787 788/* 789 * Transmit descriptors are, mercifully, very small. 790 */ 791struct ti_tx_desc { 792 ti_hostaddr ti_addr; 793#if BYTE_ORDER == BIG_ENDIAN 794 u_int16_t ti_len; 795 u_int16_t ti_flags; 796#else 797 u_int16_t ti_flags; 798 u_int16_t ti_len; 799#endif 800#if BYTE_ORDER == BIG_ENDIAN 801 u_int16_t ti_rsvd; 802 u_int16_t ti_vlan_tag; 803#else 804 u_int16_t ti_vlan_tag; 805 u_int16_t ti_rsvd; 806#endif 807}; 808 809/* 810 * NOTE! On the Alpha, we have an alignment constraint. 811 * The first thing in the packet is a 14-byte Ethernet header. 812 * This means that the packet is misaligned. To compensate, 813 * we actually offset the data 2 bytes into the cluster. This 814 * alignes the packet after the Ethernet header at a 32-bit 815 * boundary. 816 */ 817 818#define ETHER_ALIGN 2 819 820#define TI_FRAMELEN 1518 821#define TI_JUMBO_FRAMELEN 9018 822#define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 823#define TI_PAGE_SIZE PAGE_SIZE 824#define TI_MIN_FRAMELEN 60 825 826/* 827 * Buffer descriptor error flags. 828 */ 829#define TI_BDERR_CRC 0x0001 830#define TI_BDERR_COLLDETECT 0x0002 831#define TI_BDERR_LINKLOST 0x0004 832#define TI_BDERR_DECODE 0x0008 833#define TI_BDERR_ODD_NIBBLES 0x0010 834#define TI_BDERR_MAC_ABRT 0x0020 835#define TI_BDERR_RUNT 0x0040 836#define TI_BDERR_TRUNC 0x0080 837#define TI_BDERR_GIANT 0x0100 838 839/* 840 * Buffer descriptor flags. 841 */ 842#define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 843#define TI_BDFLAG_IP_CKSUM 0x0002 844#define TI_BDFLAG_END 0x0004 845#define TI_BDFLAG_MORE 0x0008 846#define TI_BDFLAG_JUMBO_RING 0x0010 847#define TI_BDFLAG_UCAST_PKT 0x0020 848#define TI_BDFLAG_MCAST_PKT 0x0040 849#define TI_BDFLAG_BCAST_PKT 0x0060 850#define TI_BDFLAG_IP_FRAG 0x0080 851#define TI_BDFLAG_IP_FRAG_END 0x0100 852#define TI_BDFLAG_VLAN_TAG 0x0200 853#define TI_BDFLAG_ERROR 0x0400 854#define TI_BDFLAG_COAL_NOW 0x0800 855#define TI_BDFLAG_MINI_RING 0x1000 856 857/* 858 * Descriptor type flags. I think these only have meaning for 859 * the Tigon 1. I had to extract them from the sample driver source 860 * since they aren't in the manual. 861 */ 862#define TI_BDTYPE_TYPE_NULL 0x0000 863#define TI_BDTYPE_SEND_BD 0x0001 864#define TI_BDTYPE_RECV_BD 0x0002 865#define TI_BDTYPE_RECV_JUMBO_BD 0x0003 866#define TI_BDTYPE_RECV_BD_LAST 0x0004 867#define TI_BDTYPE_SEND_DATA 0x0005 868#define TI_BDTYPE_SEND_DATA_LAST 0x0006 869#define TI_BDTYPE_RECV_DATA 0x0007 870#define TI_BDTYPE_RECV_DATA_LAST 0x000b 871#define TI_BDTYPE_EVENT_RUPT 0x000c 872#define TI_BDTYPE_EVENT_NO_RUPT 0x000d 873#define TI_BDTYPE_ODD_START 0x000e 874#define TI_BDTYPE_UPDATE_STATS 0x000f 875#define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 876#define TI_BDTYPE_EVENT_PROD 0x0011 877#define TI_BDTYPE_TX_CONS 0x0012 878#define TI_BDTYPE_RX_PROD 0x0013 879#define TI_BDTYPE_REFRESH_STATS 0x0014 880#define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 881#define TI_BDTYPE_SEND_DATA_COAL 0x0016 882#define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 883#define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 884#define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 885 886/* 887 * Tigon command structure. 888 */ 889struct ti_cmd_desc { 890#if BYTE_ORDER == BIG_ENDIAN 891 u_int32_t ti_cmd:8; 892 u_int32_t ti_code:12; 893 u_int32_t ti_idx:12; 894#else 895 u_int32_t ti_idx:12; 896 u_int32_t ti_code:12; 897 u_int32_t ti_cmd:8; 898#endif 899}; 900 901#define TI_CMD_HOST_STATE 0x01 902#define TI_CMD_CODE_STACK_UP 0x01 903#define TI_CMD_CODE_STACK_DOWN 0x02 904 905/* 906 * This command enables software address filtering. It's a workaround 907 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 908 */ 909#define TI_CMD_FDR_FILTERING 0x02 910#define TI_CMD_CODE_FILT_ENB 0x01 911#define TI_CMD_CODE_FILT_DIS 0x02 912 913#define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 914#define TI_CMD_UPDATE_GENCOM 0x04 915#define TI_CMD_RESET_JUMBO_RING 0x05 916#define TI_CMD_SET_PARTIAL_RX_CNT 0x06 917#define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 918#define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 919 920#define TI_CMD_SET_PROMISC_MODE 0x0A 921#define TI_CMD_CODE_PROMISC_ENB 0x01 922#define TI_CMD_CODE_PROMISC_DIS 0x02 923 924#define TI_CMD_LINK_NEGOTIATION 0x0B 925#define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 926#define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 927#define TI_CMD_CODE_NEGOTIATE_10_100 0x02 928 929#define TI_CMD_SET_MAC_ADDR 0x0C 930#define TI_CMD_CLR_PROFILE 0x0D 931 932#define TI_CMD_SET_ALLMULTI 0x0E 933#define TI_CMD_CODE_ALLMULTI_ENB 0x01 934#define TI_CMD_CODE_ALLMULTI_DIS 0x02 935 936#define TI_CMD_CLR_STATS 0x0F 937#define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 938#define TI_CMD_RFRSH_STATS 0x11 939 940#define TI_CMD_EXT_ADD_MCAST 0x12 941#define TI_CMD_EXT_DEL_MCAST 0x13 942 943/* 944 * Utility macros to make issuing commands a little simpler. Assumes 945 * that 'sc' and 'cmd' are in local scope. 946 */ 947#define TI_DO_CMD(x, y, z) \ 948 cmd.ti_cmd = x; \ 949 cmd.ti_code = y; \ 950 cmd.ti_idx = z; \ 951 ti_cmd(sc, &cmd); 952 953#define TI_DO_CMD_EXT(x, y, z, v, w) \ 954 cmd.ti_cmd = x; \ 955 cmd.ti_code = y; \ 956 cmd.ti_idx = z; \ 957 ti_cmd_ext(sc, &cmd, v, w); 958 959/* 960 * Other utility macros. 961 */ 962#define TI_INC(x, y) (x) = (x + 1) % y 963 964#define TI_UPDATE_JUMBOPROD(x, y) \ 965 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 966 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \ 967 } else { \ 968 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 969 } 970 971#define TI_UPDATE_MINIPROD(x, y) \ 972 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); 973 974#define TI_UPDATE_STDPROD(x, y) \ 975 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 976 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \ 977 } else { \ 978 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 979 } 980 981 982/* 983 * Tigon event structure. 984 */ 985struct ti_event_desc { 986#if BYTE_ORDER == BIG_ENDIAN 987 u_int32_t ti_event:8; 988 u_int32_t ti_code:12; 989 u_int32_t ti_idx:12; 990#else 991 u_int32_t ti_idx:12; 992 u_int32_t ti_code:12; 993 u_int32_t ti_event:8; 994#endif 995 u_int32_t ti_rsvd; 996}; 997 998/* 999 * Tigon events. 1000 */ 1001#define TI_EV_FIRMWARE_UP 0x01 1002#define TI_EV_STATS_UPDATED 0x04 1003 1004#define TI_EV_LINKSTAT_CHANGED 0x06 1005#define TI_EV_CODE_GIG_LINK_UP 0x01 1006#define TI_EV_CODE_LINK_DOWN 0x02 1007#define TI_EV_CODE_LINK_UP 0x03 1008 1009#define TI_EV_ERROR 0x07 1010#define TI_EV_CODE_ERR_INVAL_CMD 0x01 1011#define TI_EV_CODE_ERR_UNIMP_CMD 0x02 1012#define TI_EV_CODE_ERR_BADCFG 0x03 1013 1014#define TI_EV_MCAST_UPDATED 0x08 1015#define TI_EV_CODE_MCAST_ADD 0x01 1016#define TI_EV_CODE_MCAST_DEL 0x02 1017 1018#define TI_EV_RESET_JUMBO_RING 0x09 1019/* 1020 * Register access macros. The Tigon always uses memory mapped register 1021 * accesses and all registers must be accessed with 32 bit operations. 1022 */ 1023 1024#define CSR_WRITE_4(sc, reg, val) \ 1025 bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val) 1026 1027#define CSR_READ_4(sc, reg) \ 1028 bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg) 1029 1030#define TI_SETBIT(sc, reg, x) \ 1031 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 1032#define TI_CLRBIT(sc, reg, x) \ 1033 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 1034 1035/* 1036 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 1037 * values are tuneable. They control the actual amount of buffers 1038 * allocated for the standard, mini and jumbo receive rings. 1039 */ 1040 1041#define TI_SSLOTS 256 1042#define TI_MSLOTS 256 1043#define TI_JSLOTS 384 1044 1045#define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN) 1046#define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1047 (TI_JRAWLEN % sizeof(u_int64_t)))) 1048#define TI_JPAGESZ PAGE_SIZE 1049#define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1050#define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1051 1052/* 1053 * Ring structures. Most of these reside in host memory and we tell 1054 * the NIC where they are via the ring control blocks. The exceptions 1055 * are the tx and command rings, which live in NIC memory and which 1056 * we access via the shared memory window. 1057 */ 1058struct ti_ring_data { 1059 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; 1060 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 1061 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1062 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1063 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1064 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1065 /* 1066 * Make sure producer structures are aligned on 32-byte cache 1067 * line boundaries. 1068 */ 1069 struct ti_producer ti_ev_prodidx_r; 1070 u_int32_t ti_pad0[6]; 1071 struct ti_producer ti_return_prodidx_r; 1072 u_int32_t ti_pad1[6]; 1073 struct ti_producer ti_tx_considx_r; 1074 u_int32_t ti_pad2[6]; 1075 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */ 1076 struct ti_cmd_desc *ti_cmd_ring; /* pointer to shared mem */ 1077 struct ti_gib ti_info; 1078}; 1079 1080/* 1081 * Mbuf pointers. We need these to keep track of the virtual addresses 1082 * of our mbuf chains since we can only convert from physical to virtual, 1083 * not the other way around. 1084 */ 1085struct ti_chain_data { 1086 struct mbuf *ti_tx_chain[TI_TX_RING_CNT]; 1087 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 1088 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 1089 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 1090 /* Stick the jumbo mem management stuff here too. */ 1091 caddr_t ti_jslots[TI_JSLOTS]; 1092 void *ti_jumbo_buf; 1093}; 1094 1095struct ti_type { 1096 u_int16_t ti_vid; 1097 u_int16_t ti_did; 1098 char *ti_name; 1099}; 1100 1101#define TI_HWREV_TIGON 0x01 1102#define TI_HWREV_TIGON_II 0x02 1103#define TI_TIMEOUT 1000 1104#define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1105 1106struct ti_mc_entry { 1107 struct ether_addr mc_addr; 1108 SLIST_ENTRY(ti_mc_entry) mc_entries; 1109}; 1110 1111struct ti_jpool_entry { 1112 int slot; 1113 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1114}; 1115 1116struct ti_softc { 1117 struct arpcom arpcom; /* interface info */ 1118 bus_space_handle_t ti_bhandle; 1119 vm_offset_t ti_vhandle; 1120 bus_space_tag_t ti_btag; 1121 void *ti_intrhand; 1122 struct resource *ti_irq; 1123 struct resource *ti_res; 1124 struct ifmedia ifmedia; /* media info */ 1125 u_int8_t ti_unit; /* interface number */ 1126 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1127 u_int8_t ti_copper; /* 1000baseTX card */ 1128 u_int8_t ti_linkstat; /* Link state */ 1129 struct ti_ring_data *ti_rdata; /* rings */ 1130 struct ti_chain_data ti_cdata; /* mbufs */ 1131#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1132#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1133#define ti_tx_considx ti_rdata->ti_tx_considx_r 1134 u_int16_t ti_tx_saved_considx; 1135 u_int16_t ti_rx_saved_considx; 1136 u_int16_t ti_ev_saved_considx; 1137 u_int16_t ti_cmd_saved_prodidx; 1138 u_int16_t ti_std; /* current std ring head */ 1139 u_int16_t ti_mini; /* current mini ring head */ 1140 u_int16_t ti_jumbo; /* current jumo ring head */ 1141 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1142 SLIST_HEAD(__ti_jfreehead, ti_jpool_entry) ti_jfree_listhead; 1143 SLIST_HEAD(__ti_jinusehead, ti_jpool_entry) ti_jinuse_listhead; 1144 u_int32_t ti_stat_ticks; 1145 u_int32_t ti_rx_coal_ticks; 1146 u_int32_t ti_tx_coal_ticks; 1147 u_int32_t ti_rx_max_coal_bds; 1148 u_int32_t ti_tx_max_coal_bds; 1149 u_int32_t ti_tx_buf_ratio; 1150 int ti_if_flags; 1151 int ti_txcnt; 1152 struct mtx ti_mtx; 1153}; 1154 1155#define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1156#define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 1157 1158/* 1159 * Microchip Technology 24Cxx EEPROM control bytes 1160 */ 1161#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1162#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1163 1164/* 1165 * Note that EEPROM_START leaves transmission enabled. 1166 */ 1167#define EEPROM_START \ 1168 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1169 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1170 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1171 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1172 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1173 1174/* 1175 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1176 * that no further data can be written to the EEPROM I/O pin. 1177 */ 1178#define EEPROM_STOP \ 1179 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1180 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1181 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1182 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1183 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1184 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1185 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1186 1187 1188#ifdef __alpha__ 1189#undef vtophys 1190#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1191#endif 1192