if_tireg.h revision 63699
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 63699 2000-07-20 22:24:43Z wpaul $ 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. 41 * The first group of registers are actually copies of the PCI 42 * configuration space registers. 43 */ 44 45#define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46#define TI_PCI_CMDSTAT 0x004 47#define TI_PCI_CLASSCODE 0x008 48#define TI_PCI_BIST 0x00C 49#define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50#define TI_PCI_SUBSYS 0x02C 51#define TI_PCI_ROMBASE 0x030 52#define TI_PCI_INT 0x03C 53 54#ifndef PCIM_CMD_MWIEN 55#define PCIM_CMD_MWIEN 0x0010 56#endif 57 58/* 59 * Alteon AceNIC PCI vendor/device ID. 60 */ 61#define ALT_VENDORID 0x12AE 62#define ALT_DEVICEID_ACENIC 0x0001 63#define ALT_DEVICEID_ACENIC_COPPER 0x0002 64 65/* 66 * 3Com 3c985 PCI vendor/device ID. 67 */ 68#define TC_VENDORID 0x10B7 69#define TC_DEVICEID_3C985 0x0001 70 71/* 72 * Netgear GA620 PCI vendor/device ID. 73 */ 74#define NG_VENDORID 0x1385 75#define NG_DEVICEID_GA620 0x620A 76 77/* 78 * SGI device/vendor ID. 79 */ 80#define SGI_VENDORID 0x10A9 81#define SGI_DEVICEID_TIGON 0x0009 82 83/* 84 * DEC vendor ID, Farallon device ID. Apparently, Farallon used 85 * the DEC vendor ID in their cards by mistake. 86 */ 87#define DEC_VENDORID 0x1011 88#define DEC_DEVICEID_FARALLON_PN9000SX 0x001a 89 90/* 91 * Tigon configuration and control registers. 92 */ 93#define TI_MISC_HOST_CTL 0x040 94#define TI_MISC_LOCAL_CTL 0x044 95#define TI_SEM_AB 0x048 /* Tigon 2 only */ 96#define TI_MISC_CONF 0x050 /* Tigon 2 only */ 97#define TI_TIMER_BITS 0x054 98#define TI_TIMERREF 0x058 99#define TI_PCI_STATE 0x05C 100#define TI_MAIN_EVENT_A 0x060 101#define TI_MAILBOX_EVENT_A 0x064 102#define TI_WINBASE 0x068 103#define TI_WINDATA 0x06C 104#define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 105#define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 106#define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 107#define TI_SERIAL 0x07C 108 109/* 110 * Misc host control bits. 111 */ 112#define TI_MHC_INTSTATE 0x00000001 113#define TI_MHC_CLEARINT 0x00000002 114#define TI_MHC_RESET 0x00000008 115#define TI_MHC_BYTE_SWAP_ENB 0x00000010 116#define TI_MHC_WORD_SWAP_ENB 0x00000020 117#define TI_MHC_MASK_INTS 0x00000040 118#define TI_MHC_CHIP_REV_MASK 0xF0000000 119 120#define TI_MHC_BIGENDIAN_INIT \ 121 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 122 123#define TI_MHC_LITTLEENDIAN_INIT \ 124 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 125 126/* 127 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 128 * Rev 5 is also the Tigon 2, but is a broken version which was never 129 * used in any actual hardware, so we ignore it. 130 */ 131#define TI_REV_TIGON_I 0x40000000 132#define TI_REV_TIGON_II 0x60000000 133 134/* 135 * Firmware revision that we want. 136 */ 137#define TI_FIRMWARE_MAJOR 0xc 138#define TI_FIRMWARE_MINOR 0x4 139#define TI_FIRMWARE_FIX 0xd 140 141/* 142 * Miscelaneous Local Control register. 143 */ 144#define TI_MLC_EE_WRITE_ENB 0x00000010 145#define TI_MLC_SRAM_BANK_256K 0x00000200 146#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147#define TI_MLC_LOCALADDR_21 0x00004000 148#define TI_MLC_LOCALADDR_22 0x00008000 149#define TI_MLC_SBUS_WRITEERR 0x00080000 150#define TI_MLC_EE_CLK 0x00100000 151#define TI_MLC_EE_TXEN 0x00200000 152#define TI_MLC_EE_DOUT 0x00400000 153#define TI_MLC_EE_DIN 0x00800000 154 155/* 156 * Offset of MAC address inside EEPROM. 157 */ 158#define TI_EE_MAC_OFFSET 0x8c 159 160#define TI_DMA_ASSIST 0x11C 161#define TI_CPU_STATE 0x140 162#define TI_CPU_PROGRAM_COUNTER 0x144 163#define TI_SRAM_ADDR 0x154 164#define TI_SRAM_DATA 0x158 165#define TI_GEN_0 0x180 166#define TI_GEN_X 0x1FC 167#define TI_MAC_TX_STATE 0x200 168#define TI_MAC_RX_STATE 0x220 169#define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 170#define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 171#define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 172#define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 173#define TI_GEN_B_0 0x280 /* Tigon 2 only */ 174#define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 175 176/* 177 * Misc config register. 178 */ 179#define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 180 181/* 182 * PCI state register. 183 */ 184#define TI_PCISTATE_FORCE_RESET 0x00000001 185#define TI_PCISTATE_PROVIDE_LEN 0x00000002 186#define TI_PCISTATE_READ_MAXDMA 0x0000001C 187#define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 188#define TI_PCISTATE_MINDMA 0x0000FF00 189#define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 190#define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 191#define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 192#define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 193#define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 194#define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 195#define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 196#define TI_PCISTATE_READ_CMD 0x0F000000 197#define TI_PCISTATE_WRITE_CMD 0xF0000000 198 199#define TI_PCI_READMAX_4 0x04 200#define TI_PCI_READMAX_16 0x08 201#define TI_PCI_READMAX_32 0x0C 202#define TI_PCI_READMAX_64 0x10 203#define TI_PCI_READMAX_128 0x14 204#define TI_PCI_READMAX_256 0x18 205#define TI_PCI_READMAX_1024 0x1C 206 207#define TI_PCI_WRITEMAX_4 0x20 208#define TI_PCI_WRITEMAX_16 0x40 209#define TI_PCI_WRITEMAX_32 0x60 210#define TI_PCI_WRITEMAX_64 0x80 211#define TI_PCI_WRITEMAX_128 0xA0 212#define TI_PCI_WRITEMAX_256 0xC0 213#define TI_PCI_WRITEMAX_1024 0xE0 214 215#define TI_PCI_READ_CMD 0x06000000 216#define TI_PCI_WRITE_CMD 0x70000000 217 218/* 219 * DMA state register. 220 */ 221#define TI_DMASTATE_ENABLE 0x00000001 222#define TI_DMASTATE_PAUSE 0x00000002 223 224/* 225 * CPU state register. 226 */ 227#define TI_CPUSTATE_RESET 0x00000001 228#define TI_CPUSTATE_STEP 0x00000002 229#define TI_CPUSTATE_ROMFAIL 0x00000010 230#define TI_CPUSTATE_HALT 0x00010000 231/* 232 * MAC TX state register 233 */ 234#define TI_TXSTATE_RESET 0x00000001 235#define TI_TXSTATE_ENB 0x00000002 236#define TI_TXSTATE_STOP 0x00000004 237 238/* 239 * MAC RX state register 240 */ 241#define TI_RXSTATE_RESET 0x00000001 242#define TI_RXSTATE_ENB 0x00000002 243#define TI_RXSTATE_STOP 0x00000004 244 245/* 246 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 247 * split into 64 bit registers. Only the lower 32 bits of each mailbox 248 * are used. 249 */ 250#define TI_MB_HOSTINTR_HI 0x500 251#define TI_MB_HOSTINTR_LO 0x504 252#define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 253#define TI_MB_CMDPROD_IDX_HI 0x508 254#define TI_MB_CMDPROD_IDX_LO 0x50C 255#define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 256#define TI_MB_SENDPROD_IDX_HI 0x510 257#define TI_MB_SENDPROD_IDX_LO 0x514 258#define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 259#define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 260#define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 261#define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 262#define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 263#define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 264#define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 265#define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 266#define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 267#define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 268#define TI_MB_RSVD 0x530 269 270/* 271 * Tigon 2 general communication registers. These are 64 and 32 bit 272 * registers which are only valid after the firmware has been 273 * loaded and started. They actually exist in NIC memory but are 274 * mapped into the host memory via the shared memory region. 275 * 276 * The NIC internally maps these registers starting at address 0, 277 * so to determine the NIC address of any of these registers, we 278 * subtract 0x600 (the address of the first register). 279 */ 280 281#define TI_GCR_BASE 0x600 282#define TI_GCR_MACADDR 0x600 283#define TI_GCR_PAR0 0x600 284#define TI_GCR_PAR1 0x604 285#define TI_GCR_GENINFO_HI 0x608 286#define TI_GCR_GENINFO_LO 0x60C 287#define TI_GCR_MCASTADDR 0x610 /* obsolete */ 288#define TI_GCR_MAR0 0x610 /* obsolete */ 289#define TI_GCR_MAR1 0x614 /* obsolete */ 290#define TI_GCR_OPMODE 0x618 291#define TI_GCR_DMA_READCFG 0x61C 292#define TI_GCR_DMA_WRITECFG 0x620 293#define TI_GCR_TX_BUFFER_RATIO 0x624 294#define TI_GCR_EVENTCONS_IDX 0x628 295#define TI_GCR_CMDCONS_IDX 0x62C 296#define TI_GCR_TUNEPARMS 0x630 297#define TI_GCR_RX_COAL_TICKS 0x630 298#define TI_GCR_TX_COAL_TICKS 0x634 299#define TI_GCR_STAT_TICKS 0x638 300#define TI_GCR_TX_MAX_COAL_BD 0x63C 301#define TI_GCR_RX_MAX_COAL_BD 0x640 302#define TI_GCR_NIC_TRACING 0x644 303#define TI_GCR_GLINK 0x648 304#define TI_GCR_LINK 0x64C 305#define TI_GCR_NICTRACE_PTR 0x650 306#define TI_GCR_NICTRACE_START 0x654 307#define TI_GCR_NICTRACE_LEN 0x658 308#define TI_GCR_IFINDEX 0x65C 309#define TI_GCR_IFMTU 0x660 310#define TI_GCR_MASK_INTRS 0x664 311#define TI_GCR_GLINK_STAT 0x668 312#define TI_GCR_LINK_STAT 0x66C 313#define TI_GCR_RXRETURNCONS_IDX 0x680 314#define TI_GCR_CMDRING 0x700 315 316#define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE); 317 318/* 319 * Local memory window. The local memory window is a 2K shared 320 * memory region which can be used to access the NIC's internal 321 * SRAM. The window can be mapped to a given 2K region using 322 * the TI_WINDOW_BASE register. 323 */ 324#define TI_WINDOW 0x800 325#define TI_WINLEN 0x800 326 327#define TI_TICKS_PER_SEC 1000000 328 329/* 330 * Operation mode register. 331 */ 332#define TI_OPMODE_BYTESWAP_BD 0x00000002 333#define TI_OPMODE_WORDSWAP_BD 0x00000004 334#define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */ 335#define TI_OPMODE_BYTESWAP_DATA 0x00000010 336#define TI_OPMODE_1_DMA_ACTIVE 0x00000040 337#define TI_OPMODE_SBUS 0x00000100 338#define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 339#define TI_OPMODE_INCLUDE_CRC 0x00000400 340#define TI_OPMODE_RX_BADFRAMES 0x00000800 341#define TI_OPMODE_NO_EVENT_INTRS 0x00001000 342#define TI_OPMODE_NO_TX_INTRS 0x00002000 343#define TI_OPMODE_NO_RX_INTRS 0x00004000 344#define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ 345 346/* 347 * DMA configuration thresholds. 348 */ 349#define TI_DMA_STATE_THRESH_16W 0x00000100 350#define TI_DMA_STATE_THRESH_8W 0x00000080 351#define TI_DMA_STATE_THRESH_4W 0x00000040 352#define TI_DMA_STATE_THRESH_2W 0x00000020 353#define TI_DMA_STATE_THRESH_1W 0x00000010 354 355#define TI_DMA_STATE_FORCE_32_BIT 0x00000008 356 357/* 358 * Gigabit link status bits. 359 */ 360#define TI_GLNK_SENSE_NO_BEG 0x00002000 361#define TI_GLNK_LOOPBACK 0x00004000 362#define TI_GLNK_PREF 0x00008000 363#define TI_GLNK_1000MB 0x00040000 364#define TI_GLNK_FULL_DUPLEX 0x00080000 365#define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 366#define TI_GLNK_RX_FLOWCTL_Y 0x00800000 367#define TI_GLNK_AUTONEGENB 0x20000000 368#define TI_GLNK_ENB 0x40000000 369 370/* 371 * Link status bits. 372 */ 373#define TI_LNK_LOOPBACK 0x00004000 374#define TI_LNK_PREF 0x00008000 375#define TI_LNK_10MB 0x00010000 376#define TI_LNK_100MB 0x00020000 377#define TI_LNK_1000MB 0x00040000 378#define TI_LNK_FULL_DUPLEX 0x00080000 379#define TI_LNK_HALF_DUPLEX 0x00100000 380#define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 381#define TI_LNK_RX_FLOWCTL_Y 0x00800000 382#define TI_LNK_AUTONEGENB 0x20000000 383#define TI_LNK_ENB 0x40000000 384 385/* 386 * Ring size constants. 387 */ 388#define TI_EVENT_RING_CNT 256 389#define TI_CMD_RING_CNT 64 390#define TI_STD_RX_RING_CNT 512 391#define TI_JUMBO_RX_RING_CNT 256 392#define TI_MINI_RX_RING_CNT 1024 393#define TI_RETURN_RING_CNT 2048 394 395/* 396 * Possible TX ring sizes. 397 */ 398#define TI_TX_RING_CNT_128 128 399#define TI_TX_RING_BASE_128 0x3800 400 401#define TI_TX_RING_CNT_256 256 402#define TI_TX_RING_BASE_256 0x3000 403 404#define TI_TX_RING_CNT_512 512 405#define TI_TX_RING_BASE_512 0x2000 406 407#define TI_TX_RING_CNT TI_TX_RING_CNT_512 408#define TI_TX_RING_BASE TI_TX_RING_BASE_512 409 410/* 411 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 412 * is limited to 2MB total, and in general I think most adapters have 413 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 414 * be safe we use the largest possible value (zeroing memory that 415 * isn't there doesn't hurt anything). 416 */ 417#define TI_MEM_MAX 0x7FFFFF 418 419/* 420 * Even on the alpha, pci addresses are 32-bit quantities 421 */ 422 423#ifdef __64_bit_pci_addressing__ 424typedef struct { 425 u_int64_t ti_addr; 426} ti_hostaddr; 427#define TI_HOSTADDR(x) x.ti_addr 428#else 429typedef struct { 430 u_int32_t ti_addr_hi; 431 u_int32_t ti_addr_lo; 432} ti_hostaddr; 433#define TI_HOSTADDR(x) x.ti_addr_lo 434#endif 435 436/* 437 * Ring control block structure. The rules for the max_len field 438 * are as follows: 439 * 440 * For the send ring, max_len indicates the number of entries in the 441 * ring (128, 256 or 512). 442 * 443 * For the standard receive ring, max_len indicates the threshold 444 * used to decide when a frame should be put in the jumbo receive ring 445 * instead of the standard one. 446 * 447 * For the mini ring, max_len indicates the size of the buffers in the 448 * ring. This is the value used to decide when a frame is small enough 449 * to be placed in the mini ring. 450 * 451 * For the return receive ring, max_len indicates the number of entries 452 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 453 * 2048 for backwards compatibility). The value 1024 can only be used 454 * if the mini ring is disabled. 455 */ 456struct ti_rcb { 457 ti_hostaddr ti_hostaddr; 458#if BYTE_ORDER == BIG_ENDIAN 459 u_int16_t ti_max_len; 460 u_int16_t ti_flags; 461#else 462 u_int16_t ti_flags; 463 u_int16_t ti_max_len; 464#endif 465 u_int32_t ti_unused; 466}; 467 468#define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 469#define TI_RCB_FLAG_IP_CKSUM 0x00000002 470#define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 471#define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 472#define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 473#define TI_RCB_FLAG_HOST_RING 0x00000040 474#define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 475#define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 476#define TI_RCB_FLAG_RING_DISABLED 0x00000200 477 478struct ti_producer { 479 u_int32_t ti_idx; 480 u_int32_t ti_unused; 481}; 482 483/* 484 * Tigon statistics counters. 485 */ 486struct ti_stats { 487 /* 488 * MAC stats, taken from RFC 1643, ethernet-like MIB 489 */ 490 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 491 volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 492 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 493 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 494 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 495 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 496 volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 497 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 498 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 499 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 500 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 501 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 502 /* 503 * interface stats, taken from RFC 1213, MIB-II, interfaces group 504 */ 505 volatile u_int32_t ifIndex; /* 12 */ 506 volatile u_int32_t ifType; /* 13 */ 507 volatile u_int32_t ifMtu; /* 14 */ 508 volatile u_int32_t ifSpeed; /* 15 */ 509 volatile u_int32_t ifAdminStatus; /* 16 */ 510#define IF_ADMIN_STATUS_UP 1 511#define IF_ADMIN_STATUS_DOWN 2 512#define IF_ADMIN_STATUS_TESTING 3 513 volatile u_int32_t ifOperStatus; /* 17 */ 514#define IF_OPER_STATUS_UP 1 515#define IF_OPER_STATUS_DOWN 2 516#define IF_OPER_STATUS_TESTING 3 517#define IF_OPER_STATUS_UNKNOWN 4 518#define IF_OPER_STATUS_DORMANT 5 519 volatile u_int32_t ifLastChange; /* 18 */ 520 volatile u_int32_t ifInDiscards; /* 19 */ 521 volatile u_int32_t ifInErrors; /* 20 */ 522 volatile u_int32_t ifInUnknownProtos; /* 21 */ 523 volatile u_int32_t ifOutDiscards; /* 22 */ 524 volatile u_int32_t ifOutErrors; /* 23 */ 525 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 526 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 527 volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 528 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 529 /* 530 * more interface stats, taken from RFC 1573, MIB-IIupdate, 531 * interfaces group 532 */ 533 volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 534 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 535 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 536 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 537 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 538 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 539 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 540 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 541 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 542 volatile u_int32_t ifHighSpeed; /* 53 */ 543 volatile u_int32_t ifPromiscuousMode; /* 54 */ 544 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 545 /* 546 * Host Commands 547 */ 548 volatile u_int32_t nicCmdsHostState; /* 56 */ 549 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 550 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 551 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 552 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 553 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 554 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 555 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 556 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 557 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 558 volatile u_int32_t nicCmdsClearProfile; /* 66 */ 559 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 560 volatile u_int32_t nicCmdsClearStats; /* 68 */ 561 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 562 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 563 volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 564 volatile u_int32_t nicCmdsUnknown; /* 72 */ 565 /* 566 * NIC Events 567 */ 568 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 569 volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 570 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 571 volatile u_int32_t nicEventsError; /* 76 */ 572 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 573 volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 574 /* 575 * Ring manipulation 576 */ 577 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 578 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 579 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 580 /* 581 * Interrupts 582 */ 583 volatile u_int32_t nicInterrupts; /* 82 */ 584 volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 585 /* 586 * BD Coalessing Thresholds 587 */ 588 volatile u_int32_t nicEventThresholdHit; /* 84 */ 589 volatile u_int32_t nicSendThresholdHit; /* 85 */ 590 volatile u_int32_t nicRecvThresholdHit; /* 86 */ 591 /* 592 * DMA Attentions 593 */ 594 volatile u_int32_t nicDmaRdOverrun; /* 87 */ 595 volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 596 volatile u_int32_t nicDmaWrOverrun; /* 89 */ 597 volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 598 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 599 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 600 /* 601 * NIC Resources 602 */ 603 volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 604 volatile u_int32_t nicDmaReadRingFull; /* 94 */ 605 volatile u_int32_t nicEventRingFull; /* 95 */ 606 volatile u_int32_t nicEventProducerRingFull; /* 96 */ 607 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 608 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 609 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 610 volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 611 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 612 volatile u_int32_t nicSendBDs; /* current count 102 */ 613 volatile u_int32_t nicRecvBDs; /* current count 103 */ 614 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 615 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 616 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 617 volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 618 volatile u_int32_t nicJumboSpillOver; /* 108 */ 619 volatile u_int32_t nicSbusHangCleared; /* 109 */ 620 volatile u_int32_t nicEnqEventDelayed; /* 110 */ 621 /* 622 * Stats from MAC rx completion 623 */ 624 volatile u_int32_t nicMacRxLateColls; /* 111 */ 625 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 626 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 627 volatile u_int32_t nicMacRxMacAbort; /* 114 */ 628 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 629 /* 630 * Stats from the mac_stats area 631 */ 632 volatile u_int32_t nicMacRxDropUla; /* 116 */ 633 volatile u_int32_t nicMacRxDropMcast; /* 117 */ 634 volatile u_int32_t nicMacRxFlowControl; /* 118 */ 635 volatile u_int32_t nicMacRxDropSpace; /* 119 */ 636 volatile u_int32_t nicMacRxColls; /* 120 */ 637 /* 638 * MAC RX Attentions 639 */ 640 volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 641 volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 642 volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 643 volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 644 volatile u_int32_t nicMacReset; /* 125 */ 645 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 646 volatile u_int32_t nicMacRxBufAttns; /* 127 */ 647 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 648 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 649 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 650 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 651 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 652 /* 653 * Stats from the mac_stats area 654 */ 655 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 656 /* 657 * MAC TX Attentions 658 */ 659 volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 660 /* 661 * NIC Profile 662 */ 663 volatile u_int32_t nicProfile[32]; /* 135 */ 664 /* 665 * Pat to 1024 bytes. 666 */ 667 u_int32_t pad[75]; 668}; 669/* 670 * Tigon general information block. This resides in host memory 671 * and contains the status counters, ring control blocks and 672 * producer pointers. 673 */ 674 675struct ti_gib { 676 struct ti_stats ti_stats; 677 struct ti_rcb ti_ev_rcb; 678 struct ti_rcb ti_cmd_rcb; 679 struct ti_rcb ti_tx_rcb; 680 struct ti_rcb ti_std_rx_rcb; 681 struct ti_rcb ti_jumbo_rx_rcb; 682 struct ti_rcb ti_mini_rx_rcb; 683 struct ti_rcb ti_return_rcb; 684 ti_hostaddr ti_ev_prodidx_ptr; 685 ti_hostaddr ti_return_prodidx_ptr; 686 ti_hostaddr ti_tx_considx_ptr; 687 ti_hostaddr ti_refresh_stats_ptr; 688}; 689 690/* 691 * Buffer descriptor structures. There are basically three types 692 * of structures: normal receive descriptors, extended receive 693 * descriptors and transmit descriptors. The extended receive 694 * descriptors are optionally used only for the jumbo receive ring. 695 */ 696 697struct ti_rx_desc { 698 ti_hostaddr ti_addr; 699#if BYTE_ORDER == BIG_ENDIAN 700 u_int16_t ti_idx; 701 u_int16_t ti_len; 702#else 703 u_int16_t ti_len; 704 u_int16_t ti_idx; 705#endif 706#if BYTE_ORDER == BIG_ENDIAN 707 u_int16_t ti_type; 708 u_int16_t ti_flags; 709#else 710 u_int16_t ti_flags; 711 u_int16_t ti_type; 712#endif 713#if BYTE_ORDER == BIG_ENDIAN 714 u_int16_t ti_ip_cksum; 715 u_int16_t ti_tcp_udp_cksum; 716#else 717 u_int16_t ti_tcp_udp_cksum; 718 u_int16_t ti_ip_cksum; 719#endif 720#if BYTE_ORDER == BIG_ENDIAN 721 u_int16_t ti_error_flags; 722 u_int16_t ti_vlan_tag; 723#else 724 u_int16_t ti_vlan_tag; 725 u_int16_t ti_error_flags; 726#endif 727 u_int32_t ti_rsvd; 728 u_int32_t ti_opaque; 729}; 730 731struct ti_rx_desc_ext { 732 ti_hostaddr ti_addr1; 733 ti_hostaddr ti_addr2; 734 ti_hostaddr ti_addr3; 735#if BYTE_ORDER == BIG_ENDIAN 736 u_int16_t ti_len1; 737 u_int16_t ti_len2; 738#else 739 u_int16_t ti_len2; 740 u_int16_t ti_len1; 741#endif 742#if BYTE_ORDER == BIG_ENDIAN 743 u_int16_t ti_len3; 744 u_int16_t ti_rsvd0; 745#else 746 u_int16_t ti_rsvd0; 747 u_int16_t ti_len3; 748#endif 749 ti_hostaddr ti_addr0; 750#if BYTE_ORDER == BIG_ENDIAN 751 u_int16_t ti_idx; 752 u_int16_t ti_len0; 753#else 754 u_int16_t ti_len0; 755 u_int16_t ti_idx; 756#endif 757#if BYTE_ORDER == BIG_ENDIAN 758 u_int16_t ti_type; 759 u_int16_t ti_flags; 760#else 761 u_int16_t ti_flags; 762 u_int16_t ti_type; 763#endif 764#if BYTE_ORDER == BIG_ENDIAN 765 u_int16_t ti_ip_cksum; 766 u_int16_t ti_tcp_udp_cksum; 767#else 768 u_int16_t ti_tcp_udp_cksum; 769 u_int16_t ti_ip_cksum; 770#endif 771#if BYTE_ORDER == BIG_ENDIAN 772 u_int16_t ti_error_flags; 773 u_int16_t ti_vlan_tag; 774#else 775 u_int16_t ti_vlan_tag; 776 u_int16_t ti_error_flags; 777#endif 778 u_int32_t ti_rsvd1; 779 u_int32_t ti_opaque; 780}; 781 782/* 783 * Transmit descriptors are, mercifully, very small. 784 */ 785struct ti_tx_desc { 786 ti_hostaddr ti_addr; 787#if BYTE_ORDER == BIG_ENDIAN 788 u_int16_t ti_len; 789 u_int16_t ti_flags; 790#else 791 u_int16_t ti_flags; 792 u_int16_t ti_len; 793#endif 794#if BYTE_ORDER == BIG_ENDIAN 795 u_int16_t ti_rsvd; 796 u_int16_t ti_vlan_tag; 797#else 798 u_int16_t ti_vlan_tag; 799 u_int16_t ti_rsvd; 800#endif 801}; 802 803/* 804 * NOTE! On the Alpha, we have an alignment constraint. 805 * The first thing in the packet is a 14-byte Ethernet header. 806 * This means that the packet is misaligned. To compensate, 807 * we actually offset the data 2 bytes into the cluster. This 808 * alignes the packet after the Ethernet header at a 32-bit 809 * boundary. 810 */ 811 812#define ETHER_ALIGN 2 813 814#define TI_FRAMELEN 1518 815#define TI_JUMBO_FRAMELEN 9018 816#define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 817#define TI_PAGE_SIZE PAGE_SIZE 818#define TI_MIN_FRAMELEN 60 819 820/* 821 * Buffer descriptor error flags. 822 */ 823#define TI_BDERR_CRC 0x0001 824#define TI_BDERR_COLLDETECT 0x0002 825#define TI_BDERR_LINKLOST 0x0004 826#define TI_BDERR_DECODE 0x0008 827#define TI_BDERR_ODD_NIBBLES 0x0010 828#define TI_BDERR_MAC_ABRT 0x0020 829#define TI_BDERR_RUNT 0x0040 830#define TI_BDERR_TRUNC 0x0080 831#define TI_BDERR_GIANT 0x0100 832 833/* 834 * Buffer descriptor flags. 835 */ 836#define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 837#define TI_BDFLAG_IP_CKSUM 0x0002 838#define TI_BDFLAG_END 0x0004 839#define TI_BDFLAG_MORE 0x0008 840#define TI_BDFLAG_JUMBO_RING 0x0010 841#define TI_BDFLAG_UCAST_PKT 0x0020 842#define TI_BDFLAG_MCAST_PKT 0x0040 843#define TI_BDFLAG_BCAST_PKT 0x0060 844#define TI_BDFLAG_IP_FRAG 0x0080 845#define TI_BDFLAG_IP_FRAG_END 0x0100 846#define TI_BDFLAG_VLAN_TAG 0x0200 847#define TI_BDFLAG_ERROR 0x0400 848#define TI_BDFLAG_COAL_NOW 0x0800 849#define TI_BDFLAG_MINI_RING 0x1000 850 851/* 852 * Descriptor type flags. I think these only have meaning for 853 * the Tigon 1. I had to extract them from the sample driver source 854 * since they aren't in the manual. 855 */ 856#define TI_BDTYPE_TYPE_NULL 0x0000 857#define TI_BDTYPE_SEND_BD 0x0001 858#define TI_BDTYPE_RECV_BD 0x0002 859#define TI_BDTYPE_RECV_JUMBO_BD 0x0003 860#define TI_BDTYPE_RECV_BD_LAST 0x0004 861#define TI_BDTYPE_SEND_DATA 0x0005 862#define TI_BDTYPE_SEND_DATA_LAST 0x0006 863#define TI_BDTYPE_RECV_DATA 0x0007 864#define TI_BDTYPE_RECV_DATA_LAST 0x000b 865#define TI_BDTYPE_EVENT_RUPT 0x000c 866#define TI_BDTYPE_EVENT_NO_RUPT 0x000d 867#define TI_BDTYPE_ODD_START 0x000e 868#define TI_BDTYPE_UPDATE_STATS 0x000f 869#define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 870#define TI_BDTYPE_EVENT_PROD 0x0011 871#define TI_BDTYPE_TX_CONS 0x0012 872#define TI_BDTYPE_RX_PROD 0x0013 873#define TI_BDTYPE_REFRESH_STATS 0x0014 874#define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 875#define TI_BDTYPE_SEND_DATA_COAL 0x0016 876#define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 877#define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 878#define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 879 880/* 881 * Tigon command structure. 882 */ 883struct ti_cmd_desc { 884#if BYTE_ORDER == BIG_ENDIAN 885 u_int32_t ti_cmd:8; 886 u_int32_t ti_code:12; 887 u_int32_t ti_idx:12; 888#else 889 u_int32_t ti_idx:12; 890 u_int32_t ti_code:12; 891 u_int32_t ti_cmd:8; 892#endif 893}; 894 895#define TI_CMD_HOST_STATE 0x01 896#define TI_CMD_CODE_STACK_UP 0x01 897#define TI_CMD_CODE_STACK_DOWN 0x02 898 899/* 900 * This command enables software address filtering. It's a workaround 901 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 902 */ 903#define TI_CMD_FDR_FILTERING 0x02 904#define TI_CMD_CODE_FILT_ENB 0x01 905#define TI_CMD_CODE_FILT_DIS 0x02 906 907#define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 908#define TI_CMD_UPDATE_GENCOM 0x04 909#define TI_CMD_RESET_JUMBO_RING 0x05 910#define TI_CMD_SET_PARTIAL_RX_CNT 0x06 911#define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 912#define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 913 914#define TI_CMD_SET_PROMISC_MODE 0x0A 915#define TI_CMD_CODE_PROMISC_ENB 0x01 916#define TI_CMD_CODE_PROMISC_DIS 0x02 917 918#define TI_CMD_LINK_NEGOTIATION 0x0B 919#define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 920#define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 921#define TI_CMD_CODE_NEGOTIATE_10_100 0x02 922 923#define TI_CMD_SET_MAC_ADDR 0x0C 924#define TI_CMD_CLR_PROFILE 0x0D 925 926#define TI_CMD_SET_ALLMULTI 0x0E 927#define TI_CMD_CODE_ALLMULTI_ENB 0x01 928#define TI_CMD_CODE_ALLMULTI_DIS 0x02 929 930#define TI_CMD_CLR_STATS 0x0F 931#define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 932#define TI_CMD_RFRSH_STATS 0x11 933 934#define TI_CMD_EXT_ADD_MCAST 0x12 935#define TI_CMD_EXT_DEL_MCAST 0x13 936 937/* 938 * Utility macros to make issuing commands a little simpler. Assumes 939 * that 'sc' and 'cmd' are in local scope. 940 */ 941#define TI_DO_CMD(x, y, z) \ 942 cmd.ti_cmd = x; \ 943 cmd.ti_code = y; \ 944 cmd.ti_idx = z; \ 945 ti_cmd(sc, &cmd); 946 947#define TI_DO_CMD_EXT(x, y, z, v, w) \ 948 cmd.ti_cmd = x; \ 949 cmd.ti_code = y; \ 950 cmd.ti_idx = z; \ 951 ti_cmd_ext(sc, &cmd, v, w); 952 953/* 954 * Other utility macros. 955 */ 956#define TI_INC(x, y) (x) = (x + 1) % y 957 958#define TI_UPDATE_JUMBOPROD(x, y) \ 959 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 960 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \ 961 } else { \ 962 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 963 } 964 965#define TI_UPDATE_MINIPROD(x, y) \ 966 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); 967 968#define TI_UPDATE_STDPROD(x, y) \ 969 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 970 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \ 971 } else { \ 972 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 973 } 974 975 976/* 977 * Tigon event structure. 978 */ 979struct ti_event_desc { 980#if BYTE_ORDER == BIG_ENDIAN 981 u_int32_t ti_event:8; 982 u_int32_t ti_code:12; 983 u_int32_t ti_idx:12; 984#else 985 u_int32_t ti_idx:12; 986 u_int32_t ti_code:12; 987 u_int32_t ti_event:8; 988#endif 989 u_int32_t ti_rsvd; 990}; 991 992/* 993 * Tigon events. 994 */ 995#define TI_EV_FIRMWARE_UP 0x01 996#define TI_EV_STATS_UPDATED 0x04 997 998#define TI_EV_LINKSTAT_CHANGED 0x06 999#define TI_EV_CODE_GIG_LINK_UP 0x01 1000#define TI_EV_CODE_LINK_DOWN 0x02 1001#define TI_EV_CODE_LINK_UP 0x03 1002 1003#define TI_EV_ERROR 0x07 1004#define TI_EV_CODE_ERR_INVAL_CMD 0x01 1005#define TI_EV_CODE_ERR_UNIMP_CMD 0x02 1006#define TI_EV_CODE_ERR_BADCFG 0x03 1007 1008#define TI_EV_MCAST_UPDATED 0x08 1009#define TI_EV_CODE_MCAST_ADD 0x01 1010#define TI_EV_CODE_MCAST_DEL 0x02 1011 1012#define TI_EV_RESET_JUMBO_RING 0x09 1013/* 1014 * Register access macros. The Tigon always uses memory mapped register 1015 * accesses and all registers must be accessed with 32 bit operations. 1016 */ 1017 1018#define CSR_WRITE_4(sc, reg, val) \ 1019 bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val) 1020 1021#define CSR_READ_4(sc, reg) \ 1022 bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg) 1023 1024#define TI_SETBIT(sc, reg, x) \ 1025 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 1026#define TI_CLRBIT(sc, reg, x) \ 1027 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 1028 1029/* 1030 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 1031 * values are tuneable. They control the actual amount of buffers 1032 * allocated for the standard, mini and jumbo receive rings. 1033 */ 1034 1035#define TI_SSLOTS 256 1036#define TI_MSLOTS 256 1037#define TI_JSLOTS 384 1038 1039#define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 1040#define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1041 (TI_JRAWLEN % sizeof(u_int64_t)))) 1042#define TI_JPAGESZ PAGE_SIZE 1043#define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1044#define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1045 1046struct ti_jslot { 1047 caddr_t ti_buf; 1048 int ti_inuse; 1049}; 1050 1051/* 1052 * Ring structures. Most of these reside in host memory and we tell 1053 * the NIC where they are via the ring control blocks. The exceptions 1054 * are the tx and command rings, which live in NIC memory and which 1055 * we access via the shared memory window. 1056 */ 1057struct ti_ring_data { 1058 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; 1059 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 1060 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1061 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1062 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1063 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1064 /* 1065 * Make sure producer structures are aligned on 32-byte cache 1066 * line boundaries. 1067 */ 1068 struct ti_producer ti_ev_prodidx_r; 1069 u_int32_t ti_pad0[6]; 1070 struct ti_producer ti_return_prodidx_r; 1071 u_int32_t ti_pad1[6]; 1072 struct ti_producer ti_tx_considx_r; 1073 u_int32_t ti_pad2[6]; 1074 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */ 1075 struct ti_cmd_desc *ti_cmd_ring; /* pointer to shared mem */ 1076 struct ti_gib ti_info; 1077}; 1078 1079/* 1080 * Mbuf pointers. We need these to keep track of the virtual addresses 1081 * of our mbuf chains since we can only convert from physical to virtual, 1082 * not the other way around. 1083 */ 1084struct ti_chain_data { 1085 struct mbuf *ti_tx_chain[TI_TX_RING_CNT]; 1086 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 1087 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 1088 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 1089 /* Stick the jumbo mem management stuff here too. */ 1090 struct ti_jslot ti_jslots[TI_JSLOTS]; 1091 void *ti_jumbo_buf; 1092}; 1093 1094struct ti_type { 1095 u_int16_t ti_vid; 1096 u_int16_t ti_did; 1097 char *ti_name; 1098}; 1099 1100#define TI_HWREV_TIGON 0x01 1101#define TI_HWREV_TIGON_II 0x02 1102#define TI_TIMEOUT 1000 1103#define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1104 1105struct ti_mc_entry { 1106 struct ether_addr mc_addr; 1107 SLIST_ENTRY(ti_mc_entry) mc_entries; 1108}; 1109 1110struct ti_jpool_entry { 1111 int slot; 1112 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1113}; 1114 1115struct ti_softc { 1116 struct arpcom arpcom; /* interface info */ 1117 bus_space_handle_t ti_bhandle; 1118 vm_offset_t ti_vhandle; 1119 bus_space_tag_t ti_btag; 1120 void *ti_intrhand; 1121 struct resource *ti_irq; 1122 struct resource *ti_res; 1123 struct ifmedia ifmedia; /* media info */ 1124 u_int8_t ti_unit; /* interface number */ 1125 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1126 u_int8_t ti_copper; /* 1000baseTX card */ 1127 u_int8_t ti_linkstat; /* Link state */ 1128 struct ti_ring_data *ti_rdata; /* rings */ 1129 struct ti_chain_data ti_cdata; /* mbufs */ 1130#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1131#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1132#define ti_tx_considx ti_rdata->ti_tx_considx_r 1133 u_int16_t ti_tx_saved_considx; 1134 u_int16_t ti_rx_saved_considx; 1135 u_int16_t ti_ev_saved_considx; 1136 u_int16_t ti_cmd_saved_prodidx; 1137 u_int16_t ti_std; /* current std ring head */ 1138 u_int16_t ti_mini; /* current mini ring head */ 1139 u_int16_t ti_jumbo; /* current jumo ring head */ 1140 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1141 SLIST_HEAD(__ti_jfreehead, ti_jpool_entry) ti_jfree_listhead; 1142 SLIST_HEAD(__ti_jinusehead, ti_jpool_entry) ti_jinuse_listhead; 1143 u_int32_t ti_stat_ticks; 1144 u_int32_t ti_rx_coal_ticks; 1145 u_int32_t ti_tx_coal_ticks; 1146 u_int32_t ti_rx_max_coal_bds; 1147 u_int32_t ti_tx_max_coal_bds; 1148 u_int32_t ti_tx_buf_ratio; 1149 int ti_if_flags; 1150 int ti_txcnt; 1151}; 1152 1153/* 1154 * Microchip Technology 24Cxx EEPROM control bytes 1155 */ 1156#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1157#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1158 1159/* 1160 * Note that EEPROM_START leaves transmission enabled. 1161 */ 1162#define EEPROM_START \ 1163 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1164 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1165 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1166 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1167 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1168 1169/* 1170 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1171 * that no further data can be written to the EEPROM I/O pin. 1172 */ 1173#define EEPROM_STOP \ 1174 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1175 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1176 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1177 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1178 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1179 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1180 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1181 1182 1183#ifdef __alpha__ 1184#undef vtophys 1185#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1186#endif 1187