if_tireg.h revision 45386
1262709Sganbold/* 2266337Sian * Copyright (c) 1997, 1998, 1999 3262709Sganbold * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4262709Sganbold * 5262709Sganbold * Redistribution and use in source and binary forms, with or without 6262709Sganbold * modification, are permitted provided that the following conditions 7262709Sganbold * are met: 8262709Sganbold * 1. Redistributions of source code must retain the above copyright 9262709Sganbold * notice, this list of conditions and the following disclaimer. 10262709Sganbold * 2. Redistributions in binary form must reproduce the above copyright 11262709Sganbold * notice, this list of conditions and the following disclaimer in the 12262709Sganbold * documentation and/or other materials provided with the distribution. 13262709Sganbold * 3. All advertising materials mentioning features or use of this software 14262709Sganbold * must display the following acknowledgement: 15262709Sganbold * This product includes software developed by Bill Paul. 16262709Sganbold * 4. Neither the name of the author nor the names of any co-contributors 17262709Sganbold * may be used to endorse or promote products derived from this software 18262709Sganbold * without specific prior written permission. 19262709Sganbold * 20262709Sganbold * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21262709Sganbold * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22262709Sganbold * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23262709Sganbold * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24262709Sganbold * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25262709Sganbold * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26262709Sganbold * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27262709Sganbold * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28262709Sganbold * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29262709Sganbold * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30262709Sganbold * THE POSSIBILITY OF SUCH DAMAGE. 31262709Sganbold * 32262709Sganbold * $Id: if_tireg.h,v 1.43 1999/04/02 02:54:16 wpaul Exp $ 33262709Sganbold */ 34262709Sganbold 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. 41 * The first group of registers are actually copies of the PCI 42 * configuration space registers. 43 */ 44 45#define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46#define TI_PCI_CMDSTAT 0x004 47#define TI_PCI_CLASSCODE 0x008 48#define TI_PCI_BIST 0x00C 49#define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50#define TI_PCI_SUBSYS 0x02C 51#define TI_PCI_ROMBASE 0x030 52#define TI_PCI_INT 0x03C 53 54#ifndef PCIM_CMD_MWIEN 55#define PCIM_CMD_MWIEN 0x0010 56#endif 57 58/* 59 * Alteon AceNIC PCI vendor/device ID. 60 */ 61#define ALT_VENDORID 0x12AE 62#define ALT_DEVICEID_ACENIC 0x0001 63 64/* 65 * 3Com 3c985 PCI vendor/device ID. 66 */ 67#define TC_VENDORID 0x10B7 68#define TC_DEVICEID_3C985 0x0001 69 70/* 71 * Netgear GA620 PCI vendor/device ID. 72 */ 73#define NG_VENDORID 0x1385 74#define NG_DEVICEID_GA620 0x620A 75 76/* 77 * SGI device/vendor ID. 78 */ 79#define SGI_VENDORID 0x10A9 80#define SGI_DEVICEID_TIGON 0x0009 81 82/* 83 * Tigon configuration and control registers. 84 */ 85#define TI_MISC_HOST_CTL 0x040 86#define TI_MISC_LOCAL_CTL 0x044 87#define TI_SEM_AB 0x048 /* Tigon 2 only */ 88#define TI_MISC_CONF 0x050 /* Tigon 2 only */ 89#define TI_TIMER_BITS 0x054 90#define TI_TIMERREF 0x058 91#define TI_PCI_STATE 0x05C 92#define TI_MAIN_EVENT_A 0x060 93#define TI_MAILBOX_EVENT_A 0x064 94#define TI_WINBASE 0x068 95#define TI_WINDATA 0x06C 96#define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 97#define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 98#define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 99#define TI_SERIAL 0x07C 100 101/* 102 * Misc host control bits. 103 */ 104#define TI_MHC_INTSTATE 0x00000001 105#define TI_MHC_CLEARINT 0x00000002 106#define TI_MHC_RESET 0x00000008 107#define TI_MHC_BYTE_SWAP_ENB 0x00000010 108#define TI_MHC_WORD_SWAP_ENB 0x00000020 109#define TI_MHC_MASK_INTS 0x00000040 110#define TI_MHC_CHIP_REV_MASK 0xF0000000 111 112#define TI_MHC_BIGENDIAN_INIT \ 113 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 114 115#define TI_MHC_LITTLEENDIAN_INIT \ 116 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 117 118/* 119 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 120 * Rev 5 is also the Tigon 2, but is a broken version which was never 121 * used in any actual hardware, so we ignore it. 122 */ 123#define TI_REV_TIGON_I 0x40000000 124#define TI_REV_TIGON_II 0x60000000 125 126/* 127 * Firmware revision that we want. 128 */ 129#define TI_FIRMWARE_MAJOR 0xc 130#define TI_FIRMWARE_MINOR 0x3 131#define TI_FIRMWARE_FIX 0x9 132 133/* 134 * Miscelaneous Local Control register. 135 */ 136#define TI_MLC_EE_WRITE_ENB 0x00000010 137#define TI_MLC_SRAM_BANK_256K 0x00000200 138#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 139#define TI_MLC_LOCALADDR_21 0x00004000 140#define TI_MLC_LOCALADDR_22 0x00008000 141#define TI_MLC_SBUS_WRITEERR 0x00080000 142#define TI_MLC_EE_CLK 0x00100000 143#define TI_MLC_EE_TXEN 0x00200000 144#define TI_MLC_EE_DOUT 0x00400000 145#define TI_MLC_EE_DIN 0x00800000 146 147/* 148 * Offset of MAC address inside EEPROM. 149 */ 150#define TI_EE_MAC_OFFSET 0x8c 151 152#define TI_DMA_ASSIST 0x11C 153#define TI_CPU_STATE 0x140 154#define TI_CPU_PROGRAM_COUNTER 0x144 155#define TI_SRAM_ADDR 0x154 156#define TI_SRAM_DATA 0x158 157#define TI_GEN_0 0x180 158#define TI_GEN_X 0x1FC 159#define TI_MAC_TX_STATE 0x200 160#define TI_MAC_RX_STATE 0x220 161#define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 162#define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 163#define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 164#define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 165#define TI_GEN_B_0 0x280 /* Tigon 2 only */ 166#define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 167 168/* 169 * Misc config register. 170 */ 171#define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 172 173/* 174 * PCI state register. 175 */ 176#define TI_PCISTATE_FORCE_RESET 0x00000001 177#define TI_PCISTATE_PROVIDE_LEN 0x00000002 178#define TI_PCISTATE_READ_MAXDMA 0x0000001C 179#define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 180#define TI_PCISTATE_MINDMA 0x0000FF00 181#define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 182#define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 183#define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 184#define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 185#define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 186#define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 187#define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 188#define TI_PCISTATE_READ_CMD 0x0F000000 189#define TI_PCISTATE_WRITE_CMD 0xF0000000 190 191#define TI_PCI_READMAX_4 0x04 192#define TI_PCI_READMAX_16 0x08 193#define TI_PCI_READMAX_32 0x0C 194#define TI_PCI_READMAX_64 0x10 195#define TI_PCI_READMAX_128 0x14 196#define TI_PCI_READMAX_256 0x18 197#define TI_PCI_READMAX_1024 0x1C 198 199#define TI_PCI_WRITEMAX_4 0x20 200#define TI_PCI_WRITEMAX_16 0x40 201#define TI_PCI_WRITEMAX_32 0x60 202#define TI_PCI_WRITEMAX_64 0x80 203#define TI_PCI_WRITEMAX_128 0xA0 204#define TI_PCI_WRITEMAX_256 0xC0 205#define TI_PCI_WRITEMAX_1024 0xE0 206 207#define TI_PCI_READ_CMD 0x06000000 208#define TI_PCI_WRITE_CMD 0x70000000 209 210/* 211 * DMA state register. 212 */ 213#define TI_DMASTATE_ENABLE 0x00000001 214#define TI_DMASTATE_PAUSE 0x00000002 215 216/* 217 * CPU state register. 218 */ 219#define TI_CPUSTATE_RESET 0x00000001 220#define TI_CPUSTATE_STEP 0x00000002 221#define TI_CPUSTATE_ROMFAIL 0x00000010 222#define TI_CPUSTATE_HALT 0x00010000 223/* 224 * MAC TX state register 225 */ 226#define TI_TXSTATE_RESET 0x00000001 227#define TI_TXSTATE_ENB 0x00000002 228#define TI_TXSTATE_STOP 0x00000004 229 230/* 231 * MAC RX state register 232 */ 233#define TI_RXSTATE_RESET 0x00000001 234#define TI_RXSTATE_ENB 0x00000002 235#define TI_RXSTATE_STOP 0x00000004 236 237/* 238 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 239 * split into 64 bit registers. Only the lower 32 bits of each mailbox 240 * are used. 241 */ 242#define TI_MB_HOSTINTR_HI 0x500 243#define TI_MB_HOSTINTR_LO 0x504 244#define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 245#define TI_MB_CMDPROD_IDX_HI 0x508 246#define TI_MB_CMDPROD_IDX_LO 0x50C 247#define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 248#define TI_MB_SENDPROD_IDX_HI 0x510 249#define TI_MB_SENDPROD_IDX_LO 0x514 250#define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 251#define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 252#define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 253#define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 254#define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 255#define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 256#define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 257#define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 258#define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 259#define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 260#define TI_MB_RSVD 0x530 261 262/* 263 * Tigon 2 general communication registers. These are 64 and 32 bit 264 * registers which are only valid after the firmware has been 265 * loaded and started. They actually exist in NIC memory but are 266 * mapped into the host memory via the shared memory region. 267 * 268 * The NIC internally maps these registers starting at address 0, 269 * so to determine the NIC address of any of these registers, we 270 * subtract 0x600 (the address of the first register). 271 */ 272 273#define TI_GCR_BASE 0x600 274#define TI_GCR_MACADDR 0x600 275#define TI_GCR_PAR0 0x600 276#define TI_GCR_PAR1 0x604 277#define TI_GCR_GENINFO_HI 0x608 278#define TI_GCR_GENINFO_LO 0x60C 279#define TI_GCR_MCASTADDR 0x610 /* obsolete */ 280#define TI_GCR_MAR0 0x610 /* obsolete */ 281#define TI_GCR_MAR1 0x614 /* obsolete */ 282#define TI_GCR_OPMODE 0x618 283#define TI_GCR_DMA_READCFG 0x61C 284#define TI_GCR_DMA_WRITECFG 0x620 285#define TI_GCR_TX_BUFFER_RATIO 0x624 286#define TI_GCR_EVENTCONS_IDX 0x628 287#define TI_GCR_CMDCONS_IDX 0x62C 288#define TI_GCR_TUNEPARMS 0x630 289#define TI_GCR_RX_COAL_TICKS 0x630 290#define TI_GCR_TX_COAL_TICKS 0x634 291#define TI_GCR_STAT_TICKS 0x638 292#define TI_GCR_TX_MAX_COAL_BD 0x63C 293#define TI_GCR_RX_MAX_COAL_BD 0x640 294#define TI_GCR_NIC_TRACING 0x644 295#define TI_GCR_GLINK 0x648 296#define TI_GCR_LINK 0x64C 297#define TI_GCR_NICTRACE_PTR 0x650 298#define TI_GCR_NICTRACE_START 0x654 299#define TI_GCR_NICTRACE_LEN 0x658 300#define TI_GCR_IFINDEX 0x65C 301#define TI_GCR_IFMTU 0x660 302#define TI_GCR_MASK_INTRS 0x664 303#define TI_GCR_GLINK_STAT 0x668 304#define TI_GCR_LINK_STAT 0x66C 305#define TI_GCR_RXRETURNCONS_IDX 0x680 306#define TI_GCR_CMDRING 0x700 307 308#define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE); 309 310/* 311 * Local memory window. The local memory window is a 2K shared 312 * memory region which can be used to access the NIC's internal 313 * SRAM. The window can be mapped to a given 2K region using 314 * the TI_WINDOW_BASE register. 315 */ 316#define TI_WINDOW 0x800 317#define TI_WINLEN 0x800 318 319#define TI_TICKS_PER_SEC 1000000 320 321/* 322 * Operation mode register. 323 */ 324#define TI_OPMODE_BYTESWAP_BD 0x00000002 325#define TI_OPMODE_WORDSWAP_BD 0x00000004 326#define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */ 327#define TI_OPMODE_BYTESWAP_DATA 0x00000010 328#define TI_OPMODE_1_DMA_ACTIVE 0x00000040 329#define TI_OPMODE_SBUS 0x00000100 330#define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 331#define TI_OPMODE_INCLUDE_CRC 0x00000400 332#define TI_OPMODE_RX_BADFRAMES 0x00000800 333#define TI_OPMODE_NO_EVENT_INTRS 0x00001000 334#define TI_OPMODE_NO_TX_INTRS 0x00002000 335#define TI_OPMODE_NO_RX_INTRS 0x00004000 336#define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ 337 338/* 339 * DMA configuration thresholds. 340 */ 341#define TI_DMA_STATE_THRESH_16W 0x00000100 342#define TI_DMA_STATE_THRESH_8W 0x00000080 343#define TI_DMA_STATE_THRESH_4W 0x00000040 344#define TI_DMA_STATE_THRESH_2W 0x00000020 345#define TI_DMA_STATE_THRESH_1W 0x00000010 346 347#define TI_DMA_STATE_FORCE_32_BIT 0x00000008 348 349/* 350 * Gigabit link status bits. 351 */ 352#define TI_GLNK_SENSE_NO_BEG 0x00002000 353#define TI_GLNK_LOOPBACK 0x00004000 354#define TI_GLNK_PREF 0x00008000 355#define TI_GLNK_1000MB 0x00040000 356#define TI_GLNK_FULL_DUPLEX 0x00080000 357#define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 358#define TI_GLNK_RX_FLOWCTL_Y 0x00800000 359#define TI_GLNK_AUTONEGENB 0x20000000 360#define TI_GLNK_ENB 0x40000000 361 362/* 363 * Link status bits. 364 */ 365#define TI_LNK_LOOPBACK 0x00004000 366#define TI_LNK_PREF 0x00008000 367#define TI_LNK_10MB 0x00010000 368#define TI_LNK_100MB 0x00020000 369#define TI_LNK_1000MB 0x00040000 370#define TI_LNK_FULL_DUPLEX 0x00080000 371#define TI_LNK_HALF_DUPLEX 0x00100000 372#define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 373#define TI_LNK_RX_FLOWCTL_Y 0x00800000 374#define TI_LNK_AUTONEGENB 0x20000000 375#define TI_LNK_ENB 0x40000000 376 377/* 378 * Ring size constants. 379 */ 380#define TI_EVENT_RING_CNT 256 381#define TI_CMD_RING_CNT 64 382#define TI_STD_RX_RING_CNT 512 383#define TI_JUMBO_RX_RING_CNT 256 384#define TI_MINI_RX_RING_CNT 1024 385#define TI_RETURN_RING_CNT 2048 386 387/* 388 * Possible TX ring sizes. 389 */ 390#define TI_TX_RING_CNT_128 128 391#define TI_TX_RING_BASE_128 0x3800 392 393#define TI_TX_RING_CNT_256 256 394#define TI_TX_RING_BASE_256 0x3000 395 396#define TI_TX_RING_CNT_512 512 397#define TI_TX_RING_BASE_512 0x2000 398 399#define TI_TX_RING_CNT TI_TX_RING_CNT_512 400#define TI_TX_RING_BASE TI_TX_RING_BASE_512 401 402/* 403 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 404 * is limited to 2MB total, and in general I think most adapters have 405 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 406 * be safe we use the largest possible value (zeroing memory that 407 * isn't there doesn't hurt anything). 408 */ 409#define TI_MEM_MAX 0x7FFFFF 410 411/* 412 * Even on the alpha, pci addresses are 32-bit quantities 413 */ 414 415#ifdef __64_bit_pci_addressing__ 416typedef struct { 417 u_int64_t ti_addr; 418} ti_hostaddr; 419#define TI_HOSTADDR(x) x.ti_addr 420#else 421typedef struct { 422 u_int32_t ti_addr_hi; 423 u_int32_t ti_addr_lo; 424} ti_hostaddr; 425#define TI_HOSTADDR(x) x.ti_addr_lo 426#endif 427 428/* 429 * Ring control block structure. The rules for the max_len field 430 * are as follows: 431 * 432 * For the send ring, max_len indicates the number of entries in the 433 * ring (128, 256 or 512). 434 * 435 * For the standard receive ring, max_len indicates the threshold 436 * used to decide when a frame should be put in the jumbo receive ring 437 * instead of the standard one. 438 * 439 * For the mini ring, max_len indicates the size of the buffers in the 440 * ring. This is the value used to decide when a frame is small enough 441 * to be placed in the mini ring. 442 * 443 * For the return receive ring, max_len indicates the number of entries 444 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 445 * 2048 for backwards compatibility). The value 1024 can only be used 446 * if the mini ring is disabled. 447 */ 448struct ti_rcb { 449 ti_hostaddr ti_hostaddr; 450#if BYTE_ORDER == BIG_ENDIAN 451 u_int16_t ti_max_len; 452 u_int16_t ti_flags; 453#else 454 u_int16_t ti_flags; 455 u_int16_t ti_max_len; 456#endif 457 u_int32_t ti_unused; 458}; 459 460#define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 461#define TI_RCB_FLAG_IP_CKSUM 0x00000002 462#define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 463#define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 464#define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 465#define TI_RCB_FLAG_HOST_RING 0x00000040 466#define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 467#define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 468#define TI_RCB_FLAG_RING_DISABLED 0x00000200 469 470struct ti_producer { 471 u_int32_t ti_idx; 472 u_int32_t ti_unused; 473}; 474 475/* 476 * Tigon statistics counters. 477 */ 478struct ti_stats { 479 /* 480 * MAC stats, taken from RFC 1643, ethernet-like MIB 481 */ 482 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 483 volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 484 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 485 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 486 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 487 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 488 volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 489 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 490 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 491 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 492 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 493 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 494 /* 495 * interface stats, taken from RFC 1213, MIB-II, interfaces group 496 */ 497 volatile u_int32_t ifIndex; /* 12 */ 498 volatile u_int32_t ifType; /* 13 */ 499 volatile u_int32_t ifMtu; /* 14 */ 500 volatile u_int32_t ifSpeed; /* 15 */ 501 volatile u_int32_t ifAdminStatus; /* 16 */ 502#define IF_ADMIN_STATUS_UP 1 503#define IF_ADMIN_STATUS_DOWN 2 504#define IF_ADMIN_STATUS_TESTING 3 505 volatile u_int32_t ifOperStatus; /* 17 */ 506#define IF_OPER_STATUS_UP 1 507#define IF_OPER_STATUS_DOWN 2 508#define IF_OPER_STATUS_TESTING 3 509#define IF_OPER_STATUS_UNKNOWN 4 510#define IF_OPER_STATUS_DORMANT 5 511 volatile u_int32_t ifLastChange; /* 18 */ 512 volatile u_int32_t ifInDiscards; /* 19 */ 513 volatile u_int32_t ifInErrors; /* 20 */ 514 volatile u_int32_t ifInUnknownProtos; /* 21 */ 515 volatile u_int32_t ifOutDiscards; /* 22 */ 516 volatile u_int32_t ifOutErrors; /* 23 */ 517 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 518 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 519 volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 520 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 521 /* 522 * more interface stats, taken from RFC 1573, MIB-IIupdate, 523 * interfaces group 524 */ 525 volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 526 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 527 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 528 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 529 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 530 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 531 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 532 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 533 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 534 volatile u_int32_t ifHighSpeed; /* 53 */ 535 volatile u_int32_t ifPromiscuousMode; /* 54 */ 536 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 537 /* 538 * Host Commands 539 */ 540 volatile u_int32_t nicCmdsHostState; /* 56 */ 541 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 542 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 543 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 544 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 545 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 546 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 547 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 548 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 549 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 550 volatile u_int32_t nicCmdsClearProfile; /* 66 */ 551 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 552 volatile u_int32_t nicCmdsClearStats; /* 68 */ 553 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 554 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 555 volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 556 volatile u_int32_t nicCmdsUnknown; /* 72 */ 557 /* 558 * NIC Events 559 */ 560 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 561 volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 562 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 563 volatile u_int32_t nicEventsError; /* 76 */ 564 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 565 volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 566 /* 567 * Ring manipulation 568 */ 569 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 570 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 571 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 572 /* 573 * Interrupts 574 */ 575 volatile u_int32_t nicInterrupts; /* 82 */ 576 volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 577 /* 578 * BD Coalessing Thresholds 579 */ 580 volatile u_int32_t nicEventThresholdHit; /* 84 */ 581 volatile u_int32_t nicSendThresholdHit; /* 85 */ 582 volatile u_int32_t nicRecvThresholdHit; /* 86 */ 583 /* 584 * DMA Attentions 585 */ 586 volatile u_int32_t nicDmaRdOverrun; /* 87 */ 587 volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 588 volatile u_int32_t nicDmaWrOverrun; /* 89 */ 589 volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 590 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 591 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 592 /* 593 * NIC Resources 594 */ 595 volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 596 volatile u_int32_t nicDmaReadRingFull; /* 94 */ 597 volatile u_int32_t nicEventRingFull; /* 95 */ 598 volatile u_int32_t nicEventProducerRingFull; /* 96 */ 599 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 600 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 601 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 602 volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 603 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 604 volatile u_int32_t nicSendBDs; /* current count 102 */ 605 volatile u_int32_t nicRecvBDs; /* current count 103 */ 606 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 607 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 608 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 609 volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 610 volatile u_int32_t nicJumboSpillOver; /* 108 */ 611 volatile u_int32_t nicSbusHangCleared; /* 109 */ 612 volatile u_int32_t nicEnqEventDelayed; /* 110 */ 613 /* 614 * Stats from MAC rx completion 615 */ 616 volatile u_int32_t nicMacRxLateColls; /* 111 */ 617 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 618 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 619 volatile u_int32_t nicMacRxMacAbort; /* 114 */ 620 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 621 /* 622 * Stats from the mac_stats area 623 */ 624 volatile u_int32_t nicMacRxDropUla; /* 116 */ 625 volatile u_int32_t nicMacRxDropMcast; /* 117 */ 626 volatile u_int32_t nicMacRxFlowControl; /* 118 */ 627 volatile u_int32_t nicMacRxDropSpace; /* 119 */ 628 volatile u_int32_t nicMacRxColls; /* 120 */ 629 /* 630 * MAC RX Attentions 631 */ 632 volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 633 volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 634 volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 635 volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 636 volatile u_int32_t nicMacReset; /* 125 */ 637 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 638 volatile u_int32_t nicMacRxBufAttns; /* 127 */ 639 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 640 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 641 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 642 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 643 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 644 /* 645 * Stats from the mac_stats area 646 */ 647 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 648 /* 649 * MAC TX Attentions 650 */ 651 volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 652 /* 653 * NIC Profile 654 */ 655 volatile u_int32_t nicProfile[32]; /* 135 */ 656 /* 657 * Pat to 1024 bytes. 658 */ 659 u_int32_t pad[75]; 660}; 661/* 662 * Tigon general information block. This resides in host memory 663 * and contains the status counters, ring control blocks and 664 * producer pointers. 665 */ 666 667struct ti_gib { 668 struct ti_stats ti_stats; 669 struct ti_rcb ti_ev_rcb; 670 struct ti_rcb ti_cmd_rcb; 671 struct ti_rcb ti_tx_rcb; 672 struct ti_rcb ti_std_rx_rcb; 673 struct ti_rcb ti_jumbo_rx_rcb; 674 struct ti_rcb ti_mini_rx_rcb; 675 struct ti_rcb ti_return_rcb; 676 ti_hostaddr ti_ev_prodidx_ptr; 677 ti_hostaddr ti_return_prodidx_ptr; 678 ti_hostaddr ti_tx_considx_ptr; 679 ti_hostaddr ti_refresh_stats_ptr; 680}; 681 682/* 683 * Buffer descriptor structures. There are basically three types 684 * of structures: normal receive descriptors, extended receive 685 * descriptors and transmit descriptors. The extended receive 686 * descriptors are optionally used only for the jumbo receive ring. 687 */ 688 689struct ti_rx_desc { 690 ti_hostaddr ti_addr; 691#if BYTE_ORDER == BIG_ENDIAN 692 u_int16_t ti_idx; 693 u_int16_t ti_len; 694#else 695 u_int16_t ti_len; 696 u_int16_t ti_idx; 697#endif 698#if BYTE_ORDER == BIG_ENDIAN 699 u_int16_t ti_type; 700 u_int16_t ti_flags; 701#else 702 u_int16_t ti_flags; 703 u_int16_t ti_type; 704#endif 705#if BYTE_ORDER == BIG_ENDIAN 706 u_int16_t ti_ip_cksum; 707 u_int16_t ti_tcp_udp_cksum; 708#else 709 u_int16_t ti_tcp_udp_cksum; 710 u_int16_t ti_ip_cksum; 711#endif 712#if BYTE_ORDER == BIG_ENDIAN 713 u_int16_t ti_error_flags; 714 u_int16_t ti_vlan_tag; 715#else 716 u_int16_t ti_vlan_tag; 717 u_int16_t ti_error_flags; 718#endif 719 u_int32_t ti_rsvd; 720 u_int32_t ti_opaque; 721}; 722 723struct ti_rx_desc_ext { 724 ti_hostaddr ti_addr1; 725 ti_hostaddr ti_addr2; 726 ti_hostaddr ti_addr3; 727#if BYTE_ORDER == BIG_ENDIAN 728 u_int16_t ti_len1; 729 u_int16_t ti_len2; 730#else 731 u_int16_t ti_len2; 732 u_int16_t ti_len1; 733#endif 734#if BYTE_ORDER == BIG_ENDIAN 735 u_int16_t ti_len3; 736 u_int16_t ti_rsvd0; 737#else 738 u_int16_t ti_rsvd0; 739 u_int16_t ti_len3; 740#endif 741 ti_hostaddr ti_addr0; 742#if BYTE_ORDER == BIG_ENDIAN 743 u_int16_t ti_idx; 744 u_int16_t ti_len0; 745#else 746 u_int16_t ti_len0; 747 u_int16_t ti_idx; 748#endif 749#if BYTE_ORDER == BIG_ENDIAN 750 u_int16_t ti_type; 751 u_int16_t ti_flags; 752#else 753 u_int16_t ti_flags; 754 u_int16_t ti_type; 755#endif 756#if BYTE_ORDER == BIG_ENDIAN 757 u_int16_t ti_ip_cksum; 758 u_int16_t ti_tcp_udp_cksum; 759#else 760 u_int16_t ti_tcp_udp_cksum; 761 u_int16_t ti_ip_cksum; 762#endif 763#if BYTE_ORDER == BIG_ENDIAN 764 u_int16_t ti_error_flags; 765 u_int16_t ti_vlan_tag; 766#else 767 u_int16_t ti_vlan_tag; 768 u_int16_t ti_error_flags; 769#endif 770 u_int32_t ti_rsvd1; 771 u_int32_t ti_opaque; 772}; 773 774/* 775 * Transmit descriptors are, mercifully, very small. 776 */ 777struct ti_tx_desc { 778 ti_hostaddr ti_addr; 779#if BYTE_ORDER == BIG_ENDIAN 780 u_int16_t ti_len; 781 u_int16_t ti_flags; 782#else 783 u_int16_t ti_flags; 784 u_int16_t ti_len; 785#endif 786#if BYTE_ORDER == BIG_ENDIAN 787 u_int16_t ti_rsvd; 788 u_int16_t ti_vlan_tag; 789#else 790 u_int16_t ti_vlan_tag; 791 u_int16_t ti_rsvd; 792#endif 793}; 794 795/* 796 * NOTE! On the Alpha, we have an alignment constraint. 797 * The first thing in the packet is a 14-byte Ethernet header. 798 * This means that the packet is misaligned. To compensate, 799 * we actually offset the data 2 bytes into the cluster. This 800 * alignes the packet after the Ethernet header at a 32-bit 801 * boundary. 802 */ 803 804#ifdef __alpha__ 805#define ETHER_ALIGN 2 806#endif 807 808#ifdef __i386__ 809#define ETHER_ALIGN 0 810#endif 811 812 813#define TI_FRAMELEN 1518 814#define TI_JUMBO_FRAMELEN 9018 + ETHER_ALIGN 815#define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 816#define TI_PAGE_SIZE PAGE_SIZE 817#define TI_MIN_FRAMELEN 60 818 819/* 820 * Buffer descriptor error flags. 821 */ 822#define TI_BDERR_CRC 0x0001 823#define TI_BDERR_COLLDETECT 0x0002 824#define TI_BDERR_LINKLOST 0x0004 825#define TI_BDERR_DECODE 0x0008 826#define TI_BDERR_ODD_NIBBLES 0x0010 827#define TI_BDERR_MAC_ABRT 0x0020 828#define TI_BDERR_RUNT 0x0040 829#define TI_BDERR_TRUNC 0x0080 830#define TI_BDERR_GIANT 0x0100 831 832/* 833 * Buffer descriptor flags. 834 */ 835#define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 836#define TI_BDFLAG_IP_CKSUM 0x0002 837#define TI_BDFLAG_END 0x0004 838#define TI_BDFLAG_MORE 0x0008 839#define TI_BDFLAG_JUMBO_RING 0x0010 840#define TI_BDFLAG_UCAST_PKT 0x0020 841#define TI_BDFLAG_MCAST_PKT 0x0040 842#define TI_BDFLAG_BCAST_PKT 0x0060 843#define TI_BDFLAG_IP_FRAG 0x0080 844#define TI_BDFLAG_IP_FRAG_END 0x0100 845#define TI_BDFLAG_VLAN_TAG 0x0200 846#define TI_BDFLAG_ERROR 0x0400 847#define TI_BDFLAG_COAL_NOW 0x0800 848#define TI_BDFLAG_MINI_RING 0x1000 849 850/* 851 * Descriptor type flags. I think these only have meaning for 852 * the Tigon 1. I had to extract them from the sample driver source 853 * since they aren't in the manual. 854 */ 855#define TI_BDTYPE_TYPE_NULL 0x0000 856#define TI_BDTYPE_SEND_BD 0x0001 857#define TI_BDTYPE_RECV_BD 0x0002 858#define TI_BDTYPE_RECV_JUMBO_BD 0x0003 859#define TI_BDTYPE_RECV_BD_LAST 0x0004 860#define TI_BDTYPE_SEND_DATA 0x0005 861#define TI_BDTYPE_SEND_DATA_LAST 0x0006 862#define TI_BDTYPE_RECV_DATA 0x0007 863#define TI_BDTYPE_RECV_DATA_LAST 0x000b 864#define TI_BDTYPE_EVENT_RUPT 0x000c 865#define TI_BDTYPE_EVENT_NO_RUPT 0x000d 866#define TI_BDTYPE_ODD_START 0x000e 867#define TI_BDTYPE_UPDATE_STATS 0x000f 868#define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 869#define TI_BDTYPE_EVENT_PROD 0x0011 870#define TI_BDTYPE_TX_CONS 0x0012 871#define TI_BDTYPE_RX_PROD 0x0013 872#define TI_BDTYPE_REFRESH_STATS 0x0014 873#define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 874#define TI_BDTYPE_SEND_DATA_COAL 0x0016 875#define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 876#define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 877#define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 878 879/* 880 * Tigon command structure. 881 */ 882struct ti_cmd_desc { 883#if BYTE_ORDER == BIG_ENDIAN 884 u_int32_t ti_cmd:8; 885 u_int32_t ti_code:12; 886 u_int32_t ti_idx:12; 887#else 888 u_int32_t ti_idx:12; 889 u_int32_t ti_code:12; 890 u_int32_t ti_cmd:8; 891#endif 892}; 893 894#define TI_CMD_HOST_STATE 0x01 895#define TI_CMD_CODE_STACK_UP 0x01 896#define TI_CMD_CODE_STACK_DOWN 0x02 897 898/* 899 * This command enables software address filtering. It's a workaround 900 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 901 */ 902#define TI_CMD_FDR_FILTERING 0x02 903#define TI_CMD_CODE_FILT_ENB 0x01 904#define TI_CMD_CODE_FILT_DIS 0x02 905 906#define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 907#define TI_CMD_UPDATE_GENCOM 0x04 908#define TI_CMD_RESET_JUMBO_RING 0x05 909#define TI_CMD_SET_PARTIAL_RX_CNT 0x06 910#define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 911#define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 912 913#define TI_CMD_SET_PROMISC_MODE 0x0A 914#define TI_CMD_CODE_PROMISC_ENB 0x01 915#define TI_CMD_CODE_PROMISC_DIS 0x02 916 917#define TI_CMD_LINK_NEGOTIATION 0x0B 918#define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 919#define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 920#define TI_CMD_CODE_NEGOTIATE_10_100 0x02 921 922#define TI_CMD_SET_MAC_ADDR 0x0C 923#define TI_CMD_CLR_PROFILE 0x0D 924 925#define TI_CMD_SET_ALLMULTI 0x0E 926#define TI_CMD_CODE_ALLMULTI_ENB 0x01 927#define TI_CMD_CODE_ALLMULTI_DIS 0x02 928 929#define TI_CMD_CLR_STATS 0x0F 930#define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 931#define TI_CMD_RFRSH_STATS 0x11 932 933#define TI_CMD_EXT_ADD_MCAST 0x12 934#define TI_CMD_EXT_DEL_MCAST 0x13 935 936/* 937 * Utility macros to make issuing commands a little simpler. Assumes 938 * that 'sc' and 'cmd' are in local scope. 939 */ 940#define TI_DO_CMD(x, y, z) \ 941 cmd.ti_cmd = x; \ 942 cmd.ti_code = y; \ 943 cmd.ti_idx = z; \ 944 ti_cmd(sc, &cmd); 945 946#define TI_DO_CMD_EXT(x, y, z, v, w) \ 947 cmd.ti_cmd = x; \ 948 cmd.ti_code = y; \ 949 cmd.ti_idx = z; \ 950 ti_cmd_ext(sc, &cmd, v, w); 951 952/* 953 * Other utility macros. 954 */ 955#define TI_INC(x, y) (x) = (x + 1) % y 956 957#define TI_UPDATE_JUMBOPROD(x, y) \ 958 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 959 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \ 960 } else { \ 961 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 962 } 963 964#define TI_UPDATE_MINIPROD(x, y) \ 965 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); 966 967#define TI_UPDATE_STDPROD(x, y) \ 968 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 969 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \ 970 } else { \ 971 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 972 } 973 974 975/* 976 * Tigon event structure. 977 */ 978struct ti_event_desc { 979#if BYTE_ORDER == BIG_ENDIAN 980 u_int32_t ti_event:8; 981 u_int32_t ti_code:12; 982 u_int32_t ti_idx:12; 983#else 984 u_int32_t ti_idx:12; 985 u_int32_t ti_code:12; 986 u_int32_t ti_event:8; 987#endif 988 u_int32_t ti_rsvd; 989}; 990 991/* 992 * Tigon events. 993 */ 994#define TI_EV_FIRMWARE_UP 0x01 995#define TI_EV_STATS_UPDATED 0x04 996 997#define TI_EV_LINKSTAT_CHANGED 0x06 998#define TI_EV_CODE_GIG_LINK_UP 0x01 999#define TI_EV_CODE_LINK_DOWN 0x02 1000#define TI_EV_CODE_LINK_UP 0x03 1001 1002#define TI_EV_ERROR 0x07 1003#define TI_EV_CODE_ERR_INVAL_CMD 0x01 1004#define TI_EV_CODE_ERR_UNIMP_CMD 0x02 1005#define TI_EV_CODE_ERR_BADCFG 0x03 1006 1007#define TI_EV_MCAST_UPDATED 0x08 1008#define TI_EV_CODE_MCAST_ADD 0x01 1009#define TI_EV_CODE_MCAST_DEL 0x02 1010 1011#define TI_EV_RESET_JUMBO_RING 0x09 1012/* 1013 * Register access macros. The Tigon always uses memory mapped register 1014 * accesses and all registers must be accessed with 32 bit operations. 1015 */ 1016 1017#define CSR_WRITE_4(sc, reg, val) \ 1018 bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val) 1019 1020#define CSR_READ_4(sc, reg) \ 1021 bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg) 1022 1023#define TI_SETBIT(sc, reg, x) \ 1024 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 1025#define TI_CLRBIT(sc, reg, x) \ 1026 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 1027 1028/* 1029 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 1030 * values are tuneable. They control the actual amount of buffers 1031 * allocated for the standard, mini and jumbo receive rings. 1032 */ 1033 1034#define TI_SSLOTS 256 1035#define TI_MSLOTS 256 1036#define TI_JSLOTS 256 1037 1038#define TI_JRAWLEN (TI_JUMBO_FRAMELEN + sizeof(u_int64_t)) 1039#define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1040 (TI_JRAWLEN % sizeof(u_int64_t)))) 1041#define TI_JPAGESZ PAGE_SIZE 1042#define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1043#define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1044 1045struct ti_jslot { 1046 caddr_t ti_buf; 1047 int ti_inuse; 1048}; 1049 1050/* 1051 * Ring structures. Most of these reside in host memory and we tell 1052 * the NIC where they are via the ring control blocks. The exceptions 1053 * are the tx and command rings, which live in NIC memory and which 1054 * we access via the shared memory window. 1055 */ 1056struct ti_ring_data { 1057 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; 1058 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 1059 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1060 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1061 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1062 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1063 /* 1064 * Make sure producer structures are aligned on 32-byte cache 1065 * line boundaries. 1066 */ 1067 struct ti_producer ti_ev_prodidx_r; 1068 u_int32_t ti_pad0[6]; 1069 struct ti_producer ti_return_prodidx_r; 1070 u_int32_t ti_pad1[6]; 1071 struct ti_producer ti_tx_considx_r; 1072 u_int32_t ti_pad2[6]; 1073 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */ 1074 struct ti_cmd_desc *ti_cmd_ring; /* pointer to shared mem */ 1075 struct ti_gib ti_info; 1076}; 1077 1078/* 1079 * Mbuf pointers. We need these to keep track of the virtual addresses 1080 * of our mbuf chains since we can only convert from physical to virtual, 1081 * not the other way around. 1082 */ 1083struct ti_chain_data { 1084 struct mbuf *ti_tx_chain[TI_TX_RING_CNT]; 1085 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 1086 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 1087 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 1088 /* Stick the jumbo mem management stuff here too. */ 1089 struct ti_jslot ti_jslots[TI_JSLOTS]; 1090 void *ti_jumbo_buf; 1091}; 1092 1093struct ti_type { 1094 u_int16_t ti_vid; 1095 u_int16_t ti_did; 1096 char *ti_name; 1097}; 1098 1099#define TI_HWREV_TIGON 0x01 1100#define TI_HWREV_TIGON_II 0x02 1101#define TI_TIMEOUT 1000 1102#define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1103 1104struct ti_mc_entry { 1105 struct ether_addr mc_addr; 1106 SLIST_ENTRY(ti_mc_entry) mc_entries; 1107}; 1108 1109struct ti_jpool_entry { 1110 int slot; 1111 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1112}; 1113 1114struct ti_softc { 1115 struct arpcom arpcom; /* interface info */ 1116 bus_space_handle_t ti_bhandle; 1117#ifdef __alpha__ 1118 vm_offset_t ti_vhandle; /* alpha dense space vaddr */ 1119#endif 1120 bus_space_tag_t ti_btag; 1121 struct ifmedia ifmedia; /* media info */ 1122 u_int8_t ti_unit; /* interface number */ 1123 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1124 u_int8_t ti_linkstat; /* Link state */ 1125 caddr_t ti_rdata_ptr; /* Raw ring data */ 1126 struct ti_ring_data *ti_rdata; /* rings */ 1127 struct ti_chain_data ti_cdata; /* mbufs */ 1128#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1129#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1130#define ti_tx_considx ti_rdata->ti_tx_considx_r 1131 u_int16_t ti_tx_saved_considx; 1132 u_int16_t ti_rx_saved_considx; 1133 u_int16_t ti_ev_saved_considx; 1134 u_int16_t ti_cmd_saved_prodidx; 1135 u_int16_t ti_std; /* current std ring head */ 1136 u_int16_t ti_mini; /* current mini ring head */ 1137 u_int16_t ti_jumbo; /* current jumo ring head */ 1138 u_int16_t ti_std_old; 1139 u_int16_t ti_mini_old; 1140 u_int16_t ti_jumbo_old; 1141 u_int16_t ti_std_cnt; 1142 u_int16_t ti_mini_cnt; 1143 u_int16_t ti_jumbo_cnt; 1144 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1145 SLIST_HEAD(__ti_jfreehead, ti_jpool_entry) ti_jfree_listhead; 1146 SLIST_HEAD(__ti_jinusehead, ti_jpool_entry) ti_jinuse_listhead; 1147 u_int32_t ti_stat_ticks; 1148 u_int32_t ti_rx_coal_ticks; 1149 u_int32_t ti_tx_coal_ticks; 1150 u_int32_t ti_rx_max_coal_bds; 1151 u_int32_t ti_tx_max_coal_bds; 1152 u_int32_t ti_tx_buf_ratio; 1153 int ti_if_flags; 1154}; 1155 1156/* 1157 * Microchip Technology 24Cxx EEPROM control bytes 1158 */ 1159#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1160#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1161 1162/* 1163 * Note that EEPROM_START leaves transmission enabled. 1164 */ 1165#define EEPROM_START \ 1166 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1167 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1168 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1169 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1170 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1171 1172/* 1173 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1174 * that no further data can be written to the EEPROM I/O pin. 1175 */ 1176#define EEPROM_STOP \ 1177 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1178 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1179 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1180 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1181 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1182 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1183 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1184 1185#ifdef __alpha__ 1186#undef vtophys 1187#define vtophys(va) (pmap_kextract(((vm_offset_t) (va))) \ 1188 + 1*1024*1024*1024) 1189#endif 1190 1191