if_stereg.h revision 127937
1249259Sdim/* 2249259Sdim * Copyright (c) 1997, 1998, 1999 3249259Sdim * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4249259Sdim * 5249259Sdim * Redistribution and use in source and binary forms, with or without 6249259Sdim * modification, are permitted provided that the following conditions 7249259Sdim * are met: 8249259Sdim * 1. Redistributions of source code must retain the above copyright 9249259Sdim * notice, this list of conditions and the following disclaimer. 10249259Sdim * 2. Redistributions in binary form must reproduce the above copyright 11249259Sdim * notice, this list of conditions and the following disclaimer in the 12249259Sdim * documentation and/or other materials provided with the distribution. 13249259Sdim * 3. All advertising materials mentioning features or use of this software 14249259Sdim * must display the following acknowledgement: 15249259Sdim * This product includes software developed by Bill Paul. 16249259Sdim * 4. Neither the name of the author nor the names of any co-contributors 17249259Sdim * may be used to endorse or promote products derived from this software 18249259Sdim * without specific prior written permission. 19249259Sdim * 20249259Sdim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21249259Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22249259Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23249259Sdim * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24249259Sdim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25249259Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26249259Sdim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27249259Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28249259Sdim * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29249259Sdim * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30249259Sdim * THE POSSIBILITY OF SUCH DAMAGE. 31249259Sdim * 32249259Sdim * $FreeBSD: head/sys/pci/if_stereg.h 127937 2004-04-06 11:04:54Z ru $ 33249259Sdim */ 34249259Sdim 35249259Sdim/* 36249259Sdim * Sundance PCI device/vendor ID for the 37249259Sdim * ST201 chip. 38249259Sdim */ 39249259Sdim#define ST_VENDORID 0x13F0 40249259Sdim#define ST_DEVICEID_ST201 0x0201 41249259Sdim 42249259Sdim/* 43249259Sdim * D-Link PCI device/vendor ID for the DL10050[AB] chip 44249259Sdim */ 45249259Sdim#define DL_VENDORID 0x1186 46249259Sdim#define DL_DEVICEID_DL10050 0x1002 47249259Sdim 48249259Sdim/* 49249259Sdim * Register definitions for the Sundance Technologies ST201 PCI 50249259Sdim * fast ethernet controller. The register space is 128 bytes long and 51249259Sdim * can be accessed using either PCI I/O space or PCI memory mapping. 52249259Sdim * There are 32-bit, 16-bit and 8-bit registers. 53249259Sdim */ 54249259Sdim 55249259Sdim#define STE_DMACTL 0x00 56249259Sdim#define STE_TX_DMALIST_PTR 0x04 57249259Sdim#define STE_TX_DMABURST_THRESH 0x08 58249259Sdim#define STE_TX_DMAURG_THRESH 0x09 59249259Sdim#define STE_TX_DMAPOLL_PERIOD 0x0A 60249259Sdim#define STE_RX_DMASTATUS 0x0C 61249259Sdim#define STE_RX_DMALIST_PTR 0x10 62249259Sdim#define STE_RX_DMABURST_THRESH 0x14 63249259Sdim#define STE_RX_DMAURG_THRESH 0x15 64249259Sdim#define STE_RX_DMAPOLL_PERIOD 0x16 65249259Sdim#define STE_DEBUGCTL 0x1A 66249259Sdim#define STE_ASICCTL 0x30 67249259Sdim#define STE_EEPROM_DATA 0x34 68249259Sdim#define STE_EEPROM_CTL 0x36 69249259Sdim#define STE_FIFOCTL 0x3A 70249259Sdim#define STE_TX_STARTTHRESH 0x3C 71249259Sdim#define STE_RX_EARLYTHRESH 0x3E 72249259Sdim#define STE_EXT_ROMADDR 0x40 73249259Sdim#define STE_EXT_ROMDATA 0x44 74249259Sdim#define STE_WAKE_EVENT 0x45 75249259Sdim#define STE_TX_STATUS 0x46 76249259Sdim#define STE_TX_FRAMEID 0x47 77249259Sdim#define STE_COUNTDOWN 0x48 78249259Sdim#define STE_ISR_ACK 0x4A 79249259Sdim#define STE_IMR 0x4C 80249259Sdim#define STE_ISR 0x4E 81249259Sdim#define STE_MACCTL0 0x50 82249259Sdim#define STE_MACCTL1 0x52 83249259Sdim#define STE_PAR0 0x54 84249259Sdim#define STE_PAR1 0x56 85249259Sdim#define STE_PAR2 0x58 86249259Sdim#define STE_MAX_FRAMELEN 0x5A 87249259Sdim#define STE_RX_MODE 0x5C 88249259Sdim#define STE_TX_RECLAIM_THRESH 0x5D 89249259Sdim#define STE_PHYCTL 0x5E 90249259Sdim#define STE_MAR0 0x60 91249259Sdim#define STE_MAR1 0x62 92249259Sdim#define STE_MAR2 0x64 93249259Sdim#define STE_MAR3 0x66 94249259Sdim#define STE_STATS 0x68 95249259Sdim 96249259Sdim#define STE_LATE_COLLS 0x75 97249259Sdim#define STE_MULTI_COLLS 0x76 98249259Sdim#define STE_SINGLE_COLLS 0x77 99249259Sdim 100249259Sdim#define STE_DMACTL_RXDMA_STOPPED 0x00000001 101249259Sdim#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 102249259Sdim#define STE_DMACTL_TXDMA_STOPPED 0x00000004 103249259Sdim#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 104249259Sdim#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 105249259Sdim#define STE_DMACTL_RXDMA_STALL 0x00000100 106249259Sdim#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 107249259Sdim#define STE_DMACTL_TXDMA_STALL 0x00000400 108249259Sdim#define STE_DMACTL_TXDMA_UNSTALL 0x00000800 109249259Sdim#define STE_DMACTL_TXDMA_INPROG 0x00004000 110249259Sdim#define STE_DMACTL_DMA_HALTINPROG 0x00008000 111249259Sdim#define STE_DMACTL_RXEARLY_ENABLE 0x00020000 112249259Sdim#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 113249259Sdim#define STE_DMACTL_COUNTDOWN_MODE 0x00080000 114249259Sdim#define STE_DMACTL_MWI_DISABLE 0x00100000 115249259Sdim#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 116249259Sdim#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 117249259Sdim#define STE_DMACTL_TARGET_ABORT 0x40000000 118249259Sdim#define STE_DMACTL_MASTER_ABORT 0x80000000 119249259Sdim 120249259Sdim/* 121249259Sdim * TX DMA burst thresh is the number of 32-byte blocks that 122249259Sdim * must be loaded into the TX Fifo before a TXDMA burst request 123249259Sdim * will be issued. 124249259Sdim */ 125249259Sdim#define STE_TXDMABURST_THRESH 0x1F 126249259Sdim 127249259Sdim/* 128249259Sdim * The number of 32-byte blocks in the TX FIFO falls below the 129249259Sdim * TX DMA urgent threshold, a TX DMA urgent request will be 130249259Sdim * generated. 131249259Sdim */ 132249259Sdim#define STE_TXDMAURG_THRESH 0x3F 133249259Sdim 134249259Sdim/* 135249259Sdim * Number of 320ns intervals between polls of the TXDMA next 136249259Sdim * descriptor pointer (if we're using polling mode). 137249259Sdim */ 138249259Sdim#define STE_TXDMA_POLL_PERIOD 0x7F 139249259Sdim 140249259Sdim#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 141249259Sdim#define STE_RX_DMASTATUS_RXERR 0x00004000 142249259Sdim#define STE_RX_DMASTATUS_DMADONE 0x00008000 143249259Sdim#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 144249259Sdim#define STE_RX_DMASTATUS_RUNT 0x00020000 145249259Sdim#define STE_RX_DMASTATUS_ALIGNERR 0x00040000 146249259Sdim#define STE_RX_DMASTATUS_CRCERR 0x00080000 147249259Sdim#define STE_RX_DMASTATUS_GIANT 0x00100000 148249259Sdim#define STE_RX_DMASTATUS_DRIBBLE 0x00800000 149249259Sdim#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 150249259Sdim 151249259Sdim/* 152249259Sdim * RX DMA burst thresh is the number of 32-byte blocks that 153249259Sdim * must be present in the RX FIFO before a RXDMA bus master 154249259Sdim * request will be issued. 155249259Sdim */ 156249259Sdim#define STE_RXDMABURST_THRESH 0xFF 157249259Sdim 158249259Sdim/* 159249259Sdim * The number of 32-byte blocks in the RX FIFO falls below the 160249259Sdim * RX DMA urgent threshold, a RX DMA urgent request will be 161249259Sdim * generated. 162249259Sdim */ 163249259Sdim#define STE_RXDMAURG_THRESH 0x1F 164249259Sdim 165249259Sdim/* 166249259Sdim * Number of 320ns intervals between polls of the RXDMA complete 167249259Sdim * bit in the status field on the current RX descriptor (if we're 168249259Sdim * using polling mode). 169249259Sdim */ 170249259Sdim#define STE_RXDMA_POLL_PERIOD 0x7F 171249259Sdim 172249259Sdim#define STE_DEBUGCTL_GPIO0_CTL 0x0001 173249259Sdim#define STE_DEBUGCTL_GPIO1_CTL 0x0002 174249259Sdim#define STE_DEBUGCTL_GPIO0_DATA 0x0004 175249259Sdim#define STE_DEBUGCTL_GPIO1_DATA 0x0008 176249259Sdim 177249259Sdim#define STE_ASICCTL_ROMSIZE 0x00000002 178249259Sdim#define STE_ASICCTL_TX_LARGEPKTS 0x00000004 179249259Sdim#define STE_ASICCTL_RX_LARGEPKTS 0x00000008 180249259Sdim#define STE_ASICCTL_EXTROM_DISABLE 0x00000010 181249259Sdim#define STE_ASICCTL_PHYSPEED_10 0x00000020 182249259Sdim#define STE_ASICCTL_PHYSPEED_100 0x00000040 183249259Sdim#define STE_ASICCTL_PHYMEDIA 0x00000080 184249259Sdim#define STE_ASICCTL_FORCEDCONFIG 0x00000700 185249259Sdim#define STE_ASICCTL_D3RESET_DISABLE 0x00000800 186249259Sdim#define STE_ASICCTL_SPEEDUPMODE 0x00002000 187249259Sdim#define STE_ASICCTL_LEDMODE 0x00004000 188249259Sdim#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 189249259Sdim#define STE_ASICCTL_GLOBAL_RESET 0x00010000 190249259Sdim#define STE_ASICCTL_RX_RESET 0x00020000 191249259Sdim#define STE_ASICCTL_TX_RESET 0x00040000 192249259Sdim#define STE_ASICCTL_DMA_RESET 0x00080000 193249259Sdim#define STE_ASICCTL_FIFO_RESET 0x00100000 194249259Sdim#define STE_ASICCTL_NETWORK_RESET 0x00200000 195249259Sdim#define STE_ASICCTL_HOST_RESET 0x00400000 196249259Sdim#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 197249259Sdim#define STE_ASICCTL_EXTRESET_RESET 0x01000000 198249259Sdim#define STE_ASICCTL_SOFTINTR 0x02000000 199249259Sdim#define STE_ASICCTL_RESET_BUSY 0x04000000 200249259Sdim 201249259Sdim#define STE_ASICCTL1_GLOBAL_RESET 0x0001 202249259Sdim#define STE_ASICCTL1_RX_RESET 0x0002 203249259Sdim#define STE_ASICCTL1_TX_RESET 0x0004 204249259Sdim#define STE_ASICCTL1_DMA_RESET 0x0008 205249259Sdim#define STE_ASICCTL1_FIFO_RESET 0x0010 206249259Sdim#define STE_ASICCTL1_NETWORK_RESET 0x0020 207249259Sdim#define STE_ASICCTL1_HOST_RESET 0x0040 208249259Sdim#define STE_ASICCTL1_AUTOINIT_RESET 0x0080 209249259Sdim#define STE_ASICCTL1_EXTRESET_RESET 0x0100 210249259Sdim#define STE_ASICCTL1_SOFTINTR 0x0200 211249259Sdim#define STE_ASICCTL1_RESET_BUSY 0x0400 212249259Sdim 213249259Sdim#define STE_EECTL_ADDR 0x00FF 214249259Sdim#define STE_EECTL_OPCODE 0x0300 215249259Sdim#define STE_EECTL_BUSY 0x1000 216249259Sdim 217249259Sdim#define STE_EEOPCODE_WRITE 0x0100 218249259Sdim#define STE_EEOPCODE_READ 0x0200 219249259Sdim#define STE_EEOPCODE_ERASE 0x0300 220249259Sdim 221249259Sdim#define STE_FIFOCTL_RAMTESTMODE 0x0001 222249259Sdim#define STE_FIFOCTL_OVERRUNMODE 0x0200 223249259Sdim#define STE_FIFOCTL_RXFIFOFULL 0x0800 224249259Sdim#define STE_FIFOCTL_TX_BUSY 0x4000 225249259Sdim#define STE_FIFOCTL_RX_BUSY 0x8000 226263508Sdim 227263508Sdim/* 228263508Sdim * The number of bytes that must in present in the TX FIFO before 229263508Sdim * transmission begins. Value should be in increments of 4 bytes. 230263508Sdim */ 231263508Sdim#define STE_TXSTART_THRESH 0x1FFC 232263508Sdim 233263508Sdim/* 234263508Sdim * Number of bytes that must be present in the RX FIFO before 235263508Sdim * an RX EARLY interrupt is generated. 236263508Sdim */ 237263508Sdim#define STE_RXEARLY_THRESH 0x1FFC 238263508Sdim 239249259Sdim#define STE_WAKEEVENT_WAKEPKT_ENB 0x01 240249259Sdim#define STE_WAKEEVENT_MAGICPKT_ENB 0x02 241249259Sdim#define STE_WAKEEVENT_LINKEVT_ENB 0x04 242249259Sdim#define STE_WAKEEVENT_WAKEPOLARITY 0x08 243249259Sdim#define STE_WAKEEVENT_WAKEPKTEVENT 0x10 244249259Sdim#define STE_WAKEEVENT_MAGICPKTEVENT 0x20 245249259Sdim#define STE_WAKEEVENT_LINKEVENT 0x40 246249259Sdim#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 247249259Sdim 248249259Sdim#define STE_TXSTATUS_RECLAIMERR 0x02 249249259Sdim#define STE_TXSTATUS_STATSOFLOW 0x04 250249259Sdim#define STE_TXSTATUS_EXCESSCOLLS 0x08 251249259Sdim#define STE_TXSTATUS_UNDERRUN 0x10 252249259Sdim#define STE_TXSTATUS_TXINTR_REQ 0x40 253249259Sdim#define STE_TXSTATUS_TXDONE 0x80 254249259Sdim 255249259Sdim#define STE_ISRACK_INTLATCH 0x0001 256249259Sdim#define STE_ISRACK_HOSTERR 0x0002 257249259Sdim#define STE_ISRACK_TX_DONE 0x0004 258249259Sdim#define STE_ISRACK_MACCTL_FRAME 0x0008 259249259Sdim#define STE_ISRACK_RX_DONE 0x0010 260249259Sdim#define STE_ISRACK_RX_EARLY 0x0020 261249259Sdim#define STE_ISRACK_SOFTINTR 0x0040 262249259Sdim#define STE_ISRACK_STATS_OFLOW 0x0080 263249259Sdim#define STE_ISRACK_LINKEVENT 0x0100 264249259Sdim#define STE_ISRACK_TX_DMADONE 0x0200 265249259Sdim#define STE_ISRACK_RX_DMADONE 0x0400 266249259Sdim 267249259Sdim#define STE_IMR_HOSTERR 0x0002 268249259Sdim#define STE_IMR_TX_DONE 0x0004 269249259Sdim#define STE_IMR_MACCTL_FRAME 0x0008 270249259Sdim#define STE_IMR_RX_DONE 0x0010 271249259Sdim#define STE_IMR_RX_EARLY 0x0020 272249259Sdim#define STE_IMR_SOFTINTR 0x0040 273249259Sdim#define STE_IMR_STATS_OFLOW 0x0080 274249259Sdim#define STE_IMR_LINKEVENT 0x0100 275249259Sdim#define STE_IMR_TX_DMADONE 0x0200 276249259Sdim#define STE_IMR_RX_DMADONE 0x0400 277249259Sdim 278249259Sdim#define STE_INTRS \ 279249259Sdim (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 280249259Sdim STE_IMR_TX_DONE|STE_IMR_HOSTERR| \ 281249259Sdim STE_IMR_LINKEVENT) 282249259Sdim 283249259Sdim#define STE_ISR_INTLATCH 0x0001 284249259Sdim#define STE_ISR_HOSTERR 0x0002 285249259Sdim#define STE_ISR_TX_DONE 0x0004 286249259Sdim#define STE_ISR_MACCTL_FRAME 0x0008 287249259Sdim#define STE_ISR_RX_DONE 0x0010 288249259Sdim#define STE_ISR_RX_EARLY 0x0020 289249259Sdim#define STE_ISR_SOFTINTR 0x0040 290249259Sdim#define STE_ISR_STATS_OFLOW 0x0080 291249259Sdim#define STE_ISR_LINKEVENT 0x0100 292249259Sdim#define STE_ISR_TX_DMADONE 0x0200 293249259Sdim#define STE_ISR_RX_DMADONE 0x0400 294249259Sdim 295249259Sdim/* 296249259Sdim * Note: the Sundance manual gives the impression that the's 297249259Sdim * only one 32-bit MACCTL register. In fact, there are two 298249259Sdim * 16-bit registers side by side, and you have to access them 299249259Sdim * separately. 300249259Sdim */ 301249259Sdim#define STE_MACCTL0_IPG 0x0003 302249259Sdim#define STE_MACCTL0_FULLDUPLEX 0x0020 303249259Sdim#define STE_MACCTL0_RX_GIANTS 0x0040 304249259Sdim#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 305249259Sdim#define STE_MACCTL0_RX_FCS 0x0200 306249259Sdim#define STE_MACCTL0_FIFOLOOPBK 0x0400 307249259Sdim#define STE_MACCTL0_MACLOOPBK 0x0800 308249259Sdim 309249259Sdim#define STE_MACCTL1_COLLDETECT 0x0001 310249259Sdim#define STE_MACCTL1_CARRSENSE 0x0002 311249259Sdim#define STE_MACCTL1_TX_BUSY 0x0004 312249259Sdim#define STE_MACCTL1_TX_ERROR 0x0008 313249259Sdim#define STE_MACCTL1_STATS_ENABLE 0x0020 314249259Sdim#define STE_MACCTL1_STATS_DISABLE 0x0040 315249259Sdim#define STE_MACCTL1_STATS_ENABLED 0x0080 316249259Sdim#define STE_MACCTL1_TX_ENABLE 0x0100 317249259Sdim#define STE_MACCTL1_TX_DISABLE 0x0200 318249259Sdim#define STE_MACCTL1_TX_ENABLED 0x0400 319249259Sdim#define STE_MACCTL1_RX_ENABLE 0x0800 320249259Sdim#define STE_MACCTL1_RX_DISABLE 0x1000 321249259Sdim#define STE_MACCTL1_RX_ENABLED 0x2000 322249259Sdim#define STE_MACCTL1_PAUSED 0x4000 323249259Sdim 324249259Sdim#define STE_IPG_96BT 0x00000000 325249259Sdim#define STE_IPG_128BT 0x00000001 326249259Sdim#define STE_IPG_224BT 0x00000002 327249259Sdim#define STE_IPG_544BT 0x00000003 328249259Sdim 329249259Sdim#define STE_RXMODE_UNICAST 0x01 330249259Sdim#define STE_RXMODE_ALLMULTI 0x02 331249259Sdim#define STE_RXMODE_BROADCAST 0x04 332249259Sdim#define STE_RXMODE_PROMISC 0x08 333249259Sdim#define STE_RXMODE_MULTIHASH 0x10 334249259Sdim#define STE_RXMODE_ALLIPMULTI 0x20 335249259Sdim 336249259Sdim#define STE_PHYCTL_MCLK 0x01 337249259Sdim#define STE_PHYCTL_MDATA 0x02 338249259Sdim#define STE_PHYCTL_MDIR 0x04 339249259Sdim#define STE_PHYCTL_CLK25_DISABLE 0x08 340249259Sdim#define STE_PHYCTL_DUPLEXPOLARITY 0x10 341249259Sdim#define STE_PHYCTL_DUPLEXSTAT 0x20 342249259Sdim#define STE_PHYCTL_SPEEDSTAT 0x40 343249259Sdim#define STE_PHYCTL_LINKSTAT 0x80 344249259Sdim 345249259Sdim/* 346249259Sdim * EEPROM offsets. 347249259Sdim */ 348249259Sdim#define STE_EEADDR_CONFIGPARM 0x00 349249259Sdim#define STE_EEADDR_ASICCTL 0x02 350249259Sdim#define STE_EEADDR_SUBSYS_ID 0x04 351249259Sdim#define STE_EEADDR_SUBVEN_ID 0x08 352249259Sdim 353249259Sdim#define STE_EEADDR_NODE0 0x10 354249259Sdim#define STE_EEADDR_NODE1 0x12 355249259Sdim#define STE_EEADDR_NODE2 0x14 356249259Sdim 357249259Sdim/* PCI registers */ 358249259Sdim#define STE_PCI_VENDOR_ID 0x00 359249259Sdim#define STE_PCI_DEVICE_ID 0x02 360249259Sdim#define STE_PCI_COMMAND 0x04 361249259Sdim#define STE_PCI_STATUS 0x06 362249259Sdim#define STE_PCI_CLASSCODE 0x09 363249259Sdim#define STE_PCI_LATENCY_TIMER 0x0D 364249259Sdim#define STE_PCI_HEADER_TYPE 0x0E 365249259Sdim#define STE_PCI_LOIO 0x10 366249259Sdim#define STE_PCI_LOMEM 0x14 367249259Sdim#define STE_PCI_BIOSROM 0x30 368249259Sdim#define STE_PCI_INTLINE 0x3C 369249259Sdim#define STE_PCI_INTPIN 0x3D 370249259Sdim#define STE_PCI_MINGNT 0x3E 371249259Sdim#define STE_PCI_MINLAT 0x0F 372249259Sdim 373249259Sdim#define STE_PCI_CAPID 0x50 /* 8 bits */ 374249259Sdim#define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 375249259Sdim#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 376249259Sdim#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 377249259Sdim 378249259Sdim#define STE_PSTATE_MASK 0x0003 379249259Sdim#define STE_PSTATE_D0 0x0000 380249259Sdim#define STE_PSTATE_D1 0x0002 381249259Sdim#define STE_PSTATE_D2 0x0002 382249259Sdim#define STE_PSTATE_D3 0x0003 383249259Sdim#define STE_PME_EN 0x0010 384249259Sdim#define STE_PME_STATUS 0x8000 385249259Sdim 386249259Sdim 387249259Sdimstruct ste_stats { 388249259Sdim u_int32_t ste_rx_bytes; 389249259Sdim u_int32_t ste_tx_bytes; 390249259Sdim u_int16_t ste_tx_frames; 391249259Sdim u_int16_t ste_rx_frames; 392249259Sdim u_int8_t ste_carrsense_errs; 393249259Sdim u_int8_t ste_late_colls; 394249259Sdim u_int8_t ste_multi_colls; 395249259Sdim u_int8_t ste_single_colls; 396249259Sdim u_int8_t ste_tx_frames_defered; 397249259Sdim u_int8_t ste_rx_lost_frames; 398249259Sdim u_int8_t ste_tx_excess_defers; 399249259Sdim u_int8_t ste_tx_abort_excess_colls; 400249259Sdim u_int8_t ste_tx_bcast_frames; 401249259Sdim u_int8_t ste_rx_bcast_frames; 402249259Sdim u_int8_t ste_tx_mcast_frames; 403249259Sdim u_int8_t ste_rx_mcast_frames; 404249259Sdim}; 405249259Sdim 406249259Sdimstruct ste_frag { 407249259Sdim u_int32_t ste_addr; 408249259Sdim u_int32_t ste_len; 409249259Sdim}; 410249259Sdim 411249259Sdim#define STE_FRAG_LAST 0x80000000 412249259Sdim#define STE_FRAG_LEN 0x00001FFF 413249259Sdim 414249259Sdim#define STE_MAXFRAGS 8 415249259Sdim 416249259Sdimstruct ste_desc { 417249259Sdim u_int32_t ste_next; 418249259Sdim u_int32_t ste_ctl; 419249259Sdim struct ste_frag ste_frags[STE_MAXFRAGS]; 420249259Sdim}; 421249259Sdim 422249259Sdimstruct ste_desc_onefrag { 423249259Sdim u_int32_t ste_next; 424249259Sdim u_int32_t ste_status; 425249259Sdim struct ste_frag ste_frag; 426249259Sdim}; 427249259Sdim 428249259Sdim#define STE_TXCTL_WORDALIGN 0x00000003 429249259Sdim#define STE_TXCTL_FRAMEID 0x000003FC 430249259Sdim#define STE_TXCTL_NOCRC 0x00002000 431249259Sdim#define STE_TXCTL_TXINTR 0x00008000 432249259Sdim#define STE_TXCTL_DMADONE 0x00010000 433249259Sdim#define STE_TXCTL_DMAINTR 0x80000000 434249259Sdim 435249259Sdim#define STE_RXSTAT_FRAMELEN 0x00001FFF 436249259Sdim#define STE_RXSTAT_FRAME_ERR 0x00004000 437249259Sdim#define STE_RXSTAT_DMADONE 0x00008000 438249259Sdim#define STE_RXSTAT_FIFO_OFLOW 0x00010000 439249259Sdim#define STE_RXSTAT_RUNT 0x00020000 440249259Sdim#define STE_RXSTAT_ALIGNERR 0x00040000 441249259Sdim#define STE_RXSTAT_CRCERR 0x00080000 442249259Sdim#define STE_RXSTAT_GIANT 0x00100000 443249259Sdim#define STE_RXSTAT_DRIBBLEBITS 0x00800000 444249259Sdim#define STE_RXSTAT_DMA_OFLOW 0x01000000 445249259Sdim#define STE_RXATAT_ONEBUF 0x10000000 446249259Sdim 447249259Sdim/* 448249259Sdim * register space access macros 449249259Sdim */ 450249259Sdim#define CSR_WRITE_4(sc, reg, val) \ 451249259Sdim bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 452249259Sdim#define CSR_WRITE_2(sc, reg, val) \ 453249259Sdim bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 454249259Sdim#define CSR_WRITE_1(sc, reg, val) \ 455249259Sdim bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 456249259Sdim 457249259Sdim#define CSR_READ_4(sc, reg) \ 458249259Sdim bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 459249259Sdim#define CSR_READ_2(sc, reg) \ 460249259Sdim bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 461249259Sdim#define CSR_READ_1(sc, reg) \ 462249259Sdim bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 463249259Sdim 464249259Sdim#define STE_TIMEOUT 1000 465249259Sdim#define STE_MIN_FRAMELEN 60 466249259Sdim#define STE_PACKET_SIZE 1536 467249259Sdim#define ETHER_ALIGN 2 468249259Sdim#define STE_RX_LIST_CNT 64 469249259Sdim#define STE_TX_LIST_CNT 128 470249259Sdim#define STE_INC(x, y) (x) = (x + 1) % y 471249259Sdim#define STE_NEXT(x, y) (x + 1) % y 472249259Sdim 473249259Sdimstruct ste_type { 474249259Sdim u_int16_t ste_vid; 475249259Sdim u_int16_t ste_did; 476249259Sdim char *ste_name; 477249259Sdim}; 478249259Sdim 479249259Sdimstruct ste_list_data { 480249259Sdim struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 481249259Sdim struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 482249259Sdim}; 483249259Sdim 484249259Sdimstruct ste_chain { 485249259Sdim struct ste_desc *ste_ptr; 486249259Sdim struct mbuf *ste_mbuf; 487249259Sdim struct ste_chain *ste_next; 488249259Sdim u_int32_t ste_phys; 489249259Sdim}; 490249259Sdim 491249259Sdimstruct ste_chain_onefrag { 492249259Sdim struct ste_desc_onefrag *ste_ptr; 493249259Sdim struct mbuf *ste_mbuf; 494249259Sdim struct ste_chain_onefrag *ste_next; 495249259Sdim}; 496249259Sdim 497249259Sdimstruct ste_chain_data { 498249259Sdim struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 499249259Sdim struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 500249259Sdim struct ste_chain_onefrag *ste_rx_head; 501249259Sdim 502249259Sdim int ste_tx_prod; 503249259Sdim int ste_tx_cons; 504249259Sdim}; 505249259Sdim 506249259Sdimstruct ste_softc { 507249259Sdim struct arpcom arpcom; 508249259Sdim bus_space_tag_t ste_btag; 509249259Sdim bus_space_handle_t ste_bhandle; 510249259Sdim struct resource *ste_res; 511249259Sdim struct resource *ste_irq; 512249259Sdim void *ste_intrhand; 513249259Sdim struct ste_type *ste_info; 514249259Sdim device_t ste_miibus; 515249259Sdim device_t ste_dev; 516249259Sdim int ste_unit; 517249259Sdim int ste_tx_thresh; 518249259Sdim u_int8_t ste_link; 519249259Sdim int ste_if_flags; 520249259Sdim struct ste_chain *ste_tx_prev; 521249259Sdim struct ste_list_data *ste_ldata; 522249259Sdim struct ste_chain_data ste_cdata; 523249259Sdim struct callout_handle ste_stat_ch; 524249259Sdim struct mtx ste_mtx; 525249259Sdim u_int8_t ste_one_phy; 526249259Sdim#ifdef DEVICE_POLLING 527249259Sdim int rxcycles; 528249259Sdim#endif 529249259Sdim}; 530249259Sdim 531249259Sdim#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 532249259Sdim#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 533249259Sdim#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 534249259Sdim 535249259Sdimstruct ste_mii_frame { 536249259Sdim u_int8_t mii_stdelim; 537249259Sdim u_int8_t mii_opcode; 538249259Sdim u_int8_t mii_phyaddr; 539249259Sdim u_int8_t mii_regaddr; 540249259Sdim u_int8_t mii_turnaround; 541249259Sdim u_int16_t mii_data; 542249259Sdim}; 543249259Sdim 544249259Sdim/* 545249259Sdim * MII constants 546249259Sdim */ 547249259Sdim#define STE_MII_STARTDELIM 0x01 548249259Sdim#define STE_MII_READOP 0x02 549249259Sdim#define STE_MII_WRITEOP 0x01 550249259Sdim#define STE_MII_TURNAROUND 0x02 551249259Sdim 552249259Sdim#ifdef __alpha__ 553249259Sdim#undef vtophys 554249259Sdim#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 555249259Sdim#endif 556249259Sdim