if_stereg.h revision 67089
150128Swpaul/* 250128Swpaul * Copyright (c) 1997, 1998, 1999 350128Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450128Swpaul * 550128Swpaul * Redistribution and use in source and binary forms, with or without 650128Swpaul * modification, are permitted provided that the following conditions 750128Swpaul * are met: 850128Swpaul * 1. Redistributions of source code must retain the above copyright 950128Swpaul * notice, this list of conditions and the following disclaimer. 1050128Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150128Swpaul * notice, this list of conditions and the following disclaimer in the 1250128Swpaul * documentation and/or other materials provided with the distribution. 1350128Swpaul * 3. All advertising materials mentioning features or use of this software 1450128Swpaul * must display the following acknowledgement: 1550128Swpaul * This product includes software developed by Bill Paul. 1650128Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750128Swpaul * may be used to endorse or promote products derived from this software 1850128Swpaul * without specific prior written permission. 1950128Swpaul * 2050128Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150128Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250128Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350128Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450128Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550128Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650128Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750128Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850128Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950128Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050128Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150128Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_stereg.h 67089 2000-10-13 18:35:49Z wpaul $ 3350128Swpaul */ 3450128Swpaul 3550128Swpaul/* 3650128Swpaul * Sundance PCI device/vendor ID for the 3750128Swpaul * ST201 chip. 3850128Swpaul */ 3950128Swpaul#define ST_VENDORID 0x13F0 4050128Swpaul#define ST_DEVICEID_ST201 0x0201 4150128Swpaul 4250128Swpaul/* 4350128Swpaul * D-Link PCI device/vendor ID for the DFE-550TX. 4450128Swpaul */ 4550128Swpaul#define DL_VENDORID 0x1186 4650128Swpaul#define DL_DEVICEID_550TX 0x1002 4750128Swpaul 4850128Swpaul/* 4950128Swpaul * Register definitions for the Sundance Technologies ST201 PCI 5050128Swpaul * fast ethernet controller. The register space is 128 bytes long and 5150128Swpaul * can be accessed using either PCI I/O space or PCI memory mapping. 5250128Swpaul * There are 32-bit, 16-bit and 8-bit registers. 5350128Swpaul */ 5450128Swpaul 5550128Swpaul#define STE_DMACTL 0x00 5650128Swpaul#define STE_TX_DMALIST_PTR 0x04 5750128Swpaul#define STE_TX_DMABURST_THRESH 0x08 5850128Swpaul#define STE_TX_DMAURG_THRESH 0x09 5950128Swpaul#define STE_TX_DMAPOLL_PERIOD 0x0A 6050128Swpaul#define STE_RX_DMASTATUS 0x0C 6150128Swpaul#define STE_RX_DMALIST_PTR 0x10 6250128Swpaul#define STE_RX_DMABURST_THRESH 0x14 6350128Swpaul#define STE_RX_DMAURG_THRESH 0x15 6450128Swpaul#define STE_RX_DMAPOLL_PERIOD 0x16 6550128Swpaul#define STE_DEBUGCTL 0x1A 6650128Swpaul#define STE_ASICCTL 0x30 6750128Swpaul#define STE_EEPROM_DATA 0x34 6850128Swpaul#define STE_EEPROM_CTL 0x36 6950128Swpaul#define STE_FIFOCTL 0x3A 7050128Swpaul#define STE_TX_STARTTHRESH 0x3C 7150128Swpaul#define STE_RX_EARLYTHRESH 0x3E 7250128Swpaul#define STE_EXT_ROMADDR 0x40 7350128Swpaul#define STE_EXT_ROMDATA 0x44 7450128Swpaul#define STE_WAKE_EVENT 0x45 7550128Swpaul#define STE_TX_STATUS 0x46 7650128Swpaul#define STE_TX_FRAMEID 0x47 7750128Swpaul#define STE_COUNTDOWN 0x48 7850128Swpaul#define STE_ISR_ACK 0x4A 7950128Swpaul#define STE_IMR 0x4C 8050128Swpaul#define STE_ISR 0x4E 8150128Swpaul#define STE_MACCTL0 0x50 8250128Swpaul#define STE_MACCTL1 0x52 8350128Swpaul#define STE_PAR0 0x54 8450128Swpaul#define STE_PAR1 0x56 8550128Swpaul#define STE_PAR2 0x58 8650128Swpaul#define STE_MAX_FRAMELEN 0x5A 8750128Swpaul#define STE_RX_MODE 0x5C 8850128Swpaul#define STE_TX_RECLAIM_THRESH 0x5D 8950128Swpaul#define STE_PHYCTL 0x5E 9050128Swpaul#define STE_MAR0 0x60 9150128Swpaul#define STE_MAR1 0x64 9250128Swpaul#define STE_STATS 0x68 9350128Swpaul 9450128Swpaul#define STE_DMACTL_RXDMA_STOPPED 0x00000001 9550128Swpaul#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 9650128Swpaul#define STE_DMACTL_TXDMA_STOPPED 0x00000004 9750128Swpaul#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 9850128Swpaul#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 9950128Swpaul#define STE_DMACTL_RXDMA_STALL 0x00000100 10050128Swpaul#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 10150128Swpaul#define STE_DMACTL_TXDMA_STALL 0x00000400 10250128Swpaul#define STE_DMACTL_TXDMA_UNSTALL 0x00000800 10350128Swpaul#define STE_DMACTL_TXDMA_INPROG 0x00004000 10450128Swpaul#define STE_DMACTL_DMA_HALTINPROG 0x00008000 10550128Swpaul#define STE_DMACTL_RXEARLY_ENABLE 0x00020000 10650128Swpaul#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 10750128Swpaul#define STE_DMACTL_COUNTDOWN_MODE 0x00080000 10850128Swpaul#define STE_DMACTL_MWI_DISABLE 0x00100000 10950128Swpaul#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 11050128Swpaul#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 11150128Swpaul#define STE_DMACTL_TARGET_ABORT 0x40000000 11250128Swpaul#define STE_DMACTL_MASTER_ABORT 0x80000000 11350128Swpaul 11450128Swpaul/* 11550128Swpaul * TX DMA burst thresh is the number of 32-byte blocks that 11650128Swpaul * must be loaded into the TX Fifo before a TXDMA burst request 11750128Swpaul * will be issued. 11850128Swpaul */ 11950128Swpaul#define STE_TXDMABURST_THRESH 0x1F 12050128Swpaul 12150128Swpaul/* 12250128Swpaul * The number of 32-byte blocks in the TX FIFO falls below the 12350128Swpaul * TX DMA urgent threshold, a TX DMA urgent request will be 12450128Swpaul * generated. 12550128Swpaul */ 12650128Swpaul#define STE_TXDMAURG_THRESH 0x3F 12750128Swpaul 12850128Swpaul/* 12950128Swpaul * Number of 320ns intervals between polls of the TXDMA next 13050128Swpaul * descriptor pointer (if we're using polling mode). 13150128Swpaul */ 13250128Swpaul#define STE_TXDMA_POLL_PERIOD 0x7F 13350128Swpaul 13450128Swpaul#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 13550128Swpaul#define STE_RX_DMASTATUS_RXERR 0x00004000 13650128Swpaul#define STE_RX_DMASTATUS_DMADONE 0x00008000 13750128Swpaul#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 13850128Swpaul#define STE_RX_DMASTATUS_RUNT 0x00020000 13950128Swpaul#define STE_RX_DMASTATUS_ALIGNERR 0x00040000 14050128Swpaul#define STE_RX_DMASTATUS_CRCERR 0x00080000 14150128Swpaul#define STE_RX_DMASTATUS_GIANT 0x00100000 14250128Swpaul#define STE_RX_DMASTATUS_DRIBBLE 0x00800000 14350128Swpaul#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 14450128Swpaul 14550128Swpaul/* 14650128Swpaul * RX DMA burst thresh is the number of 32-byte blocks that 14750128Swpaul * must be present in the RX FIFO before a RXDMA bus master 14850128Swpaul * request will be issued. 14950128Swpaul */ 15050128Swpaul#define STE_RXDMABURST_THRESH 0xFF 15150128Swpaul 15250128Swpaul/* 15350128Swpaul * The number of 32-byte blocks in the RX FIFO falls below the 15450128Swpaul * RX DMA urgent threshold, a RX DMA urgent request will be 15550128Swpaul * generated. 15650128Swpaul */ 15750128Swpaul#define STE_RXDMAURG_THRESH 0x1F 15850128Swpaul 15950128Swpaul/* 16050128Swpaul * Number of 320ns intervals between polls of the RXDMA complete 16150128Swpaul * bit in the status field on the current RX descriptor (if we're 16250128Swpaul * using polling mode). 16350128Swpaul */ 16450128Swpaul#define STE_RXDMA_POLL_PERIOD 0x7F 16550128Swpaul 16650128Swpaul#define STE_DEBUGCTL_GPIO0_CTL 0x0001 16750128Swpaul#define STE_DEBUGCTL_GPIO1_CTL 0x0002 16850128Swpaul#define STE_DEBUGCTL_GPIO0_DATA 0x0004 16950128Swpaul#define STE_DEBUGCTL_GPIO1_DATA 0x0008 17050128Swpaul 17150128Swpaul#define STE_ASICCTL_ROMSIZE 0x00000002 17250128Swpaul#define STE_ASICCTL_TX_LARGEPKTS 0x00000004 17350128Swpaul#define STE_ASICCTL_RX_LARGEPKTS 0x00000008 17450128Swpaul#define STE_ASICCTL_EXTROM_DISABLE 0x00000010 17550128Swpaul#define STE_ASICCTL_PHYSPEED_10 0x00000020 17650128Swpaul#define STE_ASICCTL_PHYSPEED_100 0x00000040 17750128Swpaul#define STE_ASICCTL_PHYMEDIA 0x00000080 17850128Swpaul#define STE_ASICCTL_FORCEDCONFIG 0x00000700 17950128Swpaul#define STE_ASICCTL_D3RESET_DISABLE 0x00000800 18050128Swpaul#define STE_ASICCTL_SPEEDUPMODE 0x00002000 18150128Swpaul#define STE_ASICCTL_LEDMODE 0x00004000 18250128Swpaul#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 18350128Swpaul#define STE_ASICCTL_GLOBAL_RESET 0x00010000 18450128Swpaul#define STE_ASICCTL_RX_RESET 0x00020000 18550128Swpaul#define STE_ASICCTL_TX_RESET 0x00040000 18650128Swpaul#define STE_ASICCTL_DMA_RESET 0x00080000 18750128Swpaul#define STE_ASICCTL_FIFO_RESET 0x00100000 18850128Swpaul#define STE_ASICCTL_NETWORK_RESET 0x00200000 18950128Swpaul#define STE_ASICCTL_HOST_RESET 0x00400000 19050128Swpaul#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 19150128Swpaul#define STE_ASICCTL_EXTRESET_RESET 0x01000000 19250128Swpaul#define STE_ASICCTL_SOFTINTR 0x02000000 19350128Swpaul#define STE_ASICCTL_RESET_BUSY 0x04000000 19450128Swpaul 19550128Swpaul#define STE_ASICCTL1_GLOBAL_RESET 0x0001 19650128Swpaul#define STE_ASICCTL1_RX_RESET 0x0002 19750128Swpaul#define STE_ASICCTL1_TX_RESET 0x0004 19850128Swpaul#define STE_ASICCTL1_DMA_RESET 0x0008 19950128Swpaul#define STE_ASICCTL1_FIFO_RESET 0x0010 20050128Swpaul#define STE_ASICCTL1_NETWORK_RESET 0x0020 20150128Swpaul#define STE_ASICCTL1_HOST_RESET 0x0040 20250128Swpaul#define STE_ASICCTL1_AUTOINIT_RESET 0x0080 20350128Swpaul#define STE_ASICCTL1_EXTRESET_RESET 0x0100 20450128Swpaul#define STE_ASICCTL1_SOFTINTR 0x0200 20550128Swpaul#define STE_ASICCTL1_RESET_BUSY 0x0400 20650128Swpaul 20750128Swpaul#define STE_EECTL_ADDR 0x00FF 20850128Swpaul#define STE_EECTL_OPCODE 0x0300 20950128Swpaul#define STE_EECTL_BUSY 0x1000 21050128Swpaul 21150128Swpaul#define STE_EEOPCODE_WRITE 0x0100 21250128Swpaul#define STE_EEOPCODE_READ 0x0200 21350128Swpaul#define STE_EEOPCODE_ERASE 0x0300 21450128Swpaul 21550128Swpaul#define STE_FIFOCTL_RAMTESTMODE 0x0001 21650128Swpaul#define STE_FIFOCTL_OVERRUNMODE 0x0200 21750128Swpaul#define STE_FIFOCTL_RXFIFOFULL 0x0800 21850128Swpaul#define STE_FIFOCTL_TX_BUSY 0x4000 21950128Swpaul#define STE_FIFOCTL_RX_BUSY 0x8000 22050128Swpaul 22150128Swpaul/* 22250128Swpaul * The number of bytes that must in present in the TX FIFO before 22350128Swpaul * transmission begins. Value should be in increments of 4 bytes. 22450128Swpaul */ 22550128Swpaul#define STE_TXSTART_THRESH 0x1FFF 22650128Swpaul 22750128Swpaul/* 22850128Swpaul * Number of bytes that must be present in the RX FIFO before 22950128Swpaul * an RX EARLY interrupt is generated. 23050128Swpaul */ 23150128Swpaul#define STE_RXEARLY_THRESH 0x1FFF 23250128Swpaul 23350128Swpaul#define STE_WAKEEVENT_WAKEPKT_ENB 0x01 23450128Swpaul#define STE_WAKEEVENT_MAGICPKT_ENB 0x02 23550128Swpaul#define STE_WAKEEVENT_LINKEVT_ENB 0x04 23650128Swpaul#define STE_WAKEEVENT_WAKEPOLARITY 0x08 23750128Swpaul#define STE_WAKEEVENT_WAKEPKTEVENT 0x10 23850128Swpaul#define STE_WAKEEVENT_MAGICPKTEVENT 0x20 23950128Swpaul#define STE_WAKEEVENT_LINKEVENT 0x40 24050128Swpaul#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 24150128Swpaul 24250128Swpaul#define STE_TXSTATUS_RECLAIMERR 0x02 24350128Swpaul#define STE_TXSTATUS_STATSOFLOW 0x04 24450128Swpaul#define STE_TXSTATUS_EXCESSCOLLS 0x08 24550128Swpaul#define STE_TXSTATUS_UNDERRUN 0x10 24650128Swpaul#define STE_TXSTATUS_TXINTR_REQ 0x40 24750128Swpaul#define STE_TXSTATUS_TXDONE 0x80 24850128Swpaul 24950128Swpaul#define STE_ISRACK_INTLATCH 0x0001 25050128Swpaul#define STE_ISRACK_HOSTERR 0x0002 25150128Swpaul#define STE_ISRACK_TX_DONE 0x0004 25250128Swpaul#define STE_ISRACK_MACCTL_FRAME 0x0008 25350128Swpaul#define STE_ISRACK_RX_DONE 0x0010 25450128Swpaul#define STE_ISRACK_RX_EARLY 0x0020 25550128Swpaul#define STE_ISRACK_SOFTINTR 0x0040 25650128Swpaul#define STE_ISRACK_STATS_OFLOW 0x0080 25750128Swpaul#define STE_ISRACK_LINKEVENT 0x0100 25850128Swpaul#define STE_ISRACK_TX_DMADONE 0x0200 25950128Swpaul#define STE_ISRACK_RX_DMADONE 0x0400 26050128Swpaul 26150128Swpaul#define STE_IMR_HOSTERR 0x0002 26250128Swpaul#define STE_IMR_TX_DONE 0x0004 26350128Swpaul#define STE_IMR_MACCTL_FRAME 0x0008 26450128Swpaul#define STE_IMR_RX_DONE 0x0010 26550128Swpaul#define STE_IMR_RX_EARLY 0x0020 26650128Swpaul#define STE_IMR_SOFTINTR 0x0040 26750128Swpaul#define STE_IMR_STATS_OFLOW 0x0080 26850128Swpaul#define STE_IMR_LINKEVENT 0x0100 26950128Swpaul#define STE_IMR_TX_DMADONE 0x0200 27050128Swpaul#define STE_IMR_RX_DMADONE 0x0400 27150128Swpaul 27250128Swpaul#define STE_INTRS \ 27350128Swpaul (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE|STE_IMR_STATS_OFLOW| \ 27450128Swpaul STE_IMR_TX_DONE|STE_IMR_HOSTERR|STE_IMR_RX_EARLY) 27550128Swpaul 27650128Swpaul#define STE_ISR_INTLATCH 0x0001 27750128Swpaul#define STE_ISR_HOSTERR 0x0002 27850128Swpaul#define STE_ISR_TX_DONE 0x0004 27950128Swpaul#define STE_ISR_MACCTL_FRAME 0x0008 28050128Swpaul#define STE_ISR_RX_DONE 0x0010 28150128Swpaul#define STE_ISR_RX_EARLY 0x0020 28250128Swpaul#define STE_ISR_SOFTINTR 0x0040 28350128Swpaul#define STE_ISR_STATS_OFLOW 0x0080 28450128Swpaul#define STE_ISR_LINKEVENT 0x0100 28550128Swpaul#define STE_ISR_TX_DMADONE 0x0200 28650128Swpaul#define STE_ISR_RX_DMADONE 0x0400 28750128Swpaul 28850128Swpaul/* 28950128Swpaul * Note: the Sundance manual gives the impression that the's 29050128Swpaul * only one 32-bit MACCTL register. In fact, there are two 29150128Swpaul * 16-bit registers side by side, and you have to access them 29250128Swpaul * separately. 29350128Swpaul */ 29450128Swpaul#define STE_MACCTL0_IPG 0x0003 29550128Swpaul#define STE_MACCTL0_FULLDUPLEX 0x0020 29650128Swpaul#define STE_MACCTL0_RX_GIANTS 0x0040 29750128Swpaul#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 29850128Swpaul#define STE_MACCTL0_RX_FCS 0x0200 29950128Swpaul#define STE_MACCTL0_FIFOLOOPBK 0x0400 30050128Swpaul#define STE_MACCTL0_MACLOOPBK 0x0800 30150128Swpaul 30250128Swpaul#define STE_MACCTL1_COLLDETECT 0x0001 30350128Swpaul#define STE_MACCTL1_CARRSENSE 0x0002 30450128Swpaul#define STE_MACCTL1_TX_BUSY 0x0004 30550128Swpaul#define STE_MACCTL1_TX_ERROR 0x0008 30650128Swpaul#define STE_MACCTL1_STATS_ENABLE 0x0020 30750128Swpaul#define STE_MACCTL1_STATS_DISABLE 0x0040 30850128Swpaul#define STE_MACCTL1_STATS_ENABLED 0x0080 30950128Swpaul#define STE_MACCTL1_TX_ENABLE 0x0100 31050128Swpaul#define STE_MACCTL1_TX_DISABLE 0x0200 31150128Swpaul#define STE_MACCTL1_TX_ENABLED 0x0400 31250128Swpaul#define STE_MACCTL1_RX_ENABLE 0x0800 31350128Swpaul#define STE_MACCTL1_RX_DISABLE 0x1000 31450128Swpaul#define STE_MACCTL1_RX_ENABLED 0x2000 31550128Swpaul#define STE_MACCTL1_PAUSED 0x4000 31650128Swpaul 31750128Swpaul#define STE_IPG_96BT 0x00000000 31850128Swpaul#define STE_IPG_128BT 0x00000001 31950128Swpaul#define STE_IPG_224BT 0x00000002 32050128Swpaul#define STE_IPG_544BT 0x00000003 32150128Swpaul 32250128Swpaul#define STE_RXMODE_UNICAST 0x01 32350128Swpaul#define STE_RXMODE_ALLMULTI 0x02 32450128Swpaul#define STE_RXMODE_BROADCAST 0x04 32550128Swpaul#define STE_RXMODE_PROMISC 0x08 32650128Swpaul#define STE_RXMODE_MULTIHASH 0x10 32750128Swpaul#define STE_RXMODE_ALLIPMULTI 0x20 32850128Swpaul 32950128Swpaul#define STE_PHYCTL_MCLK 0x01 33050128Swpaul#define STE_PHYCTL_MDATA 0x02 33150128Swpaul#define STE_PHYCTL_MDIR 0x04 33250128Swpaul#define STE_PHYCTL_CLK25_DISABLE 0x08 33350128Swpaul#define STE_PHYCTL_DUPLEXPOLARITY 0x10 33450128Swpaul#define STE_PHYCTL_DUPLEXSTAT 0x20 33550128Swpaul#define STE_PHYCTL_SPEEDSTAT 0x40 33650128Swpaul#define STE_PHYCTL_LINKSTAT 0x80 33750128Swpaul 33850128Swpaul/* 33950128Swpaul * EEPROM offsets. 34050128Swpaul */ 34150128Swpaul#define STE_EEADDR_CONFIGPARM 0x00 34250128Swpaul#define STE_EEADDR_ASICCTL 0x02 34350128Swpaul#define STE_EEADDR_SUBSYS_ID 0x04 34450128Swpaul#define STE_EEADDR_SUBVEN_ID 0x08 34550128Swpaul 34650128Swpaul#define STE_EEADDR_NODE0 0x10 34750128Swpaul#define STE_EEADDR_NODE1 0x12 34850128Swpaul#define STE_EEADDR_NODE2 0x14 34950128Swpaul 35050128Swpaul/* PCI registers */ 35150128Swpaul#define STE_PCI_VENDOR_ID 0x00 35250128Swpaul#define STE_PCI_DEVICE_ID 0x02 35350128Swpaul#define STE_PCI_COMMAND 0x04 35450128Swpaul#define STE_PCI_STATUS 0x06 35550128Swpaul#define STE_PCI_CLASSCODE 0x09 35650128Swpaul#define STE_PCI_LATENCY_TIMER 0x0D 35750128Swpaul#define STE_PCI_HEADER_TYPE 0x0E 35850128Swpaul#define STE_PCI_LOIO 0x10 35950128Swpaul#define STE_PCI_LOMEM 0x14 36050128Swpaul#define STE_PCI_BIOSROM 0x30 36150128Swpaul#define STE_PCI_INTLINE 0x3C 36250128Swpaul#define STE_PCI_INTPIN 0x3D 36350128Swpaul#define STE_PCI_MINGNT 0x3E 36450128Swpaul#define STE_PCI_MINLAT 0x0F 36550128Swpaul 36650128Swpaul#define STE_PCI_CAPID 0x50 /* 8 bits */ 36750128Swpaul#define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 36850128Swpaul#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 36950128Swpaul#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 37050128Swpaul 37150128Swpaul#define STE_PSTATE_MASK 0x0003 37250128Swpaul#define STE_PSTATE_D0 0x0000 37350128Swpaul#define STE_PSTATE_D1 0x0002 37450128Swpaul#define STE_PSTATE_D2 0x0002 37550128Swpaul#define STE_PSTATE_D3 0x0003 37650128Swpaul#define STE_PME_EN 0x0010 37750128Swpaul#define STE_PME_STATUS 0x8000 37850128Swpaul 37950128Swpaul 38050128Swpaulstruct ste_stats { 38150128Swpaul u_int32_t ste_rx_bytes; 38250128Swpaul u_int32_t ste_tx_bytes; 38350128Swpaul u_int16_t ste_tx_frames; 38450128Swpaul u_int16_t ste_rx_frames; 38550128Swpaul u_int8_t ste_carrsense_errs; 38650128Swpaul u_int8_t ste_late_colls; 38750128Swpaul u_int8_t ste_multi_colls; 38850128Swpaul u_int8_t ste_single_colls; 38950128Swpaul u_int8_t ste_tx_frames_defered; 39050128Swpaul u_int8_t ste_rx_lost_frames; 39150128Swpaul u_int8_t ste_tx_excess_defers; 39250128Swpaul u_int8_t ste_tx_abort_excess_colls; 39350128Swpaul u_int8_t ste_tx_bcast_frames; 39450128Swpaul u_int8_t ste_rx_bcast_frames; 39550128Swpaul u_int8_t ste_tx_mcast_frames; 39650128Swpaul u_int8_t ste_rx_mcast_frames; 39750128Swpaul}; 39850128Swpaul 39950128Swpaulstruct ste_frag { 40050128Swpaul u_int32_t ste_addr; 40150128Swpaul u_int32_t ste_len; 40250128Swpaul}; 40350128Swpaul 40450128Swpaul#define STE_FRAG_LAST 0x80000000 40550128Swpaul#define STE_FRAG_LEN 0x00001FFF 40650128Swpaul 40750128Swpaul#define STE_MAXFRAGS 63 40850128Swpaul 40950128Swpaulstruct ste_desc { 41050128Swpaul u_int32_t ste_next; 41150128Swpaul u_int32_t ste_ctl; 41250128Swpaul struct ste_frag ste_frags[STE_MAXFRAGS]; 41350128Swpaul}; 41450128Swpaul 41550128Swpaulstruct ste_desc_onefrag { 41650128Swpaul u_int32_t ste_next; 41750128Swpaul u_int32_t ste_status; 41850128Swpaul struct ste_frag ste_frag; 41950128Swpaul}; 42050128Swpaul 42150128Swpaul#define STE_TXCTL_WORDALIGN 0x00000003 42250128Swpaul#define STE_TXCTL_FRAMEID 0x000003FC 42350128Swpaul#define STE_TXCTL_NOCRC 0x00002000 42450128Swpaul#define STE_TXCTL_TXINTR 0x00008000 42550128Swpaul#define STE_TXCTL_DMADONE 0x00010000 42650128Swpaul#define STE_TXCTL_DMAINTR 0x80000000 42750128Swpaul 42850128Swpaul#define STE_RXSTAT_FRAMELEN 0x00001FFF 42950128Swpaul#define STE_RXSTAT_FRAME_ERR 0x00004000 43050128Swpaul#define STE_RXSTAT_DMADONE 0x00008000 43150128Swpaul#define STE_RXSTAT_FIFO_OFLOW 0x00010000 43250128Swpaul#define STE_RXSTAT_RUNT 0x00020000 43350128Swpaul#define STE_RXSTAT_ALIGNERR 0x00040000 43450128Swpaul#define STE_RXSTAT_CRCERR 0x00080000 43550128Swpaul#define STE_RXSTAT_GIANT 0x00100000 43650128Swpaul#define STE_RXSTAT_DRIBBLEBITS 0x00800000 43750128Swpaul#define STE_RXSTAT_DMA_OFLOW 0x01000000 43850128Swpaul#define STE_RXATAT_ONEBUF 0x10000000 43950128Swpaul 44050128Swpaul/* 44150128Swpaul * register space access macros 44250128Swpaul */ 44350128Swpaul#define CSR_WRITE_4(sc, reg, val) \ 44450128Swpaul bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 44550128Swpaul#define CSR_WRITE_2(sc, reg, val) \ 44650128Swpaul bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 44750128Swpaul#define CSR_WRITE_1(sc, reg, val) \ 44850128Swpaul bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 44950128Swpaul 45050128Swpaul#define CSR_READ_4(sc, reg) \ 45150128Swpaul bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 45250128Swpaul#define CSR_READ_2(sc, reg) \ 45350128Swpaul bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 45450128Swpaul#define CSR_READ_1(sc, reg) \ 45550128Swpaul bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 45650128Swpaul 45754268Swpaul#define STE_TIMEOUT 1000 45854268Swpaul#define STE_MIN_FRAMELEN 60 45954268Swpaul#define STE_PACKET_SIZE 1536 46054268Swpaul#define ETHER_ALIGN 2 46154268Swpaul#define STE_RX_LIST_CNT 128 46254268Swpaul#define STE_TX_LIST_CNT 256 46354268Swpaul#define STE_INC(x, y) (x) = (x + 1) % y 46450128Swpaul 46550128Swpaulstruct ste_type { 46650128Swpaul u_int16_t ste_vid; 46750128Swpaul u_int16_t ste_did; 46850128Swpaul char *ste_name; 46950128Swpaul}; 47050128Swpaul 47150128Swpaulstruct ste_list_data { 47250128Swpaul struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 47350128Swpaul struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 47450128Swpaul u_int8_t ste_pad[STE_MIN_FRAMELEN]; 47550128Swpaul}; 47650128Swpaul 47750128Swpaulstruct ste_chain { 47850128Swpaul struct ste_desc *ste_ptr; 47950128Swpaul struct mbuf *ste_mbuf; 48050128Swpaul struct ste_chain *ste_next; 48154268Swpaul struct ste_chain *ste_prev; 48254268Swpaul u_int32_t ste_phys; 48350128Swpaul}; 48450128Swpaul 48550128Swpaulstruct ste_chain_onefrag { 48650128Swpaul struct ste_desc_onefrag *ste_ptr; 48750128Swpaul struct mbuf *ste_mbuf; 48850128Swpaul struct ste_chain_onefrag *ste_next; 48950128Swpaul}; 49050128Swpaul 49150128Swpaulstruct ste_chain_data { 49250128Swpaul struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 49350128Swpaul struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 49450128Swpaul struct ste_chain_onefrag *ste_rx_head; 49550128Swpaul 49654268Swpaul int ste_tx_prod; 49754268Swpaul int ste_tx_cons; 49854268Swpaul int ste_tx_cnt; 49950128Swpaul}; 50050128Swpaul 50150128Swpaulstruct ste_softc { 50250128Swpaul struct arpcom arpcom; 50350128Swpaul bus_space_tag_t ste_btag; 50450128Swpaul bus_space_handle_t ste_bhandle; 50550128Swpaul struct resource *ste_res; 50650128Swpaul struct resource *ste_irq; 50750128Swpaul void *ste_intrhand; 50850128Swpaul struct ste_type *ste_info; 50950128Swpaul device_t ste_miibus; 51050128Swpaul int ste_unit; 51150128Swpaul int ste_tx_thresh; 51254268Swpaul u_int8_t ste_link; 51354268Swpaul int ste_if_flags; 51450128Swpaul struct ste_list_data *ste_ldata; 51550128Swpaul struct ste_chain_data ste_cdata; 51650128Swpaul struct callout_handle ste_stat_ch; 51767089Swpaul struct mtx ste_mtx; 51850128Swpaul}; 51950128Swpaul 52067089Swpaul#define STE_LOCK(_sc) mtx_enter(&(_sc)->ste_mtx, MTX_DEF) 52167089Swpaul#define STE_UNLOCK(_sc) mtx_exit(&(_sc)->ste_mtx, MTX_DEF) 52267089Swpaul 52350128Swpaulstruct ste_mii_frame { 52450128Swpaul u_int8_t mii_stdelim; 52550128Swpaul u_int8_t mii_opcode; 52650128Swpaul u_int8_t mii_phyaddr; 52750128Swpaul u_int8_t mii_regaddr; 52850128Swpaul u_int8_t mii_turnaround; 52950128Swpaul u_int16_t mii_data; 53050128Swpaul}; 53150128Swpaul 53250128Swpaul/* 53350128Swpaul * MII constants 53450128Swpaul */ 53550128Swpaul#define STE_MII_STARTDELIM 0x01 53650128Swpaul#define STE_MII_READOP 0x02 53750128Swpaul#define STE_MII_WRITEOP 0x01 53850128Swpaul#define STE_MII_TURNAROUND 0x02 53950128Swpaul 54050128Swpaul#ifdef __alpha__ 54150128Swpaul#undef vtophys 54251360Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 54350128Swpaul#endif 544