1139825Simp/*- 250128Swpaul * Copyright (c) 1997, 1998, 1999 350128Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450128Swpaul * 550128Swpaul * Redistribution and use in source and binary forms, with or without 650128Swpaul * modification, are permitted provided that the following conditions 750128Swpaul * are met: 850128Swpaul * 1. Redistributions of source code must retain the above copyright 950128Swpaul * notice, this list of conditions and the following disclaimer. 1050128Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150128Swpaul * notice, this list of conditions and the following disclaimer in the 1250128Swpaul * documentation and/or other materials provided with the distribution. 1350128Swpaul * 3. All advertising materials mentioning features or use of this software 1450128Swpaul * must display the following acknowledgement: 1550128Swpaul * This product includes software developed by Bill Paul. 1650128Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750128Swpaul * may be used to endorse or promote products derived from this software 1850128Swpaul * without specific prior written permission. 1950128Swpaul * 2050128Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150128Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250128Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350128Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450128Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550128Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650128Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750128Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850128Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950128Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050128Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150128Swpaul * 3250477Speter * $FreeBSD: releng/10.3/sys/dev/ste/if_stereg.h 226995 2011-11-01 16:13:59Z marius $ 3350128Swpaul */ 3450128Swpaul 3550128Swpaul/* 3650128Swpaul * Sundance PCI device/vendor ID for the 3750128Swpaul * ST201 chip. 3850128Swpaul */ 3950128Swpaul#define ST_VENDORID 0x13F0 40167407Syongari#define ST_DEVICEID_ST201_1 0x0200 41167407Syongari#define ST_DEVICEID_ST201_2 0x0201 4250128Swpaul 4350128Swpaul/* 44108237Sphk * D-Link PCI device/vendor ID for the DL10050[AB] chip 4550128Swpaul */ 4650128Swpaul#define DL_VENDORID 0x1186 47108237Sphk#define DL_DEVICEID_DL10050 0x1002 4850128Swpaul 4950128Swpaul/* 5050128Swpaul * Register definitions for the Sundance Technologies ST201 PCI 5150128Swpaul * fast ethernet controller. The register space is 128 bytes long and 5250128Swpaul * can be accessed using either PCI I/O space or PCI memory mapping. 5350128Swpaul * There are 32-bit, 16-bit and 8-bit registers. 5450128Swpaul */ 5550128Swpaul 5650128Swpaul#define STE_DMACTL 0x00 5750128Swpaul#define STE_TX_DMALIST_PTR 0x04 5850128Swpaul#define STE_TX_DMABURST_THRESH 0x08 5950128Swpaul#define STE_TX_DMAURG_THRESH 0x09 6050128Swpaul#define STE_TX_DMAPOLL_PERIOD 0x0A 6150128Swpaul#define STE_RX_DMASTATUS 0x0C 6250128Swpaul#define STE_RX_DMALIST_PTR 0x10 6350128Swpaul#define STE_RX_DMABURST_THRESH 0x14 6450128Swpaul#define STE_RX_DMAURG_THRESH 0x15 6550128Swpaul#define STE_RX_DMAPOLL_PERIOD 0x16 66200912Syongari#define STE_COUNTDOWN 0x18 6750128Swpaul#define STE_DEBUGCTL 0x1A 6850128Swpaul#define STE_ASICCTL 0x30 6950128Swpaul#define STE_EEPROM_DATA 0x34 7050128Swpaul#define STE_EEPROM_CTL 0x36 7150128Swpaul#define STE_FIFOCTL 0x3A 7250128Swpaul#define STE_TX_STARTTHRESH 0x3C 7350128Swpaul#define STE_RX_EARLYTHRESH 0x3E 7450128Swpaul#define STE_EXT_ROMADDR 0x40 7550128Swpaul#define STE_EXT_ROMDATA 0x44 7650128Swpaul#define STE_WAKE_EVENT 0x45 7750128Swpaul#define STE_TX_STATUS 0x46 7850128Swpaul#define STE_TX_FRAMEID 0x47 7950128Swpaul#define STE_ISR_ACK 0x4A 8050128Swpaul#define STE_IMR 0x4C 8150128Swpaul#define STE_ISR 0x4E 8250128Swpaul#define STE_MACCTL0 0x50 8350128Swpaul#define STE_MACCTL1 0x52 8450128Swpaul#define STE_PAR0 0x54 8550128Swpaul#define STE_PAR1 0x56 8650128Swpaul#define STE_PAR2 0x58 8750128Swpaul#define STE_MAX_FRAMELEN 0x5A 8850128Swpaul#define STE_RX_MODE 0x5C 8950128Swpaul#define STE_TX_RECLAIM_THRESH 0x5D 9050128Swpaul#define STE_PHYCTL 0x5E 9150128Swpaul#define STE_MAR0 0x60 9282214Swpaul#define STE_MAR1 0x62 9382214Swpaul#define STE_MAR2 0x64 9482214Swpaul#define STE_MAR3 0x66 9550128Swpaul 96200910Syongari#define STE_STAT_RX_OCTETS_LO 0x68 97200910Syongari#define STE_STAT_RX_OCTETS_HI 0x6A 98200910Syongari#define STE_STAT_TX_OCTETS_LO 0x6C 99200910Syongari#define STE_STAT_TX_OCTETS_HI 0x6E 100200910Syongari#define STE_STAT_TX_FRAMES 0x70 101200910Syongari#define STE_STAT_RX_FRAMES 0x72 102200910Syongari#define STE_STAT_CARRIER_ERR 0x74 103200910Syongari#define STE_STAT_LATE_COLLS 0x75 104200910Syongari#define STE_STAT_MULTI_COLLS 0x76 105200910Syongari#define STE_STAT_SINGLE_COLLS 0x77 106200910Syongari#define STE_STAT_TX_DEFER 0x78 107200910Syongari#define STE_STAT_RX_LOST 0x79 108200910Syongari#define STE_STAT_TX_EXDEFER 0x7A 109200910Syongari#define STE_STAT_TX_ABORT 0x7B 110200910Syongari#define STE_STAT_TX_BCAST 0x7C 111200910Syongari#define STE_STAT_RX_BCAST 0x7D 112200910Syongari#define STE_STAT_TX_MCAST 0x7E 113200910Syongari#define STE_STAT_RX_MCAST 0x7F 114101493Sambrisko 11550128Swpaul#define STE_DMACTL_RXDMA_STOPPED 0x00000001 11650128Swpaul#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 11750128Swpaul#define STE_DMACTL_TXDMA_STOPPED 0x00000004 11850128Swpaul#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 11950128Swpaul#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 12050128Swpaul#define STE_DMACTL_RXDMA_STALL 0x00000100 12150128Swpaul#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 12250128Swpaul#define STE_DMACTL_TXDMA_STALL 0x00000400 12350128Swpaul#define STE_DMACTL_TXDMA_UNSTALL 0x00000800 12450128Swpaul#define STE_DMACTL_TXDMA_INPROG 0x00004000 12550128Swpaul#define STE_DMACTL_DMA_HALTINPROG 0x00008000 12650128Swpaul#define STE_DMACTL_RXEARLY_ENABLE 0x00020000 12750128Swpaul#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 12850128Swpaul#define STE_DMACTL_COUNTDOWN_MODE 0x00080000 12950128Swpaul#define STE_DMACTL_MWI_DISABLE 0x00100000 13050128Swpaul#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 13150128Swpaul#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 13250128Swpaul#define STE_DMACTL_TARGET_ABORT 0x40000000 13350128Swpaul#define STE_DMACTL_MASTER_ABORT 0x80000000 13450128Swpaul 13550128Swpaul/* 13650128Swpaul * TX DMA burst thresh is the number of 32-byte blocks that 13750128Swpaul * must be loaded into the TX Fifo before a TXDMA burst request 13850128Swpaul * will be issued. 13950128Swpaul */ 14050128Swpaul#define STE_TXDMABURST_THRESH 0x1F 14150128Swpaul 14250128Swpaul/* 14350128Swpaul * The number of 32-byte blocks in the TX FIFO falls below the 14450128Swpaul * TX DMA urgent threshold, a TX DMA urgent request will be 14550128Swpaul * generated. 14650128Swpaul */ 14750128Swpaul#define STE_TXDMAURG_THRESH 0x3F 14850128Swpaul 14950128Swpaul/* 15050128Swpaul * Number of 320ns intervals between polls of the TXDMA next 15150128Swpaul * descriptor pointer (if we're using polling mode). 15250128Swpaul */ 15350128Swpaul#define STE_TXDMA_POLL_PERIOD 0x7F 15450128Swpaul 15550128Swpaul#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 15650128Swpaul#define STE_RX_DMASTATUS_RXERR 0x00004000 15750128Swpaul#define STE_RX_DMASTATUS_DMADONE 0x00008000 15850128Swpaul#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 15950128Swpaul#define STE_RX_DMASTATUS_RUNT 0x00020000 16050128Swpaul#define STE_RX_DMASTATUS_ALIGNERR 0x00040000 16150128Swpaul#define STE_RX_DMASTATUS_CRCERR 0x00080000 16250128Swpaul#define STE_RX_DMASTATUS_GIANT 0x00100000 16350128Swpaul#define STE_RX_DMASTATUS_DRIBBLE 0x00800000 16450128Swpaul#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 16550128Swpaul 16650128Swpaul/* 16750128Swpaul * RX DMA burst thresh is the number of 32-byte blocks that 16850128Swpaul * must be present in the RX FIFO before a RXDMA bus master 16950128Swpaul * request will be issued. 17050128Swpaul */ 17150128Swpaul#define STE_RXDMABURST_THRESH 0xFF 17250128Swpaul 17350128Swpaul/* 17450128Swpaul * The number of 32-byte blocks in the RX FIFO falls below the 17550128Swpaul * RX DMA urgent threshold, a RX DMA urgent request will be 17650128Swpaul * generated. 17750128Swpaul */ 17850128Swpaul#define STE_RXDMAURG_THRESH 0x1F 17950128Swpaul 18050128Swpaul/* 18150128Swpaul * Number of 320ns intervals between polls of the RXDMA complete 18250128Swpaul * bit in the status field on the current RX descriptor (if we're 18350128Swpaul * using polling mode). 18450128Swpaul */ 18550128Swpaul#define STE_RXDMA_POLL_PERIOD 0x7F 18650128Swpaul 18750128Swpaul#define STE_DEBUGCTL_GPIO0_CTL 0x0001 18850128Swpaul#define STE_DEBUGCTL_GPIO1_CTL 0x0002 18950128Swpaul#define STE_DEBUGCTL_GPIO0_DATA 0x0004 19050128Swpaul#define STE_DEBUGCTL_GPIO1_DATA 0x0008 19150128Swpaul 19250128Swpaul#define STE_ASICCTL_ROMSIZE 0x00000002 19350128Swpaul#define STE_ASICCTL_TX_LARGEPKTS 0x00000004 19450128Swpaul#define STE_ASICCTL_RX_LARGEPKTS 0x00000008 19550128Swpaul#define STE_ASICCTL_EXTROM_DISABLE 0x00000010 19650128Swpaul#define STE_ASICCTL_PHYSPEED_10 0x00000020 19750128Swpaul#define STE_ASICCTL_PHYSPEED_100 0x00000040 19850128Swpaul#define STE_ASICCTL_PHYMEDIA 0x00000080 19950128Swpaul#define STE_ASICCTL_FORCEDCONFIG 0x00000700 20050128Swpaul#define STE_ASICCTL_D3RESET_DISABLE 0x00000800 20150128Swpaul#define STE_ASICCTL_SPEEDUPMODE 0x00002000 20250128Swpaul#define STE_ASICCTL_LEDMODE 0x00004000 20350128Swpaul#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 20450128Swpaul#define STE_ASICCTL_GLOBAL_RESET 0x00010000 20550128Swpaul#define STE_ASICCTL_RX_RESET 0x00020000 20650128Swpaul#define STE_ASICCTL_TX_RESET 0x00040000 20750128Swpaul#define STE_ASICCTL_DMA_RESET 0x00080000 20850128Swpaul#define STE_ASICCTL_FIFO_RESET 0x00100000 20950128Swpaul#define STE_ASICCTL_NETWORK_RESET 0x00200000 21050128Swpaul#define STE_ASICCTL_HOST_RESET 0x00400000 21150128Swpaul#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 21250128Swpaul#define STE_ASICCTL_EXTRESET_RESET 0x01000000 21350128Swpaul#define STE_ASICCTL_SOFTINTR 0x02000000 21450128Swpaul#define STE_ASICCTL_RESET_BUSY 0x04000000 21550128Swpaul 21650128Swpaul#define STE_EECTL_ADDR 0x00FF 21750128Swpaul#define STE_EECTL_OPCODE 0x0300 21850128Swpaul#define STE_EECTL_BUSY 0x1000 21950128Swpaul 22050128Swpaul#define STE_EEOPCODE_WRITE 0x0100 22150128Swpaul#define STE_EEOPCODE_READ 0x0200 22250128Swpaul#define STE_EEOPCODE_ERASE 0x0300 22350128Swpaul 22450128Swpaul#define STE_FIFOCTL_RAMTESTMODE 0x0001 22550128Swpaul#define STE_FIFOCTL_OVERRUNMODE 0x0200 22650128Swpaul#define STE_FIFOCTL_RXFIFOFULL 0x0800 22750128Swpaul#define STE_FIFOCTL_TX_BUSY 0x4000 22850128Swpaul#define STE_FIFOCTL_RX_BUSY 0x8000 22950128Swpaul 23050128Swpaul/* 23150128Swpaul * The number of bytes that must in present in the TX FIFO before 23250128Swpaul * transmission begins. Value should be in increments of 4 bytes. 23350128Swpaul */ 234101493Sambrisko#define STE_TXSTART_THRESH 0x1FFC 23550128Swpaul 23650128Swpaul/* 23750128Swpaul * Number of bytes that must be present in the RX FIFO before 23850128Swpaul * an RX EARLY interrupt is generated. 23950128Swpaul */ 240101493Sambrisko#define STE_RXEARLY_THRESH 0x1FFC 24150128Swpaul 24250128Swpaul#define STE_WAKEEVENT_WAKEPKT_ENB 0x01 24350128Swpaul#define STE_WAKEEVENT_MAGICPKT_ENB 0x02 24450128Swpaul#define STE_WAKEEVENT_LINKEVT_ENB 0x04 24550128Swpaul#define STE_WAKEEVENT_WAKEPOLARITY 0x08 24650128Swpaul#define STE_WAKEEVENT_WAKEPKTEVENT 0x10 24750128Swpaul#define STE_WAKEEVENT_MAGICPKTEVENT 0x20 24850128Swpaul#define STE_WAKEEVENT_LINKEVENT 0x40 24950128Swpaul#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 25050128Swpaul 25150128Swpaul#define STE_TXSTATUS_RECLAIMERR 0x02 25250128Swpaul#define STE_TXSTATUS_STATSOFLOW 0x04 25350128Swpaul#define STE_TXSTATUS_EXCESSCOLLS 0x08 25450128Swpaul#define STE_TXSTATUS_UNDERRUN 0x10 25550128Swpaul#define STE_TXSTATUS_TXINTR_REQ 0x40 25650128Swpaul#define STE_TXSTATUS_TXDONE 0x80 25750128Swpaul 258200884Syongari#define STE_ERR_BITS "\20" \ 259200884Syongari "\2RECLAIM\3STSOFLOW" \ 260200884Syongari "\4EXCESSCOLLS\5UNDERRUN" \ 261200884Syongari "\6INTREQ\7DONE" 262200884Syongari 26350128Swpaul#define STE_ISRACK_INTLATCH 0x0001 26450128Swpaul#define STE_ISRACK_HOSTERR 0x0002 26550128Swpaul#define STE_ISRACK_TX_DONE 0x0004 26650128Swpaul#define STE_ISRACK_MACCTL_FRAME 0x0008 26750128Swpaul#define STE_ISRACK_RX_DONE 0x0010 26850128Swpaul#define STE_ISRACK_RX_EARLY 0x0020 26950128Swpaul#define STE_ISRACK_SOFTINTR 0x0040 27050128Swpaul#define STE_ISRACK_STATS_OFLOW 0x0080 27150128Swpaul#define STE_ISRACK_LINKEVENT 0x0100 27250128Swpaul#define STE_ISRACK_TX_DMADONE 0x0200 27350128Swpaul#define STE_ISRACK_RX_DMADONE 0x0400 27450128Swpaul 27550128Swpaul#define STE_IMR_HOSTERR 0x0002 27650128Swpaul#define STE_IMR_TX_DONE 0x0004 27750128Swpaul#define STE_IMR_MACCTL_FRAME 0x0008 27850128Swpaul#define STE_IMR_RX_DONE 0x0010 27950128Swpaul#define STE_IMR_RX_EARLY 0x0020 28050128Swpaul#define STE_IMR_SOFTINTR 0x0040 28150128Swpaul#define STE_IMR_STATS_OFLOW 0x0080 28250128Swpaul#define STE_IMR_LINKEVENT 0x0100 28350128Swpaul#define STE_IMR_TX_DMADONE 0x0200 28450128Swpaul#define STE_IMR_RX_DMADONE 0x0400 28550128Swpaul 286200865Syongari#define STE_INTRS \ 287101493Sambrisko (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 288200950Syongari STE_IMR_TX_DONE|STE_IMR_SOFTINTR| \ 289200950Syongari STE_IMR_HOSTERR) 29050128Swpaul 29150128Swpaul#define STE_ISR_INTLATCH 0x0001 29250128Swpaul#define STE_ISR_HOSTERR 0x0002 29350128Swpaul#define STE_ISR_TX_DONE 0x0004 29450128Swpaul#define STE_ISR_MACCTL_FRAME 0x0008 29550128Swpaul#define STE_ISR_RX_DONE 0x0010 29650128Swpaul#define STE_ISR_RX_EARLY 0x0020 29750128Swpaul#define STE_ISR_SOFTINTR 0x0040 29850128Swpaul#define STE_ISR_STATS_OFLOW 0x0080 29950128Swpaul#define STE_ISR_LINKEVENT 0x0100 30050128Swpaul#define STE_ISR_TX_DMADONE 0x0200 30150128Swpaul#define STE_ISR_RX_DMADONE 0x0400 30250128Swpaul 30350128Swpaul/* 30450128Swpaul * Note: the Sundance manual gives the impression that the's 30550128Swpaul * only one 32-bit MACCTL register. In fact, there are two 30650128Swpaul * 16-bit registers side by side, and you have to access them 30750128Swpaul * separately. 30850128Swpaul */ 30950128Swpaul#define STE_MACCTL0_IPG 0x0003 31050128Swpaul#define STE_MACCTL0_FULLDUPLEX 0x0020 31150128Swpaul#define STE_MACCTL0_RX_GIANTS 0x0040 31250128Swpaul#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 31350128Swpaul#define STE_MACCTL0_RX_FCS 0x0200 31450128Swpaul#define STE_MACCTL0_FIFOLOOPBK 0x0400 31550128Swpaul#define STE_MACCTL0_MACLOOPBK 0x0800 31650128Swpaul 31750128Swpaul#define STE_MACCTL1_COLLDETECT 0x0001 31850128Swpaul#define STE_MACCTL1_CARRSENSE 0x0002 31950128Swpaul#define STE_MACCTL1_TX_BUSY 0x0004 32050128Swpaul#define STE_MACCTL1_TX_ERROR 0x0008 32150128Swpaul#define STE_MACCTL1_STATS_ENABLE 0x0020 32250128Swpaul#define STE_MACCTL1_STATS_DISABLE 0x0040 32350128Swpaul#define STE_MACCTL1_STATS_ENABLED 0x0080 32450128Swpaul#define STE_MACCTL1_TX_ENABLE 0x0100 32550128Swpaul#define STE_MACCTL1_TX_DISABLE 0x0200 32650128Swpaul#define STE_MACCTL1_TX_ENABLED 0x0400 32750128Swpaul#define STE_MACCTL1_RX_ENABLE 0x0800 32850128Swpaul#define STE_MACCTL1_RX_DISABLE 0x1000 32950128Swpaul#define STE_MACCTL1_RX_ENABLED 0x2000 33050128Swpaul#define STE_MACCTL1_PAUSED 0x4000 33150128Swpaul 33250128Swpaul#define STE_IPG_96BT 0x00000000 33350128Swpaul#define STE_IPG_128BT 0x00000001 33450128Swpaul#define STE_IPG_224BT 0x00000002 33550128Swpaul#define STE_IPG_544BT 0x00000003 33650128Swpaul 33750128Swpaul#define STE_RXMODE_UNICAST 0x01 33850128Swpaul#define STE_RXMODE_ALLMULTI 0x02 33950128Swpaul#define STE_RXMODE_BROADCAST 0x04 34050128Swpaul#define STE_RXMODE_PROMISC 0x08 34150128Swpaul#define STE_RXMODE_MULTIHASH 0x10 34250128Swpaul#define STE_RXMODE_ALLIPMULTI 0x20 34350128Swpaul 34450128Swpaul#define STE_PHYCTL_MCLK 0x01 34550128Swpaul#define STE_PHYCTL_MDATA 0x02 34650128Swpaul#define STE_PHYCTL_MDIR 0x04 34750128Swpaul#define STE_PHYCTL_CLK25_DISABLE 0x08 34850128Swpaul#define STE_PHYCTL_DUPLEXPOLARITY 0x10 34950128Swpaul#define STE_PHYCTL_DUPLEXSTAT 0x20 35050128Swpaul#define STE_PHYCTL_SPEEDSTAT 0x40 35150128Swpaul#define STE_PHYCTL_LINKSTAT 0x80 35250128Swpaul 353200950Syongari#define STE_TIMER_TICKS 32 354200950Syongari#define STE_TIMER_USECS(x) ((x * 10) / STE_TIMER_TICKS) 355200950Syongari 356200950Syongari#define STE_IM_RX_TIMER_MIN 0 357200950Syongari#define STE_IM_RX_TIMER_MAX 209712 358200950Syongari#define STE_IM_RX_TIMER_DEFAULT 150 359200950Syongari 36050128Swpaul/* 36150128Swpaul * EEPROM offsets. 36250128Swpaul */ 36350128Swpaul#define STE_EEADDR_CONFIGPARM 0x00 36450128Swpaul#define STE_EEADDR_ASICCTL 0x02 36550128Swpaul#define STE_EEADDR_SUBSYS_ID 0x04 36650128Swpaul#define STE_EEADDR_SUBVEN_ID 0x08 36750128Swpaul 36850128Swpaul#define STE_EEADDR_NODE0 0x10 36950128Swpaul#define STE_EEADDR_NODE1 0x12 37050128Swpaul#define STE_EEADDR_NODE2 0x14 37150128Swpaul 37250128Swpaul/* PCI registers */ 37350128Swpaul#define STE_PCI_VENDOR_ID 0x00 37450128Swpaul#define STE_PCI_DEVICE_ID 0x02 37550128Swpaul#define STE_PCI_COMMAND 0x04 37650128Swpaul#define STE_PCI_STATUS 0x06 37750128Swpaul#define STE_PCI_CLASSCODE 0x09 37850128Swpaul#define STE_PCI_LATENCY_TIMER 0x0D 37950128Swpaul#define STE_PCI_HEADER_TYPE 0x0E 38050128Swpaul#define STE_PCI_LOIO 0x10 38150128Swpaul#define STE_PCI_LOMEM 0x14 38250128Swpaul#define STE_PCI_BIOSROM 0x30 38350128Swpaul#define STE_PCI_INTLINE 0x3C 38450128Swpaul#define STE_PCI_INTPIN 0x3D 38550128Swpaul#define STE_PCI_MINGNT 0x3E 38650128Swpaul#define STE_PCI_MINLAT 0x0F 38750128Swpaul 38850128Swpaul#define STE_PCI_CAPID 0x50 /* 8 bits */ 38950128Swpaul#define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 39050128Swpaul#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 39150128Swpaul#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 39250128Swpaul 39350128Swpaul#define STE_PSTATE_MASK 0x0003 39450128Swpaul#define STE_PSTATE_D0 0x0000 39550128Swpaul#define STE_PSTATE_D1 0x0002 39650128Swpaul#define STE_PSTATE_D2 0x0002 39750128Swpaul#define STE_PSTATE_D3 0x0003 39850128Swpaul#define STE_PME_EN 0x0010 39950128Swpaul#define STE_PME_STATUS 0x8000 40050128Swpaul 401200910Syongaristruct ste_hw_stats { 402200910Syongari uint64_t rx_bytes; 403200910Syongari uint32_t rx_frames; 404200910Syongari uint32_t rx_bcast_frames; 405200910Syongari uint32_t rx_mcast_frames; 406200910Syongari uint32_t rx_lost_frames; 407200910Syongari uint64_t tx_bytes; 408200910Syongari uint32_t tx_frames; 409200910Syongari uint32_t tx_bcast_frames; 410200910Syongari uint32_t tx_mcast_frames; 411200910Syongari uint32_t tx_carrsense_errs; 412200910Syongari uint32_t tx_single_colls; 413200910Syongari uint32_t tx_multi_colls; 414200910Syongari uint32_t tx_late_colls; 415200910Syongari uint32_t tx_frames_defered; 416200910Syongari uint32_t tx_excess_defers; 417200910Syongari uint32_t tx_abort; 41850128Swpaul}; 41950128Swpaul 42050128Swpaulstruct ste_frag { 421200803Syongari uint32_t ste_addr; 422200803Syongari uint32_t ste_len; 42350128Swpaul}; 42450128Swpaul 42550128Swpaul#define STE_FRAG_LAST 0x80000000 42650128Swpaul#define STE_FRAG_LEN 0x00001FFF 42750128Swpaul 428200853Syongari/* 429200853Syongari * A TFD is 16 to 512 bytes in length which means it can have up to 126 430200853Syongari * fragments for a single Tx frame. Since most frames used in stack have 431200853Syongari * 3-4 fragments supporting 8 fragments would be enough for normal 432200853Syongari * operation. If we encounter more than 8 fragments we'll collapse them 433200853Syongari * into a frame that has less than or equal to 8 fragments. Each buffer 434200853Syongari * address of a fragment has no alignment limitation. 435200853Syongari */ 436101493Sambrisko#define STE_MAXFRAGS 8 43750128Swpaul 43850128Swpaulstruct ste_desc { 439200803Syongari uint32_t ste_next; 440200803Syongari uint32_t ste_ctl; 44150128Swpaul struct ste_frag ste_frags[STE_MAXFRAGS]; 44250128Swpaul}; 44350128Swpaul 444200853Syongari/* 445200853Syongari * A RFD has the same structure of TFD which in turn means hardware 446200853Syongari * supports scatter operation in Rx buffer. Since we just allocate Rx 447200853Syongari * buffer with m_getcl(9) there is no fragmentation at all so use 448200853Syongari * single fragment for RFD. 449200853Syongari */ 45050128Swpaulstruct ste_desc_onefrag { 451200803Syongari uint32_t ste_next; 452200803Syongari uint32_t ste_status; 45350128Swpaul struct ste_frag ste_frag; 45450128Swpaul}; 45550128Swpaul 45650128Swpaul#define STE_TXCTL_WORDALIGN 0x00000003 457200853Syongari#define STE_TXCTL_ALIGN_DIS 0x00000001 45850128Swpaul#define STE_TXCTL_FRAMEID 0x000003FC 45950128Swpaul#define STE_TXCTL_NOCRC 0x00002000 46050128Swpaul#define STE_TXCTL_TXINTR 0x00008000 46150128Swpaul#define STE_TXCTL_DMADONE 0x00010000 46250128Swpaul#define STE_TXCTL_DMAINTR 0x80000000 46350128Swpaul 46450128Swpaul#define STE_RXSTAT_FRAMELEN 0x00001FFF 46550128Swpaul#define STE_RXSTAT_FRAME_ERR 0x00004000 46650128Swpaul#define STE_RXSTAT_DMADONE 0x00008000 46750128Swpaul#define STE_RXSTAT_FIFO_OFLOW 0x00010000 46850128Swpaul#define STE_RXSTAT_RUNT 0x00020000 46950128Swpaul#define STE_RXSTAT_ALIGNERR 0x00040000 47050128Swpaul#define STE_RXSTAT_CRCERR 0x00080000 47150128Swpaul#define STE_RXSTAT_GIANT 0x00100000 47250128Swpaul#define STE_RXSTAT_DRIBBLEBITS 0x00800000 47350128Swpaul#define STE_RXSTAT_DMA_OFLOW 0x01000000 47450128Swpaul#define STE_RXATAT_ONEBUF 0x10000000 47550128Swpaul 476200853Syongari#define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN) 477200853Syongari 47850128Swpaul/* 47950128Swpaul * register space access macros 48050128Swpaul */ 48150128Swpaul#define CSR_WRITE_4(sc, reg, val) \ 482200877Syongari bus_write_4((sc)->ste_res, reg, val) 48350128Swpaul#define CSR_WRITE_2(sc, reg, val) \ 484200877Syongari bus_write_2((sc)->ste_res, reg, val) 48550128Swpaul#define CSR_WRITE_1(sc, reg, val) \ 486200877Syongari bus_write_1((sc)->ste_res, reg, val) 48750128Swpaul 48850128Swpaul#define CSR_READ_4(sc, reg) \ 489200877Syongari bus_read_4((sc)->ste_res, reg) 49050128Swpaul#define CSR_READ_2(sc, reg) \ 491200877Syongari bus_read_2((sc)->ste_res, reg) 49250128Swpaul#define CSR_READ_1(sc, reg) \ 493200877Syongari bus_read_1((sc)->ste_res, reg) 49450128Swpaul 495226995Smarius#define CSR_BARRIER(sc, reg, length, flags) \ 496226995Smarius bus_barrier((sc)->ste_res, reg, length, flags) 497226995Smarius 498200853Syongari#define STE_DESC_ALIGN 8 499200853Syongari#define STE_RX_LIST_CNT 128 500200853Syongari#define STE_TX_LIST_CNT 128 501200853Syongari#define STE_RX_LIST_SZ \ 502200853Syongari (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT) 503200853Syongari#define STE_TX_LIST_SZ \ 504200853Syongari (sizeof(struct ste_desc) * STE_TX_LIST_CNT) 505200853Syongari#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 506200853Syongari#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32) 507200853Syongari 508200913Syongari/* 509200913Syongari * Since Tx status can hold up to 31 status bytes we should 510200913Syongari * check Tx status before controller fills it up. Otherwise 511200913Syongari * Tx MAC stalls. 512200913Syongari */ 513200913Syongari#define STE_TX_INTR_FRAMES 16 514200853Syongari#define STE_TX_TIMEOUT 5 51554268Swpaul#define STE_TIMEOUT 1000 51654268Swpaul#define STE_MIN_FRAMELEN 60 51754268Swpaul#define STE_PACKET_SIZE 1536 51854268Swpaul#define STE_INC(x, y) (x) = (x + 1) % y 519200853Syongari#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y) 520101493Sambrisko#define STE_NEXT(x, y) (x + 1) % y 52150128Swpaul 52250128Swpaulstruct ste_type { 523200803Syongari uint16_t ste_vid; 524200803Syongari uint16_t ste_did; 525226995Smarius const char *ste_name; 52650128Swpaul}; 52750128Swpaul 52850128Swpaulstruct ste_list_data { 529200853Syongari struct ste_desc_onefrag *ste_rx_list; 530200853Syongari bus_addr_t ste_rx_list_paddr; 531200853Syongari struct ste_desc *ste_tx_list; 532200853Syongari bus_addr_t ste_tx_list_paddr; 53350128Swpaul}; 53450128Swpaul 53550128Swpaulstruct ste_chain { 53650128Swpaul struct ste_desc *ste_ptr; 53750128Swpaul struct mbuf *ste_mbuf; 53850128Swpaul struct ste_chain *ste_next; 539200803Syongari uint32_t ste_phys; 540200853Syongari bus_dmamap_t ste_map; 54150128Swpaul}; 54250128Swpaul 54350128Swpaulstruct ste_chain_onefrag { 54450128Swpaul struct ste_desc_onefrag *ste_ptr; 54550128Swpaul struct mbuf *ste_mbuf; 54650128Swpaul struct ste_chain_onefrag *ste_next; 547200853Syongari bus_dmamap_t ste_map; 54850128Swpaul}; 54950128Swpaul 55050128Swpaulstruct ste_chain_data { 551200853Syongari bus_dma_tag_t ste_parent_tag; 552200853Syongari bus_dma_tag_t ste_rx_tag; 553200853Syongari bus_dma_tag_t ste_tx_tag; 554200853Syongari bus_dma_tag_t ste_rx_list_tag; 555200853Syongari bus_dmamap_t ste_rx_list_map; 556200853Syongari bus_dma_tag_t ste_tx_list_tag; 557200853Syongari bus_dmamap_t ste_tx_list_map; 558200853Syongari bus_dmamap_t ste_rx_sparemap; 55950128Swpaul struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 560200853Syongari struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 56150128Swpaul struct ste_chain_onefrag *ste_rx_head; 562200853Syongari struct ste_chain *ste_last_tx; 56354268Swpaul int ste_tx_prod; 56454268Swpaul int ste_tx_cons; 565200853Syongari int ste_tx_cnt; 56650128Swpaul}; 56750128Swpaul 56850128Swpaulstruct ste_softc { 569147256Sbrooks struct ifnet *ste_ifp; 57050128Swpaul struct resource *ste_res; 571200875Syongari int ste_res_id; 572200875Syongari int ste_res_type; 57350128Swpaul struct resource *ste_irq; 57450128Swpaul void *ste_intrhand; 57550128Swpaul struct ste_type *ste_info; 57650128Swpaul device_t ste_miibus; 577101493Sambrisko device_t ste_dev; 57850128Swpaul int ste_tx_thresh; 579200856Syongari int ste_flags; 580200856Syongari#define STE_FLAG_ONE_PHY 0x0001 581200856Syongari#define STE_FLAG_LINK 0x8000 58254268Swpaul int ste_if_flags; 583199559Sjhb int ste_timer; 584200950Syongari int ste_int_rx_act; 585200950Syongari int ste_int_rx_mod; 586200853Syongari struct ste_list_data ste_ldata; 58750128Swpaul struct ste_chain_data ste_cdata; 588200865Syongari struct callout ste_callout; 589200910Syongari struct ste_hw_stats ste_stats; 59067089Swpaul struct mtx ste_mtx; 59150128Swpaul}; 59250128Swpaul 59372200Sbmilekic#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 59472200Sbmilekic#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 595122689Ssam#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 596