t4dwave.c revision 173511
1/*- 2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <dev/sound/pcm/sound.h> 28#include <dev/sound/pcm/ac97.h> 29#include <dev/sound/pci/t4dwave.h> 30 31#include <dev/pci/pcireg.h> 32#include <dev/pci/pcivar.h> 33 34SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/t4dwave.c 173511 2007-11-10 04:32:50Z ariff $"); 35 36/* -------------------------------------------------------------------- */ 37 38#define TDX_PCI_ID 0x20001023 39#define TNX_PCI_ID 0x20011023 40#define ALI_PCI_ID 0x545110b9 41#define SPA_PCI_ID 0x70181039 42 43#define TR_DEFAULT_BUFSZ 0x1000 44#define TR_TIMEOUT_CDC 0xffff 45#define TR_MAXPLAYCH 4 46/* 47 * Though, it's not clearly documented in trident datasheet, trident 48 * audio cards can't handle DMA addresses located above 1GB. The LBA 49 * (loop begin address) register which holds DMA base address is 32bits 50 * register. 51 * But the MSB 2bits are used for other purposes(I guess it is really 52 * bad idea). This effectivly limits the DMA address space up to 1GB. 53 */ 54#define TR_MAXADDR ((1 << 30) - 1) 55 56 57struct tr_info; 58 59/* channel registers */ 60struct tr_chinfo { 61 u_int32_t cso, alpha, fms, fmc, ec; 62 u_int32_t lba; 63 u_int32_t eso, delta; 64 u_int32_t rvol, cvol; 65 u_int32_t gvsel, pan, vol, ctrl; 66 u_int32_t active:1, was_active:1; 67 int index, bufhalf; 68 struct snd_dbuf *buffer; 69 struct pcm_channel *channel; 70 struct tr_info *parent; 71}; 72 73struct tr_rchinfo { 74 u_int32_t delta; 75 u_int32_t active:1, was_active:1; 76 struct snd_dbuf *buffer; 77 struct pcm_channel *channel; 78 struct tr_info *parent; 79}; 80 81/* device private data */ 82struct tr_info { 83 u_int32_t type; 84 u_int32_t rev; 85 86 bus_space_tag_t st; 87 bus_space_handle_t sh; 88 bus_dma_tag_t parent_dmat; 89 90 struct resource *reg, *irq; 91 int regtype, regid, irqid; 92 void *ih; 93 94 struct mtx *lock; 95 96 u_int32_t playchns; 97 unsigned int bufsz; 98 99 struct tr_chinfo chinfo[TR_MAXPLAYCH]; 100 struct tr_rchinfo recchinfo; 101}; 102 103/* -------------------------------------------------------------------- */ 104 105static u_int32_t tr_recfmt[] = { 106 AFMT_U8, 107 AFMT_STEREO | AFMT_U8, 108 AFMT_S8, 109 AFMT_STEREO | AFMT_S8, 110 AFMT_S16_LE, 111 AFMT_STEREO | AFMT_S16_LE, 112 AFMT_U16_LE, 113 AFMT_STEREO | AFMT_U16_LE, 114 0 115}; 116static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0}; 117 118static u_int32_t tr_playfmt[] = { 119 AFMT_U8, 120 AFMT_STEREO | AFMT_U8, 121 AFMT_S8, 122 AFMT_STEREO | AFMT_S8, 123 AFMT_S16_LE, 124 AFMT_STEREO | AFMT_S16_LE, 125 AFMT_U16_LE, 126 AFMT_STEREO | AFMT_U16_LE, 127 0 128}; 129static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0}; 130 131/* -------------------------------------------------------------------- */ 132 133/* Hardware */ 134 135static u_int32_t 136tr_rd(struct tr_info *tr, int regno, int size) 137{ 138 switch(size) { 139 case 1: 140 return bus_space_read_1(tr->st, tr->sh, regno); 141 case 2: 142 return bus_space_read_2(tr->st, tr->sh, regno); 143 case 4: 144 return bus_space_read_4(tr->st, tr->sh, regno); 145 default: 146 return 0xffffffff; 147 } 148} 149 150static void 151tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size) 152{ 153 switch(size) { 154 case 1: 155 bus_space_write_1(tr->st, tr->sh, regno, data); 156 break; 157 case 2: 158 bus_space_write_2(tr->st, tr->sh, regno, data); 159 break; 160 case 4: 161 bus_space_write_4(tr->st, tr->sh, regno, data); 162 break; 163 } 164} 165 166/* -------------------------------------------------------------------- */ 167/* ac97 codec */ 168 169static int 170tr_rdcd(kobj_t obj, void *devinfo, int regno) 171{ 172 struct tr_info *tr = (struct tr_info *)devinfo; 173 int i, j, treg, trw; 174 175 switch (tr->type) { 176 case SPA_PCI_ID: 177 treg=SPA_REG_CODECRD; 178 trw=SPA_CDC_RWSTAT; 179 break; 180 case ALI_PCI_ID: 181 if (tr->rev > 0x01) 182 treg=TDX_REG_CODECWR; 183 else 184 treg=TDX_REG_CODECRD; 185 trw=TDX_CDC_RWSTAT; 186 break; 187 case TDX_PCI_ID: 188 treg=TDX_REG_CODECRD; 189 trw=TDX_CDC_RWSTAT; 190 break; 191 case TNX_PCI_ID: 192 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD; 193 trw=TNX_CDC_RWSTAT; 194 break; 195 default: 196 printf("!!! tr_rdcd defaulted !!!\n"); 197 return -1; 198 } 199 200 i = j = 0; 201 202 regno &= 0x7f; 203 snd_mtxlock(tr->lock); 204 if (tr->type == ALI_PCI_ID) { 205 u_int32_t chk1, chk2; 206 j = trw; 207 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 208 j = tr_rd(tr, treg, 4); 209 if (i > 0) { 210 chk1 = tr_rd(tr, 0xc8, 4); 211 chk2 = tr_rd(tr, 0xc8, 4); 212 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 213 i--) 214 chk2 = tr_rd(tr, 0xc8, 4); 215 } 216 } 217 if (tr->type != ALI_PCI_ID || i > 0) { 218 tr_wr(tr, treg, regno | trw, 4); 219 j=trw; 220 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 221 j=tr_rd(tr, treg, 4); 222 } 223 snd_mtxunlock(tr->lock); 224 if (i == 0) printf("codec timeout during read of register %x\n", regno); 225 return (j >> TR_CDC_DATA) & 0xffff; 226} 227 228static int 229tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 230{ 231 struct tr_info *tr = (struct tr_info *)devinfo; 232 int i, j, treg, trw; 233 234 switch (tr->type) { 235 case SPA_PCI_ID: 236 treg=SPA_REG_CODECWR; 237 trw=SPA_CDC_RWSTAT; 238 break; 239 case ALI_PCI_ID: 240 case TDX_PCI_ID: 241 treg=TDX_REG_CODECWR; 242 trw=TDX_CDC_RWSTAT; 243 break; 244 case TNX_PCI_ID: 245 treg=TNX_REG_CODECWR; 246 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0); 247 break; 248 default: 249 printf("!!! tr_wrcd defaulted !!!"); 250 return -1; 251 } 252 253 i = 0; 254 255 regno &= 0x7f; 256#if 0 257 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno)); 258#endif 259 j=trw; 260 snd_mtxlock(tr->lock); 261 if (tr->type == ALI_PCI_ID) { 262 j = trw; 263 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 264 j = tr_rd(tr, treg, 4); 265 if (i > 0) { 266 u_int32_t chk1, chk2; 267 chk1 = tr_rd(tr, 0xc8, 4); 268 chk2 = tr_rd(tr, 0xc8, 4); 269 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 270 i--) 271 chk2 = tr_rd(tr, 0xc8, 4); 272 } 273 } 274 if (tr->type != ALI_PCI_ID || i > 0) { 275 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--) 276 j=tr_rd(tr, treg, 4); 277 if (tr->type == ALI_PCI_ID && tr->rev > 0x01) 278 trw |= 0x0100; 279 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4); 280 } 281#if 0 282 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno)); 283#endif 284 snd_mtxunlock(tr->lock); 285 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data); 286 return (i > 0)? 0 : -1; 287} 288 289static kobj_method_t tr_ac97_methods[] = { 290 KOBJMETHOD(ac97_read, tr_rdcd), 291 KOBJMETHOD(ac97_write, tr_wrcd), 292 { 0, 0 } 293}; 294AC97_DECLARE(tr_ac97); 295 296/* -------------------------------------------------------------------- */ 297/* playback channel interrupts */ 298 299#if 0 300static u_int32_t 301tr_testint(struct tr_chinfo *ch) 302{ 303 struct tr_info *tr = ch->parent; 304 int bank, chan; 305 306 bank = (ch->index & 0x20) ? 1 : 0; 307 chan = ch->index & 0x1f; 308 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan); 309} 310#endif 311 312static void 313tr_clrint(struct tr_chinfo *ch) 314{ 315 struct tr_info *tr = ch->parent; 316 int bank, chan; 317 318 bank = (ch->index & 0x20) ? 1 : 0; 319 chan = ch->index & 0x1f; 320 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4); 321} 322 323static void 324tr_enaint(struct tr_chinfo *ch, int enable) 325{ 326 struct tr_info *tr = ch->parent; 327 u_int32_t i, reg; 328 int bank, chan; 329 330 snd_mtxlock(tr->lock); 331 bank = (ch->index & 0x20) ? 1 : 0; 332 chan = ch->index & 0x1f; 333 reg = bank? TR_REG_INTENB : TR_REG_INTENA; 334 335 i = tr_rd(tr, reg, 4); 336 i &= ~(1 << chan); 337 i |= (enable? 1 : 0) << chan; 338 339 tr_clrint(ch); 340 tr_wr(tr, reg, i, 4); 341 snd_mtxunlock(tr->lock); 342} 343 344/* playback channels */ 345 346static void 347tr_selch(struct tr_chinfo *ch) 348{ 349 struct tr_info *tr = ch->parent; 350 int i; 351 352 i = tr_rd(tr, TR_REG_CIR, 4); 353 i &= ~TR_CIR_MASK; 354 i |= ch->index & 0x3f; 355 tr_wr(tr, TR_REG_CIR, i, 4); 356} 357 358static void 359tr_startch(struct tr_chinfo *ch) 360{ 361 struct tr_info *tr = ch->parent; 362 int bank, chan; 363 364 bank = (ch->index & 0x20) ? 1 : 0; 365 chan = ch->index & 0x1f; 366 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4); 367} 368 369static void 370tr_stopch(struct tr_chinfo *ch) 371{ 372 struct tr_info *tr = ch->parent; 373 int bank, chan; 374 375 bank = (ch->index & 0x20) ? 1 : 0; 376 chan = ch->index & 0x1f; 377 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4); 378} 379 380static void 381tr_wrch(struct tr_chinfo *ch) 382{ 383 struct tr_info *tr = ch->parent; 384 u_int32_t cr[TR_CHN_REGS], i; 385 386 ch->gvsel &= 0x00000001; 387 ch->fmc &= 0x00000003; 388 ch->fms &= 0x0000000f; 389 ch->ctrl &= 0x0000000f; 390 ch->pan &= 0x0000007f; 391 ch->rvol &= 0x0000007f; 392 ch->cvol &= 0x0000007f; 393 ch->vol &= 0x000000ff; 394 ch->ec &= 0x00000fff; 395 ch->alpha &= 0x00000fff; 396 ch->delta &= 0x0000ffff; 397 ch->lba &= 0x3fffffff; 398 399 cr[1]=ch->lba; 400 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol); 401 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec); 402 403 switch (tr->type) { 404 case SPA_PCI_ID: 405 case ALI_PCI_ID: 406 case TDX_PCI_ID: 407 ch->cso &= 0x0000ffff; 408 ch->eso &= 0x0000ffff; 409 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms); 410 cr[2]=(ch->eso<<16) | (ch->delta); 411 break; 412 case TNX_PCI_ID: 413 ch->cso &= 0x00ffffff; 414 ch->eso &= 0x00ffffff; 415 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso); 416 cr[2]=((ch->delta>>8)<<24) | (ch->eso); 417 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14); 418 break; 419 } 420 snd_mtxlock(tr->lock); 421 tr_selch(ch); 422 for (i=0; i<TR_CHN_REGS; i++) 423 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4); 424 snd_mtxunlock(tr->lock); 425} 426 427static void 428tr_rdch(struct tr_chinfo *ch) 429{ 430 struct tr_info *tr = ch->parent; 431 u_int32_t cr[5], i; 432 433 snd_mtxlock(tr->lock); 434 tr_selch(ch); 435 for (i=0; i<5; i++) 436 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4); 437 snd_mtxunlock(tr->lock); 438 439 440 ch->lba= (cr[1] & 0x3fffffff); 441 ch->fmc= (cr[3] & 0x0000c000) >> 14; 442 ch->rvol= (cr[3] & 0x00003f80) >> 7; 443 ch->cvol= (cr[3] & 0x0000007f); 444 ch->gvsel= (cr[4] & 0x80000000) >> 31; 445 ch->pan= (cr[4] & 0x7f000000) >> 24; 446 ch->vol= (cr[4] & 0x00ff0000) >> 16; 447 ch->ctrl= (cr[4] & 0x0000f000) >> 12; 448 ch->ec= (cr[4] & 0x00000fff); 449 switch(tr->type) { 450 case SPA_PCI_ID: 451 case ALI_PCI_ID: 452 case TDX_PCI_ID: 453 ch->cso= (cr[0] & 0xffff0000) >> 16; 454 ch->alpha= (cr[0] & 0x0000fff0) >> 4; 455 ch->fms= (cr[0] & 0x0000000f); 456 ch->eso= (cr[2] & 0xffff0000) >> 16; 457 ch->delta= (cr[2] & 0x0000ffff); 458 break; 459 case TNX_PCI_ID: 460 ch->cso= (cr[0] & 0x00ffffff); 461 ch->eso= (cr[2] & 0x00ffffff); 462 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24); 463 ch->alpha= (cr[3] & 0xfff00000) >> 20; 464 ch->fms= (cr[3] & 0x000f0000) >> 16; 465 break; 466 } 467} 468 469static u_int32_t 470tr_fmttobits(u_int32_t fmt) 471{ 472 u_int32_t bits; 473 474 bits = 0; 475 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0; 476 bits |= (fmt & AFMT_STEREO)? 0x4 : 0; 477 bits |= (fmt & AFMT_16BIT)? 0x8 : 0; 478 479 return bits; 480} 481 482/* -------------------------------------------------------------------- */ 483/* channel interface */ 484 485static void * 486trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 487{ 488 struct tr_info *tr = devinfo; 489 struct tr_chinfo *ch; 490 491 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction")); 492 ch = &tr->chinfo[tr->playchns]; 493 ch->index = tr->playchns++; 494 ch->buffer = b; 495 ch->parent = tr; 496 ch->channel = c; 497 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 498 return NULL; 499 500 return ch; 501} 502 503static int 504trpchan_setformat(kobj_t obj, void *data, u_int32_t format) 505{ 506 struct tr_chinfo *ch = data; 507 508 ch->ctrl = tr_fmttobits(format) | 0x01; 509 510 return 0; 511} 512 513static int 514trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 515{ 516 struct tr_chinfo *ch = data; 517 518 ch->delta = (speed << 12) / 48000; 519 return (ch->delta * 48000) >> 12; 520} 521 522static int 523trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 524{ 525 struct tr_chinfo *ch = data; 526 527 sndbuf_resize(ch->buffer, 2, blocksize); 528 return blocksize; 529} 530 531static int 532trpchan_trigger(kobj_t obj, void *data, int go) 533{ 534 struct tr_chinfo *ch = data; 535 536 if (!PCMTRIG_COMMON(go)) 537 return 0; 538 539 if (go == PCMTRIG_START) { 540 ch->fmc = 3; 541 ch->fms = 0; 542 ch->ec = 0; 543 ch->alpha = 0; 544 ch->lba = sndbuf_getbufaddr(ch->buffer); 545 ch->cso = 0; 546 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getbps(ch->buffer)) - 1; 547 ch->rvol = ch->cvol = 0x7f; 548 ch->gvsel = 0; 549 ch->pan = 0; 550 ch->vol = 0; 551 ch->bufhalf = 0; 552 tr_wrch(ch); 553 tr_enaint(ch, 1); 554 tr_startch(ch); 555 ch->active = 1; 556 } else { 557 tr_stopch(ch); 558 ch->active = 0; 559 } 560 561 return 0; 562} 563 564static int 565trpchan_getptr(kobj_t obj, void *data) 566{ 567 struct tr_chinfo *ch = data; 568 569 tr_rdch(ch); 570 return ch->cso * sndbuf_getbps(ch->buffer); 571} 572 573static struct pcmchan_caps * 574trpchan_getcaps(kobj_t obj, void *data) 575{ 576 return &tr_playcaps; 577} 578 579static kobj_method_t trpchan_methods[] = { 580 KOBJMETHOD(channel_init, trpchan_init), 581 KOBJMETHOD(channel_setformat, trpchan_setformat), 582 KOBJMETHOD(channel_setspeed, trpchan_setspeed), 583 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize), 584 KOBJMETHOD(channel_trigger, trpchan_trigger), 585 KOBJMETHOD(channel_getptr, trpchan_getptr), 586 KOBJMETHOD(channel_getcaps, trpchan_getcaps), 587 { 0, 0 } 588}; 589CHANNEL_DECLARE(trpchan); 590 591/* -------------------------------------------------------------------- */ 592/* rec channel interface */ 593 594static void * 595trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 596{ 597 struct tr_info *tr = devinfo; 598 struct tr_rchinfo *ch; 599 600 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction")); 601 ch = &tr->recchinfo; 602 ch->buffer = b; 603 ch->parent = tr; 604 ch->channel = c; 605 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 606 return NULL; 607 608 return ch; 609} 610 611static int 612trrchan_setformat(kobj_t obj, void *data, u_int32_t format) 613{ 614 struct tr_rchinfo *ch = data; 615 struct tr_info *tr = ch->parent; 616 u_int32_t i, bits; 617 618 bits = tr_fmttobits(format); 619 /* set # of samples between interrupts */ 620 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1; 621 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4); 622 /* set sample format */ 623 i = 0x18 | (bits << 4); 624 tr_wr(tr, TR_REG_SBCTRL, i, 1); 625 626 return 0; 627 628} 629 630static int 631trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 632{ 633 struct tr_rchinfo *ch = data; 634 struct tr_info *tr = ch->parent; 635 636 /* setup speed */ 637 ch->delta = (48000 << 12) / speed; 638 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2); 639 640 /* return closest possible speed */ 641 return (48000 << 12) / ch->delta; 642} 643 644static int 645trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 646{ 647 struct tr_rchinfo *ch = data; 648 649 sndbuf_resize(ch->buffer, 2, blocksize); 650 651 return blocksize; 652} 653 654static int 655trrchan_trigger(kobj_t obj, void *data, int go) 656{ 657 struct tr_rchinfo *ch = data; 658 struct tr_info *tr = ch->parent; 659 u_int32_t i; 660 661 if (!PCMTRIG_COMMON(go)) 662 return 0; 663 664 if (go == PCMTRIG_START) { 665 /* set up dma mode regs */ 666 tr_wr(tr, TR_REG_DMAR15, 0, 1); 667 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03; 668 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1); 669 /* set up base address */ 670 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4); 671 /* set up buffer size */ 672 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff; 673 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4); 674 /* start */ 675 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1); 676 ch->active = 1; 677 } else { 678 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1); 679 ch->active = 0; 680 } 681 682 /* return 0 if ok */ 683 return 0; 684} 685 686static int 687trrchan_getptr(kobj_t obj, void *data) 688{ 689 struct tr_rchinfo *ch = data; 690 struct tr_info *tr = ch->parent; 691 692 /* return current byte offset of channel */ 693 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer); 694} 695 696static struct pcmchan_caps * 697trrchan_getcaps(kobj_t obj, void *data) 698{ 699 return &tr_reccaps; 700} 701 702static kobj_method_t trrchan_methods[] = { 703 KOBJMETHOD(channel_init, trrchan_init), 704 KOBJMETHOD(channel_setformat, trrchan_setformat), 705 KOBJMETHOD(channel_setspeed, trrchan_setspeed), 706 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize), 707 KOBJMETHOD(channel_trigger, trrchan_trigger), 708 KOBJMETHOD(channel_getptr, trrchan_getptr), 709 KOBJMETHOD(channel_getcaps, trrchan_getcaps), 710 { 0, 0 } 711}; 712CHANNEL_DECLARE(trrchan); 713 714/* -------------------------------------------------------------------- */ 715/* The interrupt handler */ 716 717static void 718tr_intr(void *p) 719{ 720 struct tr_info *tr = (struct tr_info *)p; 721 struct tr_chinfo *ch; 722 u_int32_t active, mask, bufhalf, chnum, intsrc; 723 int tmp; 724 725 intsrc = tr_rd(tr, TR_REG_MISCINT, 4); 726 if (intsrc & TR_INT_ADDR) { 727 chnum = 0; 728 while (chnum < 64) { 729 mask = 0x00000001; 730 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); 731 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); 732 if (active) { 733 do { 734 if (active & mask) { 735 tmp = (bufhalf & mask)? 1 : 0; 736 if (chnum < tr->playchns) { 737 ch = &tr->chinfo[chnum]; 738 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */ 739 if (ch->bufhalf != tmp) { 740 chn_intr(ch->channel); 741 ch->bufhalf = tmp; 742 } 743 } 744 } 745 chnum++; 746 mask <<= 1; 747 } while (chnum & 31); 748 } else 749 chnum += 32; 750 751 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4); 752 } 753 } 754 if (intsrc & TR_INT_SB) { 755 chn_intr(tr->recchinfo.channel); 756 tr_rd(tr, TR_REG_SBR9, 1); 757 tr_rd(tr, TR_REG_SBR10, 1); 758 } 759} 760 761/* -------------------------------------------------------------------- */ 762 763/* 764 * Probe and attach the card 765 */ 766 767static int 768tr_init(struct tr_info *tr) 769{ 770 switch (tr->type) { 771 case SPA_PCI_ID: 772 tr_wr(tr, SPA_REG_GPIO, 0, 4); 773 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); 774 break; 775 case TDX_PCI_ID: 776 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); 777 break; 778 case TNX_PCI_ID: 779 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4); 780 break; 781 } 782 783 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4); 784 return 0; 785} 786 787static int 788tr_pci_probe(device_t dev) 789{ 790 switch (pci_get_devid(dev)) { 791 case SPA_PCI_ID: 792 device_set_desc(dev, "SiS 7018"); 793 return BUS_PROBE_DEFAULT; 794 case ALI_PCI_ID: 795 device_set_desc(dev, "Acer Labs M5451"); 796 return BUS_PROBE_DEFAULT; 797 case TDX_PCI_ID: 798 device_set_desc(dev, "Trident 4DWave DX"); 799 return BUS_PROBE_DEFAULT; 800 case TNX_PCI_ID: 801 device_set_desc(dev, "Trident 4DWave NX"); 802 return BUS_PROBE_DEFAULT; 803 } 804 805 return ENXIO; 806} 807 808static int 809tr_pci_attach(device_t dev) 810{ 811 u_int32_t data; 812 struct tr_info *tr; 813 struct ac97_info *codec = 0; 814 int i, dacn; 815 char status[SND_STATUSLEN]; 816 817 tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO); 818 tr->type = pci_get_devid(dev); 819 tr->rev = pci_get_revid(dev); 820 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc"); 821 822 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 823 "dac", &i) == 0) { 824 if (i < 1) 825 dacn = 1; 826 else if (i > TR_MAXPLAYCH) 827 dacn = TR_MAXPLAYCH; 828 else 829 dacn = i; 830 } else { 831 switch (tr->type) { 832 case ALI_PCI_ID: 833 dacn = 1; 834 break; 835 default: 836 dacn = TR_MAXPLAYCH; 837 break; 838 } 839 } 840 841 data = pci_read_config(dev, PCIR_COMMAND, 2); 842 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 843 pci_write_config(dev, PCIR_COMMAND, data, 2); 844 data = pci_read_config(dev, PCIR_COMMAND, 2); 845 846 tr->regid = PCIR_BAR(0); 847 tr->regtype = SYS_RES_IOPORT; 848 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid, 849 RF_ACTIVE); 850 if (tr->reg) { 851 tr->st = rman_get_bustag(tr->reg); 852 tr->sh = rman_get_bushandle(tr->reg); 853 } else { 854 device_printf(dev, "unable to map register space\n"); 855 goto bad; 856 } 857 858 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 65536); 859 860 if (tr_init(tr) == -1) { 861 device_printf(dev, "unable to initialize the card\n"); 862 goto bad; 863 } 864 tr->playchns = 0; 865 866 codec = AC97_CREATE(dev, tr, tr_ac97); 867 if (codec == NULL) goto bad; 868 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 869 870 tr->irqid = 0; 871 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid, 872 RF_ACTIVE | RF_SHAREABLE); 873 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) { 874 device_printf(dev, "unable to map interrupt\n"); 875 goto bad; 876 } 877 878 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 879 /*boundary*/0, 880 /*lowaddr*/TR_MAXADDR, 881 /*highaddr*/BUS_SPACE_MAXADDR, 882 /*filter*/NULL, /*filterarg*/NULL, 883 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 884 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 885 /*lockarg*/&Giant, &tr->parent_dmat) != 0) { 886 device_printf(dev, "unable to create dma tag\n"); 887 goto bad; 888 } 889 890 snprintf(status, 64, "at io 0x%lx irq %ld %s", 891 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave)); 892 893 if (pcm_register(dev, tr, dacn, 1)) 894 goto bad; 895 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr); 896 for (i = 0; i < dacn; i++) 897 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr); 898 pcm_setstatus(dev, status); 899 900 return 0; 901 902bad: 903 if (codec) ac97_destroy(codec); 904 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 905 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih); 906 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 907 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat); 908 if (tr->lock) snd_mtxfree(tr->lock); 909 free(tr, M_DEVBUF); 910 return ENXIO; 911} 912 913static int 914tr_pci_detach(device_t dev) 915{ 916 int r; 917 struct tr_info *tr; 918 919 r = pcm_unregister(dev); 920 if (r) 921 return r; 922 923 tr = pcm_getdevinfo(dev); 924 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 925 bus_teardown_intr(dev, tr->irq, tr->ih); 926 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 927 bus_dma_tag_destroy(tr->parent_dmat); 928 snd_mtxfree(tr->lock); 929 free(tr, M_DEVBUF); 930 931 return 0; 932} 933 934static int 935tr_pci_suspend(device_t dev) 936{ 937 int i; 938 struct tr_info *tr; 939 940 tr = pcm_getdevinfo(dev); 941 942 for (i = 0; i < tr->playchns; i++) { 943 tr->chinfo[i].was_active = tr->chinfo[i].active; 944 if (tr->chinfo[i].active) { 945 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP); 946 } 947 } 948 949 tr->recchinfo.was_active = tr->recchinfo.active; 950 if (tr->recchinfo.active) { 951 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP); 952 } 953 954 return 0; 955} 956 957static int 958tr_pci_resume(device_t dev) 959{ 960 int i; 961 struct tr_info *tr; 962 963 tr = pcm_getdevinfo(dev); 964 965 if (tr_init(tr) == -1) { 966 device_printf(dev, "unable to initialize the card\n"); 967 return ENXIO; 968 } 969 970 if (mixer_reinit(dev) == -1) { 971 device_printf(dev, "unable to initialize the mixer\n"); 972 return ENXIO; 973 } 974 975 for (i = 0; i < tr->playchns; i++) { 976 if (tr->chinfo[i].was_active) { 977 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START); 978 } 979 } 980 981 if (tr->recchinfo.was_active) { 982 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START); 983 } 984 985 return 0; 986} 987 988static device_method_t tr_methods[] = { 989 /* Device interface */ 990 DEVMETHOD(device_probe, tr_pci_probe), 991 DEVMETHOD(device_attach, tr_pci_attach), 992 DEVMETHOD(device_detach, tr_pci_detach), 993 DEVMETHOD(device_suspend, tr_pci_suspend), 994 DEVMETHOD(device_resume, tr_pci_resume), 995 { 0, 0 } 996}; 997 998static driver_t tr_driver = { 999 "pcm", 1000 tr_methods, 1001 PCM_SOFTC_SIZE, 1002}; 1003 1004DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, 0, 0); 1005MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1006MODULE_VERSION(snd_t4dwave, 1); 1007