ich.c revision 94647
179047Scg/* 279047Scg * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 379148Scg * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 479047Scg * All rights reserved. 579047Scg * 679047Scg * Redistribution and use in source and binary forms, with or without 779047Scg * modification, are permitted provided that the following conditions 879047Scg * are met: 979047Scg * 1. Redistributions of source code must retain the above copyright 1079047Scg * notice, this list of conditions and the following disclaimer. 1179047Scg * 2. Redistributions in binary form must reproduce the above copyright 1279047Scg * notice, this list of conditions and the following disclaimer in the 1379047Scg * documentation and/or other materials provided with the distribution. 1479047Scg * 1579047Scg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1679047Scg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1779047Scg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1879047Scg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1979047Scg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2079047Scg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2179047Scg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2279047Scg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 2379047Scg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2479047Scg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 2579047Scg * SUCH DAMAGE. 2679047Scg */ 2779047Scg 2879047Scg#include <dev/sound/pcm/sound.h> 2979047Scg#include <dev/sound/pcm/ac97.h> 3079148Scg#include <dev/sound/pci/ich.h> 3179047Scg 3279047Scg#include <pci/pcireg.h> 3379047Scg#include <pci/pcivar.h> 3479047Scg 3582180ScgSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 94647 2002-04-14 10:39:59Z jhay $"); 3682180Scg 3779047Scg/* -------------------------------------------------------------------- */ 3879047Scg 3979047Scg#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 4079148Scg#define ICH_DTBL_LENGTH 32 4179148Scg#define ICH_DEFAULT_BUFSZ 16384 4283617Scg#define ICH_MAX_BUFSZ 65536 4379047Scg 4490880Salfred#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 4590880Salfred 4679047Scg/* buffer descriptor */ 4779047Scgstruct ich_desc { 4879047Scg volatile u_int32_t buffer; 4979047Scg volatile u_int32_t length; 5079047Scg}; 5179047Scg 5279047Scgstruct sc_info; 5379047Scg 5479047Scg/* channel registers */ 5579047Scgstruct sc_chinfo { 5688361Sorion u_int32_t num:8, run:1, run_save:1; 5788361Sorion u_int32_t blksz, blkcnt, spd; 5879148Scg u_int32_t regbase, spdreg; 5988206Sorion u_int32_t imask; 6082478Scg u_int32_t civ; 6179148Scg 6279047Scg struct snd_dbuf *buffer; 6379047Scg struct pcm_channel *channel; 6479047Scg struct sc_info *parent; 6579148Scg 6679148Scg struct ich_desc *dtbl; 6779047Scg}; 6879047Scg 6979047Scg/* device private data */ 7079047Scgstruct sc_info { 7179148Scg device_t dev; 7283617Scg int hasvra, hasvrm, hasmic; 7383617Scg unsigned int chnum, bufsz; 7490880Salfred int sample_size, swap_reg; 7579047Scg 7679148Scg struct resource *nambar, *nabmbar, *irq; 7779148Scg int nambarid, nabmbarid, irqid; 7879047Scg bus_space_tag_t nambart, nabmbart; 7979047Scg bus_space_handle_t nambarh, nabmbarh; 8079047Scg bus_dma_tag_t dmat; 8179148Scg bus_dmamap_t dtmap; 8279148Scg void *ih; 8379047Scg 8479047Scg struct ac97_info *codec; 8579148Scg struct sc_chinfo ch[3]; 8688033Sorion int ac97rate; 8779148Scg struct ich_desc *dtbl; 8879047Scg}; 8979047Scg 9079047Scg/* -------------------------------------------------------------------- */ 9179047Scg 9279148Scgstatic u_int32_t ich_fmt[] = { 9379047Scg AFMT_STEREO | AFMT_S16_LE, 9479047Scg 0 9579047Scg}; 9679148Scgstatic struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 9779148Scgstatic struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 9879047Scg 9979047Scg/* -------------------------------------------------------------------- */ 10079047Scg/* Hardware */ 10179047Scgstatic u_int32_t 10279047Scgich_rd(struct sc_info *sc, int regno, int size) 10379047Scg{ 10479047Scg switch (size) { 10579047Scg case 1: 10679148Scg return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 10779047Scg case 2: 10879148Scg return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 10979047Scg case 4: 11079148Scg return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 11179047Scg default: 11279047Scg return 0xffffffff; 11379047Scg } 11479047Scg} 11579047Scg 11679047Scgstatic void 11779047Scgich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 11879047Scg{ 11979047Scg switch (size) { 12079047Scg case 1: 12179148Scg bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 12279047Scg break; 12379047Scg case 2: 12479148Scg bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 12579047Scg break; 12679047Scg case 4: 12779148Scg bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 12879047Scg break; 12979047Scg } 13079047Scg} 13179047Scg 13279047Scg/* ac97 codec */ 13379047Scgstatic int 13479047Scgich_waitcd(void *devinfo) 13579047Scg{ 13679047Scg int i; 13779047Scg u_int32_t data; 13879047Scg struct sc_info *sc = (struct sc_info *)devinfo; 13979148Scg 14079148Scg for (i = 0; i < ICH_TIMEOUT; i++) { 14179148Scg data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 14279047Scg if ((data & 0x01) == 0) 14379047Scg return 0; 14479047Scg } 14579047Scg device_printf(sc->dev, "CODEC semaphore timeout\n"); 14679047Scg return ETIMEDOUT; 14779047Scg} 14879047Scg 14979047Scgstatic int 15079047Scgich_rdcd(kobj_t obj, void *devinfo, int regno) 15179047Scg{ 15279047Scg struct sc_info *sc = (struct sc_info *)devinfo; 15379148Scg 15479047Scg regno &= 0xff; 15579047Scg ich_waitcd(sc); 15679148Scg 15779148Scg return bus_space_read_2(sc->nambart, sc->nambarh, regno); 15879047Scg} 15979047Scg 16079047Scgstatic int 16179148Scgich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 16279047Scg{ 16379047Scg struct sc_info *sc = (struct sc_info *)devinfo; 16479148Scg 16579047Scg regno &= 0xff; 16679047Scg ich_waitcd(sc); 16779148Scg bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 16879148Scg 16979047Scg return 0; 17079047Scg} 17179047Scg 17279047Scgstatic kobj_method_t ich_ac97_methods[] = { 17379047Scg KOBJMETHOD(ac97_read, ich_rdcd), 17479047Scg KOBJMETHOD(ac97_write, ich_wrcd), 17579047Scg { 0, 0 } 17679047Scg}; 17779047ScgAC97_DECLARE(ich_ac97); 17879047Scg 17979047Scg/* -------------------------------------------------------------------- */ 18079148Scg/* common routines */ 18179047Scg 18279047Scgstatic void 18379148Scgich_filldtbl(struct sc_chinfo *ch) 18479047Scg{ 18579148Scg u_int32_t base; 18682478Scg int i; 18779047Scg 18879148Scg base = vtophys(sndbuf_getbuf(ch->buffer)); 18979148Scg ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 19079148Scg if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 19179148Scg ch->blkcnt = 2; 19279148Scg ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 19379047Scg } 19479047Scg 19579148Scg for (i = 0; i < ICH_DTBL_LENGTH; i++) { 19682478Scg ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 19790880Salfred ch->dtbl[i].length = ICH_BDC_IOC 19890880Salfred | (ch->blksz / ch->parent->sample_size); 19979047Scg } 20079047Scg} 20179047Scg 20279148Scgstatic int 20379148Scgich_resetchan(struct sc_info *sc, int num) 20479047Scg{ 20579148Scg int i, cr, regbase; 20679047Scg 20779148Scg if (num == 0) 20879148Scg regbase = ICH_REG_PO_BASE; 20979148Scg else if (num == 1) 21079148Scg regbase = ICH_REG_PI_BASE; 21179148Scg else if (num == 2) 21279148Scg regbase = ICH_REG_MC_BASE; 21379148Scg else 21479148Scg return ENXIO; 21579047Scg 21679148Scg ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 21779148Scg DELAY(100); 21879148Scg ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 21979148Scg for (i = 0; i < ICH_TIMEOUT; i++) { 22079148Scg cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 22179148Scg if (cr == 0) 22279148Scg return 0; 22379148Scg } 22479047Scg 22579148Scg device_printf(sc->dev, "cannot reset channel %d\n", num); 22679148Scg return ENXIO; 22779047Scg} 22879047Scg 22979148Scg/* -------------------------------------------------------------------- */ 23079148Scg/* channel interface */ 23179047Scg 23279047Scgstatic void * 23379148Scgichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 23479047Scg{ 23579047Scg struct sc_info *sc = devinfo; 23679047Scg struct sc_chinfo *ch; 23783617Scg unsigned int num; 23879047Scg 23979148Scg num = sc->chnum++; 24079148Scg ch = &sc->ch[num]; 24179148Scg ch->num = num; 24279047Scg ch->buffer = b; 24379047Scg ch->channel = c; 24479047Scg ch->parent = sc; 24579047Scg ch->run = 0; 24679148Scg ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 24779148Scg ch->blkcnt = 2; 24883617Scg ch->blksz = sc->bufsz / ch->blkcnt; 24979047Scg 25079148Scg switch(ch->num) { 25179148Scg case 0: /* play */ 25279148Scg KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 25379148Scg ch->regbase = ICH_REG_PO_BASE; 25479148Scg ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 25588206Sorion ch->imask = ICH_GLOB_STA_POINT; 25679148Scg break; 25779047Scg 25882478Scg case 1: /* record */ 25979148Scg KASSERT(dir == PCMDIR_REC, ("wrong direction")); 26082478Scg ch->regbase = ICH_REG_PI_BASE; 26182478Scg ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 26288206Sorion ch->imask = ICH_GLOB_STA_PIINT; 26379148Scg break; 26479047Scg 26582478Scg case 2: /* mic */ 26679148Scg KASSERT(dir == PCMDIR_REC, ("wrong direction")); 26782478Scg ch->regbase = ICH_REG_MC_BASE; 26882478Scg ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 26988206Sorion ch->imask = ICH_GLOB_STA_MINT; 27079148Scg break; 27179047Scg 27279148Scg default: 27379148Scg return NULL; 27479047Scg } 27579047Scg 27683617Scg if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 27779148Scg return NULL; 27879047Scg 27979148Scg ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 28079047Scg 28179148Scg return ch; 28279047Scg} 28379047Scg 28479047Scgstatic int 28579148Scgichchan_setformat(kobj_t obj, void *data, u_int32_t format) 28679047Scg{ 28779047Scg return 0; 28879047Scg} 28979047Scg 29079047Scgstatic int 29179148Scgichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 29279047Scg{ 29379047Scg struct sc_chinfo *ch = data; 29479047Scg struct sc_info *sc = ch->parent; 29579047Scg 29688033Sorion if (ch->spdreg) { 29788033Sorion int r; 29888033Sorion if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 29988033Sorion sc->ac97rate = 48000; 30089516Sorion r = (speed * 48000) / sc->ac97rate; 30194647Sjhay /* 30294647Sjhay * Cast the return value of ac97_setrate() to u_int so that 30394647Sjhay * the math don't overflow into the negative range. 30494647Sjhay */ 30594647Sjhay ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 30694647Sjhay sc->ac97rate) / 48000; 30788033Sorion } else { 30888361Sorion ch->spd = 48000; 30988033Sorion } 31088361Sorion return ch->spd; 31179047Scg} 31279047Scg 31379047Scgstatic int 31479148Scgichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 31579047Scg{ 31679047Scg struct sc_chinfo *ch = data; 31779148Scg struct sc_info *sc = ch->parent; 31879047Scg 31979148Scg ch->blksz = blocksize; 32079148Scg ich_filldtbl(ch); 32182478Scg ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 32279047Scg 32379148Scg return ch->blksz; 32479047Scg} 32579047Scg 32679047Scgstatic int 32779148Scgichchan_trigger(kobj_t obj, void *data, int go) 32879047Scg{ 32979047Scg struct sc_chinfo *ch = data; 33079047Scg struct sc_info *sc = ch->parent; 33179047Scg 33279047Scg switch (go) { 33379047Scg case PCMTRIG_START: 33479047Scg ch->run = 1; 33579148Scg ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 33689516Sorion ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 33779047Scg break; 33879148Scg 33979047Scg case PCMTRIG_ABORT: 34079148Scg ich_resetchan(sc, ch->num); 34179047Scg ch->run = 0; 34279047Scg break; 34379047Scg } 34479047Scg return 0; 34579047Scg} 34679047Scg 34779047Scgstatic int 34879148Scgichchan_getptr(kobj_t obj, void *data) 34979047Scg{ 35079047Scg struct sc_chinfo *ch = data; 35179047Scg struct sc_info *sc = ch->parent; 35282478Scg u_int32_t pos; 35379047Scg 35482478Scg ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 35579148Scg 35682478Scg pos = ch->civ * ch->blksz; 35779148Scg 35879148Scg return pos; 35979047Scg} 36079047Scg 36179047Scgstatic struct pcmchan_caps * 36279148Scgichchan_getcaps(kobj_t obj, void *data) 36379047Scg{ 36479148Scg struct sc_chinfo *ch = data; 36579148Scg 36679148Scg return ch->spdreg? &ich_vrcaps : &ich_caps; 36779047Scg} 36879047Scg 36979148Scgstatic kobj_method_t ichchan_methods[] = { 37079148Scg KOBJMETHOD(channel_init, ichchan_init), 37179148Scg KOBJMETHOD(channel_setformat, ichchan_setformat), 37279148Scg KOBJMETHOD(channel_setspeed, ichchan_setspeed), 37379148Scg KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 37479148Scg KOBJMETHOD(channel_trigger, ichchan_trigger), 37579148Scg KOBJMETHOD(channel_getptr, ichchan_getptr), 37679148Scg KOBJMETHOD(channel_getcaps, ichchan_getcaps), 37779047Scg { 0, 0 } 37879047Scg}; 37979148ScgCHANNEL_DECLARE(ichchan); 38079047Scg 38179047Scg/* -------------------------------------------------------------------- */ 38279047Scg/* The interrupt handler */ 38379148Scg 38479047Scgstatic void 38579047Scgich_intr(void *p) 38679047Scg{ 38779047Scg struct sc_info *sc = (struct sc_info *)p; 38879047Scg struct sc_chinfo *ch; 38988206Sorion u_int32_t cbi, lbi, lvi, st, gs; 39079148Scg int i; 39179047Scg 39288215Sorion gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 39388206Sorion if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 39488206Sorion /* Clear resume interrupt(s) - nothing doing with them */ 39588206Sorion ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 39688206Sorion } 39788206Sorion gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 39888206Sorion 39979148Scg for (i = 0; i < 3; i++) { 40079148Scg ch = &sc->ch[i]; 40188206Sorion if ((ch->imask & gs) == 0) 40288206Sorion continue; 40388206Sorion gs &= ~ch->imask; 40490880Salfred st = ich_rd(sc, ch->regbase + 40590880Salfred (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 40690880Salfred 2); 40779148Scg st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 40888206Sorion if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 40979148Scg /* block complete - update buffer */ 41088206Sorion if (ch->run) 41188206Sorion chn_intr(ch->channel); 41288206Sorion lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 41388206Sorion cbi = ch->civ % ch->blkcnt; 41488206Sorion if (cbi == 0) 41588206Sorion cbi = ch->blkcnt - 1; 41688206Sorion else 41788206Sorion cbi--; 41888206Sorion lbi = lvi % ch->blkcnt; 41988206Sorion if (cbi >= lbi) 42088206Sorion lvi += cbi - lbi; 42188206Sorion else 42288206Sorion lvi += cbi + ch->blkcnt - lbi; 42388206Sorion lvi %= ICH_DTBL_LENGTH; 42488206Sorion ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 42588206Sorion 42679047Scg } 42788206Sorion /* clear status bit */ 42890880Salfred ich_wr(sc, ch->regbase + 42990880Salfred (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 43090880Salfred st, 2); 43179047Scg } 43288206Sorion if (gs != 0) { 43388206Sorion device_printf(sc->dev, 43488206Sorion "Unhandled interrupt, gs_intr = %x\n", gs); 43588206Sorion } 43679047Scg} 43779047Scg 43888033Sorion/* ------------------------------------------------------------------------- */ 43988033Sorion/* Sysctl to control ac97 speed (some boards overclocked ac97). */ 44088033Sorion 44188033Sorionstatic int 44288033Sorionich_initsys(struct sc_info* sc) 44388033Sorion{ 44488033Sorion#ifdef SND_DYNSYSCTL 44588033Sorion SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 44688033Sorion SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 44788033Sorion OID_AUTO, "ac97rate", CTLFLAG_RW, 44888033Sorion &sc->ac97rate, 48000, 44988033Sorion "AC97 link rate (default = 48000)"); 45088033Sorion#endif /* SND_DYNSYSCTL */ 45188033Sorion return 0; 45288033Sorion} 45388033Sorion 45479047Scg/* -------------------------------------------------------------------- */ 45588108Sorion/* Calibrate card (some boards are overclocked and need scaling) */ 45688108Sorion 45788108Sorionstatic 45888108Sorionunsigned int ich_calibrate(struct sc_info *sc) 45988108Sorion{ 46089516Sorion struct sc_chinfo *ch = &sc->ch[1]; 46189516Sorion struct timeval t1, t2; 46289516Sorion u_int8_t ociv, nciv; 46389516Sorion u_int32_t wait_us, actual_48k_rate, bytes; 46489516Sorion 46589516Sorion /* 46689516Sorion * Grab audio from input for fixed interval and compare how 46788108Sorion * much we actually get with what we expect. Interval needs 46888108Sorion * to be sufficiently short that no interrupts are 46989516Sorion * generated. 47089516Sorion */ 47189516Sorion 47288108Sorion KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 47388108Sorion 47489516Sorion bytes = sndbuf_getsize(ch->buffer) / 2; 47589516Sorion ichchan_setblocksize(0, ch, bytes); 47688108Sorion 47789516Sorion /* 47889516Sorion * our data format is stereo, 16 bit so each sample is 4 bytes. 47989516Sorion * assuming we get 48000 samples per second, we get 192000 bytes/sec. 48089516Sorion * we're going to start recording with interrupts disabled and measure 48189516Sorion * the time taken for one block to complete. we know the block size, 48289516Sorion * we know the time in microseconds, we calculate the sample rate: 48389516Sorion * 48489516Sorion * actual_rate [bps] = bytes / (time [s] * 4) 48589516Sorion * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 48689516Sorion * actual_rate [Hz] = (bytes * 250000) / time [us] 48789516Sorion */ 48888108Sorion 48989516Sorion /* prepare */ 49089516Sorion ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 49189516Sorion nciv = ociv; 49289516Sorion ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 49388108Sorion 49489516Sorion /* start */ 49589516Sorion microtime(&t1); 49689516Sorion ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 49788108Sorion 49889516Sorion /* wait */ 49989516Sorion while (nciv == ociv) { 50089516Sorion microtime(&t2); 50189516Sorion if (t2.tv_sec - t1.tv_sec > 1) 50289516Sorion break; 50389516Sorion nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 50489516Sorion } 50589516Sorion microtime(&t2); 50689516Sorion 50789516Sorion /* stop */ 50889516Sorion ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 50989516Sorion 51089516Sorion /* reset */ 51189516Sorion DELAY(100); 51289516Sorion ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 51389516Sorion 51489516Sorion /* turn time delta into us */ 51589516Sorion wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 51689516Sorion 51789516Sorion if (nciv == ociv) { 51889516Sorion device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 51989516Sorion return 0; 52089516Sorion } 52189516Sorion 52289516Sorion actual_48k_rate = (bytes * 250000) / wait_us; 52389516Sorion 52489516Sorion if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 52588108Sorion sc->ac97rate = actual_48k_rate; 52688108Sorion } else { 52788108Sorion sc->ac97rate = 48000; 52888108Sorion } 52988209Sorion 53089516Sorion if (bootverbose || sc->ac97rate != 48000) { 53189516Sorion device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 53289516Sorion if (sc->ac97rate != actual_48k_rate) 53389516Sorion printf(", will use %d Hz", sc->ac97rate); 53489516Sorion printf("\n"); 53589516Sorion } 53688209Sorion 53788108Sorion return sc->ac97rate; 53888108Sorion} 53988108Sorion 54088108Sorion/* -------------------------------------------------------------------- */ 54179148Scg/* Probe and attach the card */ 54279047Scg 54379148Scgstatic void 54479148Scgich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 54579148Scg{ 54679148Scg return; 54779148Scg} 54879047Scg 54979047Scgstatic int 55079047Scgich_init(struct sc_info *sc) 55179047Scg{ 55279047Scg u_int32_t stat; 55379148Scg int sz; 55479047Scg 55579148Scg ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 55679047Scg DELAY(600000); 55779148Scg stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 55879148Scg 55979047Scg if ((stat & ICH_GLOB_STA_PCR) == 0) 56079148Scg return ENXIO; 56179047Scg 56279148Scg ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 56379047Scg 56483617Scg if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 56579148Scg return ENXIO; 56683617Scg if (sc->hasmic && ich_resetchan(sc, 2)) 56783617Scg return ENXIO; 56879148Scg 56979148Scg if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 57079148Scg return ENOSPC; 57179148Scg 57279148Scg sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 57379148Scg if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 57479148Scg bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 57579148Scg return ENOSPC; 57679047Scg } 57779148Scg 57879148Scg return 0; 57979047Scg} 58079047Scg 58179047Scgstatic int 58279047Scgich_pci_probe(device_t dev) 58379047Scg{ 58479148Scg switch(pci_get_devid(dev)) { 58579148Scg case 0x71958086: 58679148Scg device_set_desc(dev, "Intel 443MX"); 58779148Scg return 0; 58879047Scg 58979148Scg case 0x24158086: 59079148Scg device_set_desc(dev, "Intel 82801AA (ICH)"); 59179047Scg return 0; 59279148Scg 59379148Scg case 0x24258086: 59485946Speter device_set_desc(dev, "Intel 82801AB (ICH)"); 59579148Scg return 0; 59679148Scg 59779148Scg case 0x24458086: 59879148Scg device_set_desc(dev, "Intel 82801BA (ICH2)"); 59979148Scg return 0; 60079148Scg 60185946Speter case 0x24858086: 60285946Speter device_set_desc(dev, "Intel 82801CA (ICH3)"); 60385946Speter return 0; 60485946Speter 60590880Salfred case SIS7012ID: 60690880Salfred device_set_desc(dev, "SiS 7012"); 60790880Salfred return 0; 60890880Salfred 60979148Scg default: 61079047Scg return ENXIO; 61179148Scg } 61279047Scg} 61379047Scg 61479047Scgstatic int 61579047Scgich_pci_attach(device_t dev) 61679047Scg{ 61779047Scg u_int32_t data; 61886708Sorion u_int16_t extcaps; 61979047Scg struct sc_info *sc; 62079047Scg char status[SND_STATUSLEN]; 62179047Scg 62279047Scg if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 62379047Scg device_printf(dev, "cannot allocate softc\n"); 62479047Scg return ENXIO; 62579047Scg } 62679047Scg 62779047Scg bzero(sc, sizeof(*sc)); 62879047Scg sc->dev = dev; 62979047Scg 63090880Salfred /* 63190880Salfred * The SiS 7012 register set isn't quite like the standard ich. 63290880Salfred * There really should be a general "quirks" mechanism. 63390880Salfred */ 63490880Salfred if (pci_get_devid(dev) == SIS7012ID) { 63590880Salfred sc->swap_reg = 1; 63690880Salfred sc->sample_size = 1; 63790880Salfred } else { 63890880Salfred sc->swap_reg = 0; 63990880Salfred sc->sample_size = 2; 64090880Salfred } 64190880Salfred 64279047Scg data = pci_read_config(dev, PCIR_COMMAND, 2); 64379047Scg data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 64479047Scg pci_write_config(dev, PCIR_COMMAND, data, 2); 64579047Scg data = pci_read_config(dev, PCIR_COMMAND, 2); 64679047Scg 64779047Scg sc->nambarid = PCIR_NAMBAR; 64879047Scg sc->nabmbarid = PCIR_NABMBAR; 64979148Scg sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 65079148Scg sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 65179148Scg 65279047Scg if (!sc->nambar || !sc->nabmbar) { 65379047Scg device_printf(dev, "unable to map IO port space\n"); 65479047Scg goto bad; 65579047Scg } 65679148Scg 65779047Scg sc->nambart = rman_get_bustag(sc->nambar); 65879047Scg sc->nambarh = rman_get_bushandle(sc->nambar); 65979047Scg sc->nabmbart = rman_get_bustag(sc->nabmbar); 66079047Scg sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 66179047Scg 66283617Scg sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 66382478Scg if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 66483617Scg NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 66579047Scg device_printf(dev, "unable to create dma tag\n"); 66679047Scg goto bad; 66779047Scg } 66879047Scg 66989516Sorion sc->irqid = 0; 67089516Sorion sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 67189516Sorion if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 67289516Sorion device_printf(dev, "unable to map interrupt\n"); 67389516Sorion goto bad; 67489516Sorion } 67589516Sorion 67679148Scg if (ich_init(sc)) { 67779047Scg device_printf(dev, "unable to initialize the card\n"); 67879047Scg goto bad; 67979047Scg } 68079047Scg 68179047Scg sc->codec = AC97_CREATE(dev, sc, ich_ac97); 68279047Scg if (sc->codec == NULL) 68379047Scg goto bad; 68479047Scg mixer_init(dev, ac97_getmixerclass(), sc->codec); 68579148Scg 68679047Scg /* check and set VRA function */ 68786795Sorion extcaps = ac97_getextcaps(sc->codec); 68886708Sorion sc->hasvra = extcaps & AC97_EXTCAP_VRA; 68986708Sorion sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 69094647Sjhay sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 69194647Sjhay ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 69279047Scg 69384641Scg if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 69479148Scg goto bad; 69579047Scg 69683617Scg pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 69783617Scg pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 69883617Scg if (sc->hasmic) 69983617Scg pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 70079148Scg 70184641Scg snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 70284641Scg rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 70379148Scg 70479047Scg pcm_setstatus(dev, status); 70579047Scg 70688033Sorion ich_initsys(sc); 70788108Sorion ich_calibrate(sc); 70888033Sorion 70979047Scg return 0; 71079047Scg 71179047Scgbad: 71279047Scg if (sc->codec) 71379047Scg ac97_destroy(sc->codec); 71489516Sorion if (sc->ih) 71589516Sorion bus_teardown_intr(dev, sc->irq, sc->ih); 71689516Sorion if (sc->irq) 71789516Sorion bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 71879047Scg if (sc->nambar) 71979047Scg bus_release_resource(dev, SYS_RES_IOPORT, 72079047Scg sc->nambarid, sc->nambar); 72179047Scg if (sc->nabmbar) 72279047Scg bus_release_resource(dev, SYS_RES_IOPORT, 72379047Scg sc->nabmbarid, sc->nabmbar); 72479047Scg free(sc, M_DEVBUF); 72579047Scg return ENXIO; 72679047Scg} 72779047Scg 72879047Scgstatic int 72979047Scgich_pci_detach(device_t dev) 73079047Scg{ 73179047Scg struct sc_info *sc; 73279047Scg int r; 73379047Scg 73479047Scg r = pcm_unregister(dev); 73579047Scg if (r) 73679047Scg return r; 73779047Scg sc = pcm_getdevinfo(dev); 73879047Scg 73979148Scg bus_teardown_intr(dev, sc->irq, sc->ih); 74079148Scg bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 74179047Scg bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 74279047Scg bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 74379047Scg bus_dma_tag_destroy(sc->dmat); 74479047Scg free(sc, M_DEVBUF); 74579047Scg return 0; 74679047Scg} 74779047Scg 74879047Scgstatic int 74988361Sorionich_pci_suspend(device_t dev) 75088361Sorion{ 75188361Sorion struct sc_info *sc; 75288361Sorion int i; 75388361Sorion 75488361Sorion sc = pcm_getdevinfo(dev); 75588361Sorion for (i = 0 ; i < 3; i++) { 75688361Sorion sc->ch[i].run_save = sc->ch[i].run; 75788361Sorion if (sc->ch[i].run) { 75888361Sorion ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 75988361Sorion } 76088361Sorion } 76188361Sorion 76288361Sorion /* ACLINK shut off */ 76388361Sorion ich_wr(sc,ICH_REG_GLOB_CNT, ICH_GLOB_CTL_SHUT, 4); 76488361Sorion return 0; 76588361Sorion} 76688361Sorion 76788361Sorionstatic int 76879047Scgich_pci_resume(device_t dev) 76979047Scg{ 77079047Scg struct sc_info *sc; 77188361Sorion int i; 77279047Scg 77379047Scg sc = pcm_getdevinfo(dev); 77479047Scg 77579047Scg /* Reinit audio device */ 77679047Scg if (ich_init(sc) == -1) { 77779047Scg device_printf(dev, "unable to reinitialize the card\n"); 77879047Scg return ENXIO; 77979047Scg } 78079047Scg /* Reinit mixer */ 78179047Scg if (mixer_reinit(dev) == -1) { 78279047Scg device_printf(dev, "unable to reinitialize the mixer\n"); 78379047Scg return ENXIO; 78479047Scg } 78588361Sorion /* Re-start DMA engines */ 78688361Sorion for (i = 0 ; i < 3; i++) { 78788361Sorion struct sc_chinfo *ch = &sc->ch[i]; 78888361Sorion if (sc->ch[i].run_save) { 78988361Sorion ichchan_setblocksize(0, ch, ch->blksz); 79088361Sorion ichchan_setspeed(0, ch, ch->spd); 79188361Sorion ichchan_trigger(0, ch, PCMTRIG_START); 79288361Sorion } 79388361Sorion } 79479047Scg return 0; 79579047Scg} 79679047Scg 79779047Scgstatic device_method_t ich_methods[] = { 79879047Scg /* Device interface */ 79979047Scg DEVMETHOD(device_probe, ich_pci_probe), 80079047Scg DEVMETHOD(device_attach, ich_pci_attach), 80179047Scg DEVMETHOD(device_detach, ich_pci_detach), 80288361Sorion DEVMETHOD(device_suspend, ich_pci_suspend), 80379047Scg DEVMETHOD(device_resume, ich_pci_resume), 80479047Scg { 0, 0 } 80579047Scg}; 80679047Scg 80779047Scgstatic driver_t ich_driver = { 80879047Scg "pcm", 80979047Scg ich_methods, 81082180Scg PCM_SOFTC_SIZE, 81179047Scg}; 81279047Scg 81379047ScgDRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 81479047ScgMODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 81579047ScgMODULE_VERSION(snd_ich, 1); 816