cmireg.h revision 72016
133965Sjdp/* 2218822Sdim * Copyright (c) 2000 The NetBSD Foundation, Inc. 3218822Sdim * All rights reserved. 433965Sjdp * 533965Sjdp * This code is derived from software contributed to The NetBSD Foundation 633965Sjdp * by Takuya SHIOZAKI <AoiMoe@imou.to> . 733965Sjdp * 833965Sjdp * Redistribution and use in source and binary forms, with or without 933965Sjdp * modification, are permitted provided that the following conditions 1033965Sjdp * are met: 1133965Sjdp * 1. Redistributions of source code must retain the above copyright 1233965Sjdp * notice, this list of conditions and the following disclaimer. 1333965Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1433965Sjdp * notice, this list of conditions and the following disclaimer in the 1533965Sjdp * documentation and/or other materials provided with the distribution. 1633965Sjdp * 1733965Sjdp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1833965Sjdp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19218822Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20218822Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2133965Sjdp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2233965Sjdp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23218822Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2433965Sjdp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2533965Sjdp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2633965Sjdp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2733965Sjdp * SUCH DAMAGE. 2877298Sobrien * 2977298Sobrien * $FreeBSD: head/sys/dev/sound/pci/cmireg.h 72016 2001-02-04 19:13:40Z cg $ 3033965Sjdp */ 3133965Sjdp 3277298Sobrien/* C-Media CMI8x38 Audio Chip Support */ 3333965Sjdp 3433965Sjdp#ifndef _DEV_PCI_CMPCIREG_H_ 3533965Sjdp#define _DEV_PCI_CMPCIREG_H_ (1) 3633965Sjdp 3733965Sjdp/* 3833965Sjdp * PCI Configuration Registers 3933965Sjdp */ 4077298Sobrien 4133965Sjdp#define CMPCI_PCI_IOBASEREG (PCI_MAPREG_START) 4233965Sjdp 4333965Sjdp/* 4433965Sjdp * I/O Space 4533965Sjdp */ 4633965Sjdp 4733965Sjdp#define CMPCI_REG_FUNC_0 0x00 4833965Sjdp# define CMPCI_REG_CH0_DIR 0x00000001 4933965Sjdp# define CMPCI_REG_CH1_DIR 0x00000002 5033965Sjdp# define CMPCI_REG_CH0_PAUSE 0x00000004 5177298Sobrien# define CMPCI_REG_CH1_PAUSE 0x00000008 5277298Sobrien# define CMPCI_REG_CH0_ENABLE 0x00010000 5377298Sobrien# define CMPCI_REG_CH1_ENABLE 0x00020000 5433965Sjdp# define CMPCI_REG_CH0_RESET 0x00040000 5533965Sjdp# define CMPCI_REG_CH1_RESET 0x00080000 5633965Sjdp 5733965Sjdp#define CMPCI_REG_FUNC_1 0x04 5833965Sjdp# define CMPCI_REG_JOY_ENABLE 0x00000002 59130561Sobrien# define CMPCI_REG_UART_ENABLE 0x00000004 60130561Sobrien# define CMPCI_REG_LEGACY_ENABLE 0x00000008 6133965Sjdp# define CMPCI_REG_BREQ 0x00000010 6233965Sjdp# define CMPCI_REG_MCBINTR_ENABLE 0x00000020 6333965Sjdp# define CMPCI_REG_SPDIFOUT_DAC 0x00000040 64130561Sobrien# define CMPCI_REG_SPDIF_LOOP 0x00000080 65130561Sobrien# define CMPCI_REG_SPDIF0_ENABLE 0x00000100 66130561Sobrien# define CMPCI_REG_SPDIF1_ENABLE 0x00000200 6777298Sobrien# define CMPCI_REG_DAC_FS_SHIFT 10 68130561Sobrien# define CMPCI_REG_DAC_FS_MASK 0x00000007 6933965Sjdp# define CMPCI_REG_ADC_FS_SHIFT 13 7077298Sobrien# define CMPCI_REG_ADC_FS_MASK 0x00000007 71130561Sobrien 7277298Sobrien#define CMPCI_REG_CHANNEL_FORMAT 0x08 73130561Sobrien# define CMPCI_REG_CH0_FORMAT_SHIFT 0 7433965Sjdp# define CMPCI_REG_CH0_FORMAT_MASK 0x00000003 75130561Sobrien# define CMPCI_REG_CH1_FORMAT_SHIFT 2 7633965Sjdp# define CMPCI_REG_CH1_FORMAT_MASK 0x00000003 7777298Sobrien# define CMPCI_REG_FORMAT_MONO 0x00000000 7877298Sobrien# define CMPCI_REG_FORMAT_STEREO 0x00000001 7933965Sjdp# define CMPCI_REG_FORMAT_8BIT 0x00000000 8033965Sjdp# define CMPCI_REG_FORMAT_16BIT 0x00000002 8133965Sjdp 8233965Sjdp#define CMPCI_REG_INTR_CTRL 0x0c 8360484Sobrien# define CMPCI_REG_CH0_INTR_ENABLE 0x00010000 8433965Sjdp# define CMPCI_REG_CH1_INTR_ENABLE 0x00020000 8533965Sjdp# define CMPCI_REG_TDMA_INTR_ENABLE 0x00040000 86130561Sobrien 8733965Sjdp#define CMPCI_REG_INTR_STATUS 0x10 88130561Sobrien# define CMPCI_REG_CH0_INTR 0x00000001 89130561Sobrien# define CMPCI_REG_CH1_INTR 0x00000002 90130561Sobrien# define CMPCI_REG_CH0_BUSY 0x00000004 91130561Sobrien# define CMPCI_REG_CH1_BUSY 0x00000008 92130561Sobrien# define CMPCI_REG_LEGACY_STEREO 0x00000010 93130561Sobrien# define CMPCI_REG_LEGACY_HDMA 0x00000020 94130561Sobrien# define CMPCI_REG_DMASTAT 0x00000040 95130561Sobrien# define CMPCI_REG_XDO46 0x00000080 96130561Sobrien# define CMPCI_REG_HTDMA_INTR 0x00004000 9733965Sjdp# define CMPCI_REG_LTDMA_INTR 0x00008000 9833965Sjdp# define CMPCI_REG_UART_INTR 0x00010000 99130561Sobrien# define CMPCI_REG_MCB_INTR 0x04000000 10033965Sjdp# define CMPCI_REG_VCO 0x08000000 101130561Sobrien# define CMPCI_REG_ANY_INTR 0x80000000 102130561Sobrien 103130561Sobrien#define CMPCI_REG_LEGACY_CTRL 0x14 104130561Sobrien# define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000 105130561Sobrien# define CMPCI_REG_SPDIF_COPYRIGHT 0x00400000 106218822Sdim# define CMPCI_REG_XSPDIF_ENABLE 0x00800000 107130561Sobrien# define CMPCI_REG_FMSEL_SHIFT 24 10833965Sjdp# define CMPCI_REG_FMSEL_MASK 0x00000003 109130561Sobrien# define CMPCI_REG_VSBSEL_SHIFT 26 110130561Sobrien# define CMPCI_REG_VSBSEL_MASK 0x00000003 11133965Sjdp# define CMPCI_REG_VMPUSEL_SHIFT 29 112130561Sobrien# define CMPCI_REG_VMPUSEL_MASK 0x00000003 113130561Sobrien 114130561Sobrien#define CMPCI_REG_MISC 0x18 11533965Sjdp# define CMPCI_REG_POWER_DOWN 0x80000000 116130561Sobrien# define CMPCI_REG_BUS_AND_DSP_RESET 0x40000000 117130561Sobrien# define CMPCI_REG_W_SPDIF_48L 0x01000000 118130561Sobrien# define CMPCI_REG_SPDIF_48K 0x00008000 119130561Sobrien# define CMPCI_REG_FM_ENABLE 0x00080000 120130561Sobrien 121130561Sobrien#define CMPCI_REG_SBDATA 0x22 122130561Sobrien#define CMPCI_REG_SBADDR 0x23 12377298Sobrien# define CMPCI_SB16_MIXER_RESET 0x00 12433965Sjdp# define CMPCI_SB16_MIXER_MASTER_L 0x30 12577298Sobrien# define CMPCI_SB16_MIXER_MASTER_R 0x31 126130561Sobrien# define CMPCI_SB16_MIXER_VOICE_L 0x32 12733965Sjdp# define CMPCI_SB16_MIXER_VOICE_R 0x33 12833965Sjdp# define CMPCI_SB16_MIXER_FM_L 0x34 12933965Sjdp# define CMPCI_SB16_MIXER_FM_R 0x35 13033965Sjdp# define CMPCI_SB16_MIXER_CDDA_L 0x36 13133965Sjdp# define CMPCI_SB16_MIXER_CDDA_R 0x37 13233965Sjdp# define CMPCI_SB16_MIXER_LINE_L 0x38 13333965Sjdp# define CMPCI_SB16_MIXER_LINE_R 0x39 13433965Sjdp# define CMPCI_SB16_MIXER_MIC 0x3A 13533965Sjdp# define CMPCI_SB16_MIXER_SPEAKER 0x3B 13633965Sjdp# define CMPCI_SB16_MIXER_OUTMIX 0x3C 13777298Sobrien# define CMPCI_SB16_SW_MIC 0x01 13877298Sobrien# define CMPCI_SB16_SW_CD_R 0x02 13933965Sjdp# define CMPCI_SB16_SW_CD_L 0x04 14033965Sjdp# define CMPCI_SB16_SW_CD (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R) 14133965Sjdp# define CMPCI_SB16_SW_LINE_R 0x08 14233965Sjdp# define CMPCI_SB16_SW_LINE_L 0x10 14333965Sjdp# define CMPCI_SB16_SW_LINE (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R) 14433965Sjdp# define CMPCI_SB16_SW_FM_R 0x20 14533965Sjdp# define CMPCI_SB16_SW_FM_L 0x40 14633965Sjdp# define CMPCI_SB16_SW_FM (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R) 14733965Sjdp# define CMPCI_SB16_MIXER_ADCMIX_L 0x3D 148218822Sdim# define CMPCI_SB16_MIXER_ADCMIX_R 0x3E 14933965Sjdp# define CMPCI_SB16_MIXER_FM_SRC_R 0x20 15060484Sobrien# define CMPCI_SB16_MIXER_LINE_SRC_R 0x08 15133965Sjdp# define CMPCI_SB16_MIXER_CD_SRC_R 0x02 15233965Sjdp# define CMPCI_SB16_MIXER_MIC_SRC 0x01 15333965Sjdp# define CMPCI_SB16_MIXER_SRC_R_TO_L(v) ((v) << 1) 15433965Sjdp 15533965Sjdp# define CMPCI_SB16_MIXER_INGAIN_L 0x3F 15633965Sjdp# define CMPCI_SB16_MIXER_INGAIN_R 0x40 15733965Sjdp# define CMPCI_SB16_MIXER_OUTGAIN_L 0x41 15833965Sjdp# define CMPCI_SB16_MIXER_OUTGAIN_R 0x42 15933965Sjdp# define CMPCI_SB16_MIXER_AGC 0x43 16033965Sjdp# define CMPCI_SB16_MIXER_TREBLE_L 0x44 16133965Sjdp# define CMPCI_SB16_MIXER_TREBLE_R 0x45 16233965Sjdp# define CMPCI_SB16_MIXER_BASS_L 0x46 16338889Sjdp# define CMPCI_SB16_MIXER_BASS_R 0x47 16433965Sjdp# define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1) 16533965Sjdp 16633965Sjdp# define CMPCI_ADJUST_MIC_GAIN(sc, x) cmpci_adjust((x), 0xf8) 16733965Sjdp# define CMPCI_ADJUST_GAIN(sc, x) cmpci_adjust((x), 0xf8) 16833965Sjdp# define CMPCI_ADJUST_2_GAIN(sc, x) cmpci_adjust((x), 0xc0) 16933965Sjdp 17033965Sjdp#define CMPCI_REG_MPU_BASE 0x40 17133965Sjdp#define CMPCI_REG_MPU_SIZE 0x10 17233965Sjdp#define CMPCI_REG_FM_BASE 0x50 17333965Sjdp#define CMPCI_REG_FM_SIZE 0x10 17433965Sjdp 17533965Sjdp#define CMPCI_REG_AUX_MIC 0x25 17633965Sjdp# define CMPCI_AUX_SELECT_R 0x80 17733965Sjdp# define CMPCI_AUX_SELECT_L 0x40 17833965Sjdp# define CMPCI_AUX_MUTE_R 0x20 17933965Sjdp# define CMPCI_AUX_MUTE_L 0x10 18033965Sjdp# define CMPCI_VAD_MIC 0x0e 18133965Sjdp# define CMPCI_MIC_QUIET 0x01 18233965Sjdp 18377298Sobrien#define CMPCI_REG_DMA0_BASE 0x80 18433965Sjdp#define CMPCI_REG_DMA0_BYTES 0x84 185218822Sdim#define CMPCI_REG_DMA0_SAMPLES 0x86 186218822Sdim#define CMPCI_REG_DMA1_BASE 0x88 187218822Sdim#define CMPCI_REG_DMA1_BYTES 0x8C 188218822Sdim#define CMPCI_REG_DMA1_SAMPLES 0x8E 189218822Sdim 190218822Sdim/* sample rate */ 191218822Sdim#define CMPCI_REG_RATE_5512 0 192218822Sdim#define CMPCI_REG_RATE_11025 1 193218822Sdim#define CMPCI_REG_RATE_22050 2 194218822Sdim#define CMPCI_REG_RATE_44100 3 195218822Sdim#define CMPCI_REG_RATE_8000 4 196218822Sdim#define CMPCI_REG_RATE_16000 5 197218822Sdim#define CMPCI_REG_RATE_32000 6 198218822Sdim#define CMPCI_REG_RATE_48000 7 199218822Sdim#define CMPCI_REG_NUMRATE 8 200218822Sdim 201218822Sdim#endif /* _DEV_PCI_CMPCIREG_H_ */ 202218822Sdim 203218822Sdim/* end of file */ 204218822Sdim