mss.c revision 56774
1/* 2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 3 * Copyright Luigi Rizzo, 1997,1998 4 * Copyright by Hannu Savolainen 1994, 1995 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/sound/isa/mss.c 56774 2000-01-29 00:18:29Z cg $ 29 */ 30 31#include <dev/sound/pcm/sound.h> 32 33/* board-specific include files */ 34#include <dev/sound/isa/mss.h> 35#include <dev/sound/chip.h> 36 37#include "gusc.h" 38#if notyet 39#include "midi.h" 40#endif /* notyet */ 41 42#define MSS_BUFFSIZE (65536 - 256) 43#define abs(x) (((x) < 0) ? -(x) : (x)) 44 45struct mss_info; 46 47struct mss_chinfo { 48 struct mss_info *parent; 49 pcm_channel *channel; 50 snd_dbuf *buffer; 51 int dir; 52}; 53 54struct mss_info { 55 struct resource *io_base; /* primary I/O address for the board */ 56 int io_rid; 57 struct resource *conf_base; /* and the opti931 also has a config space */ 58 int conf_rid; 59 struct resource *irq; 60 int irq_rid; 61 struct resource *drq1; /* play */ 62 int drq1_rid; 63 struct resource *drq2; /* rec */ 64 int drq2_rid; 65 bus_dma_tag_t parent_dmat; 66 67 int pdma, rdma; 68 int bd_id; /* used to hold board-id info, eg. sb version, 69 * mss codec type, etc. etc. 70 */ 71 int opti_offset; /* offset from config_base for opti931 */ 72 u_long bd_flags; /* board-specific flags */ 73 struct mss_chinfo pch, rch; 74}; 75 76static int mss_probe(device_t dev); 77static int mss_attach(device_t dev); 78 79static driver_intr_t mss_intr; 80 81/* prototypes for local functions */ 82static int mss_detect(device_t dev, struct mss_info *mss); 83static char *ymf_test(device_t dev, struct mss_info *mss); 84static void ad_unmute(struct mss_info *mss); 85 86/* mixer set funcs */ 87static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right); 88static int mss_set_recsrc(struct mss_info *mss, int mask); 89 90/* io funcs */ 91static int ad_wait_init(struct mss_info *mss, int x); 92static int ad_read(struct mss_info *mss, int reg); 93static void ad_write(struct mss_info *mss, int reg, u_char data); 94static void ad_write_cnt(struct mss_info *mss, int reg, u_short data); 95 96/* io primitives */ 97static void conf_wr(struct mss_info *mss, u_char reg, u_char data); 98static u_char conf_rd(struct mss_info *mss, u_char reg); 99 100static int pnpmss_probe(device_t dev); 101static int pnpmss_attach(device_t dev); 102 103static driver_intr_t opti931_intr; 104 105static int mssmix_init(snd_mixer *m); 106static int mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right); 107static int mssmix_setrecsrc(snd_mixer *m, u_int32_t src); 108static snd_mixer mss_mixer = { 109 "MSS mixer", 110 mssmix_init, 111 mssmix_set, 112 mssmix_setrecsrc, 113}; 114 115static int ymmix_init(snd_mixer *m); 116static int ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right); 117static int ymmix_setrecsrc(snd_mixer *m, u_int32_t src); 118static snd_mixer yamaha_mixer = { 119 "OPL3-SAx mixer", 120 ymmix_init, 121 ymmix_set, 122 ymmix_setrecsrc, 123}; 124 125static devclass_t pcm_devclass; 126 127/* channel interface */ 128static void *msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir); 129static int msschan_setdir(void *data, int dir); 130static int msschan_setformat(void *data, u_int32_t format); 131static int msschan_setspeed(void *data, u_int32_t speed); 132static int msschan_setblocksize(void *data, u_int32_t blocksize); 133static int msschan_trigger(void *data, int go); 134static int msschan_getptr(void *data); 135static pcmchan_caps *msschan_getcaps(void *data); 136 137static pcmchan_caps mss_caps = { 138 4000, 48000, 139 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, 140 AFMT_STEREO | AFMT_S16_LE 141}; 142 143static pcmchan_caps guspnp_caps = { 144 4000, 48000, 145 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_A_LAW, 146 AFMT_STEREO | AFMT_S16_LE 147}; 148 149static pcmchan_caps opti931_caps = { 150 4000, 48000, 151 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE, 152 AFMT_STEREO | AFMT_S16_LE 153}; 154 155static pcm_channel mss_chantemplate = { 156 msschan_init, 157 msschan_setdir, 158 msschan_setformat, 159 msschan_setspeed, 160 msschan_setblocksize, 161 msschan_trigger, 162 msschan_getptr, 163 msschan_getcaps, 164}; 165 166#define MD_AD1848 0x91 167#define MD_AD1845 0x92 168#define MD_CS42XX 0xA1 169#define MD_OPTI931 0xB1 170#define MD_OPTI925 0xB2 171#define MD_GUSPNP 0xB8 172#define MD_GUSMAX 0xB9 173#define MD_YM0020 0xC1 174#define MD_VIVO 0xD1 175 176#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */ 177 178#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX) 179 180static int 181port_rd(struct resource *port, int off) 182{ 183 if (port) 184 return bus_space_read_1(rman_get_bustag(port), 185 rman_get_bushandle(port), 186 off); 187 else 188 return -1; 189} 190 191static void 192port_wr(struct resource *port, int off, u_int8_t data) 193{ 194 if (port) 195 return bus_space_write_1(rman_get_bustag(port), 196 rman_get_bushandle(port), 197 off, data); 198} 199 200static int 201io_rd(struct mss_info *mss, int reg) 202{ 203 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 204 return port_rd(mss->io_base, reg); 205} 206 207static void 208io_wr(struct mss_info *mss, int reg, u_int8_t data) 209{ 210 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 211 return port_wr(mss->io_base, reg, data); 212} 213 214static void 215conf_wr(struct mss_info *mss, u_char reg, u_char value) 216{ 217 port_wr(mss->conf_base, 0, reg); 218 port_wr(mss->conf_base, 1, value); 219} 220 221static u_char 222conf_rd(struct mss_info *mss, u_char reg) 223{ 224 port_wr(mss->conf_base, 0, reg); 225 return port_rd(mss->conf_base, 1); 226} 227 228static void 229opti_wr(struct mss_info *mss, u_char reg, u_char value) 230{ 231 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 232 port_wr(mss->conf_base, mss->opti_offset + 1, value); 233} 234 235static u_char 236opti_rd(struct mss_info *mss, u_char reg) 237{ 238 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 239 return port_rd(mss->conf_base, mss->opti_offset + 1); 240} 241 242static void 243gus_wr(struct mss_info *mss, u_char reg, u_char value) 244{ 245 port_wr(mss->conf_base, 3, reg); 246 port_wr(mss->conf_base, 5, value); 247} 248 249static u_char 250gus_rd(struct mss_info *mss, u_char reg) 251{ 252 port_wr(mss->conf_base, 3, reg); 253 return port_rd(mss->conf_base, 5); 254} 255 256static void 257mss_release_resources(struct mss_info *mss, device_t dev) 258{ 259 if (mss->irq) { 260 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid, 261 mss->irq); 262 mss->irq = 0; 263 } 264 if (mss->drq1) { 265 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid, 266 mss->drq1); 267 mss->drq1 = 0; 268 mss->pdma = -1; 269 } 270 if (mss->drq2) { 271 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid, 272 mss->drq2); 273 mss->drq2 = 0; 274 mss->rdma = -1; 275 } 276 if (mss->io_base) { 277 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid, 278 mss->io_base); 279 mss->io_base = 0; 280 } 281 if (mss->conf_base) { 282 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 283 mss->conf_base); 284 mss->conf_base = 0; 285 } 286 free(mss, M_DEVBUF); 287} 288 289static int 290mss_alloc_resources(struct mss_info *mss, device_t dev) 291{ 292 int ok = 1; 293 if (!mss->io_base) 294 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 295 0, ~0, 1, RF_ACTIVE); 296 if (!mss->irq) 297 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid, 298 0, ~0, 1, RF_ACTIVE); 299 if (!mss->drq1) 300 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid, 301 0, ~0, 1, RF_ACTIVE); 302 if (mss->conf_rid >= 0 && !mss->conf_base) 303 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 304 0, ~0, 1, RF_ACTIVE); 305 if (mss->drq2_rid >= 0 && !mss->drq2) 306 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid, 307 0, ~0, 1, RF_ACTIVE); 308 309 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0; 310 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0; 311 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0; 312 313 if (ok) { 314 mss->pdma = rman_get_start(mss->drq1); 315 isa_dma_acquire(mss->pdma); 316 isa_dmainit(mss->pdma, MSS_BUFFSIZE); 317 mss->bd_flags &= ~BD_F_DUPLEX; 318 if (mss->drq2) { 319 mss->rdma = rman_get_start(mss->drq2); 320 isa_dma_acquire(mss->rdma); 321 isa_dmainit(mss->rdma, MSS_BUFFSIZE); 322 mss->bd_flags |= BD_F_DUPLEX; 323 } else mss->rdma = mss->pdma; 324 } 325 return ok; 326} 327 328#if NGUSC > 0 329/* 330 * XXX This might be better off in the gusc driver. 331 */ 332static void 333gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt) 334{ 335 static const unsigned char irq_bits[16] = { 336 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7 337 }; 338 static const unsigned char dma_bits[8] = { 339 0, 1, 0, 2, 0, 3, 4, 5 340 }; 341 device_t parent = device_get_parent(dev); 342 unsigned char irqctl, dmactl; 343 int s; 344 345 s = splhigh(); 346 347 port_wr(alt, 0x0f, 0x05); 348 port_wr(alt, 0x00, 0x0c); 349 port_wr(alt, 0x0b, 0x00); 350 351 port_wr(alt, 0x0f, 0x00); 352 353 irqctl = irq_bits[isa_get_irq(parent)]; 354#if notyet 355#if NMIDI > 0 356 /* Share the IRQ with the MIDI driver. */ 357 irqctl |= 0x40; 358#endif /* NMIDI > 0 */ 359#endif /* notyet */ 360 dmactl = dma_bits[isa_get_drq(parent)]; 361 if (device_get_flags(parent) & DV_F_DUAL_DMA) 362 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK] 363 << 3; 364 365 /* 366 * Set the DMA and IRQ control latches. 367 */ 368 port_wr(alt, 0x00, 0x0c); 369 port_wr(alt, 0x0b, dmactl | 0x80); 370 port_wr(alt, 0x00, 0x4c); 371 port_wr(alt, 0x0b, irqctl); 372 373 port_wr(alt, 0x00, 0x0c); 374 port_wr(alt, 0x0b, dmactl); 375 port_wr(alt, 0x00, 0x4c); 376 port_wr(alt, 0x0b, irqctl); 377 378 port_wr(mss->conf_base, 2, 0); 379 port_wr(alt, 0x00, 0x0c); 380 port_wr(mss->conf_base, 2, 0); 381 382 splx(s); 383} 384#endif /* NGUSC > 0 */ 385 386static int 387mss_init(struct mss_info *mss, device_t dev) 388{ 389 u_char r6, r9; 390 struct resource *alt; 391 int rid, tmp; 392 393 mss->bd_flags |= BD_F_MCE_BIT; 394 switch(mss->bd_id) { 395 case MD_OPTI931: 396 /* 397 * The MED3931 v.1.0 allocates 3 bytes for the config 398 * space, whereas v.2.0 allocates 4 bytes. What I know 399 * for sure is that the upper two ports must be used, 400 * and they should end on a boundary of 4 bytes. So I 401 * need the following trick. 402 */ 403 mss->opti_offset = 404 (rman_get_start(mss->conf_base) & ~3) + 2 405 - rman_get_start(mss->conf_base); 406 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset)); 407 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */ 408 ad_write(mss, 10, 2); /* enable interrupts */ 409 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */ 410 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */ 411 break; 412 413 case MD_GUSPNP: 414 case MD_GUSMAX: 415 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */ 416 DELAY(1000 * 30); 417 /* release reset and enable DAC */ 418 gus_wr(mss, 0x4c /* _URSTI */, 3); 419 DELAY(1000 * 30); 420 /* end of reset */ 421 422 rid = 0; 423 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 424 0, ~0, 1, RF_ACTIVE); 425 if (alt == NULL) { 426 printf("XXX couldn't init GUS PnP/MAX\n"); 427 break; 428 } 429 port_wr(alt, 0, 0xC); /* enable int and dma */ 430#if NGUSC > 0 431 if (mss->bd_id == MD_GUSMAX) 432 gusmax_setup(mss, dev, alt); 433#endif 434 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt); 435 436 /* 437 * unmute left & right line. Need to go in mode3, unmute, 438 * and back to mode 2 439 */ 440 tmp = ad_read(mss, 0x0c); 441 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */ 442 ad_write(mss, 0x19, 0); /* unmute left */ 443 ad_write(mss, 0x1b, 0); /* unmute right */ 444 ad_write(mss, 0x0c, tmp); /* restore old mode */ 445 446 /* send codec interrupts on irq1 and only use that one */ 447 gus_wr(mss, 0x5a, 0x4f); 448 449 /* enable access to hidden regs */ 450 tmp = gus_rd(mss, 0x5b /* IVERI */); 451 gus_wr(mss, 0x5b, tmp | 1); 452 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4))); 453 break; 454 455 case MD_YM0020: 456 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */ 457 r6 = conf_rd(mss, OPL3SAx_DMACONF); 458 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */ 459 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);) 460 /* yamaha - set volume to max */ 461 conf_wr(mss, OPL3SAx_VOLUMEL, 0); 462 conf_wr(mss, OPL3SAx_VOLUMER, 0); 463 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b); 464 break; 465 } 466 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931) 467 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */ 468 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4); 469 ad_write(mss, 10, 2); /* int enable */ 470 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 471 /* the following seem required on the CS4232 */ 472 ad_unmute(mss); 473 return 0; 474} 475 476/* 477 * mss_probe() is the probe routine. Note, it is not necessary to 478 * go through this for PnP devices, since they are already 479 * indentified precisely using their PnP id. 480 * 481 * The base address supplied in the device refers to the old MSS 482 * specs where the four 4 registers in io space contain configuration 483 * information. Some boards (as an example, early MSS boards) 484 * has such a block of registers, whereas others (generally CS42xx) 485 * do not. In order to distinguish between the two and do not have 486 * to supply two separate probe routines, the flags entry in isa_device 487 * has a bit to mark this. 488 * 489 */ 490 491static int 492mss_probe(device_t dev) 493{ 494 u_char tmp, tmpx; 495 int flags, irq, drq, result = ENXIO, setres = 0; 496 struct mss_info *mss; 497 498 if (isa_get_vendorid(dev)) return ENXIO; /* not yet */ 499 500 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 501 if (!mss) return ENXIO; 502 bzero(mss, sizeof *mss); 503 504 mss->io_rid = 0; 505 mss->conf_rid = -1; 506 mss->irq_rid = 0; 507 mss->drq1_rid = 0; 508 mss->drq2_rid = -1; 509 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 510 0, ~0, 8, RF_ACTIVE); 511 if (!mss->io_base) { 512 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530)); 513 mss->io_rid = 0; 514 /* XXX verify this */ 515 setres = 1; 516 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid, 517 0x530, 8); 518 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 519 0, ~0, 8, RF_ACTIVE); 520 } 521 if (!mss->io_base) goto no; 522 523 /* got irq/dma regs? */ 524 flags = device_get_flags(dev); 525 irq = isa_get_irq(dev); 526 drq = isa_get_drq(dev); 527 528 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end; 529 530 /* 531 * Check if the IO port returns valid signature. The original MS 532 * Sound system returns 0x04 while some cards 533 * (AudioTriX Pro for example) return 0x00 or 0x0f. 534 */ 535 536 device_set_desc(dev, "MSS"); 537 tmpx = tmp = io_rd(mss, 3); 538 if (tmp == 0xff) { /* Bus float */ 539 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp)); 540 device_set_flags(dev, flags & ~DV_F_TRUE_MSS); 541 goto mss_probe_end; 542 } 543 tmp &= 0x3f; 544 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) { 545 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n", 546 rman_get_start(mss->io_base), tmpx)); 547 goto no; 548 } 549 if (irq > 11) { 550 printf("MSS: Bad IRQ %d\n", irq); 551 goto no; 552 } 553 if (!(drq == 0 || drq == 1 || drq == 3)) { 554 printf("MSS: Bad DMA %d\n", drq); 555 goto no; 556 } 557 if (tmpx & 0x80) { 558 /* 8-bit board: only drq1/3 and irq7/9 */ 559 if (drq == 0) { 560 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n"); 561 goto no; 562 } 563 if (!(irq == 7 || irq == 9)) { 564 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", 565 irq); 566 goto no; 567 } 568 } 569 mss_probe_end: 570 result = mss_detect(dev, mss); 571 no: 572 mss_release_resources(mss, dev); 573#if 0 574 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev, 575 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */ 576#endif 577 return result; 578} 579 580static int 581mss_detect(device_t dev, struct mss_info *mss) 582{ 583 int i; 584 u_char tmp = 0, tmp1, tmp2; 585 char *name, *yamaha; 586 587 if (mss->bd_id != 0) { 588 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id, 589 device_get_desc(dev)); 590 return 0; 591 } 592 593 name = "AD1848"; 594 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */ 595 596 /* 597 * Check that the I/O address is in use. 598 * 599 * bit 7 of the base I/O port is known to be 0 after the chip has 600 * performed its power on initialization. Just assume this has 601 * happened before the OS is starting. 602 * 603 * If the I/O address is unused, it typically returns 0xff. 604 */ 605 606 for (i = 0; i < 10; i++) 607 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000); 608 else break; 609 610 if (i >= 10) { /* Not a AD1848 */ 611 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp)); 612 goto no; 613 } 614 /* 615 * Test if it's possible to change contents of the indirect 616 * registers. Registers 0 and 1 are ADC volume registers. The bit 617 * 0x10 is read only so try to avoid using it. 618 */ 619 620 ad_write(mss, 0, 0xaa); 621 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */ 622 tmp1 = ad_read(mss, 0); 623 tmp2 = ad_read(mss, 1); 624 if (tmp1 != 0xaa || tmp2 != 0x45) { 625 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2)); 626 goto no; 627 } 628 629 ad_write(mss, 0, 0x45); 630 ad_write(mss, 1, 0xaa); 631 tmp1 = ad_read(mss, 0); 632 tmp2 = ad_read(mss, 1); 633 if (tmp1 != 0x45 || tmp2 != 0xaa) { 634 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2)); 635 goto no; 636 } 637 638 /* 639 * The indirect register I12 has some read only bits. Lets try to 640 * change them. 641 */ 642 643 tmp = ad_read(mss, 12); 644 ad_write(mss, 12, (~tmp) & 0x0f); 645 tmp1 = ad_read(mss, 12); 646 647 if ((tmp & 0x0f) != (tmp1 & 0x0f)) { 648 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp)); 649 goto no; 650 } 651 652 /* 653 * NOTE! Last 4 bits of the reg I12 tell the chip revision. 654 * 0x01=RevB 655 * 0x0A=RevC. also CS4231/CS4231A and OPTi931 656 */ 657 658 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);) 659 660 /* 661 * The original AD1848/CS4248 has just 16 indirect registers. This 662 * means that I0 and I16 should return the same value (etc.). Ensure 663 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails 664 * with new parts. 665 */ 666 667 ad_write(mss, 12, 0); /* Mode2=disabled */ 668#if 0 669 for (i = 0; i < 16; i++) { 670 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) { 671 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n", 672 i, tmp1, tmp2)); 673 /* 674 * note - this seems to fail on the 4232 on I11. So we just break 675 * rather than fail. (which makes this test pointless - cg) 676 */ 677 break; /* return 0; */ 678 } 679 } 680#endif 681 /* 682 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 683 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231. 684 * 685 * On the OPTi931, however, I12 is readonly and only contains the 686 * chip revision ID (as in the CS4231A). The upper bits return 0. 687 */ 688 689 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */ 690 691 tmp1 = ad_read(mss, 12); 692 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */ 693 if ((tmp1 & 0xf0) == 0x00) { 694 BVDDB(printf("this should be an OPTi931\n");) 695 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit; 696 /* 697 * The 4231 has bit7=1 always, and bit6 we just set to 1. 698 * We want to check that this is really a CS4231 699 * Verify that setting I0 doesn't change I16. 700 */ 701 ad_write(mss, 16, 0); /* Set I16 to known value */ 702 ad_write(mss, 0, 0x45); 703 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit; 704 705 ad_write(mss, 0, 0xaa); 706 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */ 707 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1)); 708 goto no; 709 } 710 /* Verify that some bits of I25 are read only. */ 711 tmp1 = ad_read(mss, 25); /* Original bits */ 712 ad_write(mss, 25, ~tmp1); /* Invert all bits */ 713 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) { 714 int id; 715 716 /* It's at least CS4231 */ 717 name = "CS4231"; 718 mss->bd_id = MD_CS42XX; 719 720 /* 721 * It could be an AD1845 or CS4231A as well. 722 * CS4231 and AD1845 report the same revision info in I25 723 * while the CS4231A reports different. 724 */ 725 726 id = ad_read(mss, 25) & 0xe7; 727 /* 728 * b7-b5 = version number; 729 * 100 : all CS4231 730 * 101 : CS4231A 731 * 732 * b2-b0 = chip id; 733 */ 734 switch (id) { 735 736 case 0xa0: 737 name = "CS4231A"; 738 mss->bd_id = MD_CS42XX; 739 break; 740 741 case 0xa2: 742 name = "CS4232"; 743 mss->bd_id = MD_CS42XX; 744 break; 745 746 case 0xb2: 747 /* strange: the 4231 data sheet says b4-b3 are XX 748 * so this should be the same as 0xa2 749 */ 750 name = "CS4232A"; 751 mss->bd_id = MD_CS42XX; 752 break; 753 754 case 0x80: 755 /* 756 * It must be a CS4231 or AD1845. The register I23 757 * of CS4231 is undefined and it appears to be read 758 * only. AD1845 uses I23 for setting sample rate. 759 * Assume the chip is AD1845 if I23 is changeable. 760 */ 761 762 tmp = ad_read(mss, 23); 763 764 ad_write(mss, 23, ~tmp); 765 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */ 766 name = "AD1845"; 767 mss->bd_id = MD_AD1845; 768 } 769 ad_write(mss, 23, tmp); /* Restore */ 770 771 yamaha = ymf_test(dev, mss); 772 if (yamaha) { 773 mss->bd_id = MD_YM0020; 774 name = yamaha; 775 } 776 break; 777 778 case 0x83: /* CS4236 */ 779 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */ 780 name = "CS4236"; 781 mss->bd_id = MD_CS42XX; 782 break; 783 784 default: /* Assume CS4231 */ 785 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);) 786 mss->bd_id = MD_CS42XX; 787 } 788 } 789 ad_write(mss, 25, tmp1); /* Restore bits */ 790gotit: 791 BVDDB(printf("mss_detect() - Detected %s\n", name)); 792 device_set_desc(dev, name); 793 device_set_flags(dev, 794 ((device_get_flags(dev) & ~DV_F_DEV_MASK) | 795 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK))); 796 return 0; 797no: 798 return ENXIO; 799} 800 801static char * 802ymf_test(device_t dev, struct mss_info *mss) 803{ 804 static int ports[] = {0x370, 0x310, 0x538}; 805 int p, i, j, version; 806 static char *chipset[] = { 807 NULL, /* 0 */ 808 "OPL3-SA2 (YMF711)", /* 1 */ 809 "OPL3-SA3 (YMF715)", /* 2 */ 810 "OPL3-SA3 (YMF715)", /* 3 */ 811 "OPL3-SAx (YMF719)", /* 4 */ 812 "OPL3-SAx (YMF719)", /* 5 */ 813 "OPL3-SAx (YMF719)", /* 6 */ 814 "OPL3-SAx (YMF719)", /* 7 */ 815 }; 816 817 for (p = 0; p < 3; p++) { 818 mss->conf_rid = 1; 819 mss->conf_base = bus_alloc_resource(dev, 820 SYS_RES_IOPORT, 821 &mss->conf_rid, 822 ports[p], ports[p] + 1, 2, 823 RF_ACTIVE); 824 if (!mss->conf_base) return 0; 825 826 /* Test the index port of the config registers */ 827 i = port_rd(mss->conf_base, 0); 828 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF); 829 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0; 830 port_wr(mss->conf_base, 0, i); 831 if (!j) { 832 bus_release_resource(dev, SYS_RES_IOPORT, 833 mss->conf_rid, mss->conf_base); 834 mss->conf_base = 0; 835 continue; 836 } 837 version = conf_rd(mss, OPL3SAx_MISC) & 0x07; 838 return chipset[version]; 839 } 840 return NULL; 841} 842 843static int 844mss_doattach(device_t dev, struct mss_info *mss) 845{ 846 snddev_info *d = device_get_softc(dev); 847 void *ih; 848 int flags = device_get_flags(dev); 849 char status[SND_STATUSLEN]; 850 851 if (!mss_alloc_resources(mss, dev)) goto no; 852 mss_init(mss, dev); 853 if (flags & DV_F_TRUE_MSS) { 854 /* has IRQ/DMA registers, set IRQ and DMA addr */ 855 static char interrupt_bits[12] = 856 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20}; 857 static char pdma_bits[4] = {1, 2, -1, 3}; 858 static char valid_rdma[4] = {1, 0, -1, 0}; 859 char bits; 860 861 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1) 862 goto no; 863 io_wr(mss, 0, bits | 0x40); /* config port */ 864 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n"); 865 /* Write IRQ+DMA setup */ 866 if (pdma_bits[mss->pdma] == -1) goto no; 867 bits |= pdma_bits[mss->pdma]; 868 if (mss->pdma != mss->rdma) { 869 if (mss->rdma == valid_rdma[mss->pdma]) bits |= 4; 870 else { 871 printf("invalid dual dma config %d:%d\n", 872 mss->pdma, mss->rdma); 873 goto no; 874 } 875 } 876 io_wr(mss, 0, bits); 877 printf("drq/irq conf %x\n", io_rd(mss, 0)); 878 } 879 mixer_init(d, (mss->bd_id == MD_YM0020)? &yamaha_mixer : &mss_mixer, mss); 880 switch (mss->bd_id) { 881 case MD_OPTI931: 882 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, opti931_intr, mss, &ih); 883 break; 884 default: 885 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, mss_intr, mss, &ih); 886 } 887 if (mss->pdma == mss->rdma) 888 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX); 889 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 890 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT, 891 /*highaddr*/BUS_SPACE_MAXADDR, 892 /*filter*/NULL, /*filterarg*/NULL, 893 /*maxsize*/MSS_BUFFSIZE, /*nsegments*/1, 894 /*maxsegz*/0x3ffff, 895 /*flags*/0, &mss->parent_dmat) != 0) { 896 device_printf(dev, "unable to create dma tag\n"); 897 goto no; 898 } 899 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d", 900 rman_get_start(mss->io_base), rman_get_start(mss->irq), mss->pdma); 901 if (mss->pdma != mss->rdma) snprintf(status + strlen(status), 902 SND_STATUSLEN - strlen(status), ":%d", mss->rdma); 903 904 if (pcm_register(dev, mss, 1, 1)) goto no; 905 pcm_addchan(dev, PCMDIR_REC, &mss_chantemplate, mss); 906 pcm_addchan(dev, PCMDIR_PLAY, &mss_chantemplate, mss); 907 pcm_setstatus(dev, status); 908 909 return 0; 910no: 911 mss_release_resources(mss, dev); 912 return ENXIO; 913} 914 915static int 916mss_attach(device_t dev) 917{ 918 struct mss_info *mss; 919 int flags = device_get_flags(dev); 920 921 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 922 if (!mss) return ENXIO; 923 bzero(mss, sizeof *mss); 924 925 mss->io_rid = 0; 926 mss->conf_rid = -1; 927 mss->irq_rid = 0; 928 mss->drq1_rid = 0; 929 mss->drq2_rid = -1; 930 if (flags & DV_F_DUAL_DMA) { 931 bus_set_resource(dev, SYS_RES_DRQ, 1, 932 flags & DV_F_DRQ_MASK, 1); 933 mss->drq2_rid = 1; 934 } 935 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT; 936 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss); 937 return mss_doattach(dev, mss); 938} 939 940static device_method_t mss_methods[] = { 941 /* Device interface */ 942 DEVMETHOD(device_probe, mss_probe), 943 DEVMETHOD(device_attach, mss_attach), 944 945 { 0, 0 } 946}; 947 948static driver_t mss_driver = { 949 "pcm", 950 mss_methods, 951 sizeof(snddev_info), 952}; 953 954DRIVER_MODULE(mss, isa, mss_driver, pcm_devclass, 0, 0); 955 956/* 957 * main irq handler for the CS423x. The OPTi931 code is 958 * a separate one. 959 * The correct way to operate for a device with multiple internal 960 * interrupt sources is to loop on the status register and ack 961 * interrupts until all interrupts are served and none are reported. At 962 * this point the IRQ line to the ISA IRQ controller should go low 963 * and be raised at the next interrupt. 964 * 965 * Since the ISA IRQ controller is sent EOI _before_ passing control 966 * to the isr, it might happen that we serve an interrupt early, in 967 * which case the status register at the next interrupt should just 968 * say that there are no more interrupts... 969 */ 970 971static void 972mss_intr(void *arg) 973{ 974 struct mss_info *mss = arg; 975 u_char c = 0, served = 0; 976 int i; 977 978 DEB(printf("mss_intr\n")); 979 ad_read(mss, 11); /* fake read of status bits */ 980 981 /* loop until there are interrupts, but no more than 10 times. */ 982 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) { 983 /* get exact reason for full-duplex boards */ 984 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30; 985 c &= ~served; 986 if (mss->pch.buffer->dl && (c & 0x10)) { 987 served |= 0x10; 988 chn_intr(mss->pch.channel); 989 } 990 if (mss->rch.buffer->dl && (c & 0x20)) { 991 served |= 0x20; 992 chn_intr(mss->rch.channel); 993 } 994 /* now ack the interrupt */ 995 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */ 996 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 997 } 998 if (i == 10) { 999 BVDDB(printf("mss_intr: irq, but not from mss\n")); 1000 } else if (served == 0) { 1001 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c)); 1002 /* 1003 * this should not happen... I have no idea what to do now. 1004 * maybe should do a sanity check and restart dmas ? 1005 */ 1006 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 1007 } 1008} 1009 1010/* 1011 * AD_WAIT_INIT waits if we are initializing the board and 1012 * we cannot modify its settings 1013 */ 1014static int 1015ad_wait_init(struct mss_info *mss, int x) 1016{ 1017 int arg = x, n = 0; /* to shut up the compiler... */ 1018 for (; x > 0; x--) 1019 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10); 1020 else return n; 1021 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n); 1022 return n; 1023} 1024 1025static int 1026ad_read(struct mss_info *mss, int reg) 1027{ 1028 u_long flags; 1029 int x; 1030 1031 flags = spltty(); 1032 ad_wait_init(mss, 201); 1033 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 1034 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 1035 x = io_rd(mss, MSS_IDATA); 1036 splx(flags); 1037 /* printf("ad_read %d, %x\n", reg, x); */ 1038 return x; 1039} 1040 1041static void 1042ad_write(struct mss_info *mss, int reg, u_char data) 1043{ 1044 u_long flags; 1045 1046 int x; 1047 /* printf("ad_write %d, %x\n", reg, data); */ 1048 flags = spltty(); 1049 ad_wait_init(mss, 1002); 1050 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 1051 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 1052 io_wr(mss, MSS_IDATA, data); 1053 splx(flags); 1054} 1055 1056static void 1057ad_write_cnt(struct mss_info *mss, int reg, u_short cnt) 1058{ 1059 ad_write(mss, reg+1, cnt & 0xff); 1060 ad_write(mss, reg, cnt >> 8); /* upper base must be last */ 1061} 1062 1063static void 1064wait_for_calibration(struct mss_info *mss) 1065{ 1066 int t; 1067 1068 /* 1069 * Wait until the auto calibration process has finished. 1070 * 1071 * 1) Wait until the chip becomes ready (reads don't return 0x80). 1072 * 2) Wait until the ACI bit of I11 gets on 1073 * 3) Wait until the ACI bit of I11 gets off 1074 */ 1075 1076 t = ad_wait_init(mss, 1000); 1077 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n"); 1078 1079 /* 1080 * The calibration mode for chips that support it is set so that 1081 * we never see ACI go on. 1082 */ 1083 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) { 1084 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--); 1085 } else { 1086 /* 1087 * XXX This should only be enabled for cards that *really* 1088 * need it. Are there any? 1089 */ 1090 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100); 1091 } 1092 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100); 1093} 1094 1095static void 1096ad_unmute(struct mss_info *mss) 1097{ 1098 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE); 1099 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE); 1100} 1101 1102static void 1103ad_enter_MCE(struct mss_info *mss) 1104{ 1105 int prev; 1106 1107 mss->bd_flags |= BD_F_MCE_BIT; 1108 ad_wait_init(mss, 203); 1109 prev = io_rd(mss, MSS_INDEX); 1110 prev &= ~MSS_TRD; 1111 io_wr(mss, MSS_INDEX, prev | MSS_MCE); 1112} 1113 1114static void 1115ad_leave_MCE(struct mss_info *mss) 1116{ 1117 u_long flags; 1118 u_char prev; 1119 1120 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) { 1121 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n")); 1122 return; 1123 } 1124 1125 ad_wait_init(mss, 1000); 1126 1127 flags = spltty(); 1128 mss->bd_flags &= ~BD_F_MCE_BIT; 1129 1130 prev = io_rd(mss, MSS_INDEX); 1131 prev &= ~MSS_TRD; 1132 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */ 1133 wait_for_calibration(mss); 1134 splx(flags); 1135} 1136 1137/* 1138 * only one source can be set... 1139 */ 1140static int 1141mss_set_recsrc(struct mss_info *mss, int mask) 1142{ 1143 u_char recdev; 1144 1145 switch (mask) { 1146 case SOUND_MASK_LINE: 1147 case SOUND_MASK_LINE3: 1148 recdev = 0; 1149 break; 1150 1151 case SOUND_MASK_CD: 1152 case SOUND_MASK_LINE1: 1153 recdev = 0x40; 1154 break; 1155 1156 case SOUND_MASK_IMIX: 1157 recdev = 0xc0; 1158 break; 1159 1160 case SOUND_MASK_MIC: 1161 default: 1162 mask = SOUND_MASK_MIC; 1163 recdev = 0x80; 1164 } 1165 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev); 1166 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev); 1167 return mask; 1168} 1169 1170/* there are differences in the mixer depending on the actual sound card. */ 1171static int 1172mss_mixer_set(struct mss_info *mss, int dev, int left, int right) 1173{ 1174 int regoffs; 1175 mixer_tab *mix_d = (mss->bd_id == MD_OPTI931)? &opti931_devices : &mix_devices; 1176 u_char old, val; 1177 1178 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) { 1179 DEB(printf("nbits = 0 for dev %d\n", dev)); 1180 return -1; 1181 } 1182 1183 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */ 1184 1185 /* Set the left channel */ 1186 1187 regoffs = (*mix_d)[dev][LEFT_CHN].regno; 1188 old = val = ad_read(mss, regoffs); 1189 /* if volume is 0, mute chan. Otherwise, unmute. */ 1190 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f; 1191 change_bits(mix_d, &val, dev, LEFT_CHN, left); 1192 ad_write(mss, regoffs, val); 1193 1194 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n", 1195 dev, regoffs, old, val)); 1196 1197 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */ 1198 /* Set the right channel */ 1199 regoffs = (*mix_d)[dev][RIGHT_CHN].regno; 1200 old = val = ad_read(mss, regoffs); 1201 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f; 1202 change_bits(mix_d, &val, dev, RIGHT_CHN, right); 1203 ad_write(mss, regoffs, val); 1204 1205 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n", 1206 dev, regoffs, old, val)); 1207 } 1208 return 0; /* success */ 1209} 1210 1211static int 1212mss_speed(struct mss_chinfo *ch, int speed) 1213{ 1214 struct mss_info *mss = ch->parent; 1215 /* 1216 * In the CS4231, the low 4 bits of I8 are used to hold the 1217 * sample rate. Only a fixed number of values is allowed. This 1218 * table lists them. The speed-setting routines scans the table 1219 * looking for the closest match. This is the only supported method. 1220 * 1221 * In the CS4236, there is an alternate metod (which we do not 1222 * support yet) which provides almost arbitrary frequency setting. 1223 * In the AD1845, it looks like the sample rate can be 1224 * almost arbitrary, and written directly to a register. 1225 * In the OPTi931, there is a SB command which provides for 1226 * almost arbitrary frequency setting. 1227 * 1228 */ 1229 ad_enter_MCE(mss); 1230 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */ 1231 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */ 1232 ad_write(mss, 23, speed & 0xff); /* Speed LSB */ 1233 /* XXX must also do something in I27 for the ad1845 */ 1234 } else { 1235 int i, sel = 0; /* assume entry 0 does not contain -1 */ 1236 static int speeds[] = 1237 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050, 1238 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615}; 1239 1240 for (i = 1; i < 16; i++) 1241 if (speeds[i] > 0 && 1242 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i; 1243 speed = speeds[sel]; 1244 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel); 1245 } 1246 ad_leave_MCE(mss); 1247 1248 return speed; 1249} 1250 1251/* 1252 * mss_format checks that the format is supported (or defaults to AFMT_U8) 1253 * and returns the bit setting for the 1848 register corresponding to 1254 * the desired format. 1255 * 1256 * fixed lr970724 1257 */ 1258 1259static int 1260mss_format(struct mss_chinfo *ch, u_int32_t format) 1261{ 1262 struct mss_info *mss = ch->parent; 1263 int i, arg = format & ~AFMT_STEREO; 1264 1265 /* 1266 * The data format uses 3 bits (just 2 on the 1848). For each 1267 * bit setting, the following array returns the corresponding format. 1268 * The code scans the array looking for a suitable format. In 1269 * case it is not found, default to AFMT_U8 (not such a good 1270 * choice, but let's do it for compatibility...). 1271 */ 1272 1273 static int fmts[] = 1274 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW, 1275 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1}; 1276 1277 for (i = 0; i < 8; i++) if (arg == fmts[i]) break; 1278 arg = i << 1; 1279 if (format & AFMT_STEREO) arg |= 1; 1280 arg <<= 4; 1281 ad_enter_MCE(mss); 1282 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg); 1283 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */ 1284 ad_leave_MCE(mss); 1285 return format; 1286} 1287 1288static int 1289mss_trigger(struct mss_chinfo *ch, int go) 1290{ 1291 struct mss_info *mss = ch->parent; 1292 u_char m; 1293 int retry, wr, cnt; 1294 1295 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0; 1296 m = ad_read(mss, 9); 1297 switch (go) { 1298 case PCMTRIG_START: 1299 cnt = (ch->buffer->dl / ch->buffer->sample_size) - 1; 1300 1301 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m);); 1302 m |= wr? I9_PEN : I9_CEN; /* enable DMA */ 1303 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt); 1304 break; 1305 1306 case PCMTRIG_STOP: 1307 case PCMTRIG_ABORT: /* XXX check this... */ 1308 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */ 1309#if 0 1310 /* 1311 * try to disable DMA by clearing count registers. Not sure it 1312 * is needed, and it might cause false interrupts when the 1313 * DMA is re-enabled later. 1314 */ 1315 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0); 1316#endif 1317 } 1318 /* on the OPTi931 the enable bit seems hard to set... */ 1319 for (retry = 10; retry > 0; retry--) { 1320 ad_write(mss, 9, m); 1321 if (ad_read(mss, 9) == m) break; 1322 } 1323 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \ 1324 m, ad_read(mss, 9))); 1325 return 0; 1326} 1327 1328static struct isa_pnp_id pnpmss_ids[] = { 1329 {0x0000630e, "CS423x"}, /* CSC0000 */ 1330 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */ 1331 {0x01000000, "CMI8330"}, /* @@@0001 */ 1332 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */ 1333 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */ 1334 {0x1093143e, "OPTi931"}, /* OPT9310 */ 1335 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */ 1336 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */ 1337#if 0 1338 {0x0000561e, "GusPnP"}, /* GRV0000 */ 1339#endif 1340 {0}, 1341}; 1342 1343static int 1344pnpmss_probe(device_t dev) 1345{ 1346 u_int32_t lid, vid; 1347 1348 lid = isa_get_logicalid(dev); 1349 vid = isa_get_vendorid(dev); 1350 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */ 1351 return ENXIO; 1352 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids); 1353} 1354 1355static int 1356pnpmss_attach(device_t dev) 1357{ 1358 struct mss_info *mss; 1359 1360 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 1361 if (!mss) 1362 return ENXIO; 1363 bzero(mss, sizeof *mss); 1364 1365 mss->io_rid = 0; 1366 mss->conf_rid = -1; 1367 mss->irq_rid = 0; 1368 mss->drq1_rid = 0; 1369 mss->drq2_rid = 1; 1370 1371 switch (isa_get_logicalid(dev)) { 1372 case 0x0000630e: /* CSC0000 */ 1373 case 0x0001630e: /* CSC0100 */ 1374 mss->bd_flags |= BD_F_MSS_OFFSET; 1375 mss->bd_id = MD_CS42XX; 1376 break; 1377 1378 case 0x2100a865: /* YHM0021 */ 1379 mss->io_rid = 1; 1380 mss->conf_rid = 4; 1381 mss->bd_id = MD_YM0020; 1382 break; 1383 1384 case 0x1110d315: /* ENS1011 */ 1385 mss->io_rid = 1; 1386 mss->bd_id = MD_VIVO; 1387 break; 1388 1389 case 0x1093143e: /* OPT9310 */ 1390 mss->bd_flags |= BD_F_MSS_OFFSET; 1391 mss->conf_rid = 3; 1392 mss->bd_id = MD_OPTI931; 1393 break; 1394 1395 case 0x5092143e: /* OPT9250 XXX guess */ 1396 mss->io_rid = 1; 1397 mss->conf_rid = 3; 1398 mss->bd_id = MD_OPTI925; 1399 break; 1400 1401 case 0x1022b839: /* NMX2210 */ 1402 mss->io_rid = 1; 1403 mss->bd_id = MD_CS42XX; 1404 break; 1405 1406#if 0 1407 case 0x0000561e: /* GRV0000 */ 1408 mss->bd_flags |= BD_F_MSS_OFFSET; 1409 mss->io_rid = 2; 1410 mss->conf_rid = 1; 1411 mss->drq1_rid = 1; 1412 mss->drq2_rid = 0; 1413 mss->bd_id = MD_GUSPNP; 1414 break; 1415#endif 1416 /* Unknown MSS default. We could let the CSC0000 stuff match too */ 1417 default: 1418 mss->bd_flags |= BD_F_MSS_OFFSET; 1419 mss->bd_id = MD_CS42XX; 1420 break; 1421 } 1422 return mss_doattach(dev, mss); 1423} 1424 1425static device_method_t pnpmss_methods[] = { 1426 /* Device interface */ 1427 DEVMETHOD(device_probe, pnpmss_probe), 1428 DEVMETHOD(device_attach, pnpmss_attach), 1429 1430 { 0, 0 } 1431}; 1432 1433static driver_t pnpmss_driver = { 1434 "pcm", 1435 pnpmss_methods, 1436 sizeof(snddev_info), 1437}; 1438 1439DRIVER_MODULE(pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0); 1440 1441/* 1442 * the opti931 seems to miss interrupts when working in full 1443 * duplex, so we try some heuristics to catch them. 1444 */ 1445static void 1446opti931_intr(void *arg) 1447{ 1448 struct mss_info *mss = (struct mss_info *)arg; 1449 u_char masked = 0, i11, mc11, c = 0; 1450 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */ 1451 int loops = 10; 1452 1453#if 0 1454 reason = io_rd(mss, MSS_STATUS); 1455 if (!(reason & 1)) {/* no int, maybe a shared line ? */ 1456 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11))); 1457 return; 1458 } 1459#endif 1460 i11 = ad_read(mss, 11); /* XXX what's for ? */ 1461 again: 1462 1463 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc; 1464 mc11 &= 0x0c; 1465 if (c & 0x10) { 1466 DEB(printf("Warning: CD interrupt\n");) 1467 mc11 |= 0x10; 1468 } 1469 if (c & 0x20) { 1470 DEB(printf("Warning: MPU interrupt\n");) 1471 mc11 |= 0x20; 1472 } 1473 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\ 1474 mc11, masked)); 1475 masked |= mc11; 1476 /* 1477 * the nice OPTi931 sets the IRQ line before setting the bits in 1478 * mc11. So, on some occasions I have to retry (max 10 times). 1479 */ 1480 if (mc11 == 0) { /* perhaps can return ... */ 1481 reason = io_rd(mss, MSS_STATUS); 1482 if (reason & 1) { 1483 DEB(printf("one more try...\n");) 1484 if (--loops) goto again; 1485 else DDB(printf("intr, but mc11 not set\n");) 1486 } 1487 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11)); 1488 return; 1489 } 1490 1491 if (mss->rch.buffer->dl && (mc11 & 8)) chn_intr(mss->rch.channel); 1492 if (mss->pch.buffer->dl && (mc11 & 4)) chn_intr(mss->pch.channel); 1493 opti_wr(mss, 11, ~mc11); /* ack */ 1494 if (--loops) goto again; 1495 DEB(printf("xxx too many loops\n");) 1496} 1497 1498#if NGUSC > 0 1499 1500static int 1501guspcm_probe(device_t dev) 1502{ 1503 struct sndcard_func *func; 1504 1505 func = device_get_ivars(dev); 1506 if (func == NULL || func->func != SCF_PCM) 1507 return ENXIO; 1508 1509 device_set_desc(dev, "GUS CS4231"); 1510 return 0; 1511} 1512 1513static int 1514guspcm_attach(device_t dev) 1515{ 1516 device_t parent = device_get_parent(dev); 1517 struct mss_info *mss; 1518 int base, flags; 1519 unsigned char ctl; 1520 1521 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 1522 if (mss == NULL) 1523 return ENOMEM; 1524 bzero(mss, sizeof *mss); 1525 1526 mss->bd_flags = BD_F_MSS_OFFSET; 1527 mss->io_rid = 2; 1528 mss->conf_rid = 1; 1529 mss->irq_rid = 0; 1530 mss->drq1_rid = 1; 1531 mss->drq2_rid = -1; 1532 1533 if (isa_get_vendorid(parent) == 0) 1534 mss->bd_id = MD_GUSMAX; 1535 else { 1536 mss->bd_id = MD_GUSPNP; 1537 mss->drq2_rid = 0; 1538 goto skip_setup; 1539 } 1540 1541 flags = device_get_flags(parent); 1542 if (flags & DV_F_DUAL_DMA) 1543 mss->drq2_rid = 0; 1544 1545 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 1546 0, ~0, 8, RF_ACTIVE); 1547 1548 if (mss->conf_base == NULL) { 1549 mss_release_resources(mss, dev); 1550 return ENXIO; 1551 } 1552 1553 base = isa_get_port(parent); 1554 1555 ctl = 0x40; /* CS4231 enable */ 1556 if (isa_get_drq(dev) > 3) 1557 ctl |= 0x10; /* 16-bit dma channel 1 */ 1558 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3) 1559 ctl |= 0x20; /* 16-bit dma channel 2 */ 1560 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */ 1561 port_wr(mss->conf_base, 6, ctl); 1562 1563skip_setup: 1564 return mss_doattach(dev, mss); 1565} 1566 1567static device_method_t guspcm_methods[] = { 1568 DEVMETHOD(device_probe, guspcm_probe), 1569 DEVMETHOD(device_attach, guspcm_attach), 1570 1571 { 0, 0 } 1572}; 1573 1574static driver_t guspcm_driver = { 1575 "pcm", 1576 guspcm_methods, 1577 sizeof(snddev_info), 1578}; 1579 1580DRIVER_MODULE(guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0); 1581#endif /* NGUSC > 0 */ 1582 1583static int 1584mssmix_init(snd_mixer *m) 1585{ 1586 struct mss_info *mss = mix_getdevinfo(m); 1587 1588 mix_setdevs(m, MODE2_MIXER_DEVICES); 1589 mix_setrecdevs(m, MSS_REC_DEVICES); 1590 switch(mss->bd_id) { 1591 case MD_OPTI931: 1592 mix_setdevs(m, OPTI931_MIXER_DEVICES); 1593 ad_write(mss, 20, 0x88); 1594 ad_write(mss, 21, 0x88); 1595 break; 1596 1597 case MD_AD1848: 1598 mix_setdevs(m, MODE1_MIXER_DEVICES); 1599 break; 1600 1601 case MD_GUSPNP: 1602 case MD_GUSMAX: 1603 /* this is only necessary in mode 3 ... */ 1604 ad_write(mss, 22, 0x88); 1605 ad_write(mss, 23, 0x88); 1606 break; 1607 } 1608 return 0; 1609} 1610 1611static int 1612mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 1613{ 1614 struct mss_info *mss = mix_getdevinfo(m); 1615 1616 mss_mixer_set(mss, dev, left, right); 1617 1618 return left | (right << 8); 1619} 1620 1621static int 1622mssmix_setrecsrc(snd_mixer *m, u_int32_t src) 1623{ 1624 struct mss_info *mss = mix_getdevinfo(m); 1625 1626 src = mss_set_recsrc(mss, src); 1627 return src; 1628} 1629 1630static int 1631ymmix_init(snd_mixer *m) 1632{ 1633 struct mss_info *mss = mix_getdevinfo(m); 1634 1635 mssmix_init(m); 1636 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC); 1637 /* Set master volume */ 1638 conf_wr(mss, OPL3SAx_VOLUMEL, 7); 1639 conf_wr(mss, OPL3SAx_VOLUMER, 7); 1640 1641 return 0; 1642} 1643 1644static int 1645ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 1646{ 1647 struct mss_info *mss = mix_getdevinfo(m); 1648 int t; 1649 1650 switch (dev) { 1651 case SOUND_MIXER_VOLUME: 1652 if (left) t = 15 - (left * 15) / 100; 1653 else t = 0x80; /* mute */ 1654 conf_wr(mss, OPL3SAx_VOLUMEL, t); 1655 if (right) t = 15 - (right * 15) / 100; 1656 else t = 0x80; /* mute */ 1657 conf_wr(mss, OPL3SAx_VOLUMER, t); 1658 break; 1659 1660 case SOUND_MIXER_MIC: 1661 t = left; 1662 if (left) t = 31 - (left * 31) / 100; 1663 else t = 0x80; /* mute */ 1664 conf_wr(mss, OPL3SAx_MIC, t); 1665 break; 1666 1667 case SOUND_MIXER_BASS: 1668 case SOUND_MIXER_TREBLE: 1669 /* Later maybe */ 1670 1671 default: 1672 mss_mixer_set(mss, dev, left, right); 1673 } 1674 1675 return left | (right << 8); 1676} 1677 1678static int 1679ymmix_setrecsrc(snd_mixer *m, u_int32_t src) 1680{ 1681 struct mss_info *mss = mix_getdevinfo(m); 1682 src = mss_set_recsrc(mss, src); 1683 return src; 1684} 1685 1686/* channel interface */ 1687static void * 1688msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) 1689{ 1690 struct mss_info *mss = devinfo; 1691 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch; 1692 1693 ch->parent = mss; 1694 ch->channel = c; 1695 ch->buffer = b; 1696 ch->buffer->bufsize = MSS_BUFFSIZE; 1697 if (chn_allocbuf(ch->buffer, mss->parent_dmat) == -1) return NULL; 1698 return ch; 1699} 1700 1701static int 1702msschan_setdir(void *data, int dir) 1703{ 1704 struct mss_chinfo *ch = data; 1705 1706 ch->buffer->chan = (dir == PCMDIR_PLAY)? ch->parent->pdma : ch->parent->rdma; 1707 ch->dir = dir; 1708 return 0; 1709} 1710 1711static int 1712msschan_setformat(void *data, u_int32_t format) 1713{ 1714 struct mss_chinfo *ch = data; 1715 1716 mss_format(ch, format); 1717 return 0; 1718} 1719 1720static int 1721msschan_setspeed(void *data, u_int32_t speed) 1722{ 1723 struct mss_chinfo *ch = data; 1724 1725 return mss_speed(ch, speed); 1726} 1727 1728static int 1729msschan_setblocksize(void *data, u_int32_t blocksize) 1730{ 1731 return blocksize; 1732} 1733 1734static int 1735msschan_trigger(void *data, int go) 1736{ 1737 struct mss_chinfo *ch = data; 1738 1739 if (go == PCMTRIG_EMLDMAWR) return 0; 1740 buf_isadma(ch->buffer, go); 1741 mss_trigger(ch, go); 1742 return 0; 1743} 1744 1745static int 1746msschan_getptr(void *data) 1747{ 1748 struct mss_chinfo *ch = data; 1749 return buf_isadmaptr(ch->buffer); 1750} 1751 1752static pcmchan_caps * 1753msschan_getcaps(void *data) 1754{ 1755 struct mss_chinfo *ch = data; 1756 1757 switch(ch->parent->bd_id) { 1758 case MD_OPTI931: 1759 return &opti931_caps; 1760 break; 1761 1762 case MD_GUSPNP: 1763 case MD_GUSMAX: 1764 return &guspnp_caps; 1765 break; 1766 1767 default: 1768 return &mss_caps; 1769 break; 1770 } 1771} 1772