166550Snyan/* $FreeBSD: releng/10.3/sys/dev/snc/dp83932reg.h 139749 2005-01-06 01:43:34Z imp $ */ 266550Snyan/* $NecBSD: dp83932reg.h,v 1.2 1999/02/12 05:50:13 kmatsuda Exp $ */ 366550Snyan/* $NetBSD: if_snreg.h,v 1.4 1997/06/15 20:20:12 scottr Exp $ */ 466550Snyan 5139749Simp/*- 666550Snyan * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk) 766550Snyan * You may use, copy, and modify this program so long as you retain the 866550Snyan * copyright line. 966550Snyan */ 1066550Snyan 1166550Snyan/* 1266550Snyan * if_snreg.h -- National Semiconductor DP8393X (SONIC) register defs 1366550Snyan */ 1466550Snyan 1566550Snyan/* 1666550Snyan * SONIC registers as seen by the processor 1766550Snyan */ 1866550Snyan#define SNCR_CR 0x00 /* Command */ 1966550Snyan#define SNCR_DCR 0x01 /* Data Configuration */ 2066550Snyan#define SNCR_RCR 0x02 /* Receive Control */ 2166550Snyan#define SNCR_TCR 0x03 /* Transmit Control */ 2266550Snyan#define SNCR_IMR 0x04 /* Interrupt Mask */ 2366550Snyan#define SNCR_ISR 0x05 /* Interrupt Status */ 2466550Snyan#define SNCR_UTDA 0x06 /* Upper Transmit Descriptor Address */ 2566550Snyan#define SNCR_CTDA 0x07 /* Current Transmit Descriptor Address */ 2666550Snyan#define SNCR_TPS 0x08 /* Transmit Packet Size */ 2766550Snyan#define SNCR_TFC 0x09 /* Transmit Fragment Count */ 2866550Snyan#define SNCR_TSA0 0x0a /* Transmit Start Address 0 */ 2966550Snyan#define SNCR_TSA1 0x0b /* Transmit Start Address 1 */ 3066550Snyan#define SNCR_TFS 0x0c /* Transmit Fragment Size */ 3166550Snyan#define SNCR_URDA 0x0d /* Upper Receive Descriptor Address */ 3266550Snyan#define SNCR_CRDA 0x0e /* Current Receive Descriptor Address */ 3366550Snyan#define SNCR_CRBA0 0x0f /* Current Receive Buffer Address 0 */ 3466550Snyan#define SNCR_CRBA1 0x10 /* Current Receive Buffer Address 1 */ 3566550Snyan#define SNCR_RBWC0 0x11 /* Remaining Buffer Word Count 0 */ 3666550Snyan#define SNCR_RBWC1 0x12 /* Remaining Buffer Word Count 1 */ 3766550Snyan#define SNCR_EOBC 0x13 /* End Of Buffer Word Count */ 3866550Snyan#define SNCR_URRA 0x14 /* Upper Receive Resource Address */ 3966550Snyan#define SNCR_RSA 0x15 /* Resource Start Address */ 4066550Snyan#define SNCR_REA 0x16 /* Resource End Address */ 4166550Snyan#define SNCR_RRP 0x17 /* Resource Read Pointer */ 4266550Snyan#define SNCR_RWP 0x18 /* Resource Write Pointer */ 4366550Snyan#define SNCR_TRBA0 0x19 /* Temporary Receive Buffer Address 0 */ 4466550Snyan#define SNCR_TRBA1 0x1a /* Temporary Receive Buffer Address 1 */ 4566550Snyan#define SNCR_TBWC0 0x1b /* Temporary Buffer Word Count 0 */ 4666550Snyan#define SNCR_TBWC1 0x1c /* Temporary Buffer Word Count 1 */ 4766550Snyan#define SNCR_ADDR0 0x1d /* Address Generator 0 */ 4866550Snyan#define SNCR_ADDR1 0x1e /* Address Generator 1 */ 4966550Snyan#define SNCR_LLFA 0x1f /* Last Link Field Address */ 5066550Snyan#define SNCR_TTDA 0x20 /* Temp Transmit Descriptor Address */ 5166550Snyan#define SNCR_CEP 0x21 /* CAM Entry Pointer */ 5266550Snyan#define SNCR_CAP2 0x22 /* CAM Address Port 2 */ 5366550Snyan#define SNCR_CAP1 0x23 /* CAM Address Port 1 */ 5466550Snyan#define SNCR_CAP0 0x24 /* CAM Address Port 0 */ 5566550Snyan#define SNCR_CE 0x25 /* CAM Enable */ 5666550Snyan#define SNCR_CDP 0x26 /* CAM Descriptor Pointer */ 5766550Snyan#define SNCR_CDC 0x27 /* CAM Descriptor Count */ 5866550Snyan#define SNCR_SR 0x28 /* Silicon Revision */ 5966550Snyan#define SNCR_WT0 0x29 /* Watchdog Timer 0 */ 6066550Snyan#define SNCR_WT1 0x2a /* Watchdog Timer 1 */ 6166550Snyan#define SNCR_RSC 0x2b /* Receive Sequence Counter */ 6266550Snyan#define SNCR_CRCT 0x2c /* CRC Error Tally */ 6366550Snyan#define SNCR_FAET 0x2d /* FAE Tally */ 6466550Snyan#define SNCR_MPT 0x2e /* Missed Packet Tally */ 6566550Snyan#define SNCR_MDT 0x2f /* Maximum Deferral Timer */ 6666550Snyan#define SNCR_RTC 0x30 /* Receive Test Control */ 6766550Snyan#define SNCR_TTC 0x31 /* Transmit Test Control */ 6866550Snyan#define SNCR_DTC 0x32 /* DMA Test Control */ 6966550Snyan#define SNCR_CC0 0x33 /* CAM Comparison 0 */ 7066550Snyan#define SNCR_CC1 0x34 /* CAM Comparison 1 */ 7166550Snyan#define SNCR_CC2 0x35 /* CAM Comparison 2 */ 7266550Snyan#define SNCR_CM 0x36 /* CAM Match */ 7366550Snyan#define SNCR_RES1 0x37 /* reserved */ 7466550Snyan#define SNCR_RES2 0x38 /* reserved */ 7566550Snyan#define SNCR_RBC 0x39 /* Receiver Byte Count */ 7666550Snyan#define SNCR_RES3 0x3a /* reserved */ 7766550Snyan#define SNCR_TBO 0x3b /* Transmitter Backoff Counter */ 7866550Snyan#define SNCR_TRC 0x3c /* Transmitter Random Counter */ 7966550Snyan#define SNCR_TBM 0x3d /* Transmitter Backoff Mask */ 8066550Snyan#define SNCR_RES4 0x3e /* Reserved */ 8166550Snyan#define SNCR_DCR2 0x3f /* Data Configuration 2 (AVF) */ 8266550Snyan 8366550Snyan#define SNC_NREGS 0x40 8466550Snyan 8566550Snyan/* 8666550Snyan * Register Interpretations 8766550Snyan */ 8866550Snyan 8966550Snyan/* 9066550Snyan * The command register is used for issuing commands to the SONIC. 9166550Snyan * With the exception of CR_RST, the bit is reset when the operation 9266550Snyan * completes. 9366550Snyan */ 9466550Snyan#define CR_LCAM 0x0200 /* load CAM with descriptor at s_cdp */ 9566550Snyan#define CR_RRRA 0x0100 /* read next RRA descriptor at s_rrp */ 9666550Snyan#define CR_RST 0x0080 /* software reset */ 9766550Snyan#define CR_ST 0x0020 /* start timer */ 9866550Snyan#define CR_STP 0x0010 /* stop timer */ 9966550Snyan#define CR_RXEN 0x0008 /* receiver enable */ 10066550Snyan#define CR_RXDIS 0x0004 /* receiver disable */ 10166550Snyan#define CR_TXP 0x0002 /* transmit packets */ 10266550Snyan#define CR_HTX 0x0001 /* halt transmission */ 10366550Snyan 10466550Snyan/* 10566550Snyan * The data configuration register establishes the SONIC's bus cycle 10666550Snyan * operation. This register can only be accessed when the SONIC is in 10766550Snyan * reset mode (s_cr.CR_RST is set.) 10866550Snyan */ 10966550Snyan#define DCR_EXBUS 0x8000 /* extended bus mode (AVF) */ 11066550Snyan#define DCR_LBR 0x2000 /* latched bus retry */ 11166550Snyan#define DCR_PO1 0x1000 /* programmable output 1 */ 11266550Snyan#define DCR_PO0 0x0800 /* programmable output 0 */ 11366550Snyan#define DCR_STERM 0x0400 /* synchronous termination */ 11466550Snyan#define DCR_USR1 0x0200 /* reflects USR1 input pin */ 11566550Snyan#define DCR_USR0 0x0100 /* reflects USR0 input pin */ 11666550Snyan#define DCR_WC1 0x0080 /* wait state control 1 */ 11766550Snyan#define DCR_WC0 0x0040 /* wait state control 0 */ 11866550Snyan#define DCR_DW 0x0020 /* data width select */ 11966550Snyan#define DCR_BMS 0x0010 /* DMA block mode select */ 12066550Snyan#define DCR_RFT1 0x0008 /* receive FIFO threshold control 1 */ 12166550Snyan#define DCR_RFT0 0x0004 /* receive FIFO threshold control 0 */ 12266550Snyan#define DCR_TFT1 0x0002 /* transmit FIFO threshold control 1 */ 12366550Snyan#define DCR_TFT0 0x0001 /* transmit FIFO threshold control 0 */ 12466550Snyan 12566550Snyan/* data configuration register aliases */ 12666550Snyan#define DCR_SYNC DCR_STERM /* synchronous (memory cycle 2 clocks) */ 12766550Snyan#define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */ 12866550Snyan 12966550Snyan#define DCR_WAIT0 0 /* 0 wait states added */ 13066550Snyan#define DCR_WAIT1 DCR_WC0 /* 1 wait state added */ 13166550Snyan#define DCR_WAIT2 DCR_WC1 /* 2 wait states added */ 13266550Snyan#define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */ 13366550Snyan 13466550Snyan#define DCR_DW16 0 /* use 16-bit DMA accesses */ 13566550Snyan#define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */ 13666550Snyan 13766550Snyan#define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */ 13866550Snyan#define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */ 13966550Snyan 14066550Snyan#define DCR_RFT4 0 /* receive threshold 4 bytes */ 14166550Snyan#define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */ 14266550Snyan#define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */ 14366550Snyan#define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */ 14466550Snyan 14566550Snyan#define DCR_TFT8 0 /* transmit threshold 8 bytes */ 14666550Snyan#define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */ 14766550Snyan#define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */ 14866550Snyan#define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */ 14966550Snyan 15066550Snyan/* 15166550Snyan * The receive control register is used to filter incoming packets and 15266550Snyan * provides status information on packets received. 15366550Snyan * The contents of the register are copied into the RXpkt.status field 15466550Snyan * when a packet is received. RCR_MC - RCR_PRX are then reset. 15566550Snyan */ 15666550Snyan#define RCR_ERR 0x8000 /* accept packets with CRC errors */ 15766550Snyan#define RCR_RNT 0x4000 /* accept runt (length < 64) packets */ 15866550Snyan#define RCR_BRD 0x2000 /* accept broadcast packets */ 15966550Snyan#define RCR_PRO 0x1000 /* accept all physical address packets */ 16066550Snyan#define RCR_AMC 0x0800 /* accept all multicast packets */ 16166550Snyan#define RCR_LB1 0x0400 /* loopback control 1 */ 16266550Snyan#define RCR_LB0 0x0200 /* loopback control 0 */ 16366550Snyan#define RCR_MC 0x0100 /* multicast packet received */ 16466550Snyan#define RCR_BC 0x0080 /* broadcast packet received */ 16566550Snyan#define RCR_LPKT 0x0040 /* last packet in RBA (RBWC < EOBC) */ 16666550Snyan#define RCR_CRS 0x0020 /* carrier sense activity */ 16766550Snyan#define RCR_COL 0x0010 /* collision activity */ 16866550Snyan#define RCR_CRC 0x0008 /* CRC error */ 16966550Snyan#define RCR_FAE 0x0004 /* frame alignment error */ 17066550Snyan#define RCR_LBK 0x0002 /* loopback packet received */ 17166550Snyan#define RCR_PRX 0x0001 /* packet received without errors */ 17266550Snyan 17366550Snyan/* receiver control register aliases */ 17466550Snyan/* the loopback control bits provide the following options */ 17566550Snyan#define RCR_LBNONE 0 /* no loopback - normal operation */ 17666550Snyan#define RCR_LBMAC RCR_LB0 /* MAC loopback */ 17766550Snyan#define RCR_LBENDEC RCR_LB1 /* ENDEC loopback */ 17866550Snyan#define RCR_LBTRANS (RCR_LB1|RCR_LB0) /* transceiver loopback */ 17966550Snyan 18066550Snyan/* 18166550Snyan * The transmit control register controls the SONIC's transmit operations. 18266550Snyan * TCR_PINT - TCR_EXDIS are loaded from the TXpkt.config field at the 18366550Snyan * start of transmission. TCR_EXD-TCR_PTX are cleared at the beginning 18466550Snyan * of transmission and updated when the transmission is completed. 18566550Snyan */ 18666550Snyan#define TCR_PINT 0x8000 /* interrupt when transmission starts */ 18766550Snyan#define TCR_POWC 0x4000 /* program out of window collision timer */ 18866550Snyan#define TCR_CRCI 0x2000 /* transmit packet without 4 byte FCS */ 18966550Snyan#define TCR_EXDIS 0x1000 /* disable excessive deferral timer */ 19066550Snyan#define TCR_EXD 0x0400 /* excessive deferrals occurred (>3.2ms) */ 19166550Snyan#define TCR_DEF 0x0200 /* deferred transmissions occurred */ 19266550Snyan#define TCR_NCRS 0x0100 /* carrier not present during transmission */ 19366550Snyan#define TCR_CRSL 0x0080 /* carrier lost during transmission */ 19466550Snyan#define TCR_EXC 0x0040 /* excessive collisions (>16) detected */ 19566550Snyan#define TCR_OWC 0x0020 /* out of window (bad) collision occurred */ 19666550Snyan#define TCR_PMB 0x0008 /* packet monitored bad - the tansmitted 19766550Snyan * packet had a bad source address or CRC */ 19866550Snyan#define TCR_FU 0x0004 /* FIFO underrun (memory access failed) */ 19966550Snyan#define TCR_BCM 0x0002 /* byte count mismatch (TXpkt.pkt_size 20066550Snyan * != sum(TXpkt.frag_size) */ 20166550Snyan#define TCR_PTX 0x0001 /* packet transmitted without errors */ 20266550Snyan#define TCR_NC 0xf000 /* after transmission, # of colls */ 20366550Snyan 20466550Snyan/* transmit control register aliases */ 20566550Snyan#define TCR_OWCSFD 0 /* start after start of frame delimiter */ 20666550Snyan#define TCR_OWCPRE TCR_POWC /* start after first bit of preamble */ 20766550Snyan 20866550Snyan 20966550Snyan/* 21066550Snyan * The interrupt mask register masks the interrupts that 21166550Snyan * are generated from the interrupt status register. 21266550Snyan * All reserved bits should be written with 0. 21366550Snyan */ 21466550Snyan#define IMR_BREN 0x4000 /* bus retry occurred enable */ 21566550Snyan#define IMR_HBLEN 0x2000 /* heartbeat lost enable */ 21666550Snyan#define IMR_LCDEN 0x1000 /* load CAM done interrupt enable */ 21766550Snyan#define IMR_PINTEN 0x0800 /* programmable interrupt enable */ 21866550Snyan#define IMR_PRXEN 0x0400 /* packet received enable */ 21966550Snyan#define IMR_PTXEN 0x0200 /* packet transmitted enable */ 22066550Snyan#define IMR_TXEREN 0x0100 /* transmit error enable */ 22166550Snyan#define IMR_TCEN 0x0080 /* timer complete enable */ 22266550Snyan#define IMR_RDEEN 0x0040 /* receive descriptors exhausted enable */ 22366550Snyan#define IMR_RBEEN 0x0020 /* receive buffers exhausted enable */ 22466550Snyan#define IMR_RBAEEN 0x0010 /* receive buffer area exceeded enable */ 22566550Snyan#define IMR_CRCEN 0x0008 /* CRC tally counter rollover enable */ 22666550Snyan#define IMR_FAEEN 0x0004 /* FAE tally counter rollover enable */ 22766550Snyan#define IMR_MPEN 0x0002 /* MP tally counter rollover enable */ 22866550Snyan#define IMR_RFOEN 0x0001 /* receive FIFO overrun enable */ 22966550Snyan 23066550Snyan 23166550Snyan/* 23266550Snyan * The interrupt status register indicates the source of an interrupt when 23366550Snyan * the INT pin goes active. The interrupt is acknowledged by writing 23466550Snyan * the appropriate bit(s) in this register. 23566550Snyan */ 23666550Snyan#define ISR_ALL 0x7fff /* all interrupts */ 23766550Snyan#define ISR_BR 0x4000 /* bus retry occurred */ 23866550Snyan#define ISR_HBL 0x2000 /* CD heartbeat lost */ 23966550Snyan#define ISR_LCD 0x1000 /* load CAM command has completed */ 24066550Snyan#define ISR_PINT 0x0800 /* programmed interrupt from TXpkt.config */ 24166550Snyan#define ISR_PKTRX 0x0400 /* packet received */ 24266550Snyan#define ISR_TXDN 0x0200 /* no remaining packets to be transmitted */ 24366550Snyan#define ISR_TXER 0x0100 /* packet transmission caused error */ 24466550Snyan#define ISR_TC 0x0080 /* timer complete */ 24566550Snyan#define ISR_RDE 0x0040 /* receive descriptors exhausted */ 24666550Snyan#define ISR_RBE 0x0020 /* receive buffers exhausted */ 24766550Snyan#define ISR_RBAE 0x0010 /* receive buffer area exceeded */ 24866550Snyan#define ISR_CRC 0x0008 /* CRC tally counter rollover */ 24966550Snyan#define ISR_FAE 0x0004 /* FAE tally counter rollover */ 25066550Snyan#define ISR_MP 0x0002 /* MP tally counter rollover */ 25166550Snyan#define ISR_RFO 0x0001 /* receive FIFO overrun */ 25266550Snyan 25366550Snyan/* 25466550Snyan * The second data configuration register allows additional user defined 25566550Snyan * pins to be controlled. These bits are only available if s_dcr.DCR_EXBUS 25666550Snyan * is set. 25766550Snyan */ 25866550Snyan#define DCR2_EXPO3 0x8000 /* EXUSR3 output */ 25966550Snyan#define DCR2_EXPO2 0x4000 /* EXUSR2 output */ 26066550Snyan#define DCR2_EXPO1 0x2000 /* EXUSR1 output */ 26166550Snyan#define DCR2_EXPO0 0x1000 /* EXUSR0 output */ 26266550Snyan#define DCR2_HD 0x0800 /* heart beat disable (83934/83936) */ 26366550Snyan#define DCR2_JD 0x0200 /* TPI jabber timer disable (83934/83936) */ 26466550Snyan#define DCR2_AUTO 0x0100 /* AUI/TPI auto selection (83934/83936) */ 26566550Snyan#define DCR2_XWRAP 0x0040 /* TPI transceiver loopback (83934/83936) */ 26666550Snyan#define DCR2_FD 0x0020 /* full duplex (83936) */ 26766550Snyan#define DCR2_PHL 0x0010 /* extend HOLD signal by 1/2 clock */ 26866550Snyan#define DCR2_LRDY 0x0008 /* set latched ready mode */ 26966550Snyan#define DCR2_PCM 0x0004 /* packet compress on match */ 27066550Snyan#define DCR2_PCNM 0x0002 /* packet compress on mismatch */ 27166550Snyan#define DCR2_RJM 0x0001 /* reject on match */ 272